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Author	SHA1	Message	Date
Rodolphe de Saint Léger	620468666f	bcc32 now updates pc and not scan (which is only 16 bits wide)	2025-05-20 20:23:17 +02:00
Rodolphe de Saint Léger	5d4b8809d0	Add DIVU/DIVS	2025-05-20 11:47:11 +02:00
Rodolphe de Saint Léger	ac5497e797	Added MULU/MULS	2025-05-19 18:56:04 +02:00
Rodolphe de Saint Léger	93831dd116	Changed MOVE.w/l as,<ea> implementation to reflect real behavior	2025-05-19 18:02:33 +02:00
Rodolphe de Saint Léger	b7910339a3	Fixed ASL/ASR	2025-05-19 15:27:30 +02:00
Rodolphe de Saint Léger	7daa27e15f	Fixed RESET	2025-05-19 14:33:03 +02:00
Rodolphe de Saint Léger	0d93bfe32d	Fixed CHK ... Added 68000 only Bcc	2025-05-19 14:14:07 +02:00
Rodolphe de Saint Léger	d2d7171a18	Fixed LSL/LSR/ROL/ROR	2025-05-19 12:16:18 +02:00
Rodolphe de Saint Léger	4aad8cbc96	Fixed MOVEM ... - register list is fetched before EA resolution - pre/post EA mode MUST use ar indirect register micro-routine	2025-05-19 11:37:54 +02:00
Rodolphe de Saint Léger	cee4710070	Fixed NEG.w	2025-05-19 00:06:00 +02:00
Rodolphe de Saint Léger	bd74a9661f	Fixed CLR	2025-05-18 23:15:52 +02:00
Rodolphe de Saint Léger	7920f8c6da	First regression tests and bug fixes ... Import tests from https://github.com/SingleStepTests/m68000 Added: - Single Step mode for Core - 68000/68010 only indexed EA mode Fixed: - Added a real CMP in CoreALU (for CCR eXtend bit unaffected) - Correct microcode branching for all post incremented destination ea - Fixed PC relative calculation for all related EA - used of au instead of dt for indexed EA calculation - Fixed EXG with same register - Fixed Link/unlk with A7 - Fixed Bcc/BRA/BSR	2025-05-18 22:59:19 +02:00
Rodolphe de Saint Léger	0a4e1a5764	add movem declaration	2025-05-13 11:10:19 +02:00
rdesaintleger	b016a8fd9e	CPU Commit (WIP)	2025-05-13 10:03:25 +02:00
Rodolphe De Saint Leger	4abd895f87	Initial commit	2025-05-13 07:52:04 +00:00