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Fixed CHK

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Added 68000 only Bcc
This commit is contained in:
Rodolphe de Saint Léger 2025-05-19 14:14:07 +02:00
parent d2d7171a18
commit 0d93bfe32d
7 changed files with 737 additions and 636 deletions
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22
miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java
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@ -1592,6 +1592,7 @@ public class CoreGenerator {
addBeginFormattedControlFlow("if (word_chk(dar[ry], dar[rx]))");
settvn(6);
addFormattedMicroInsn("mpc = (sswi & 0x%04x) != 0 ? trap2000 : trap0000", SSWI_FMT2);
addFormattedMicroInsn("continue");
addEndControlFlow();
microprefetch(true, null); // prefetch ir from pc and resume execution
@ -1600,6 +1601,7 @@ public class CoreGenerator {
addBeginFormattedControlFlow("if (word_chk(dt, dar[rx]))");
settvn(6);
addFormattedMicroInsn("mpc = (sswi & 0x%04x) != 0 ? trap2000 : trap0000", SSWI_FMT2);
addFormattedMicroInsn("continue");
addEndControlFlow();
microprefetch(true, null); // prefetch ir from pc and resume execution
@ -2545,11 +2547,13 @@ public class CoreGenerator {
addState("op_bcc16");
addBeginFormattedControlFlow("if (!testCC((ir & 0x0f00) >> 8))");
addFormattedMicroInsn("scan += 2");
consume(10, 2, 0);
microprefetch(true, null); // prefetch ir from pc and resume execution
addEndControlFlow();
addState("op_bra16");
anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, null);
consume(10, 2, 0);
addFormattedMicroInsn("scan = (short) dt");
addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow
@ -2557,11 +2561,19 @@ public class CoreGenerator {
addState("op_bcc32");
addBeginFormattedControlFlow("if (!testCC((ir & 0x0f00) >> 8))");
addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_DNGR);
addFormattedMicroInsn("scan += 4");
addEndControlFlow();
consume(14, 3, 0);
microprefetch(true, null); // prefetch ir from pc and resume execution
addEndControlFlow();
addState("op_bra32");
addBeginFormattedControlFlow("if ((sswi & 0x%04x) != 0)", SSWI_DNGR);
addFormattedMicroInsn("mpc = op_bra8");
addFormattedMicroInsn("continue");
addEndControlFlow();
anyread32("dt", SSW_DF | SSW_P, "pc + scan", 0, false, null);
consume(14, 3, 0);
addFormattedMicroInsn("scan = dt");
addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow
@ -2577,6 +2589,9 @@ public class CoreGenerator {
microprefetch(true, null); // prefetch ir from pc and resume execution
addState("op_bsr16");
anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> {
addFormattedMicroInsn("scan += 2");
});
consume(18, 2, 2);
addFormattedMicroInsn("au = dar[sp] - 4");
addFormattedMicroInsn("dar[sp] = au");
@ -2586,6 +2601,13 @@ public class CoreGenerator {
microprefetch(true, null); // prefetch ir from pc and resume execution
addState("op_bsr32");
addBeginFormattedControlFlow("if ((sswi & 0x%04x) != 0)", SSWI_DNGR);
addFormattedMicroInsn("mpc = op_bsr8");
addFormattedMicroInsn("continue");
addEndControlFlow();
anyread32("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> {
addFormattedMicroInsn("scan += 4");
});
consume(22, 3, 2);
addFormattedMicroInsn("au = dar[sp] - 4");
addFormattedMicroInsn("dar[sp] = au");

12
miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java
View file

@ -544,14 +544,14 @@ public class CorePLAGenerator {
appendOP(gen, entries, array, 0x50fc, 0xf0ff, "trapcc", "op_trapcc", "dbrr", "dbrr");
appendOP(gen, entries, array, 0x6000, 0xff00, "bra_rel8", "op_bra8", "dbrr", "dbrr");
appendOP(gen, entries, array, 0x6000, 0xffff, "bra_rel16", "op_imm16", "op_bra16", "dbrr");
appendOP(gen, entries, array, 0x60ff, 0xffff, "bra_rel32", "op_imm32", "op_bra32", "dbrr");
appendOP(gen, entries, array, 0x6000, 0xffff, "bra_rel16", "op_bra16", "dbrr", "dbrr");
appendOP(gen, entries, array, 0x60ff, 0xffff, "bra_rel32", "op_bra32", "dbrr", "dbrr");
appendOP(gen, entries, array, 0x6100, 0xff00, "bsr_rel8", "op_bsr8", "dbrr", "dbrr");
appendOP(gen, entries, array, 0x6100, 0xffff, "bsr_rel16", "op_imm16", "op_bsr16", "dbrr");
appendOP(gen, entries, array, 0x61ff, 0xffff, "bsr_rel32", "op_imm32", "op_bsr32", "dbrr");
appendOP(gen, entries, array, 0x6100, 0xffff, "bsr_rel16", "op_bsr16", "dbrr", "dbrr");
appendOP(gen, entries, array, 0x61ff, 0xffff, "bsr_rel32", "op_bsr32", "dbrr", "dbrr");
appendOP(gen, entries, array, 0x6000, 0xf000, "bcc_rel8", "op_bcc8", "dbrr", "dbrr");
appendOP(gen, entries, array, 0x6000, 0xf0ff, "bcc_rel16", "op_imm16", "op_bcc16", "dbrr");
appendOP(gen, entries, array, 0x60ff, 0xf0ff, "bcc_rel32", "op_imm32", "op_bcc32", "dbrr");
appendOP(gen, entries, array, 0x6000, 0xf0ff, "bcc_rel16", "op_bcc16", "dbrr", "dbrr");
appendOP(gen, entries, array, 0x60ff, 0xf0ff, "bcc_rel32", "op_bcc32", "dbrr", "dbrr");
appendOP(gen, entries, array, 0x7000, 0xf100, "moveq_imm8o_dd", move(gen, "l", "imm8o", "dd"), "dbrr", "dbrr");

1310
miggy-emu/src/main/java/miggy/cpupoet/Core.java
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File diff suppressed because it is too large Load diff

12
miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java
View file

@ -107,7 +107,7 @@ public class CoreALU {
*/
public static final int SSWI_XRMW = 1 << 6;
/**
* Downgrade to 68000 for Bcc/dais
* Downgrade to 68000 for Bcc/CHK/dais
*/
public static final int SSWI_DNGR = 1 << 5;
/**
@ -1141,8 +1141,14 @@ public class CoreALU {
return true;
}
/* leave N flag and continue execution */
sr ^= (sr ^ z) & (FL_C | FL_V | FL_Z);
if ((sswi & SSWI_DNGR) != 0) {
int n = (dst >> 28) & FL_N;
sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N);
} else {
/* leave N flag and continue execution */
sr ^= (sr ^ z) & (FL_C | FL_V | FL_Z);
}
return false;
}

12
miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java
View file

@ -2114,23 +2114,23 @@ public enum MacroPLA {
subq_l_imm3_adr32(0x51b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_subl_ir_ea),
bra_rel16(0x6000, 0xffff, op_imm16, op_bra16, dbrr),
bra_rel16(0x6000, 0xffff, op_bra16, dbrr, dbrr),
bcc_rel16(0x6000, 0xf0ff, op_imm16, op_bcc16, dbrr),
bcc_rel16(0x6000, 0xf0ff, op_bcc16, dbrr, dbrr),
bra_rel8(0x6000, 0xff00, op_bra8, dbrr, dbrr),
bcc_rel8(0x6000, 0xf000, op_bcc8, dbrr, dbrr),
bra_rel32(0x60ff, 0xffff, op_imm32, op_bra32, dbrr),
bra_rel32(0x60ff, 0xffff, op_bra32, dbrr, dbrr),
bcc_rel32(0x60ff, 0xf0ff, op_imm32, op_bcc32, dbrr),
bcc_rel32(0x60ff, 0xf0ff, op_bcc32, dbrr, dbrr),
bsr_rel16(0x6100, 0xffff, op_imm16, op_bsr16, dbrr),
bsr_rel16(0x6100, 0xffff, op_bsr16, dbrr, dbrr),
bsr_rel8(0x6100, 0xff00, op_bsr8, dbrr, dbrr),
bsr_rel32(0x61ff, 0xffff, op_imm32, op_bsr32, dbrr),
bsr_rel32(0x61ff, 0xffff, op_bsr32, dbrr, dbrr),
moveq_imm8o_dd(0x7000, 0xf100, gen_movel_im_dd, dbrr, dbrr),

5
miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java
View file

@ -91,8 +91,8 @@ public class InstructionTests extends TestCase {
public void testBcc() {
CoreTest test = new CoreTest(0xffffff + 1, true);
test.executeBinTest("Bcc", 373, 466, 570, 1547, 1695, 1782, 2166, 2224, 2441);
test.executeBinTest("BSR", 25, 573, 814, 1357, 1443, 1509, 1734, 1934, 2232, 2338);
test.executeBinTest("Bcc");
test.executeBinTest("BSR");
}
public void testDBcc() {
@ -104,6 +104,7 @@ public class InstructionTests extends TestCase {
public void testMisc() {
CoreTest test = new CoreTest(0xffffff + 1, true);
test.executeBinTest("CHK");
test.executeBinTest("NOP");
test.executeBinTest("EXG");
test.executeBinTest("SWAP");

BIN
miggy-emu/src/test/resources/miggy/cpupoet/CHK.json.bin Normal file
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Binary file not shown.