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https://bitbucket.org/rslr/miggy-cpu.git
synced 2026-06-12 19:16:29 +00:00
add movem declaration
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commit
0a4e1a5764
4 changed files with 1300 additions and 1160 deletions
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@ -1254,18 +1254,18 @@ public class CoreGenerator {
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addFormattedMicroInsn("break");
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addState("ea_dpc32_read");
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//setclr16("sswi", SSWI_EAFH, 0);
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//addState("ea_dpc32");
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setclr16("sswi", SSWI_EAFH, 0);
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addState("ea_dpc32");
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fetchimm16("at", 0);
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addFormattedMicroInsn("at = ((short) at) + pc"); // add pc to temporary register
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//addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH);
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//consume(4, 1, 0);
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//addFormattedMicroInsn("nmpc = decoded.a3");
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//addFormattedMicroInsn("break");
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//addEndControlFlow();
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addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH);
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consume(4, 1, 0);
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addFormattedMicroInsn("nmpc = decoded.a3");
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addFormattedMicroInsn("break");
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addEndControlFlow();
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consume(12, 3, 0);
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addState("eapc_read32");
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//setclr16("sswi", 0, SSWI_EAFH);
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setclr16("sswi", 0, SSWI_EAFH);
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addFormattedMicroInsn("alub = dt"); // save dt to alub
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anyread32("dt", SSW_DF | SSW_P, "at", 0, false, null);
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addClearSSW();
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@ -1291,13 +1291,13 @@ public class CoreGenerator {
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addFormattedMicroInsn("mpc = eapc_read16");
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addFormattedMicroInsn("continue");
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ea_dais_calculate_microcode("dpci", "32", true, true);
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ea_dais_calculate_microcode("dpci", "32", true, false);
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addState("ea_dpci32_fetch");
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//addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH);
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//consume(8, 1, 0);
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//addFormattedMicroInsn("nmpc = decoded.a3");
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//addFormattedMicroInsn("break");
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//addEndControlFlow();
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addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH);
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consume(8, 1, 0);
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addFormattedMicroInsn("nmpc = decoded.a3");
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addFormattedMicroInsn("break");
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addEndControlFlow();
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consume(14, 3, 0);
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addFormattedMicroInsn("mpc = eapc_read32");
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addFormattedMicroInsn("continue");
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@ -1820,7 +1820,7 @@ public class CoreGenerator {
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addFormattedMicroInsn("mpc = %d", loop);
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addFormattedMicroInsn("continue");
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addState("op_movemw_aisp_rr");
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addState("op_movemw_aips_rr");
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// read extension word
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anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> {
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addFormattedMicroInsn("scan += 2");
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@ -1881,7 +1881,7 @@ public class CoreGenerator {
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addFormattedMicroInsn("mpc = %d", loop);
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addFormattedMicroInsn("continue");
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addState("op_moveml_aisp_rr");
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addState("op_moveml_aips_rr");
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// read extension word
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anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> {
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addFormattedMicroInsn("scan += 2");
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@ -425,6 +425,54 @@ public class CorePLAGenerator {
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appendOP(gen, entries, array, 0x4e7a, 0xffff, "movec_cr_rz", "op_movec_cr_rz", "dbrr", "dbrr");
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appendOP(gen, entries, array, 0x4e7b, 0xffff, "movec_rz_cr", "op_movec_rz_cr", "dbrr", "dbrr");
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appendOP_eas(0x4890, 0xffc0, "movem_w_list", EA_CTRL, "16", (opcode, opmask, opname, n1, mode) -> {
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//opname = String.format("%s", opname);
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appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_movemw_rr_ea");
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});
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appendOP_eas(0x4890, 0xffc0, "movem_w_listp", EA_PAIS, "16", (opcode, opmask, opname, n1, mode) -> {
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//opname = String.format("%s", opname);
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appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_movemw_rr_pais");
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});
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appendOP_eas(0x48d0, 0xffc0, "movem_l_list", EA_CTRL, "32", (opcode, opmask, opname, n1, mode) -> {
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//opname = String.format("%s", opname);
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appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_moveml_rr_ea");
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});
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appendOP_eas(0x48d0, 0xffc0, "movem_l_listp", EA_PAIS, "32", (opcode, opmask, opname, n1, mode) -> {
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//opname = String.format("%s", opname);
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appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_moveml_rr_pais");
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});
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appendOP_eas(0x4c90, 0xffc0, "movem_w", EA_CTRL, "16", (opcode, opmask, opname, n1, mode) -> {
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opname = String.format("%s_list", opname);
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appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_movemw_ea_rr");
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});
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appendOP_eas(0x4c90, 0xffc0, "movem_w", EA_AIPS, "16", (opcode, opmask, opname, n1, mode) -> {
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opname = String.format("%s_list", opname);
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appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_movemw_aips_rr");
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});
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appendOP_eas(0x4cd0, 0xffc0, "movem_l", EA_CTRL, "32", (opcode, opmask, opname, n1, mode) -> {
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opname = String.format("%s_list", opname);
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appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_moveml_ea_rr");
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});
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appendOP_eas(0x4cd0, 0xffc0, "movem_l", EA_AIPS, "32", (opcode, opmask, opname, n1, mode) -> {
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opname = String.format("%s_list", opname);
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appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_moveml_aips_rr");
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});
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appendOP_eas(0x4e90, 0xffc0, "jsr", EA_CTRL, "16", (opcode, opmask, opname, n1, mode) -> {
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opname = String.format("%s", opname);
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File diff suppressed because it is too large
Load diff
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@ -60,10 +60,12 @@ import static miggy.cpupoet.Core.ea_das8;
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import static miggy.cpupoet.Core.ea_das8_read;
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import static miggy.cpupoet.Core.ea_dpc16;
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import static miggy.cpupoet.Core.ea_dpc16_read;
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import static miggy.cpupoet.Core.ea_dpc32;
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import static miggy.cpupoet.Core.ea_dpc32_read;
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import static miggy.cpupoet.Core.ea_dpc8_read;
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import static miggy.cpupoet.Core.ea_dpci16;
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import static miggy.cpupoet.Core.ea_dpci16_read;
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import static miggy.cpupoet.Core.ea_dpci32;
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import static miggy.cpupoet.Core.ea_dpci32_read;
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import static miggy.cpupoet.Core.ea_dpci8_read;
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import static miggy.cpupoet.Core.ea_imm16_read;
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@ -383,6 +385,14 @@ import static miggy.cpupoet.Core.op_move_as_usp;
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import static miggy.cpupoet.Core.op_move_usp_as;
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import static miggy.cpupoet.Core.op_movec_cr_rz;
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import static miggy.cpupoet.Core.op_movec_rz_cr;
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import static miggy.cpupoet.Core.op_moveml_aips_rr;
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import static miggy.cpupoet.Core.op_moveml_ea_rr;
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import static miggy.cpupoet.Core.op_moveml_rr_ea;
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import static miggy.cpupoet.Core.op_moveml_rr_pais;
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import static miggy.cpupoet.Core.op_movemw_aips_rr;
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import static miggy.cpupoet.Core.op_movemw_ea_rr;
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import static miggy.cpupoet.Core.op_movemw_rr_ea;
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import static miggy.cpupoet.Core.op_movemw_rr_pais;
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import static miggy.cpupoet.Core.op_movepl_das_dd;
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import static miggy.cpupoet.Core.op_movepl_dd_das;
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import static miggy.cpupoet.Core.op_movepw_das_dd;
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@ -1801,8 +1811,40 @@ public enum MacroPLA {
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ext_w_ds(0x4880, 0xfff8, op_extw_ds, dbrr, dbrr),
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movem_w_list_ais(0x4890, 0xfff8, ea_ais16, dbrr, op_movemw_rr_ea),
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movem_w_listp_pais(0x48a0, 0xfff8, ea_pais16, dbrr, op_movemw_rr_pais),
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movem_w_list_das(0x48a8, 0xfff8, ea_das16, dbrr, op_movemw_rr_ea),
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movem_w_list_dais(0x48b0, 0xfff8, ea_dais16, dbrr, op_movemw_rr_ea),
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movem_w_list_adr16(0x48b8, 0xffff, ea_adr16s16, dbrr, op_movemw_rr_ea),
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movem_w_list_adr32(0x48b9, 0xffff, ea_adr32s16, dbrr, op_movemw_rr_ea),
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movem_w_list_dpc(0x48ba, 0xffff, ea_dpc16, dbrr, op_movemw_rr_ea),
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movem_w_list_dpci(0x48bb, 0xffff, ea_dpci16, dbrr, op_movemw_rr_ea),
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ext_l_ds(0x48c0, 0xfff8, op_extl_ds, dbrr, dbrr),
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movem_l_list_ais(0x48d0, 0xfff8, ea_ais32, dbrr, op_moveml_rr_ea),
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movem_l_listp_pais(0x48e0, 0xfff8, ea_pais32, dbrr, op_moveml_rr_pais),
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movem_l_list_das(0x48e8, 0xfff8, ea_das32, dbrr, op_moveml_rr_ea),
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movem_l_list_dais(0x48f0, 0xfff8, ea_dais32, dbrr, op_moveml_rr_ea),
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movem_l_list_adr16(0x48f8, 0xffff, ea_adr16s32, dbrr, op_moveml_rr_ea),
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movem_l_list_adr32(0x48f9, 0xffff, ea_adr32s32, dbrr, op_moveml_rr_ea),
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movem_l_list_dpc(0x48fa, 0xffff, ea_dpc32, dbrr, op_moveml_rr_ea),
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movem_l_list_dpci(0x48fb, 0xffff, ea_dpci32, dbrr, op_moveml_rr_ea),
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extb_l_ds(0x49c0, 0xfff8, op_extbl_ds, dbrr, dbrr),
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tst_b_ds(0x4a00, 0xfff8, gen_tstb_ds, dbrr, dbrr),
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@ -1855,6 +1897,38 @@ public enum MacroPLA {
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illegal(0x4afc, 0xffff, op_illegal, dbrr, dbrr),
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movem_w_ais_list(0x4c90, 0xfff8, ea_ais16, dbrr, op_movemw_ea_rr),
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movem_w_aips_list(0x4c98, 0xfff8, ea_aips16, dbrr, op_movemw_aips_rr),
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movem_w_das_list(0x4ca8, 0xfff8, ea_das16, dbrr, op_movemw_ea_rr),
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movem_w_dais_list(0x4cb0, 0xfff8, ea_dais16, dbrr, op_movemw_ea_rr),
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movem_w_adr16_list(0x4cb8, 0xffff, ea_adr16s16, dbrr, op_movemw_ea_rr),
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movem_w_adr32_list(0x4cb9, 0xffff, ea_adr32s16, dbrr, op_movemw_ea_rr),
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movem_w_dpc_list(0x4cba, 0xffff, ea_dpc16, dbrr, op_movemw_ea_rr),
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movem_w_dpci_list(0x4cbb, 0xffff, ea_dpci16, dbrr, op_movemw_ea_rr),
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movem_l_ais_list(0x4cd0, 0xfff8, ea_ais32, dbrr, op_moveml_ea_rr),
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movem_l_aips_list(0x4cd8, 0xfff8, ea_aips32, dbrr, op_moveml_aips_rr),
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movem_l_das_list(0x4ce8, 0xfff8, ea_das32, dbrr, op_moveml_ea_rr),
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movem_l_dais_list(0x4cf0, 0xfff8, ea_dais32, dbrr, op_moveml_ea_rr),
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movem_l_adr16_list(0x4cf8, 0xffff, ea_adr16s32, dbrr, op_moveml_ea_rr),
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movem_l_adr32_list(0x4cf9, 0xffff, ea_adr32s32, dbrr, op_moveml_ea_rr),
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movem_l_dpc_list(0x4cfa, 0xffff, ea_dpc32, dbrr, op_moveml_ea_rr),
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movem_l_dpci_list(0x4cfb, 0xffff, ea_dpci32, dbrr, op_moveml_ea_rr),
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trap_imm4(0x4e40, 0xfff0, op_trap, dbrr, dbrr),
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link_as_imm16(0x4e50, 0xfff8, op_imm16, op_link_as_imm16, dbrr),
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