Fixed CLR

miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java

@@ -1484,28 +1484,34 @@ public class CoreGenerator {
 		addState("op_clrb_ds");
 		decode_dy();
 		addFormattedMicroInsn("dar[ry] &= ~0xff");
+		setclr16("sr", FL_Z, FL_N | FL_V | FL_C);
 		microprefetch(true, null); // prefetch ir and resume execution
 
 		addState("op_clrw_ds");
 		decode_dy();
 		addFormattedMicroInsn("dar[ry] &= ~0xffff");
+		setclr16("sr", FL_Z, FL_N | FL_V | FL_C);
 		microprefetch(true, null); // prefetch ir and resume execution
 
 		addState("op_clrl_ds");
 		decode_dy();
 		addFormattedMicroInsn("dar[ry] = 0");
+		setclr16("sr", FL_Z, FL_N | FL_V | FL_C);
 		microprefetch(true, null); // prefetch ir and resume execution
 
 		addState("op_clrb_ea");
 		addFormattedMicroInsn("dt = 0");
+		setclr16("sr", FL_Z, FL_N | FL_V | FL_C);
 		microprefetch(true, "8"); // prefetch ir and resume execution
 
 		addState("op_clrw_ea");
 		addFormattedMicroInsn("dt = 0");
+		setclr16("sr", FL_Z, FL_N | FL_V | FL_C);
 		microprefetch(true, "16"); // prefetch ir and resume execution
 
 		addState("op_clrl_ea");
 		addFormattedMicroInsn("dt = 0");
+		setclr16("sr", FL_Z, FL_N | FL_V | FL_C);
 		microprefetch(true, "32"); // prefetch ir and resume execution
 
 		addState("op_lea_ea_ad");

miggy-emu/src/main/java/miggy/cpupoet/Core.java

@@ -3876,28 +3876,34 @@ public abstract class Core extends CoreALU {
           case 237: /* op_clrb_ds */
           ry = ir & 0x0007;
           dar[ry] &= ~0xff;
+          sr = (sr & ~0x000b) | 0x0004;
           mpc = resume_prefetch;
           continue;
           case 238: /* op_clrw_ds */
           ry = ir & 0x0007;
           dar[ry] &= ~0xffff;
+          sr = (sr & ~0x000b) | 0x0004;
           mpc = resume_prefetch;
           continue;
           case 239: /* op_clrl_ds */
           ry = ir & 0x0007;
           dar[ry] = 0;
+          sr = (sr & ~0x000b) | 0x0004;
           mpc = resume_prefetch;
           continue;
           case 240: /* op_clrb_ea */
           dt = 0;
+          sr = (sr & ~0x000b) | 0x0004;
           mpc = ea_resume_write8;
           continue;
           case 241: /* op_clrw_ea */
           dt = 0;
+          sr = (sr & ~0x000b) | 0x0004;
           mpc = ea_resume_write16;
           continue;
           case 242: /* op_clrl_ea */
           dt = 0;
+          sr = (sr & ~0x000b) | 0x0004;
           mpc = ea_resume_write32;
           continue;
           case 243: /* op_lea_ea_ad */

miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java

@@ -110,9 +110,9 @@ public class InstructionTests extends TestCase {
 			test.executeBinTest("TST.b");
 			test.executeBinTest("TST.w");
 			test.executeBinTest("TST.l");
-//			test.executeBinTest("CLR.b");
-//			test.executeBinTest("CLR.w");
-//			test.executeBinTest("CLR.l");
+			test.executeBinTest("CLR.b");
+			test.executeBinTest("CLR.w");
+			test.executeBinTest("CLR.l");
 			test.executeBinTest("TRAP");
 			test.executeBinTest("TRAPV");
 		}