CPU Commit (WIP)

miggy-emu/src/test/java/miggy/cpupoet/CoreTest.java

@@ -0,0 +1,242 @@
+package miggy.cpupoet;
+
+import java.nio.ByteBuffer;
+import java.nio.ByteOrder;
+import java.util.HashSet;
+import java.util.Set;
+
+public class CoreTest extends Core {
+	private final ByteBuffer memory;
+	private final Set<Integer> berrs = new HashSet<Integer>();
+	
+	public static void main(String[] args) {
+		ResetTest test2 = new ResetTest();
+		
+		test2.testReset();
+
+		CoreTest test = new CoreTest();
+		
+		int pc = test.memory.capacity() - 0x800;
+		
+		test.setInitialSSP(0x040000);
+		test.setInitialPC(pc);
+		
+		test.write16(pc, 0x4848);
+		test.write16(pc + 2, 0x0200);
+		test.write16(pc + 4, 0x1234);
+		test.write16(pc + 6, 0x4849);
+		test.write32(4 << 2, 0x090000);
+		
+		//test.setclrSSWI(SSWI_XTRP | SSWI_XBRK, 0);
+		
+		test.execute(Integer.MAX_VALUE);
+		test.execute(Integer.MAX_VALUE);
+		test.execute(Integer.MAX_VALUE);
+	}
+
+	public CoreTest() {
+		/* allocate 512 MiB */
+		this.memory = ByteBuffer.allocate(512 * 1024);
+		
+		memory.order(ByteOrder.BIG_ENDIAN);
+	}
+	
+	public void setInitialSSP(int ssp) {
+		write32(0, ssp);
+	}
+	
+	public void setInitialPC(int ssp) {
+		write32(4, ssp);
+	}
+
+	public Set<Integer> getBErrs() {
+		return berrs;
+	}
+
+	@Override
+	public int fetch16(int aob) {
+		return read16(aob);
+	}
+
+	@Override
+	public int fetch32(int aob) {
+		return read32(aob);
+	}
+	
+	protected int check8(int aob) {
+		if (((aob & 0x7fffffff) + 1 >= memory.capacity()) || berrs.contains(aob)) {
+			setclrSSW(SSW_BR, 0);
+
+			return -1;
+		}
+
+		return aob;
+	}
+	
+	protected int check16(int aob) {
+		if ((aob &= 0x7fffffff) + 2 >= memory.capacity() || berrs.contains(aob)) {
+			setclrSSW(SSW_BR, 0);
+
+			return -1;
+		}
+
+		return aob;
+	}
+	
+	protected int check32(int aob) {
+		if ((aob &= 0x7fffffff) + 4 >= memory.capacity() || berrs.contains(aob)) {
+			setclrSSW(SSW_BR, 0);
+
+			return -1;
+		}
+
+		return aob;
+	}
+
+	@Override
+	public byte read8(int aob) {
+		aob = check8(aob);
+		
+		return aob < 0 ? 0 : memory.get(aob);
+	}
+
+	@Override
+	public short read16(int aob) {
+		aob = check16(aob);
+		
+		return aob < 0 ? 0 : memory.getShort(aob);
+	}
+
+	@Override
+	public int read32(int aob) {
+		aob = check32(aob);
+		
+		return aob < 0 ? 0 : memory.getInt(aob);
+	}
+
+	@Override
+	public void write8(int aob, int dob) {
+		aob = check8(aob);
+		
+		if (aob >= 0) {
+			memory.put(aob, (byte) dob);
+		}
+	}
+
+	@Override
+	public void write16(int aob, int dob) {
+		aob = check16(aob);
+		
+		if (aob >= 0) {
+			memory.putShort(aob, (short) dob);
+		}
+	}
+
+	@Override
+	public void write32(int aob, int dob) {
+		aob = check32(aob);
+		
+		if (aob >= 0) {
+			memory.putInt(aob, dob);
+		}
+	}
+
+	@Override
+	public int handle_interrupt(int level) {
+		return IRQ_AVEC;
+	}
+
+	@Override
+	public int handle_bkpt(int pc, int data) {
+		return BKPT_RPIR | BKPT_EXIT | 0x4e71;
+	}
+
+	public int getPC() {
+		return pc;
+	}
+
+	public void setPC(int pc) {
+		this.pc = pc;
+	}
+
+	public int getScan() {
+		return scan;
+	}
+
+	public void setScan(int scan) {
+		this.scan = scan;
+	}
+
+	public int getAluB() {
+		return alub;
+	}
+
+	public void setAluB(int alub) {
+		this.alub = alub;
+	}
+
+	public int getIRB() {
+		return irb;
+	}
+
+	public void setIRB(int irb) {
+		this.irb = irb;
+	}
+
+	public int getIR() {
+		return ir;
+	}
+
+	public void setIR(int ir) {
+		this.ir = ir;
+	}
+
+	public int getMPC() {
+		return mpc;
+	}
+
+	public void setMPC(int mpc) {
+		this.mpc = mpc;
+	}
+
+	public int getCIP() {
+		return cip;
+	}
+
+	public void setCIP(int cip) {
+		this.cip = cip;
+	}
+
+	public int getAU() {
+		return au;
+	}
+
+	public void setAU(int au) {
+		this.au = au;
+	}
+
+	public int getAT() {
+		return at;
+	}
+
+	public void setAT(int at) {
+		this.at = at;
+	}
+
+	public int getDT() {
+		return dt;
+	}
+
+	public void setDT(int dt) {
+		this.dt = dt;
+	}
+
+	public int getSlice() {
+		return slice;
+	}
+
+	public void setSlice(int slice) {
+		this.slice = slice;
+	}
+
+}

miggy-emu/src/test/java/miggy/cpupoet/ResetTest.java

@@ -0,0 +1,57 @@
+package miggy.cpupoet;
+
+import junit.framework.TestCase;
+
+public class ResetTest extends TestCase {
+	public void testReset() {
+		CoreTest core = new CoreTest();
+		
+		core.setInitialSSP(0x4000);
+		core.setInitialPC(0x8000);
+
+		core.write16(0x8000, 0x4849);
+		
+		core.getBErrs().add(0);
+		core.getBErrs().add(4);
+		core.getBErrs().add(0x8000);
+		
+		core.execute(50);
+		
+		assertTrue(core.getISP() != 0x4000); // isp did not fetch because of bus err
+		assertTrue(core.getPC() != 0x8000);
+		assertEquals(CoreALU.SSWI_DERR, core.getSSWI() & CoreALU.SSWI_DERR);
+
+		core.getBErrs().remove(0);
+		core.execute(50);
+
+		assertTrue(core.getISP() != 0x4000); // still not fetched because CPU is stuck on dbrr
+		assertTrue(core.getPC() != 0x8000);
+		assertEquals(CoreALU.SSWI_DERR, core.getSSWI() & CoreALU.SSWI_DERR);
+
+		core.pulse_reset(); // now pulse reset signal		
+		core.execute(50);
+		
+		assertTrue(core.getISP() == 0x4000); // isp fetched
+		assertTrue(core.getPC() != 0x8000); // but not PC
+		assertEquals(CoreALU.SSWI_DERR, core.getSSWI() & CoreALU.SSWI_DERR);
+		core.pulse_reset(); // pulse reset signal again
+		
+		core.getBErrs().remove(4); // unlock pc
+		core.execute(50);
+
+		// now both fetched, but still stuck to dbrr because prefetch of irb failed
+		assertTrue(core.getISP() == 0x4000);
+		assertTrue(core.getPC() == 0x8000);
+		assertEquals(CoreALU.SSWI_DERR, core.getSSWI() & CoreALU.SSWI_DERR);
+		
+		core.getBErrs().remove(0x8000);
+		core.pulse_reset();
+		core.execute(50);
+
+		// we did exit because of breackpoint
+		assertTrue(core.getISP() == 0x4000);
+		assertTrue(core.getCIP() == 0x8000);
+		assertTrue(core.getPC() == 0x8002);
+		assertEquals(0, core.getSSWI() & CoreALU.SSWI_DERR);
+	}
+}