diff --git a/.gitignore b/.gitignore index b24d71e..71dc97e 100644 --- a/.gitignore +++ b/.gitignore @@ -1,50 +1,18 @@ -# These are some examples of commonly ignored file patterns. -# You should customize this list as applicable to your project. -# Learn more about .gitignore: -# https://www.atlassian.com/git/tutorials/saving-changes/gitignore - -# Node artifact files -node_modules/ -dist/ - # Compiled Java class files *.class -# Compiled Python bytecode -*.py[cod] - -# Log files -*.log - -# Package files -*.jar - # Maven target/ dist/ -# JetBrains IDE -.idea/ - -# Unit test reports -TEST*.xml - # Generated by MacOS .DS_Store # Generated by Windows Thumbs.db -# Applications -*.app -*.exe -*.war - -# Large media files -*.mp4 -*.tiff -*.avi -*.flv -*.mov -*.wmv +.classpath +.settings +.project +/target/ diff --git a/miggy-emu/Changes.md b/miggy-emu/Changes.md new file mode 100644 index 0000000..2b2d1b6 --- /dev/null +++ b/miggy-emu/Changes.md @@ -0,0 +1,14 @@ +**This is a 68010 emulator** + +This implementation focus on being binary compatible with code written by the 68010, adding additional features on unused bits. Care has been taken about to have same behaviour when not using/enabling additional features. + +*The following changes are applied* + +- flow trace mode is available (bit 14 in SR) +- interrupt/master supervisor is available (bit 12 in SR) +- 68020 effective addressing modes bits are available in the extension word. +- 68020 additional instructions are available. +- bra/bcc/bsr can use 32 bits displacement +- exception stack frame $2000 can be enabled using a specific bit in SSWI +- 32 bits access can be recovered using specific bits in SSW (will use 16 bits by default) + diff --git a/miggy-emu/pom.xml b/miggy-emu/pom.xml new file mode 100644 index 0000000..11c1bfb --- /dev/null +++ b/miggy-emu/pom.xml @@ -0,0 +1,19 @@ + + 4.0.0 + + miggy + miggy-root + 0.0.1-SNAPSHOT + + miggy-emu + miggy-emu + + + com.squareup + javapoet + 1.13.0 + + + \ No newline at end of file diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java new file mode 100644 index 0000000..b4f4d66 --- /dev/null +++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java @@ -0,0 +1,3912 @@ +package miggy.cpu.genpoet; + +import static javax.lang.model.element.Modifier.ABSTRACT; +import static javax.lang.model.element.Modifier.FINAL; +import static javax.lang.model.element.Modifier.PRIVATE; +import static javax.lang.model.element.Modifier.PROTECTED; +import static javax.lang.model.element.Modifier.PUBLIC; +import static javax.lang.model.element.Modifier.STATIC; +import static miggy.cpupoet.CoreALU.EAX_BS; +import static miggy.cpupoet.CoreALU.EAX_EXT; +import static miggy.cpupoet.CoreALU.EAX_IS; +import static miggy.cpupoet.CoreALU.EAX_ISL; +import static miggy.cpupoet.CoreALU.EAX_SCL; +import static miggy.cpupoet.CoreALU.EAX_SIZ; +import static miggy.cpupoet.CoreALU.FL_C; +import static miggy.cpupoet.CoreALU.FL_N; +import static miggy.cpupoet.CoreALU.FL_V; +import static miggy.cpupoet.CoreALU.FL_X; +import static miggy.cpupoet.CoreALU.FL_Z; +import static miggy.cpupoet.CoreALU.SR_M; +import static miggy.cpupoet.CoreALU.SR_S; +import static miggy.cpupoet.CoreALU.SR_T0; +import static miggy.cpupoet.CoreALU.SR_T1; +import static miggy.cpupoet.CoreALU.SSWI_AVEC; +import static miggy.cpupoet.CoreALU.SSWI_DERR; +import static miggy.cpupoet.CoreALU.SSWI_EAFH; +import static miggy.cpupoet.CoreALU.SSWI_FMT2; +import static miggy.cpupoet.CoreALU.SSW_32; +import static miggy.cpupoet.CoreALU.SSW_BR; +import static miggy.cpupoet.CoreALU.SSW_BY; +import static miggy.cpupoet.CoreALU.SSW_D; +import static miggy.cpupoet.CoreALU.SSW_DF; +import static miggy.cpupoet.CoreALU.SSW_HB; +import static miggy.cpupoet.CoreALU.SSW_IF; +import static miggy.cpupoet.CoreALU.SSW_P; +import static miggy.cpupoet.CoreALU.SSW_RM; +import static miggy.cpupoet.CoreALU.SSW_RR; +import static miggy.cpupoet.CoreALU.SSW_RW; +import static miggy.cpupoet.CoreALU.SSW_S; +import static miggy.cpupoet.CoreALU.SSW_WD; + +import java.io.IOException; +import java.util.ArrayList; +import java.util.List; +import java.util.Set; +import java.util.TreeMap; +import java.util.TreeSet; + +import com.squareup.javapoet.FieldSpec; +import com.squareup.javapoet.JavaFile; +import com.squareup.javapoet.MethodSpec; +import com.squareup.javapoet.TypeSpec; + +import miggy.cpu.genpoet.CorePLAGenerator.MacroEntry; +import miggy.cpu.genpoet.CorePLAGenerator.OPEntry; +import miggy.cpupoet.CoreALU; + +public class CoreGenerator { + List blocks = new ArrayList<>(); + + private static final int SSW_AC = 1 << 18; // transfer not critical (but address error is critical) + private static final int SSW_AL = 1 << 17; // transfer aligned (generation time) + private static final int SSW_CR = 1 << 16; // transfer critical (generation time) + + private static final FieldInt16Constant SR_I = new FieldInt16Constant("SR_I", CoreALU.SR_I); + private static final FieldInt16Constant SSW_RS = new FieldInt16Constant("SSW_RS", CoreALU.SSW_RS); + private static final FieldInt16Constant SSW_HL = new FieldInt16Constant("SSW_HL", CoreALU.SSW_HL); + private static final FieldInt16Constant SSWI_PSLC = new FieldInt16Constant("SSWI_PSLC", CoreALU.SSWI_PSLC); + + public static final int GEN_BYTE = 0x0001; + public static final int GEN_WORD = 0x0002; + public static final int GEN_LONG = 0x0004; + public static final int GEN_DDDS = 0x0008; + public static final int GEN_ASDD = 0x0010; + public static final int GEN_EADD = 0x0020; + public static final int GEN_IMM3 = 0x0040; + public static final int GEN_NUPT = 0x0080; + + /** + * exit from emulation loop as soon as possible (may take trap depending on + * RPIR) + */ + private static final FieldInt32Constant BKPT_EXIT = new FieldInt32Constant("BKPT_EXIT", 1 << 16); + /** + * replace IR by lower 16 bits handler return code and continue execution + */ + private static final FieldInt32Constant BKPT_RPIR = new FieldInt32Constant("BKPT_RPIR", 1 << 17); + + /** + * exit from emulation loop as soon as possible (may take trap if SKIP not set) + */ + private static final FieldInt32Constant LINEA_EXIT = new FieldInt32Constant("LINEA_EXIT", 1 << 16); + /** + * skip linea opcode (do not take trap), lower 16 bits are sign extended and + * added to PC + */ + private static final FieldInt32Constant LINEA_SKIP = new FieldInt32Constant("LINEA_SKIP", 1 << 17); + + /** + * exit from emulation loop as soon as possible (may take trap if SKIP not set) + */ + private static final FieldInt32Constant ILL_EXIT = new FieldInt32Constant("ILL_EXIT", 1 << 16); + /** + * skip illegal opcode (do not take trap), lower 16 bits are sign extended and + * added to PC + */ + private static final FieldInt32Constant ILL_SKIP = new FieldInt32Constant("ILL_SKIP", 1 << 17); + + /** + * exit from emulation loop as soon as possible (may take trap if IGNR not set) + */ + private static final FieldInt16Constant TRACE_EXIT = new FieldInt16Constant("TRACE_EXIT", 1 << 15); + /** + * ignore trace trap + */ + private static final FieldInt16Constant TRACE_IGNR = new FieldInt16Constant("TRACE_IGNR", 1 << 14); + + /** + * exit from emulation loop as soon as possible (make take trap if IGNR not set) + */ + private static final FieldInt16Constant IRQ_EXIT = new FieldInt16Constant("IRQ_EXIT", 1 << 15); + /** + * unable to determine vector + */ + private static final FieldInt16Constant IRQ_IERR = new FieldInt16Constant("IRQ_IERR", 1 << 14); + /** + * use spurious if IERR, AVEC if globally set, or provided vector in other cases + */ + private static final FieldInt16Constant IRQ_DFLT = new FieldInt16Constant("IRQ_DFLT", 0 << 12); + /** + * force auto-vector interrupt (regardless of global setting) + */ + private static final FieldInt16Constant IRQ_AVEC = new FieldInt16Constant("IRQ_AVEC", 1 << 12); + /** + * force spurious interrupt vector + */ + private static final FieldInt16Constant IRQ_SPUR = new FieldInt16Constant("IRQ_SPUR", 2 << 12); + /** + * ignore interrupt + */ + private static final FieldInt16Constant IRQ_IGNR = new FieldInt16Constant("IRQ_IGNR", 3 << 12); + + private static final FieldSpec pc = FieldSpec.builder(int.class, "pc", PROTECTED).build(); + private static final FieldSpec alub = FieldSpec.builder(int.class, "alub", PROTECTED).build(); + private static final FieldSpec irb = FieldSpec.builder(int.class, "irb", PROTECTED).build(); + private static final FieldSpec ir = FieldSpec.builder(int.class, "ir", PROTECTED).build(); + private static final FieldSpec mpc = FieldSpec.builder(int.class, "mpc", PROTECTED).initializer("$L", "reset") + .build(); + private static final FieldSpec cip = FieldSpec.builder(int.class, "cip", PROTECTED).build(); + private static final FieldSpec au = FieldSpec.builder(int.class, "au", PROTECTED).build(); + private static final FieldSpec at = FieldSpec.builder(int.class, "at", PROTECTED).build(); + private static final FieldSpec dt = FieldSpec.builder(int.class, "dt", PROTECTED).build(); + + private static final FieldSpec slice = FieldSpec.builder(int.class, "slice", PROTECTED).initializer("$L", "0") + .build(); + private static final FieldSpec scan = FieldSpec.builder(int.class, "scan", PROTECTED).build(); + + private static final FieldSpec sswi = FieldSpec.builder(int.class, "sswi", PROTECTED).build(); + + public static void main(String[] args) throws IOException { + JavaFile javaFile = JavaFile.builder("miggy.cpupoet", coreType()).build(); + + javaFile.writeTo(System.out); + } + + public CoreGenerator() { + reset_microcode(); + berr_microcode(); + trap2000_microcode(); + trap0000_microcode(); + interrupt_microcode(); + writeea_microcode(); + imm16_microcode(); + imm32_microcode(); + ea_aid_microcode(); + ea_ais_microcode(); + ea_aipd_microcode(); + ea_aips_microcode(); + ea_paid_microcode(); + ea_pais_microcode(); + ea_dad_microcode(); + ea_das_microcode(); + ea_daid_microcode(); + ea_dais_microcode(); + ea_dpc_microcode(); + ea_dpci_microcode(); + ea_adr16d_microcode(); + ea_adr16s_microcode(); + ea_adr32d_microcode(); + ea_adr32s_microcode(); + ea_imm_microcode(); + op_movep_microcode(); + misc_microcode(); + op_movem_microcode(); + op_bcc_microcode(); + op_bkpt_microcode(); + op_illegal_microcode(); + op_jmp_microcode(); + op_linea_microcode(); + op_linef_microcode(); + op_nop_microcode(); + op_rte_microcode(); + op_rtr_microcode(); + op_rts_microcode(); + op_reset_microcode(); + op_trapv_microcode(); + } + + private void reset_microcode() { + addState("reset"); + consume(40, 6, 0); + // clear trace, disable interrupts and set supervisor mode + setclr16("sr", SR_S | SR_I.value, SR_T1 | SR_T0 | SR_M); + addFormattedMicroInsn("sp = spi(sr)"); // update stack pointer index + setclr16("ssw", 0, SSW_RS.value | SSW_HL.value); // clear pending reset and halt + // clear pending trace, ea fetch and double bus fault + setclr16("sswi", 0, SR_T1 | SR_T0 | SSWI_EAFH | SSWI_DERR); + setclr32("vbr", 0, ~0); // clear vbr register + fetch32("dar[sp]", SSW_CR | SSW_S, null, 0x00000000); // critical supervisor program fetch of ssp + fetch32("pc", SSW_CR | SSW_S, null, 0x00000004); // critical supervisor program fetch of pc + addFormattedMicroInsn("mpc = resume_berr"); // resume with critical pc fetch + addFormattedMicroInsn("continue"); + + /* double bus fault entry point */ + addState("dbrr"); + setclr("ssw", SSW_HL.value, 0); // halt cpu + setclr("sswi", SSWI_DERR, 0); // and set double bus fault + addFormattedMicroInsn("nmpc = halt"); // never exit ! + + /* halt entry point */ + addState("halt"); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) != 0)", SSW_RS.value); + // handle pending reset + addFormattedMicroInsn("mpc = reset"); + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((ssw & 0x%04x) != 0)", SSW_HL.value); + // handle halt + addFormattedMicroInsn("elapsed += Math.max(0, slice - elapsed)"); + addEndControlFlow(); + addFormattedMicroInsn("break"); + } + + private void berr_microcode() { + // entry point for non critical 32 bits fetch bus events + addState("bevtf32"); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) != 0)", SSW_BR); + setclr16("ssw", 0, SSW_WD); + addFormattedMicroInsn("mpc = berr"); // handle bus error + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((ssw & 0x%04x) == 0)", SSW_WD); + addFormattedMicroInsn("dib <<= 16"); // shift dib to keep dibh + // indicate bus error handler that dibh needs to be saved + setclr16("ssw", SSW_WD, SSW_32); + addFormattedMicroInsn("dib |= fetch16(aob += 2) & 0xffff"); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0)", SSW_BR | SSW_RS.value); + addFormattedMicroInsn("mpc = nmpc"); // dib is dirty, jump to next pc (without exiting) + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addEndControlFlow(); + addFormattedMicroInsn("mpc = bevt"); // handle bus error + addFormattedMicroInsn("continue"); + + // entry point for non critical 32 bits read bus events + addState("bevtr32"); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) != 0)", SSW_BR); + setclr16("ssw", 0, SSW_WD); + addFormattedMicroInsn("mpc = berr"); // handle bus error + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((ssw & 0x%04x) == 0)", SSW_WD); + addFormattedMicroInsn("dib <<= 16"); // shift dib to keep dibh + // indicate bus error handler that dibh needs to be saved + setclr16("ssw", SSW_WD, SSW_32); + addFormattedMicroInsn("dib |= read16(aob += 2) & 0xffff"); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0)", SSW_BR | SSW_RS.value); + addFormattedMicroInsn("mpc = nmpc"); // dib is dirty, jump to next pc (without exiting) + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addEndControlFlow(); + + // entry point for non critical 32 bits write bus events + addState("bevtw32"); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) != 0)", SSW_BR); + setclr16("ssw", 0, SSW_WD); + addFormattedMicroInsn("mpc = berr"); // handle bus error + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((ssw & 0x%04x) == 0)", SSW_WD); + setclr16("ssw", 0, SSW_32); + addFormattedMicroInsn("write16(aob += 2, dob)"); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0)", SSW_BR | SSW_RS.value); + addClearSSW(); + addFormattedMicroInsn("break"); // write succeeded, can exit if needed + addEndControlFlow(); + addEndControlFlow(); + addFormattedMicroInsn("mpc = bevt"); // handle bus error + addFormattedMicroInsn("continue"); + + /* entry point for non critical 8/16 bits bus events */ + addState("bevt"); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0)", SSW_BR); + addFormattedMicroInsn("mpc = halt"); // reset will be handled in halt microcode + addFormattedMicroInsn("continue"); + addEndControlFlow(); + + /* bus error entry point */ + addState("berr"); + consume(126, 4, 26); + + /* vdt1 contains sswi pending bits, tvn and ssw (with RR flipped) */ + addFormattedMicroInsn("vdt1 = ((sswi & 0x%04x) << 16) | ((tvn & 0x3fc) << 14) | ((ssw ^ ~0x%04x) & 0x%04x)", + SR_T1 | SR_T0 | SSWI_EAFH, SSW_RR, (~SSW_BR) & 0xffff); + + settvn(2); // set tvn AFTER previous tvn has been saved (in vdt1) + addFormattedMicroInsn("mpc = trap8000"); + addFormattedMicroInsn("continue"); + + /* address error entry point */ + addState("aerr"); + consume(126, 4, 26); + + /* vdt1 contains sswi pending bits, tvn and ssw (with RR flipped) */ + addFormattedMicroInsn("vdt1 = ((sswi & 0x%04x) << 16) | ((tvn & 0x3fc) << 14) | ((ssw ^ ~0x%04x) & 0x%04x)", + SR_T1 | SR_T0 | SSWI_EAFH, SSW_RR, (~SSW_BR) & 0xffff); + + settvn(3); // set tvn AFTER previous tvn has been saved (in vdt1) + + addState("trap8000"); + + addBeginFormattedControlFlow("if ((vdt1 & 0x%04x) == 0)", SSW_BY); + /* + * for byte access, ensure aob is even and set HB according to requested + * address. Also adjust dob according to HB + */ + addBeginFormattedControlFlow("if ((aob & 0x000000001) != 0)"); + addFormattedMicroInsn("aob -= 1"); + setclr16("vdt1", 0, SSW_HB); + addNextFormattedControlFlow("else"); + setclr16("vdt1", SSW_HB, 0); + addBeginFormattedControlFlow("if ((vdt1 & 0x%04x) == 0)", SSW_RW); + addFormattedMicroInsn("dob <<= 8"); + addEndControlFlow(); + addEndControlFlow(); + addEndControlFlow(); + + addFormattedMicroInsn("vat1 = at"); + addFormattedMicroInsn("vat2 = au"); + addFormattedMicroInsn("vat3 = aob"); + addFormattedMicroInsn("vdt2 = dob"); + addFormattedMicroInsn("vdt3 = dib"); // not available in original 68010, added to save dib high bits + addFormattedMicroInsn("sp = spi(sr | 0x%04x)", SR_S); + addFormattedMicroInsn("au = dar[sp] - %d", 29 << 1); // allocate 29 words on supervisor stack + addFormattedMicroInsn("dar[sp] = au"); // update supervisor stack pointer + + write16(SSW_CR | SSW_S | SSW_D, "au", "sr", 0 << 1, false); // write sr to stack frame + write32(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "pc", 1 << 1, false); // write pc to stack frame + write32(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "vat3", 5 << 1, false); // write saved aob to stack frame + + addBeginFormattedControlFlow("if ((vdt1 & 0x%04x) == 0)", SSW_RW); + addBeginFormattedControlFlow("if ((vdt1 & 0x%04x) == 0)", SSW_32); + write32(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "vdt2", 8 << 1, false); // write dob to stack frame (32 bits) + addNextFormattedControlFlow("else"); + write16(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "vdt2", 8 << 1, false); // write dob to stack frame (16 bits + // only) + addEndControlFlow(); + addNextFormattedControlFlow("else if ((vdt1 & 0x%04x) == 0x%04x)", SSW_32 | SSW_WD, SSW_WD); + write16(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "vdt3 >> 16", 9 << 1, false); + addEndControlFlow(); + + write16(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "irb", 12 << 1, false); // write prefetch to stack frame + write16(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "nmpc", 13 << 1, false); // write next mpc to stack frame + write16(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "scan", 14 << 1, false); // write scan value + write32(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "alub", 15 << 1, false); // write alub to stack frame + write32(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "vat1", 17 << 1, false); // write saved at to stack frame + write32(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "vat2", 19 << 1, false); // write saved au to stack frame + write16(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "vdt1 >> 16", 23 << 1, false); // write sswi and tvn to stack + // frame + write16(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "ir", 24 << 1, false); // write ir to stack frame + write32(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "dt", 25 << 1, false); // write dt to stack frame + write32(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "cip", 27 << 1, false); // write previous pc value + + addState("resume_trap8000"); + + writevob(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 8, 3 << 1); // always update vob + write16(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "vdt1", 4 << 1, false); // always update ssw + + setclr16("sr", SR_S, SR_T1 | SR_T0); // clear trace and set supervisor mode + setclr("sswi", 0, SR_T1 | SR_T0 | SSWI_EAFH); // clear pending trace and ea fetch + + read32("pc", SSW_CR | SSW_S, "tvn + vbr", 0); // fetch pc from tvn + + /* + * specific entry for reset and bus error frames where prefetch error is fatal + */ + addState("resume_berr"); + addFormattedMicroInsn("scan = 0"); // clear scan value + addFormattedMicroInsn("tvn = 0"); // clear tvn + addFormattedMicroInsn("nmpc = resume"); + prefetchir(SSW_CR | SSW_S, true); + addClearSSW(); + addFormattedMicroInsn("break"); + } + + private void trap2000_microcode() { + addState("trap2000"); + /* consume is set by caller */ + + addFormattedMicroInsn("sp = spi(sr | 0x%04x)", SR_S); // select supervisor stack + addFormattedMicroInsn("au = dar[sp] - %d", 6 << 1); // allocate 6 words on supervisor stack + addFormattedMicroInsn("dar[sp] = au"); // update supervisor stack pointer + + write16(SSW_CR | SSW_S | SSW_D, "au", "sr", 0 << 1, false); // write sr to stack frame + write32(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "pc + scan", 1 << 1, false); // write next pc to stack frame + writevob(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 2, 3 << 1); // write frame format and vector offset + write32(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "cip", 4 << 1, false); // write previous pc to stack frame + + addFormattedMicroInsn("mpc = enter_trap0000"); // set next entry + addFormattedMicroInsn("continue"); + } + + private void trap0000_microcode() { + addState("trapill"); + addFormattedMicroInsn("pc = cip"); // make pc point to current instruction + addFormattedMicroInsn("scan = 0"); // reset scan value + + addState("trap0000"); + /* consume is set by caller */ + + addFormattedMicroInsn("sp = spi(sr | 0x%04x)", SR_S); // select supervisor stack + addFormattedMicroInsn("au = dar[sp] - %d", 4 << 1); // allocate 4 words on supervisor stack + addFormattedMicroInsn("dar[sp] = au"); // update supervisor stack pointer + + write16(SSW_CR | SSW_S | SSW_D, "au", "sr", 0 << 1, false); // write sr to stack frame + write32(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "pc + scan", 1 << 1, false); // write pc to stack frame + writevob(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 0, 3 << 1); // write frame format and vector offset + + addState("enter_trap0000"); + setclr16("sr", SR_S, SR_T1 | SR_T0); // clear trace and set supervisor mode + setclr("sswi", 0, SR_T1 | SR_T0 | SSWI_EAFH); // clear pending trace and ea fetch + + read32("pc", SSW_AC | SSW_S, "tvn + vbr", 0); // fetch pc from tvn + + addFormattedMicroInsn("mpc = execute_trap"); // set next entry + addFormattedMicroInsn("continue"); + } + + private void interrupt_microcode() { + addState("uninitialized"); + settvn(15); + read32("pc", SSW_AC | SSW_S, "tvn + vbr", 0); // fetch pc from new tvn + addFormattedMicroInsn("mpc = enter_irq"); + addFormattedMicroInsn("continue"); + + addState("interrupt"); + consume(46, 5, 4); + addFormattedMicroInsn("hdlr = handle_interrupt((sswi & 0x%04x) >> 8)", SR_I.value); + addFormattedMicroInsn("exit |= (hdlr & 0x%04x) != 0", IRQ_EXIT.value); + addBeginFormattedControlFlow("if ((hdlr & 0x%04x) != 0x%04x)", IRQ_IGNR.value, IRQ_IGNR.value); + setclr16("sswi", 0, SR_I.value); + addFormattedMicroInsn("sp = spi(sr)"); // update stack pointer index + addFormattedMicroInsn("mpc = resume"); // set next entry + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((hdlr & 0x%04x) == 0x%04x)", IRQ_IGNR.value, IRQ_SPUR.value); + settvn(24); + addNextFormattedControlFlow("else if ((hdlr & 0x%04x) == 0x%04x)", IRQ_IGNR.value, IRQ_AVEC.value); + addFormattedMicroInsn("tvn = %d + (sswi & 0x%04x) >> 6", 24 << 2, SR_I.value); + addNextFormattedControlFlow("else if ((hdlr & 0x%04x) != 0)", IRQ_IERR.value); + settvn(24); + addNextFormattedControlFlow("else if ((sswi & 0x%04x) != 0)", SSWI_AVEC); + addFormattedMicroInsn("tvn = %d + (sswi & 0x%04x) >> 6", 24 << 2, SR_I.value); + addNextFormattedControlFlow("else"); + addFormattedMicroInsn("tvn = (hdlr & 0xff) << 2"); + addEndControlFlow(); + + addFormattedMicroInsn("sp = spi(sr | 0x%04x)", SR_S); // select msp (or isp) + addFormattedMicroInsn("au = dar[sp] - %d", 4 << 1); // allocate 4 words on supervisor stack + addFormattedMicroInsn("dar[sp] = au"); // update supervisor stack pointer + write16(SSW_CR | SSW_S | SSW_D, "au", "sr", 0 << 1, false); // write sr to stack frame + write32(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", "pc", 1 << 1, false); // write pc to stack frame + + setclr16("sr", SR_S, 0); // set supervisor mode + + /* check for 'master' ssp mode */ + addBeginFormattedControlFlow("if ((sr & 0x%04x) != 0)", SR_M); + addFormattedMicroInsn("sp = spi(sr & ~0x%04x)", SR_M); // select isp + addFormattedMicroInsn("at = dar[sp] - %d", 4 << 1); // allocate 4 words on interrupt stack + addFormattedMicroInsn("dar[sp] = at"); // update interrupt stack pointer + write16(SSW_CR | SSW_S | SSW_D, "at", "sr", 0 << 1, false); // write sr to interrupt stack frame + write32(SSW_CR | SSW_S | SSW_D | SSW_AL, "at", "pc", 1 << 1, false); // write pc to interrupt stack frame + addEndControlFlow(); + + // clear trace, update interrupt level and set supervisor mode (in sr) + addFormattedMicroInsn("sr = (sswi & 0x%04x) | (sr & ~0x%04x)", SR_I.value, SR_T1 | SR_T0 | SR_M | SR_I.value); + // clear pending trace, ea fetch and pending interrupt + setclr16("sswi", 0, SR_T1 | SR_T0 | SSWI_EAFH | SR_I.value); + + read32("pc", SSW_AC | SSW_S, "tvn + vbr", 0); // fetch pc from saved tvn + + addBeginFormattedControlFlow("if (pc == 0x00000000)"); + addFormattedMicroInsn("mpc = uninitialized"); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + + addState("enter_irq"); + // write frame format and vector offset (on master stack) + writevob(SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 0, 3 << 1); + + addBeginFormattedControlFlow("if ((sr & 0x%04x) != 0)", SR_M); + // write frame format and vector offset (on interrupt stack) + writevob(SSW_CR | SSW_S | SSW_D | SSW_AL, "at", 1, 3 << 1); + addFormattedMicroInsn("sr &= ~0x%04x", SR_M); // clear master flag + addEndControlFlow(); + + addState("execute_trap"); + addFormattedMicroInsn("scan = 0"); // clear scan value + addFormattedMicroInsn("tvn = 0"); // clear tvn + addState("resume_prefetch"); + addFormattedMicroInsn("nmpc = resume"); + prefetchir(0, true); + addClearSSW(); + + addState("resume"); + // check for pending halt + addBeginFormattedControlFlow("if ((ssw & 0x%04x) != 0)", SSW_RS.value | SSW_HL.value); + addFormattedMicroInsn("nmpc = resume"); + addFormattedMicroInsn("mpc = halt"); + addFormattedMicroInsn("continue"); + // check for pending trace + addNextFormattedControlFlow("else if ((sswi & 0x%04x) != 0)", SR_T1 | SR_T0); + consume(38, 4, 4); + addFormattedMicroInsn("hdlr = handle_trace(cip)"); + addFormattedMicroInsn("exit |= (hdlr & 0x%04x) != 0", TRACE_EXIT.value); + addBeginFormattedControlFlow("if ((hdlr & 0x%04x) == 0)", TRACE_IGNR.value); + settvn(9); + addFormattedMicroInsn("mpc = (sswi & 0x%04x) != 0 ? trap2000 : trap0000", SSWI_FMT2); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + setclr16("sswi", 0, SR_T1 | SR_T0); + addEndControlFlow(); + + addState("resume_notrace"); + addFormattedMicroInsn("ipend = sswi & 0x%04x", SR_I.value); + // lastly, check for pending interrupt (and nmi) + addBeginFormattedControlFlow("if ((ipend == 0x%04x) || ((sr & 0x%04x) < ipend))", SR_I.value, SR_I.value); + addFormattedMicroInsn("mpc = interrupt"); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addFormattedMicroInsn("cip = pc + scan"); + addFormattedMicroInsn("pc = cip + 2"); + addFormattedMicroInsn("scan = 0"); + addFormattedMicroInsn("ir = irb & 0xffff"); + addFormattedMicroInsn("decoded = MacroPLA.decode(ir)"); + addFormattedMicroInsn("nmpc = decoded.a1"); + addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T1); + addFormattedMicroInsn("break"); + + addState("op_stop"); + check_privileged(); + // update SR register from immediate value + addFormattedMicroInsn("sr = dt & 0x%04x", SR_T1 | SR_T0 | SR_S | SR_M | SR_I.value | FL_C | FL_V | FL_Z | FL_N | FL_X); + // enter stop loop + addFormattedMicroInsn("nmpc = op_stop_loop"); + + addState("op_stop_loop"); + // check for pending reset or halt + addBeginFormattedControlFlow("if ((ssw & 0x%04x) != 0)", SSW_RS.value | SSW_HL.value); + addFormattedMicroInsn("nmpc = op_stop_loop"); + addFormattedMicroInsn("mpc = halt"); + addFormattedMicroInsn("continue"); + // check for pending trace + addNextFormattedControlFlow("else if ((sswi & 0x%04x) != 0)", SR_T1 | SR_T0); + consume(38, 4, 4); + addFormattedMicroInsn("hdlr = handle_trace(cip)"); + addFormattedMicroInsn("exit |= (hdlr & 0x%04x) != 0", TRACE_EXIT.value); + addBeginFormattedControlFlow("if ((hdlr & 0x%04x) == 0)", TRACE_IGNR.value); + settvn(9); + addFormattedMicroInsn("mpc = (sswi & 0x%04x) != 0 ? trap2000 : trap0000", SSWI_FMT2); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + setclr16("sswi", 0, SR_T1 | SR_T0); + addFormattedMicroInsn("mpc = resume_notrace"); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addFormattedMicroInsn("ipend = sswi & 0x%04x", SR_I.value); + // lastly, check for pending interrupt (and nmi) + addBeginFormattedControlFlow("if ((ipend == 0x%04x) || ((sr & 0x%04x) < ipend))", SR_I.value, SR_I.value); + addFormattedMicroInsn("mpc = interrupt"); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + // no trace / reset / halt / interrupt, eat all remaining cycles and exit + addFormattedMicroInsn("elapsed += Math.max(0, slice - elapsed)"); + addFormattedMicroInsn("break"); + + } + + private void writeea_microcode() { + addState("ea_resume_write8"); + prefetchir(0, false); + write8(SSW_D, "at", "dt", 0, false); + addClearSSW(); + addFormattedMicroInsn("mpc = resume"); + addFormattedMicroInsn("continue"); + + addState("ea_resume_write16"); + prefetchir(0, false); + write16(SSW_D, "at", "dt", 0, false); + addClearSSW(); + addFormattedMicroInsn("mpc = resume"); + addFormattedMicroInsn("continue"); + + addState("ea_resume_write32"); + prefetchir(0, false); + write32(SSW_D, "at", "dt", 0, false); + addClearSSW(); + addFormattedMicroInsn("mpc = resume"); + addFormattedMicroInsn("continue"); + } + + private void imm16_microcode() { + addState("op_imm16"); + fetchimm16("dt", 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addClearSSW(); + addFormattedMicroInsn("break"); + } + + private void imm32_microcode() { + addState("op_imm32"); + fetchimm32("dt", 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addClearSSW(); + addFormattedMicroInsn("break"); + } + + private void ea_aid_microcode() { + addState("ea_aid8"); + decode_ax(); + addFormattedMicroInsn("at = dar[rx]"); // save address to temporary register + consume(2, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + + addState("ea_aid16"); + decode_ax(); + addFormattedMicroInsn("at = dar[rx]"); // save address to temporary register + consume(2, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + + addState("ea_aid32"); + decode_ax(); + addFormattedMicroInsn("at = dar[rx]"); // save address to temporary register + consume(2, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + } + + private void ea_ais_microcode() { + addState("ea_ais8_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_ais8"); + decode_ay(); + addFormattedMicroInsn("at = dar[ry]"); // save address to temporary register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(2, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(4, 1, 0); + + addState("ea_read8"); + setclr16("sswi", 0, SSWI_EAFH); + addFormattedMicroInsn("alub = dt"); // save dt to alub + read8("dt", 0, "at"); + addClearSSW(); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + + addState("ea_ais16_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_ais16"); + decode_ay(); + addFormattedMicroInsn("at = dar[ry]"); // save address to temporary register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(2, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(4, 1, 0); + + addState("ea_read16"); + setclr16("sswi", 0, SSWI_EAFH); + addFormattedMicroInsn("alub = dt"); // save dt to alub + read16("dt", 0, "at"); + addClearSSW(); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + + addState("ea_ais32_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_ais32"); + decode_ay(); + addFormattedMicroInsn("at = dar[ry]"); // save address to temporary register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(2, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(8, 2, 0); + + addState("ea_read32"); + setclr16("sswi", 0, SSWI_EAFH); + addFormattedMicroInsn("alub = dt"); // save dt to alub + read32("dt", 0, "at"); + addClearSSW(); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + } + + private void ea_aipd_microcode() { + addState("ea_aipd8_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_aipd8"); + addFormattedMicroInsn("rx = (ir >> 9) & 0x0007"); // retrieve address register index + addBeginFormattedControlFlow("if (rx == 7)"); + addFormattedMicroInsn("at = dar[sp]"); // save address to temporary register + addFormattedMicroInsn("dar[sp] += 2"); // increment address register + addNextFormattedControlFlow("else"); + addFormattedMicroInsn("rx |= 8"); + addFormattedMicroInsn("at = dar[rx]"); // save address to temporary register + addFormattedMicroInsn("dar[rx] += 1"); // increment address register + addEndControlFlow(); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(4, 1, 0); + addFormattedMicroInsn("mpc = ead_read8"); + addFormattedMicroInsn("continue"); + + addState("ea_aipd16_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_aipd16"); + decode_ax(); + addFormattedMicroInsn("at = dar[rx]"); // save address to temporary register + addFormattedMicroInsn("dar[rx] += 2"); // increment address register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(4, 1, 0); + addFormattedMicroInsn("mpc = ead_read16"); + addFormattedMicroInsn("continue"); + + addState("ea_aipd32_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_aipd32"); + decode_ax(); + addFormattedMicroInsn("at = dar[rx]"); // save address to temporary register + addFormattedMicroInsn("dar[rx] += 4"); // increment address register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(4, 1, 0); + addFormattedMicroInsn("mpc = ead_read32"); + addFormattedMicroInsn("continue"); + } + + private void ea_aips_microcode() { + addState("ea_aips8_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_aips8"); + addFormattedMicroInsn("ry = ir & 0x0007"); // retrieve address register index + addBeginFormattedControlFlow("if (ry == 7)"); + addFormattedMicroInsn("at = dar[sp]"); // save address to temporary register + addFormattedMicroInsn("dar[sp] += 2"); // increment address register + addNextFormattedControlFlow("else"); + addFormattedMicroInsn("ry |= 8"); + addFormattedMicroInsn("at = dar[ry]"); // save address to temporary register + addFormattedMicroInsn("dar[ry] += 1"); // increment address register + addEndControlFlow(); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(4, 1, 0); + addFormattedMicroInsn("mpc = ea_read8"); + addFormattedMicroInsn("continue"); + + addState("ea_aips16_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_aips16"); + decode_ay(); + addFormattedMicroInsn("at = dar[ry]"); // save address to temporary register + addFormattedMicroInsn("dar[ry] += 2"); // increment address register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(4, 1, 0); + addFormattedMicroInsn("mpc = ea_read16"); + addFormattedMicroInsn("continue"); + + addState("ea_aips32_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_aips32"); + decode_ay(); + addFormattedMicroInsn("at = dar[ry]"); // save address to temporary register + addFormattedMicroInsn("dar[ry] += 4"); // increment address register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(8, 2, 0); + addFormattedMicroInsn("mpc = ea_read32"); + addFormattedMicroInsn("continue"); + } + + private void ea_paid_microcode() { + addState("ea_paid8_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_paid8"); + addFormattedMicroInsn("rx = (ir >> 9) & 0x0007"); // retrieve address register index + addBeginFormattedControlFlow("if (rx == 7)"); + addFormattedMicroInsn("dar[sp] -= 2"); // decrement address register + addFormattedMicroInsn("at = dar[sp]"); // save address to temporary register + addNextFormattedControlFlow("else"); + addFormattedMicroInsn("rx |= 8"); + addFormattedMicroInsn("dar[rx] -= 1"); // decrement address register + addFormattedMicroInsn("at = dar[rx]"); // save address to temporary register + addEndControlFlow(); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(6, 1, 0); + addState("ead_read8"); + setclr16("sswi", 0, SSWI_EAFH); + addFormattedMicroInsn("alub = dt"); // save dt to alub + read8("dt", 0, "at"); + addClearSSW(); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + + addState("ea_paid16_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_paid16"); + decode_ax(); + addFormattedMicroInsn("dar[rx] -= 2"); // decrement address register + addFormattedMicroInsn("at = dar[rx]"); // save address to temporary register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(6, 1, 0); + addState("ead_read16"); + setclr16("sswi", 0, SSWI_EAFH); + addFormattedMicroInsn("alub = dt"); // save dt to alub + read16("dt", 0, "at"); + addClearSSW(); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + + addState("ea_paid32_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_paid32"); + decode_ax(); + addFormattedMicroInsn("dar[rx] -= 4"); // decrement address register + addFormattedMicroInsn("at = dar[rx]"); // save address to temporary register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(10, 2, 0); + addState("ead_read32"); + setclr16("sswi", 0, SSWI_EAFH); + addFormattedMicroInsn("alub = dt"); // save dt to alub + read32("dt", 0, "at"); + addClearSSW(); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + } + + private void ea_pais_microcode() { + addState("ea_pais8_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_pais8"); + addFormattedMicroInsn("ry = ir & 0x0007"); // retrieve address register index + addBeginFormattedControlFlow("if (ry == 7)"); + addFormattedMicroInsn("dar[sp] -= 2"); // decrement address register + addFormattedMicroInsn("at = dar[sp]"); // save address to temporary register + addNextFormattedControlFlow("else"); + addFormattedMicroInsn("ry |= 8"); + addFormattedMicroInsn("dar[ry] -= 1"); // decrement address register + addFormattedMicroInsn("at = dar[ry]"); // save address to temporary register + addEndControlFlow(); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(6, 1, 0); + addFormattedMicroInsn("mpc = ea_read8"); + addFormattedMicroInsn("continue"); + + addState("ea_pais16_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_pais16"); + decode_ay(); + addFormattedMicroInsn("dar[ry] -= 2"); // decrement address register + addFormattedMicroInsn("at = dar[ry]"); // save address to temporary register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(6, 1, 0); + addFormattedMicroInsn("mpc = ea_read16"); + addFormattedMicroInsn("continue"); + + addState("ea_pais32_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_pais32"); + decode_ay(); + addFormattedMicroInsn("dar[ry] -= 4"); // decrement address register + addFormattedMicroInsn("at = dar[ry]"); // save address to temporary register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(10, 2, 0); + addFormattedMicroInsn("mpc = ea_read32"); + addFormattedMicroInsn("continue"); + } + + private void ea_dad_microcode() { + addState("ea_dad8"); + fetchimm16("at", 0); + addClearSSW(); + decode_ax(); + addFormattedMicroInsn("at = ((short) at) + dar[rx]"); // add address to temporary register + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + + addState("ea_dad16"); + fetchimm16("at", 0); + addClearSSW(); + decode_ax(); + addFormattedMicroInsn("at = ((short) at) + dar[rx]"); // add address to temporary register + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + + addState("ea_dad32"); + fetchimm16("at", 0); + addClearSSW(); + decode_ax(); + addFormattedMicroInsn("at = ((short) at) + dar[rx]"); // add address to temporary register + consume(4, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + } + + private void ea_das_microcode() { + addState("ea_das8_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_das8"); + fetchimm16("at", 0); + addClearSSW(); + decode_ay(); + addFormattedMicroInsn("at = ((short) at) + dar[ry]"); // add address to temporary register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(8, 2, 0); + addFormattedMicroInsn("mpc = ea_read8"); + addFormattedMicroInsn("continue"); + + addState("ea_das16_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_das16"); + fetchimm16("at", 0); + addClearSSW(); + decode_ay(); + addFormattedMicroInsn("at = ((short) at) + dar[ry]"); // add address to temporary register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(8, 2, 0); + addFormattedMicroInsn("mpc = ea_read16"); + addFormattedMicroInsn("continue"); + + addState("ea_das32_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_das32"); + fetchimm16("at", 0); + addClearSSW(); + decode_ay(); + addFormattedMicroInsn("at = ((short) at) + dar[ry]"); // add address to temporary register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(12, 3, 0); + addFormattedMicroInsn("mpc = ea_read32"); + addFormattedMicroInsn("continue"); + } + + private void ea_daix_fetch_helpers() { + addState("ea_daix_imm32"); + anyread32(null, SSW_DF | SSW_P | SSW_AL, "pc + scan", 0, true, () -> { + addFormattedMicroInsn("scan += 4"); + }); + addFormattedMicroInsn("break"); + addState("ea_dais_imm16"); + anyread16(null, SSW_DF | SSW_P | SSW_AL, "pc + scan", 0, true, () -> { + addFormattedMicroInsn("scan += 2"); + }); + addFormattedMicroInsn("break"); + } + + private void ea_daix_calculate_microcode(String ea, String size, boolean pc, Runnable addEARegister) { + anyread16(null, SSW_IF | SSW_P, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 2"); + }); // fetch extension word to irb + addClearSSW(); + addBeginFormattedControlFlow("if ((irb & 0x%04x) == 0)", EAX_EXT); + addFormattedMicroInsn("at = (byte) irb"); // sign extend irb and set at + // retrieve register index (use ry) as scratch register + addFormattedMicroInsn("rz = (irb >> 12) & 0x000f"); + addBeginFormattedControlFlow("if (rz == 0x000f)"); + addFormattedMicroInsn("rz = sp"); // if using a7, change to right stack pointer + addEndControlFlow(); + // retrieve index register in dt + addFormattedMicroInsn("dt = (irb & 0x%04x) == 0 ? (short) dar[rz] : dar[rz]", EAX_SIZ); + // apply scale and add to at + addFormattedMicroInsn("at += dt << ((irb & 0x%04x) >> 9)", EAX_SCL); + + if (pc) { + addFormattedMicroInsn("at += pc"); // add pc to at + } else { + addEARegister.run(); + } + + addFormattedMicroInsn("mpc = ea_%s%s_fetch", ea, size); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + + addFormattedMicroInsn("at = dt = 0"); // resets at and dt + + // compute index value (in dt) + addBeginFormattedControlFlow("if ((irb & 0x%04x) == 0)", EAX_IS); + // retrieve register index (use ry) as scratch register + addFormattedMicroInsn("rz = (irb >> 12) & 0x000f"); + addBeginFormattedControlFlow("if (rz == 0x000f)"); + addFormattedMicroInsn("rz = sp"); // if using a7, change to right stack pointer + addEndControlFlow(); + // retrieve index register in dt + addFormattedMicroInsn("dt = (irb & 0x%04x) == 0 ? (short) dar[rz] : dar[rz]", EAX_SIZ); + // apply scale + addFormattedMicroInsn("dt <<= ((irb & 0x%04x) >> 9)", EAX_SCL); + addEndControlFlow(); + + // add base register to at + addBeginFormattedControlFlow("if ((irb & 0x%04x) == 0)", EAX_BS); + if (pc) { + addFormattedMicroInsn("at += pc"); // add pc to at + } else { + addEARegister.run(); + } + addEndControlFlow(); + + // retrieve base displacement if any + addFormattedMicroInsn("nmpc = ea_%s%s_base", ea, size); + + addBeginFormattedControlFlow("if ((irb & 0x%04x) == 0)", 1 << 5); + addFormattedMicroInsn("mpc = ea_%s%s_no_base", ea, size); + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((irb & 0x%04x) == 0)", 1 << 4); + addFormattedMicroInsn("mpc = ea_dais_imm16", ea, size); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addFormattedMicroInsn("mpc = ea_daix_imm32", ea, size); + addFormattedMicroInsn("continue"); + + addState(String.format("ea_%s%s_base", ea, size)); + addFormattedMicroInsn("at += dib"); + addClearSSW(); + addState(String.format("ea_%s%s_no_base", ea, size)); + + // memory indirect preindex, add dt to at and reset dt + addBeginFormattedControlFlow("if ((irb & 0x%04x) == 0)", 1 << 2); + addFormattedMicroInsn("at += dt"); + addFormattedMicroInsn("dt = 0"); + + // no memory indirect operation, process to ea fetch + addBeginFormattedControlFlow("if ((irb & 0x%04x) == 0)", EAX_ISL); + addFormattedMicroInsn("mpc = ea_%s%s_fetch", ea, size); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addEndControlFlow(); + + // fetch memory operand and replace at + read32("at", 0, "at"); + + // add post index (if still here) + addFormattedMicroInsn("at += dt"); + addClearSSW(); + + // retrieve outer displacement if any + addFormattedMicroInsn("nmpc = ea_%s%s_outer", ea, size); + + addBeginFormattedControlFlow("if ((irb & 0x%04x) == 0)", 1 << 1); + addFormattedMicroInsn("mpc = ea_%s%s_fetch", ea, size); + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((irb & 0x%04x) == 0)", 1 << 0); + addFormattedMicroInsn("mpc = ea_dais_imm16", ea, size); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addFormattedMicroInsn("mpc = ea_daix_imm32", ea, size); + addFormattedMicroInsn("continue"); + + addState(String.format("ea_%s%s_outer", ea, size)); + addFormattedMicroInsn("at += dib"); + addClearSSW(); + } + + private void ea_dais_calculate_microcode(String ea, String size, boolean pc, boolean forcefetch) { + addState(String.format("ea_%s%s_read", ea, size)); + + if (!forcefetch) { + setclr16("sswi", SSWI_EAFH, 0); + addState(String.format("ea_%s%s", ea, size)); + } + + ea_daix_calculate_microcode(ea, size, pc, () -> { + decode_ay(); + addFormattedMicroInsn("at += dar[ry]"); // retrieve register value and add to at + }); + } + + private void ea_daid_calculate_microcode(String ea, String size, boolean pc, boolean forcefetch) { + addState(String.format("ea_%s%s", ea, size)); + ea_daix_calculate_microcode(ea, size, pc, () -> { + decode_ax(); + addFormattedMicroInsn("at += dar[rx]"); // retrieve register value and add to at + }); + } + + private void ea_daid_microcode() { + ea_daid_calculate_microcode("daid", "8", false, false); + addState("ea_daid8_fetch"); + consume(8, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + + ea_daid_calculate_microcode("daid", "16", false, false); + addState("ea_daid16_fetch"); + consume(8, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + + ea_daid_calculate_microcode("daid", "32", false, false); + addState("ea_daid32_fetch"); + consume(8, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + } + + private void ea_dais_microcode() { + ea_daix_fetch_helpers(); + + ea_dais_calculate_microcode("dais", "8", false, false); + addState("ea_dais8_fetch"); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(8, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(10, 2, 0); + addFormattedMicroInsn("mpc = ea_read8"); + addFormattedMicroInsn("continue"); + + ea_dais_calculate_microcode("dais", "16", false, false); + addState("ea_dais16_fetch"); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(8, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(10, 2, 0); + addFormattedMicroInsn("mpc = ea_read16"); + addFormattedMicroInsn("continue"); + + ea_dais_calculate_microcode("dais", "32", false, false); + addState("ea_dais32_fetch"); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(8, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(14, 3, 0); + addFormattedMicroInsn("mpc = ea_read32"); + addFormattedMicroInsn("continue"); + } + + private void ea_dpc_microcode() { + addState("ea_dpc8_read"); + consume(8, 2, 0); + fetchimm16("at", 0); + addFormattedMicroInsn("at = ((short) at) + pc"); // add pc to temporary register + addState("eapc_read8"); + setclr16("sswi", 0, SSWI_EAFH); + addFormattedMicroInsn("alub = dt"); // save dt to alub + anyread8(null, SSW_DF | SSW_P, "at", 0); + addFormattedMicroInsn("dt = (byte) dib"); + addClearSSW(); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + + addState("ea_dpc16_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_dpc16"); + fetchimm16("at", 0); + addFormattedMicroInsn("at = ((short) at) + pc"); // add pc to temporary register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 0, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(8, 2, 0); + addState("eapc_read16"); + setclr16("sswi", 0, SSWI_EAFH); + addFormattedMicroInsn("alub = dt"); // save dt to alub + anyread16(null, SSW_DF | SSW_P, "at", 0, false, null); + addFormattedMicroInsn("dt = (short) dib"); + addClearSSW(); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + + addState("ea_dpc32_read"); + //setclr16("sswi", SSWI_EAFH, 0); + //addState("ea_dpc32"); + fetchimm16("at", 0); + addFormattedMicroInsn("at = ((short) at) + pc"); // add pc to temporary register + //addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + //consume(4, 1, 0); + //addFormattedMicroInsn("nmpc = decoded.a3"); + //addFormattedMicroInsn("break"); + //addEndControlFlow(); + consume(12, 3, 0); + addState("eapc_read32"); + //setclr16("sswi", 0, SSWI_EAFH); + addFormattedMicroInsn("alub = dt"); // save dt to alub + anyread32("dt", SSW_DF | SSW_P, "at", 0, false, null); + addClearSSW(); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + } + + private void ea_dpci_microcode() { + ea_dais_calculate_microcode("dpci", "8", true, true); + addState("ea_dpci8_fetch"); + consume(10, 2, 0); + addFormattedMicroInsn("mpc = eapc_read8"); + addFormattedMicroInsn("continue"); + + ea_dais_calculate_microcode("dpci", "16", true, false); + addState("ea_dpci16_fetch"); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(8, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(10, 2, 0); + addFormattedMicroInsn("mpc = eapc_read16"); + addFormattedMicroInsn("continue"); + + ea_dais_calculate_microcode("dpci", "32", true, true); + addState("ea_dpci32_fetch"); + //addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + //consume(8, 1, 0); + //addFormattedMicroInsn("nmpc = decoded.a3"); + //addFormattedMicroInsn("break"); + //addEndControlFlow(); + consume(14, 3, 0); + addFormattedMicroInsn("mpc = eapc_read32"); + addFormattedMicroInsn("continue"); + } + + private void ea_adr16d_microcode() { + addState("ea_adr16d8"); + fetchimm16(null, 0); + addClearSSW(); + addFormattedMicroInsn("at = (short) dib"); // add address to temporary register + consume(4, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + + addState("ea_adr16d16"); + fetchimm16(null, 0); + addClearSSW(); + addFormattedMicroInsn("at = (short) dib"); // add address to temporary register + consume(4, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + + addState("ea_adr16d32"); + fetchimm16(null, 0); + addClearSSW(); + addFormattedMicroInsn("at = (short) dib"); // add address to temporary register + consume(4, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + } + + private void ea_adr16s_microcode() { + addState("ea_adr16s8_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_adr16s8"); + fetchimm16(null, 0); + addFormattedMicroInsn("at = (short) dib"); // add address to temporary register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + addClearSSW(); + consume(4, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(8, 2, 0); + addFormattedMicroInsn("mpc = ea_read8"); + addFormattedMicroInsn("continue"); + + addState("ea_adr16s16_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_adr16s16"); + fetchimm16(null, 0); + addFormattedMicroInsn("at = (short) dib"); // add address to temporary register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + addClearSSW(); + consume(4, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(8, 2, 0); + addFormattedMicroInsn("mpc = ea_read16"); + addFormattedMicroInsn("continue"); + + addState("ea_adr16s32_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_adr16s32"); + fetchimm16(null, 0); + addFormattedMicroInsn("at = (short) dib"); // add address to temporary register + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + addClearSSW(); + consume(4, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(12, 3, 0); + addFormattedMicroInsn("mpc = ea_read32"); + addFormattedMicroInsn("continue"); + } + + private void ea_adr32d_microcode() { + addState("ea_adr32d8"); + addState("ea_adr32d16"); + addState("ea_adr32d32"); + fetchimm32("at", 0); + addClearSSW(); + consume(8, 2, 0); + addFormattedMicroInsn("nmpc = decoded.a2"); + addFormattedMicroInsn("break"); + } + + private void ea_adr32s_microcode() { + addState("ea_adr32s8_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_adr32s8"); + fetchimm32("at", 0); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + addClearSSW(); + consume(8, 2, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(12, 3, 0); + addFormattedMicroInsn("mpc = ea_read8"); + addFormattedMicroInsn("continue"); + + addState("ea_adr32s16_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_adr32s16"); + fetchimm32("at", 0); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + addClearSSW(); + consume(8, 2, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(12, 3, 0); + addFormattedMicroInsn("mpc = ea_read16"); + addFormattedMicroInsn("continue"); + + addState("ea_adr32s32_read"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_adr32s32"); + fetchimm32("at", 0); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + addClearSSW(); + consume(8, 2, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + consume(16, 4, 0); + addFormattedMicroInsn("mpc = ea_read32"); + addFormattedMicroInsn("continue"); + } + + private void ea_imm_microcode() { + addState("ea_imm8_read"); + fetchimm16(null, 0); + addClearSSW(); + consume(4, 1, 0); + addFormattedMicroInsn("dt = (byte) dib"); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + + addState("ea_imm16_read"); + fetchimm16(null, 0); + addClearSSW(); + consume(4, 1, 0); + addFormattedMicroInsn("dt = (short) dib"); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + + addState("ea_imm32_read"); + fetchimm32("dt", 0); + addClearSSW(); + consume(8, 2, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + } + + private void misc_microcode() { + addState("op_clrb_ds"); + decode_dy(); + addFormattedMicroInsn("dar[ry] &= ~0xff"); + microprefetch(true, null); // prefetch ir and resume execution + + addState("op_clrw_ds"); + decode_dy(); + addFormattedMicroInsn("dar[ry] &= ~0xffff"); + microprefetch(true, null); // prefetch ir and resume execution + + addState("op_clrl_ds"); + decode_dy(); + addFormattedMicroInsn("dar[ry] = 0"); + microprefetch(true, null); // prefetch ir and resume execution + + addState("op_clrb_ea"); + addFormattedMicroInsn("dt = 0"); + microprefetch(true, "8"); // prefetch ir and resume execution + + addState("op_clrw_ea"); + addFormattedMicroInsn("dt = 0"); + microprefetch(true, "16"); // prefetch ir and resume execution + + addState("op_clrl_ea"); + addFormattedMicroInsn("dt = 0"); + microprefetch(true, "32"); // prefetch ir and resume execution + + addState("op_lea_ea_ad"); + decode_ax(); + addFormattedMicroInsn("dar[rx] = at"); + microprefetch(true, null); // prefetch ir and resume execution + + addState("op_pea"); + addFormattedMicroInsn("au = dar[sp] - 4"); + addFormattedMicroInsn("dar[sp] = au"); + write32(SSW_D, "au", "at", 0, false); + microprefetch(true, null); // prefetch ir and resume execution + + addState("op_swap_ds"); + decode_dy(); + addFormattedMicroInsn("dar[ry] = (dar[ry] << 16) | (dar[ry] >>> 16)"); + addFormattedMicroInsn("long_tst(dar[ry])"); + microprefetch(true, null); // prefetch ir and resume execution + + addState("op_extw_ds"); + decode_dy(); + addFormattedMicroInsn("dar[ry] = (dar[ry] & ~0xffff) | (((byte) dar[ry]) & 0xffff)"); + addFormattedMicroInsn("word_tst(dar[ry])"); + microprefetch(true, null); // prefetch ir and resume execution + + addState("op_extl_ds"); + decode_dy(); + addFormattedMicroInsn("dar[ry] = (short) dar[ry]"); + addFormattedMicroInsn("long_tst(dar[ry])"); + microprefetch(true, null); // prefetch ir and resume execution + + addState("op_extbl_ds"); + decode_dy(); + addFormattedMicroInsn("dar[ry] = (byte) dar[ry]"); + addFormattedMicroInsn("long_tst(dar[ry])"); + microprefetch(true, null); // prefetch ir and resume execution + + addState("op_exg_dd_ds"); + decode_dy(); + decode_dx(); + // exchange values without temporary + addFormattedMicroInsn("dar[rx] ^= dar[ry]"); + addFormattedMicroInsn("dar[ry] ^= dar[rx]"); + addFormattedMicroInsn("dar[rx] ^= dar[ry]"); + microprefetch(true, null); // prefetch ir and resume execution + + addState("op_exg_ad_as"); + decode_ay(); + decode_ax(); + // exchange values without temporary + addFormattedMicroInsn("dar[rx] ^= dar[ry]"); + addFormattedMicroInsn("dar[ry] ^= dar[rx]"); + addFormattedMicroInsn("dar[rx] ^= dar[ry]"); + microprefetch(true, null); // prefetch ir and resume execution + + addState("op_exg_dd_as"); + decode_ay(); + decode_dx(); + // exchange values without temporary + addFormattedMicroInsn("dar[rx] ^= dar[ry]"); + addFormattedMicroInsn("dar[ry] ^= dar[rx]"); + addFormattedMicroInsn("dar[rx] ^= dar[ry]"); + microprefetch(true, null); // prefetch ir and resume execution + + addState("op_scc_b_ds"); + decode_dy(); + addBeginFormattedControlFlow("if (testCC((ir & 0x0f00) >> 8))"); + addFormattedMicroInsn("dar[ry] |= 0xff"); + addNextFormattedControlFlow("else"); + addFormattedMicroInsn("dar[ry] &= ~0xff"); + addEndControlFlow(); + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_scc_b_ea"); + addFormattedMicroInsn("dt = testCC((ir & 0x0f00) >> 8) ? -1 : 0"); + microprefetch(true, "8"); // prefetch ir from pc and resume execution + + addState("op_chk_w_ds"); + decode_dy(); + decode_dx(); + addBeginFormattedControlFlow("if (word_chk(dar[ry], dar[rx]))"); + settvn(6); + addFormattedMicroInsn("mpc = (sswi & 0x%04x) != 0 ? trap2000 : trap0000", SSWI_FMT2); + addEndControlFlow(); + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_chk_w_ea"); + addFormattedMicroInsn("rx = (ir >> 9) & 0x0007"); // retrieve data register index + addBeginFormattedControlFlow("if (word_chk(dt, dar[rx]))"); + settvn(6); + addFormattedMicroInsn("mpc = (sswi & 0x%04x) != 0 ? trap2000 : trap0000", SSWI_FMT2); + addEndControlFlow(); + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_link_as_imm16"); + addFormattedMicroInsn("au = dar[sp] - %d", 4); // allocate 2 words on stack + addFormattedMicroInsn("dar[sp] = au + ((short) dt)"); // update stack pointer + decode_ay(); + write32(SSW_D, "au", "dar[ry]", 0, false); + addFormattedMicroInsn("dar[ry] = au"); // update frame pointer + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_link_as_imm32"); + addFormattedMicroInsn("au = dar[sp] - %d", 4); // allocate 2 words on stack + addFormattedMicroInsn("dar[sp] = au + dt"); // update stack pointer + decode_ay(); + write32(SSW_D, "au", "dar[ry]", 0, false); + addFormattedMicroInsn("dar[ry] = au"); // update frame pointer + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_unlk_as"); + decode_ay(); + addFormattedMicroInsn("au = dar[ry]"); // retrieve linked stack pointer + addFormattedMicroInsn("dar[sp] = au + %d", 4); // restore stack pointer + read32("dar[ry]", 0, "au"); // restore address register value + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_move_usp_as"); + check_privileged(); + decode_ay(); + addFormattedMicroInsn("dar[ry] = dar[15]"); + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_move_as_usp"); + check_privileged(); + decode_ay(); + addFormattedMicroInsn("dar[15] = dar[ry]"); + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_movec_cr_rz"); + check_privileged(); + anyread16(null, SSW_IF | SSW_P, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 2"); + }); // fetch extension word to irb + addClearSSW(); + addFormattedMicroInsn("rz = (irb >> 12) & 0x000f"); + addBeginFormattedControlFlow("if (rz == 0x000f)"); + addFormattedMicroInsn("rz = sp"); // if using a7, change to right stack pointer + addEndControlFlow(); + addFormattedMicroInsn("dt = irb & 0x0fff"); + addBeginFormattedControlFlow("if (dt == 0x000)"); + addFormattedMicroInsn("dar[rz] = sfc"); + addNextFormattedControlFlow("else if (dt == 0x001)"); + addFormattedMicroInsn("dar[rz] = dfc"); + addNextFormattedControlFlow("else if (dt == 0x800)"); + addFormattedMicroInsn("dar[rz] = dar[15]"); + addNextFormattedControlFlow("else if (dt == 0x801)"); + addFormattedMicroInsn("dar[rz] = vbr"); + addNextFormattedControlFlow("else if (dt == 0x803)"); + addFormattedMicroInsn("dar[rz] = dar[17]"); + addNextFormattedControlFlow("else if (dt == 0x804)"); + addFormattedMicroInsn("dar[rz] = dar[16]"); + addNextFormattedControlFlow("else"); + settvn(4); // set illegal exception trap + addFormattedMicroInsn("mpc = trapill"); // set micro pc + addFormattedMicroInsn("continue"); // branch to trap subroutine + addEndControlFlow(); + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_movec_rz_cr"); + check_privileged(); + anyread16(null, SSW_IF | SSW_P, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 2"); + }); // fetch extension word to irb + addClearSSW(); + addFormattedMicroInsn("rz = (irb >> 12) & 0x000f"); + addBeginFormattedControlFlow("if (rz == 0x000f)"); + addFormattedMicroInsn("rz = sp"); // if using a7, change to right stack pointer + addEndControlFlow(); + addFormattedMicroInsn("dt = irb & 0x0fff"); + addBeginFormattedControlFlow("if (dt == 0x000)"); + addFormattedMicroInsn("sfc = dar[rz] & 0x7"); + addNextFormattedControlFlow("else if (dt == 0x001)"); + addFormattedMicroInsn("dfc = dar[rz] & 0x7"); + addNextFormattedControlFlow("else if (dt == 0x800)"); + addFormattedMicroInsn("dar[15] = dar[rz]"); + addNextFormattedControlFlow("else if (dt == 0x801)"); + addFormattedMicroInsn("vbr = dar[rz]"); + addNextFormattedControlFlow("else if (dt == 0x803)"); + addFormattedMicroInsn("dar[17] = dar[rz]"); + addNextFormattedControlFlow("else if (dt == 0x804)"); + addFormattedMicroInsn("dar[16] = dar[rz]"); + addNextFormattedControlFlow("else"); + settvn(4); // set illegal exception trap + addFormattedMicroInsn("mpc = trapill"); // set micro pc + addFormattedMicroInsn("continue"); // branch to trap subroutine + addEndControlFlow(); + microprefetch(true, null); // prefetch ir from pc and resume execution + } + + private void op_movem_microcode() { + addState("op_movemw_rr_ea"); + // read extension word + anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 2"); + }); + prefetchir(0, false); + addFormattedMicroInsn("alub = 0"); + int loop = blocks.size(); + + addFormattedMicroInsn("nmpc = %d", loop); + blocks.add(new MicroBlock()); + addBeginFormattedControlFlow("if (alub >= 16)"); + addClearSSW(); + addFormattedMicroInsn("mpc = resume"); + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((dt & (1 << alub)) == 0)"); + addFormattedMicroInsn("alub += 1", loop); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addFormattedMicroInsn("rz = alub == 15 ? sp : alub"); + write16(SSW_D, "at", "dar[rz]" , 0, true, () -> { + addFormattedMicroInsn("alub += 1"); + addFormattedMicroInsn("at += 2"); + }); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + + addState("op_movemw_rr_pais"); + // read extension word + anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 2"); + }); + prefetchir(0, false); + addFormattedMicroInsn("alub = 0"); + loop = blocks.size(); + + addFormattedMicroInsn("nmpc = %d", loop); + blocks.add(new MicroBlock()); + addBeginFormattedControlFlow("if (alub >= 16)"); + addClearSSW(); + decode_ay(); + addFormattedMicroInsn("dar[ry] = at"); + addFormattedMicroInsn("mpc = resume"); + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((dt & (1 << alub)) == 0)"); + addFormattedMicroInsn("alub += 1", loop); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addFormattedMicroInsn("rz = alub == 0 ? sp : 15 - alub"); + addFormattedMicroInsn("at -= 2"); + write16(SSW_D, "at", "dar[rz]" , 0, true, () -> { + addFormattedMicroInsn("alub += 1"); + }); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + + + addState("op_moveml_rr_ea"); + // read extension word + anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 2"); + }); + prefetchir(0, false); + addFormattedMicroInsn("alub = 0"); + loop = blocks.size(); + + addFormattedMicroInsn("nmpc = %d", loop); + blocks.add(new MicroBlock()); + addBeginFormattedControlFlow("if (alub >= 16)"); + addClearSSW(); + addFormattedMicroInsn("mpc = resume"); + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((dt & (1 << alub)) == 0)"); + addFormattedMicroInsn("alub += 1", loop); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addFormattedMicroInsn("rz = alub == 15 ? sp : alub"); + write32(SSW_D, "at", "dar[rz]" , 0, true, () -> { + addFormattedMicroInsn("alub += 1"); + addFormattedMicroInsn("at += 4"); + }); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + + addState("op_moveml_rr_pais"); + // read extension word + anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 2"); + }); + prefetchir(0, false); + addFormattedMicroInsn("alub = 0"); + loop = blocks.size(); + + addFormattedMicroInsn("nmpc = %d", loop); + blocks.add(new MicroBlock()); + addBeginFormattedControlFlow("if (alub >= 16)"); + addClearSSW(); + decode_ay(); + addFormattedMicroInsn("dar[ry] = at"); + addFormattedMicroInsn("mpc = resume"); + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((dt & (1 << alub)) == 0)"); + addFormattedMicroInsn("alub += 1", loop); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addFormattedMicroInsn("rz = alub == 0 ? sp : 15 - alub"); + addFormattedMicroInsn("at -= 4"); + write32(SSW_D, "at", "dar[rz]" , 0, true, () -> { + addFormattedMicroInsn("alub += 1"); + }); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + + // XXX should have another entry for dpc/dpci to have ssw program function code + addState("op_movemw_ea_rr"); + // read extension word + anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 2"); + }); + prefetchir(0, false); + addFormattedMicroInsn("alub = 0"); + loop = blocks.size(); + + addFormattedMicroInsn("nmpc = %d", loop); + blocks.add(new MicroBlock()); + addBeginFormattedControlFlow("if (alub >= 16)"); + addClearSSW(); + addFormattedMicroInsn("mpc = resume"); + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((dt & (1 << alub)) == 0)"); + addFormattedMicroInsn("alub += 1", loop); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addFormattedMicroInsn("rz = alub == 15 ? sp : alub"); + anyread16(null, SSW_DF, "at", 0, false, () -> { + addFormattedMicroInsn("alub += 1"); + addFormattedMicroInsn("at += 2"); + }); + addFormattedMicroInsn("dar[rz] = (short) dib"); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + + addState("op_movemw_aisp_rr"); + // read extension word + anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 2"); + }); + prefetchir(0, false); + addFormattedMicroInsn("alub = 0"); + loop = blocks.size(); + + addFormattedMicroInsn("nmpc = %d", loop); + blocks.add(new MicroBlock()); + addBeginFormattedControlFlow("if (alub >= 16)"); + addClearSSW(); + decode_ay(); + addFormattedMicroInsn("dar[ry] = at"); + addFormattedMicroInsn("mpc = resume"); + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((dt & (1 << alub)) == 0)"); + addFormattedMicroInsn("alub += 1", loop); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addFormattedMicroInsn("rz = alub == 15 ? sp : alub"); + anyread16(null, SSW_DF, "at", 0, false, () -> { + addFormattedMicroInsn("alub += 1"); + addFormattedMicroInsn("at += 2"); + }); + addFormattedMicroInsn("dar[rz] = (short) dib"); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + + // XXX should have another entry for dpc/dpci to have ssw program function code + addState("op_moveml_ea_rr"); + // read extension word + anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 2"); + }); + prefetchir(0, false); + addFormattedMicroInsn("alub = 0"); + loop = blocks.size(); + + addFormattedMicroInsn("nmpc = %d", loop); + blocks.add(new MicroBlock()); + addBeginFormattedControlFlow("if (alub >= 16)"); + addClearSSW(); + addFormattedMicroInsn("mpc = resume"); + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((dt & (1 << alub)) == 0)"); + addFormattedMicroInsn("alub += 1", loop); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addFormattedMicroInsn("rz = alub == 15 ? sp : alub"); + anyread32(null, SSW_DF, "at", 0, false, () -> { + addFormattedMicroInsn("alub += 1"); + addFormattedMicroInsn("at += 4"); + }); + addFormattedMicroInsn("dar[rz] = dib"); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + + addState("op_moveml_aisp_rr"); + // read extension word + anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 2"); + }); + prefetchir(0, false); + addFormattedMicroInsn("alub = 0"); + loop = blocks.size(); + + addFormattedMicroInsn("nmpc = %d", loop); + blocks.add(new MicroBlock()); + addBeginFormattedControlFlow("if (alub >= 16)"); + addClearSSW(); + decode_ay(); + addFormattedMicroInsn("dar[ry] = at"); + addFormattedMicroInsn("mpc = resume"); + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((dt & (1 << alub)) == 0)"); + addFormattedMicroInsn("alub += 1", loop); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addFormattedMicroInsn("rz = alub == 15 ? sp : alub"); + anyread32(null, SSW_DF, "at", 0, false, () -> { + addFormattedMicroInsn("alub += 1"); + addFormattedMicroInsn("at += 4"); + }); + addFormattedMicroInsn("dar[rz] = dib"); + addFormattedMicroInsn("mpc = %d", loop); + addFormattedMicroInsn("continue"); + } + + private void decode_dy() { + addFormattedMicroInsn("ry = ir & 0x0007"); // retrieve data register index + } + + private void decode_ay() { + addFormattedMicroInsn("ry = ir & 0x0007"); // retrieve address register index + addFormattedMicroInsn("ry = ry == 7 ? sp : ry | 8"); // convert to dar offset + } + + private void decode_dx() { + addFormattedMicroInsn("rx = (ir >> 9) & 0x0007"); // retrieve data register index + } + + private void decode_ax() { + addFormattedMicroInsn("rx = (ir >> 9) & 0x0007"); // retrieve data register index + addFormattedMicroInsn("rx = rx == 7 ? sp : rx | 8"); // convert to dar offset + } + + private void check_privileged() { + // check for supervisor mode + addBeginFormattedControlFlow("if ((sr & 0x%04x) == 0)", SR_S); + consume(38, 4, 4); + settvn(8); // set privilege exception trap + addFormattedMicroInsn("mpc = trapill"); // set micro pc + addFormattedMicroInsn("continue"); // branch to trap subroutine + addEndControlFlow(); + } + + public String gen_move(String size, String src, String dst) { + String msrc = src; + + if ("imm8o".equals(src)) { + msrc = "im"; + } else if ("imm8".equals(src) || "imm16".equals(src) || "imm32".equals(src)) { + msrc = "dt"; + } else if ("ea".equals(src)) { + msrc = "dt"; + } + + String mnemonic = String.format("gen_move%s_%s_%s", size, msrc, dst); + + for(MicroBlock block : blocks) { + if (mnemonic.equals(block.name)) { + return mnemonic; + } + + } + + addState(mnemonic); + + boolean hasrx = false; + boolean hasry = false; + boolean ccr = true; + + if ("sr".equals(src) || "sr".equals(dst)) { + check_privileged(); + } + + String rsrc = null; + + if ("imm8o".equals(src)) { + addFormattedMicroInsn("dt = (byte) ir"); + + rsrc = "dt"; + } else if ("imm8".equals(src) || "imm16".equals(src) || "imm32".equals(src)) { + rsrc = "dt"; + } else if ("dd".equals(src)) { + if (!hasrx) { + decode_dx(); + hasrx = true; + } + rsrc = "dar[rx]"; + } else if ("ds".equals(src)) { + if (!hasry) { + decode_dy(); + hasry = true; + } + + rsrc = "dar[ry]"; + } else if ("ad".equals(src)) { + if (!hasrx) { + decode_ax(); + hasrx = true; + } + rsrc = "dar[rx]"; + } else if ("as".equals(src)) { + if (!hasry) { + decode_ay(); + hasry = true; + } + rsrc = "dar[ry]"; + } else if ("ea".equals(src)) { + rsrc = "dt"; + } else if ("sr".equals(src) || "ccr".equals(src)) { + rsrc = "sr"; + ccr &= false; + } else { + throw new IllegalStateException(); + } + + String rdst = null; + + if ("dd".equals(dst)) { + if (!hasrx) { + decode_dx(); + hasrx = true; + } + rdst = "dar[rx]"; + } else if ("ds".equals(dst)) { + if (!hasry) { + decode_dy(); + hasry = true; + } + + rdst = "dar[ry]"; + } else if ("ad".equals(dst)) { + if (!hasrx) { + decode_ax(); + hasrx = true; + } + rdst = "dar[rx]"; + ccr &= false; + } else if ("as".equals(dst)) { + if (!hasry) { + decode_ay(); + hasry = true; + } + rdst = "dar[ry]"; + ccr &= false; + } else if ("ea".equals(dst)) { + rdst = "dt"; + } else if ("sr".equals(dst) || "ccr".equals(dst)) { + rdst = "sr"; + ccr &= false; + } else { + throw new IllegalStateException(); + } + + if (ccr) { + if ("b".equals(size)) { + addFormattedMicroInsn("byte_tst(%s)", rsrc); // perform byte operation + } else if ("w".equals(size)) { + addFormattedMicroInsn("word_tst(%s)", rsrc); // perform word operation + } else if ("l".equals(size)) { + addFormattedMicroInsn("long_tst(%s)", rsrc); // perform long word operation + } else { + throw new IllegalStateException(); + } + } + + if ("ea".equals(dst)) { + if ("sr".equals(src)) { + addFormattedMicroInsn("dt = (%s & 0x%04x)", rsrc, SR_T1 | SR_T0 | SR_S | SR_M | SR_I.value | FL_C | FL_V | FL_Z | FL_N | FL_X); + } else if ("ccr".equals(src)) { + addFormattedMicroInsn("dt = (%s & 0x%04x)", rsrc, FL_C | FL_V | FL_Z | FL_N | FL_X); + } else if (!"dt".equals(rsrc)) { + addFormattedMicroInsn("dt = %s", rsrc); // copy source to data temporary + } + + if ("b".equals(size)) { + microprefetch(true, "8"); + } else if ("w".equals(size)) { + microprefetch(true, "16"); + } else if ("l".equals(size)) { + microprefetch(true, "32"); + } else { + throw new IllegalStateException(); + } + } else { + if ("as".equals(dst) || "ad".equals(dst)) { + if ("w".equals(size)) { + addFormattedMicroInsn("%s = (short) %s", rdst, rsrc); + } else if ("l".equals(size)) { + addFormattedMicroInsn("%s = %s", rdst, rsrc); + } else { + throw new IllegalStateException(); + } + + microprefetch(true, null); + } else { + if ("sr".equals(dst)) { + addFormattedMicroInsn("%s = %s & 0x%04x", rdst, rsrc, SR_T1 | SR_T0 | SR_S | SR_M | SR_I.value | FL_C | FL_V | FL_Z | FL_N | FL_X); + } else if ("ccr".equals(dst)) { + addFormattedMicroInsn("%s = (%s & ~0xff) | (%s & 0x%04x)", rdst, rdst, rsrc, FL_C | FL_V | FL_Z | FL_N | FL_X); + } else if ("ccr".equals(src)) { + addFormattedMicroInsn("%s = (%s & ~0xffff) | (%s & 0x%04x)", rdst, rdst, rsrc, FL_C | FL_V | FL_Z | FL_N | FL_X); + } else if ("b".equals(size)) { + addFormattedMicroInsn("%s = (%s & ~0xff) | (%s & 0xff)", rdst, rdst, rsrc); + } else if ("w".equals(size)) { + addFormattedMicroInsn("%s = (%s & ~0xffff) | (%s & 0xffff)", rdst, rdst, rsrc); + } else if ("l".equals(size)) { + addFormattedMicroInsn("%s = %s", rdst, rsrc); + } else { + throw new IllegalStateException(); + } + + microprefetch(true, null); + } + } + + return mnemonic; + } + + public String gen_dyadic(String name, String size, String src, String dst) { + boolean update = true; + String msrc = src; + String op = name; + + if ("btst".equals(name)) { + update = false; + } else if ("cmp".equals(name) || "cmpm".equals(name)) { + update = false; + op = "sub"; + } + + if ("imm3".equals(src)) { + msrc = "ir"; + } else if ("imm8".equals(src) || "imm16".equals(src) || "imm32".equals(src)) { + if ("ea".equals(dst)) { + msrc = "im"; + } else { + msrc = "dt"; + } + } else if ("ea".equals(src)) { + if ("ea".equals(dst)) { + msrc = "im"; + } else { + msrc = "dt"; + } + } + + String mnemonic = String.format("gen_%s%s_%s_%s", name, size, msrc, dst); + + for(MicroBlock block : blocks) { + if (mnemonic.equals(block.name)) { + return mnemonic; + } + } + + addState(mnemonic); + + boolean hasrx = false; + boolean hasry = false; + + if ("sr".equals(src) || "sr".equals(dst)) { + check_privileged(); + } + + String rsrc = null; + + if ("imm3".equals(src)) { + addFormattedMicroInsn("alub = (ir >> 9) & 0x0007"); // retrieve immediate data + addBeginFormattedControlFlow("if (alub == 0)"); + addFormattedMicroInsn("alub = 8"); // when immediate data if zero... use 8 + addEndControlFlow(); + + rsrc = "alub"; + } else if ("imm8".equals(src) || "imm16".equals(src) || "imm32".equals(src)) { + if ("ea".equals(dst)) { + rsrc = "alub"; + } else { + rsrc = "dt"; + } + } else if ("dd".equals(src)) { + if (!hasrx) { + decode_dx(); + hasrx = true; + } + rsrc = "dar[rx]"; + } else if ("ds".equals(src)) { + if (!hasry) { + decode_dy(); + hasry = true; + } + + rsrc = "dar[ry]"; + } else if ("ad".equals(src)) { + if (!hasrx) { + decode_ax(); + hasrx = true; + } + rsrc = "dar[rx]"; + } else if ("as".equals(src)) { + if (!hasry) { + decode_ay(); + hasry = true; + } + rsrc = "dar[ry]"; + } else if ("ea".equals(src)) { + if ("ea".equals(dst)) { + rsrc = "alub"; + } else { + rsrc = "dt"; + } + } else if ("sr".equals(src) || "ccr".equals(src)) { + rsrc = "sr"; + } + + String rdst = null; + String optype = null; + boolean exsrc = false; + + if ("dd".equals(dst)) { + if (!hasrx) { + decode_dx(); + hasrx = true; + } + rdst = "dar[rx]"; + } else if ("ds".equals(dst)) { + if (!hasry) { + decode_dy(); + hasry = true; + } + + rdst = "dar[ry]"; + } else if ("ad".equals(dst)) { + if (!hasrx) { + decode_ax(); + hasrx = true; + } + rdst = "dar[rx]"; + exsrc |= true; + } else if ("as".equals(dst)) { + if (!hasry) { + decode_ay(); + hasry = true; + } + rdst = "dar[ry]"; + } else if ("ea".equals(dst)) { + rdst = "dt"; + } else if ("sr".equals(dst) || "ccr".equals(dst)) { + rdst = "sr"; + } + + if (("as".equals(dst) || "ad".equals(dst))) { + if ("add".equals(op)) { + optype = "+"; + } else if ("sub".equals(op)) { + optype = "-"; + } else { + throw new IllegalStateException(); + } + } else if ("sr".equals(dst) || "ccr".equals(dst)) { + if ("or".equals(op)) { + optype = "|"; + } else if ("and".equals(op)) { + optype = "&"; + } else if ("eor".equals(op)) { + optype = "^"; + } else { + throw new IllegalStateException(); + } + } + + if (update) { + boolean writeback = true; + + if (("as".equals(dst) || "ad".equals(dst)) && (!"cmp".equals(name))) { + writeback &= false; + + if ("l".equals(size)) { + addFormattedMicroInsn("%s = %s %s %s", rdst, rdst, optype, rsrc); // perform long word operation + } else if ("w".equals(size)) { + addFormattedMicroInsn("%s = %s %s ((short) %s)", rdst, rdst, optype, rsrc); // perform word operation + } else { + throw new IllegalStateException(); + } + } else if ("sr".equals(dst)) { + writeback &= false; + if ("and".equals(op)) { + addFormattedMicroInsn("%s = %s %s %s", rdst, rdst, optype, rsrc); + } else { + addFormattedMicroInsn("%s = (%s %s %s) & 0x%04x", rdst, rdst, optype, rsrc, SR_T1 | SR_T0 | SR_S | SR_M | SR_I.value | FL_C | FL_V | FL_Z | FL_N | FL_X); + } + } else if ("ccr".equals(dst)) { + writeback &= false; + + if ("and".equals(op)) { + addFormattedMicroInsn("%s = (%s & ~0xff) | (%s %s %s & 0x%02x)", rdst, rdst, rdst, optype, rsrc, FL_C | FL_V | FL_Z | FL_N | FL_X); + } else { + addFormattedMicroInsn("%s = (%s & ~0xff) | ((%s %s %s) & 0x%02x)", rdst, rdst, rdst, optype, rsrc, FL_C | FL_V | FL_Z | FL_N | FL_X); + } + } else if ("b".equals(size)) { + addFormattedMicroInsn("dt = byte_%s(%s, %s)", op, rsrc, rdst); // perform byte operation + } else if ("l".equals(size)) { + addFormattedMicroInsn("dt = long_%s(%s, %s)", op, rsrc, rdst); // perform long word operation + } else if ("w".equals(size) && exsrc) { + addFormattedMicroInsn("dt = long_%s((short) %s, %s)", op, rsrc, rdst); // perform long word operation + } else if ("w".equals(size)) { + addFormattedMicroInsn("dt = word_%s(%s, %s)", op, rsrc, rdst); // perform word operation + } else { + throw new IllegalStateException(); + } + + if (writeback) { + if ("ea".equals(dst)) { + if ("b".equals(size)) { + microprefetch(true, "8"); + } else if ("w".equals(size)) { + microprefetch(true, "16"); + } else if ("l".equals(size)) { + microprefetch(true, "32"); + } else { + throw new IllegalStateException(); + } + } else { + if ("dd".equals(dst)) { + if ("b".equals(size)) { + addFormattedMicroInsn("dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff)"); // update register with result + } else if ("w".equals(size)) { + addFormattedMicroInsn("dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff)"); // update register with result + } else if ("l".equals(size)) { + addFormattedMicroInsn("dar[rx] = dt"); // update register with result + } else { + throw new IllegalStateException(); + } + } else if ("ds".equals(dst)) { + if ("b".equals(size)) { + addFormattedMicroInsn("dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff)"); // update register with result + } else if ("w".equals(size)) { + addFormattedMicroInsn("dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff)"); // update register with result + } else if ("l".equals(size)) { + addFormattedMicroInsn("dar[ry] = dt"); // update register with result + } else { + throw new IllegalStateException(); + } + } else if ("as".equals(dst) | "ad".equals(dst)) { + addFormattedMicroInsn("dar[rx] = dt"); // update register with result + } else { + throw new IllegalStateException(); + } + + microprefetch(true, null); + } + } else { + microprefetch(true, null); + } + } else { + if ("b".equals(size)) { + addFormattedMicroInsn("byte_%s(%s, %s)", op, rsrc, rdst); // perform byte operation + } else if ("l".equals(size)) { + addFormattedMicroInsn("long_%s(%s, %s)", op, rsrc, rdst); // perform long word operation + } else if ("w".equals(size) && exsrc) { + addFormattedMicroInsn("long_%s((short) %s, %s)", op, rsrc, rdst); // perform long word operation (with src word sign extend) + } else if ("w".equals(size)) { + addFormattedMicroInsn("word_%s(%s, %s)", op, rsrc, rdst); // perform word operation + } else { + throw new IllegalStateException(); + } + + microprefetch(true, null); + } + + return mnemonic; + } + + public String gen_monadic(String name, String size, String dst) { + String mnemonic = String.format("gen_%s%s_%s", name, size, dst); + boolean update = !"tst".equals(name); + + for(MicroBlock block : blocks) { + if (mnemonic.equals(block.name)) { + return mnemonic; + } + + } + + addState(mnemonic); + + boolean hasrx = false; + boolean hasry = false; + boolean shift = false; + + if ("asl".equals(name) || "asr".equals(name) || "lsl".equals(name) || "lsr".equals(name) || "rol".equals(name) || "ror".equals(name)) { + shift = true; + } + + String rdst = null; + + if ("dd".equals(dst)) { + if (!hasrx) { + decode_dx(); + hasrx = true; + } + rdst = "dar[rx]"; + } else if ("ds".equals(dst)) { + if (!hasry) { + decode_dy(); + hasry = true; + } + + rdst = "dar[ry]"; + } else if ("ad".equals(dst)) { + if (!hasrx) { + decode_ax(); + hasrx = true; + } + rdst = "dar[rx]"; + } else if ("as".equals(dst)) { + if (!hasry) { + decode_ay(); + hasry = true; + } + rdst = "dar[ry]"; + } else if ("ea".equals(dst)) { + rdst = "dt"; + } + + if (update) { + if ("b".equals(size)) { + addFormattedMicroInsn(shift ? "dt = byte_%s(1, %s)" : "dt = byte_%s(%s)", name, rdst); // perform byte operation + } else if ("w".equals(size)) { + addFormattedMicroInsn(shift ? "dt = word_%s(1, %s)" : "dt = word_%s(%s)", name, rdst); // perform word operation + } else if ("l".equals(size)) { + addFormattedMicroInsn(shift ? "dt = long_%s(1, %s)" : "dt = long_%s(%s)", name, rdst); // perform long word operation + } else { + throw new IllegalStateException(); + } + + if ("ea".equals(dst)) { + if ("b".equals(size)) { + microprefetch(true, "8"); + } else if ("w".equals(size)) { + microprefetch(true, "16"); + } else if ("l".equals(size)) { + microprefetch(true, "32"); + } else { + throw new IllegalStateException(); + } + } else { + if ("dd".equals(dst)) { + if ("b".equals(size)) { + addFormattedMicroInsn("dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff)"); // update register with result + } else if ("w".equals(size)) { + addFormattedMicroInsn("dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff)"); // update register with result + } else if ("l".equals(size)) { + addFormattedMicroInsn("dar[rx] = dt"); // update register with result + } else { + throw new IllegalStateException(); + } + } else if ("ds".equals(dst)) { + if ("b".equals(size)) { + addFormattedMicroInsn("dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff)"); // update register with result + } else if ("w".equals(size)) { + addFormattedMicroInsn("dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff)"); // update register with result + } else if ("l".equals(size)) { + addFormattedMicroInsn("dar[ry] = dt"); // update register with result + } else { + throw new IllegalStateException(); + } + } else if ("ad".equals(dst)) { + if ("w".equals(size)) { + addFormattedMicroInsn("dar[rx] = (short) dt"); // update register with result + } else if ("l".equals(size)) { + addFormattedMicroInsn("dar[rx] = dt"); // update register with result + } else { + throw new IllegalStateException(); + } + } else if ("as".equals(dst)) { + if ("w".equals(size)) { + addFormattedMicroInsn("dar[ry] = (short) dt"); // update register with result + } else if ("l".equals(size)) { + addFormattedMicroInsn("dar[ry] = dt"); // update register with result + } else { + throw new IllegalStateException(); + } + } else { + throw new IllegalStateException(); + } + + microprefetch(true, null); + } + } else { + if ("b".equals(size)) { + addFormattedMicroInsn(shift ? "byte_%s(1, %s)" : "byte_%s(%s)", name, rdst); // perform byte operation + } else if ("w".equals(size)) { + addFormattedMicroInsn(shift ? "word_%s(1, %s)" : "word_%s(%s)", name, rdst); // perform word operation + } else if ("l".equals(size)) { + addFormattedMicroInsn(shift ? "long_%s(1, %s)" : "long_%s(%s)", name, rdst); // perform long word operation + } else { + throw new IllegalStateException(); + } + + microprefetch(true, null); + } + + return mnemonic; + } + + private void op_bcc_microcode() { + addState("op_bcc8"); + addBeginFormattedControlFlow("if (!testCC((ir & 0x0f00) >> 8))"); + consume(6, 1, 0); + microprefetch(true, null); // prefetch ir from pc and resume execution + addEndControlFlow(); + + addState("op_bra8"); + consume(10, 2, 0); + addFormattedMicroInsn("scan = pc + ((byte) ir)"); + addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_bcc16"); + addBeginFormattedControlFlow("if (!testCC((ir & 0x0f00) >> 8))"); + consume(10, 2, 0); + microprefetch(true, null); // prefetch ir from pc and resume execution + addEndControlFlow(); + + addState("op_bra16"); + consume(10, 2, 0); + addFormattedMicroInsn("scan = pc + dt"); + addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_bcc32"); + addBeginFormattedControlFlow("if (!testCC((ir & 0x0f00) >> 8))"); + consume(14, 3, 0); + microprefetch(true, null); // prefetch ir from pc and resume execution + addEndControlFlow(); + + addState("op_bra32"); + consume(14, 3, 0); + addFormattedMicroInsn("scan = pc + dt"); + addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_bsr8"); + consume(18, 2, 2); + addFormattedMicroInsn("au = dar[sp] - 4"); + addFormattedMicroInsn("dar[sp] = au"); + write32(SSW_D, "au", "pc + scan", 0, false); + addFormattedMicroInsn("scan = pc + ((byte) ir)"); + addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_bsr16"); + consume(18, 2, 2); + addFormattedMicroInsn("au = dar[sp] - 4"); + addFormattedMicroInsn("dar[sp] = au"); + write32(SSW_D, "au", "pc + scan", 0, false); + addFormattedMicroInsn("scan = pc + dt"); + addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_bsr32"); + consume(22, 3, 2); + addFormattedMicroInsn("au = dar[sp] - 4"); + addFormattedMicroInsn("dar[sp] = au"); + write32(SSW_D, "au", "pc + scan", 0, false); + addFormattedMicroInsn("scan = pc + dt"); + addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_dbcc"); + addBeginFormattedControlFlow("if (testCC((ir & 0x0f00) >> 8))"); + consume(10, 2, 0); + addFormattedMicroInsn("scan += 2"); // skip displacement word + microprefetch(true, null); // prefetch ir from pc and resume execution + addEndControlFlow(); + decode_dy(); + // decrement and update data register + addFormattedMicroInsn("dar[ry] = (dar[ry] & ~0xffff) | ((dt = ((short) dar[ry]) - 1) & 0xffff)"); + addBeginFormattedControlFlow("if (dt == -1)"); + consume(16, 3, 0); + addFormattedMicroInsn("scan += 2"); // skip displacement word + microprefetch(true, null); // prefetch ir from pc and resume execution + addEndControlFlow(); + fetch16("scan", 0, "pc + scan"); + consume(10, 2, 0); + microprefetch(true, null); // prefetch ir from pc and resume execution + } + + private void op_bkpt_microcode() { + addState("op_bkpt"); + consume(42, 5, 4); + addFormattedMicroInsn("hdlr = handle_bkpt(cip, ir & 0x0007)"); + addFormattedMicroInsn("exit |= (hdlr & 0x%08x) != 0", BKPT_EXIT.value); + addBeginFormattedControlFlow("if ((hdlr & 0x%08x) != 0)", BKPT_RPIR.value); + addFormattedMicroInsn("ir = hdlr & 0xffff"); + addFormattedMicroInsn("sp = spi(sr)"); // update stack pointer index + addFormattedMicroInsn("decoded = MacroPLA.decode(ir)"); + addFormattedMicroInsn("nmpc = decoded.a1"); + addFormattedMicroInsn("break"); + addEndControlFlow(); + + settvn(4); // set illegal exception trap + addFormattedMicroInsn("mpc = trapill"); // set micro pc + addFormattedMicroInsn("continue"); // branch to trap subroutine + } + + private void op_illegal_microcode() { + addState("op_illegal"); + consume(38, 4, 4); + addFormattedMicroInsn("hdlr = handle_illegal(cip, ir)"); + addFormattedMicroInsn("exit |= (hdlr & 0x%08x) != 0", ILL_EXIT.value); + addBeginFormattedControlFlow("if ((hdlr & 0x%08x) != 0)", ILL_SKIP.value); + addFormattedMicroInsn("scan += (short) hdlr"); + addFormattedMicroInsn("sp = spi(sr)"); // update stack pointer index + microprefetch(true, null); // prefetch ir and resume execution + addEndControlFlow(); + + settvn(4); // set illegal exception trap + addFormattedMicroInsn("mpc = trapill"); // set micro pc + addFormattedMicroInsn("continue"); // branch to trap subroutine + } + + private void op_jmp_microcode() { + addState("op_jmp"); + addFormattedMicroInsn("pc = at"); // set pc from effective address + addFormattedMicroInsn("scan = 0"); // clear scan value + addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow + microprefetch(true, null); // prefetch ir from pc and resume execution + + addState("op_jsr"); + addFormattedMicroInsn("au = dar[sp] - 4"); + addFormattedMicroInsn("dar[sp] = au"); + write32(SSW_D, "au", "pc + scan", 0, false); + addFormattedMicroInsn("pc = at"); // set pc from effective address + addFormattedMicroInsn("scan = 0"); // clear scan value + addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow + microprefetch(true, null); // prefetch ir from pc and resume execution + } + + private void op_linea_microcode() { + addState("op_linea"); + consume(38, 4, 4); + addFormattedMicroInsn("hdlr = handle_linea(cip, ir & 0x0fff)"); + addFormattedMicroInsn("exit |= (hdlr & 0x%08x) != 0", LINEA_EXIT.value); + addBeginFormattedControlFlow("if ((hdlr & 0x%08x) != 0)", LINEA_SKIP.value); + addFormattedMicroInsn("scan += (short) hdlr"); + addFormattedMicroInsn("sp = spi(sr)"); // update stack pointer index + microprefetch(true, null); // prefetch ir and resume execution + addEndControlFlow(); + + settvn(10); // set linea exception trap + addFormattedMicroInsn("mpc = trapill"); // set micro pc + addFormattedMicroInsn("continue"); // branch to trap subroutine + } + + private void op_linef_microcode() { + addState("op_linef"); + consume(38, 4, 4); + settvn(11); // set linef exception trap + addFormattedMicroInsn("mpc = trapill"); // set micro pc + addFormattedMicroInsn("continue"); // branch to trap subroutine + } + + private void op_movep_microcode() { + addState("op_movepw_dd_das"); + decode_dx(); + addFormattedMicroInsn("dt = dar[rx]"); // retrieve data register value + prefetchir(0, false); + write8(SSW_D, "at", "dt >> 8", 0, false); + write8(SSW_D | SSW_AL, "at", "dt", 2, false); + addFormattedMicroInsn("mpc = resume"); + addFormattedMicroInsn("continue"); + + addState("op_movepw_das_dd"); + decode_dx(); + read8("dt", 0, "at", 0); + read8(null, SSW_AL, "at", 2); + addFormattedMicroInsn("dt = (dt << 8) | (dib & 0xff)"); + addFormattedMicroInsn("dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff)"); + microprefetch(true, null); + + addState("op_movepl_dd_das"); + decode_dx(); + addFormattedMicroInsn("dt = dar[rx]"); // retrieve data register value + prefetchir(0, false); + write8(SSW_D, "at", "dt >> 24", 0, false); + write8(SSW_D | SSW_AL, "at", "dt >> 16", 2, false); + write8(SSW_D | SSW_AL, "at", "dt >> 8", 4, false); + write8(SSW_D | SSW_AL, "at", "dt", 6, false); + addFormattedMicroInsn("mpc = resume"); + addFormattedMicroInsn("continue"); + + addState("op_movepl_das_dd"); + decode_dx(); + read8("dt", 0, "at", 0); + read8(null, SSW_AL, "at", 2); + addFormattedMicroInsn("dt = (dt << 8) | (dib & 0xff)"); + read8(null, SSW_AL, "at", 4); + addFormattedMicroInsn("dt = (dt << 8) | (dib & 0xff)"); + read8(null, SSW_AL, "at", 6); + addFormattedMicroInsn("dt = (dt << 8) | (dib & 0xff)"); + addFormattedMicroInsn("dar[rx] = dt"); + microprefetch(true, null); + + } + + private void op_nop_microcode() { + addState("op_nop"); + consume(4, 1, 0); + microprefetch(true, null); + } + + private void op_rte_microcode() { + addState("op_rte"); + // check for supervisor mode + addBeginFormattedControlFlow("if ((sr & 0x%04x) == 0)", SR_S); + consume(38, 4, 4); + settvn(8); // set privilege exception trap + addFormattedMicroInsn("mpc = trapill"); // set micro pc + addFormattedMicroInsn("continue"); // branch to trap subroutine + addEndControlFlow(); + addFormattedMicroInsn("au = dar[sp]"); // retrieve supervisor stack pointer + + addState("check_vob"); + read16(null, SSW_CR | SSW_S, "au", 3 << 1); // read vob from stack frame + // select rte implementation according to stack frame on master stack + addFormattedMicroInsn("mpc = select_rte(dib)"); + addFormattedMicroInsn("continue"); + + addState("rteill"); + consume(50, 7, 4); + settvn(14); + addFormattedMicroInsn("mpc = trapill"); // set next entry + addFormattedMicroInsn("continue"); + + addState("exit_trap"); + read32("pc", SSW_CR | SSW_S | SSW_AL, "au", 1 << 1); // read pc from stack frame + read16(null, SSW_CR | SSW_S | SSW_AL, "au", 0); // read sr from stack frame + addFormattedMicroInsn("sr = dib & 0x%04x", + SR_T1 | SR_T0 | SR_S | SR_M | SR_I.value | FL_C | FL_V | FL_Z | FL_N | FL_X); + addFormattedMicroInsn("sp = spi(sr)"); // update stack pointer index + addFormattedMicroInsn("scan = 0"); // reset scan value + microprefetch(true, null); + + // specific routine for restore state from a $0 format frame + // au already contains sp, since vob has been read, assume au is word aligned + addState("rte0000"); + consume(24, 6, 0); + addFormattedMicroInsn("dar[sp] = au + %d", 4 << 1); // update supervisor stack pointer + addFormattedMicroInsn("mpc = exit_trap"); + addFormattedMicroInsn("continue"); + + // specific routine for restore state from a $1 format frame + // au already contains sp, since vob has been read, assume au is word aligned + addState("rte1000"); + // do not do anything with the throw away stack frame. drop it and fallback to + // master frame + addFormattedMicroInsn("dar[sp] = au + %d", 4 << 1); // update interrupt supervisor stack pointer + addFormattedMicroInsn("au = dar[sp = spi(sr | 0x%04x)]", SR_M); // retrieve master supervisor stack pointer + + // select rte implementation again according to stack frame on master stack + addFormattedMicroInsn("mpc = check_vob"); + addFormattedMicroInsn("continue"); + + // specific routine for restore state from a $2 format frame + // au already contains sp, since vob has been read, assume au is word aligned + addState("rte2000"); + consume(24, 6, 0); // use timing of rte0000 + addFormattedMicroInsn("dar[sp] = au + %d", 6 << 1); // update supervisor stack pointer + addFormattedMicroInsn("mpc = exit_trap"); + addFormattedMicroInsn("continue"); + + addState("rte8000"); + consume(110, 26, 0); + read32("cip", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 27 << 1); // read cip + read32("dt", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 25 << 1); // read dt + read16("ir", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 24 << 1); // read ir + addFormattedMicroInsn("decoded = MacroPLA.decode(ir)"); // ensure ir is decoded (for RMW re-run) + read16(null, SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 23 << 1); // read sswi + addFormattedMicroInsn("vdt1 = dib << 16"); // save dibh in vdt1 + read32("vat2", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 19 << 1); // read au + read32("vat1", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 17 << 1); // read at + read32("alub", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 15 << 1); // read alub + read16("scan", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 14 << 1); // read scan value + read16("nmpc", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 13 << 1); // read next mpc + read16("irb", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 12 << 1); // read prefetch buffer + + read32("vat3", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 5 << 1); // read saved aob + read16(null, SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 4 << 1); // read ssw + addFormattedMicroInsn("vdt1 |= dib & 0xffff"); + + read32("pc", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 1 << 1); // read pc + + addBeginFormattedControlFlow("if ((vdt1 & 0x%04x) == 0)", SSW_RR); + // processor re-run requested + addFormattedMicroInsn("elapsed += 2"); // will take two more cycles to execute + addBeginFormattedControlFlow("if ((vdt1 & 0x%04x) != 0)", SSW_RM); + // read/modify/write case, jump to a3 to retry decoded instruction + addFormattedMicroInsn("nmpc = decoded.a3"); + setclr16("vdt1", 0, SSW_MASK); // clear ssw before returning + addNextFormattedControlFlow("else"); + + // need to read dob (or dibh) for retry + addBeginFormattedControlFlow("if ((vdt1 & 0x%04x) == 0)", SSW_RW); + // choose between short or long dob + addBeginFormattedControlFlow("if ((vdt1 & 0x%04x) != 0)", SSW_32); + read32("vdt2", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 8 << 1); // read dobh/l + addNextFormattedControlFlow("else"); + read16("vdt2", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 8 << 1); // read dobl + addEndControlFlow(); + addNextFormattedControlFlow("else if ((vdt1 & 0x%04x) == 0x%04x)", SSW_32 | SSW_WD, SSW_WD); + read16("vdt3", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 9 << 1); // read dibh only + addFormattedMicroInsn("vdt3 <<= 16"); // adjust vdt3 for dibh + addEndControlFlow(); + + addFormattedMicroInsn("ssw = (ssw & 0x%04x) | ((vdt1 ^ ~0x%04x) & 0x%04x)", SSW_RS.value | SSW_HL.value, SSW_RR, + SSW_MASK & ~SSW_BR); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0x%04x)", SSW_32 | SSW_BY, SSW_BY); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0)", SSW_HB); + addFormattedMicroInsn("vat3 += 1"); // add 1 to aob to match low byte + addNextFormattedControlFlow("else"); + setclr16("ssw", 0, SSW_HB); // ensure HB is cleared before access + addFormattedMicroInsn("vdt2 >>= 8"); // set dob data to low byte + addEndControlFlow(); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0x%04x)", SSW_DF | SSW_RW, SSW_DF | SSW_RW); + addFormattedMicroInsn("vdt3 = read8(vat3)"); + addNextFormattedControlFlow("else if ((ssw & 0x%04x) == 0)", SSW_DF | SSW_RW); + addFormattedMicroInsn("write8(vat3, vdt2)"); + addEndControlFlow(); + addNextFormattedControlFlow("else if ((vat3 & 0x000000001) != 0)"); + /* misaligned transfer, signal address error */ + consume(126, 4, 26); + settvn(3); + addFormattedMicroInsn("mpc = resume_trap8000"); + addFormattedMicroInsn("continue"); + addNextFormattedControlFlow("else if ((ssw & 0x%04x) == 0)", SSW_32); + // 16 bits access (aligned) + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0x%04x)", SSW_IF | SSW_DF | SSW_RW, SSW_IF | SSW_RW); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0x%04x)", SSW_P | SSW_D, SSW_P); + addFormattedMicroInsn("irb = fetch16(vat3)"); + addNextFormattedControlFlow("else"); + addFormattedMicroInsn("irb = read16(vat3)"); + addEndControlFlow(); + addNextFormattedControlFlow("else if ((ssw & 0x%04x) == 0x%04x)", SSW_IF | SSW_DF | SSW_RW | SSW_WD, + SSW_DF | SSW_RW | SSW_WD); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0x%04x)", SSW_P | SSW_D, SSW_P); + addFormattedMicroInsn("vdt3 = (vdt3 & ~0xffff) | fetch16(vat3) & 0xffff"); + addNextFormattedControlFlow("else"); + addFormattedMicroInsn("vdt3 = (vdt3 & ~0xffff) | read16(vat3) & 0xffff"); + addEndControlFlow(); + addNextFormattedControlFlow("else if ((ssw & 0x%04x) == 0x%04x)", SSW_IF | SSW_DF | SSW_RW, SSW_DF | SSW_RW); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0x%04x)", SSW_P | SSW_D, SSW_P); + addFormattedMicroInsn("vdt3 = fetch16(vat3)"); + addNextFormattedControlFlow("else"); + addFormattedMicroInsn("vdt3 = read16(vat3)"); + addEndControlFlow(); + addNextFormattedControlFlow("else if ((ssw & 0x%04x) == 0)", SSW_IF | SSW_DF | SSW_RW); + addFormattedMicroInsn("write16(vat3, vdt2)"); + addEndControlFlow(); + addNextFormattedControlFlow("else"); + // 32 bits access (aligned on 16 bits boundary) + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0x%04x)", SSW_IF | SSW_DF | SSW_RW, SSW_IF | SSW_RW); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0x%04x)", SSW_P | SSW_D, SSW_P); + addFormattedMicroInsn("vdt3 = fetch32(vat3)"); + addNextFormattedControlFlow("else"); + addFormattedMicroInsn("vdt3 = read32(vat3)"); + addEndControlFlow(); + addNextFormattedControlFlow("else if ((ssw & 0x%04x) == 0)", SSW_IF | SSW_DF | SSW_RW); + addFormattedMicroInsn("write32(vat3, vdt2)"); + addEndControlFlow(); + addEndControlFlow(); + + // update vdt1 according to new ssw (may be used to resume berr/aerr trap + addFormattedMicroInsn("vdt1 = (vdt1 & ~0xffff) | ((ssw ^ ~0x%04x) & 0x%04x)", SSW_RR, (~SSW_BR) & 0xffff); + + addBeginFormattedControlFlow("if ((ssw & 0x%04x) != 0)", SSW_BR); + /* got bus error, retry with current frame */ + consume(126, 4, 26); + settvn(2); + addFormattedMicroInsn("mpc = resume_trap8000"); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + addEndControlFlow(); + addNextFormattedControlFlow("else if ((vdt1 & 0x%04x) != 0)", SSW_RW); + // software read retry requested, need to read dibh/l + addBeginFormattedControlFlow("if ((vdt1 & 0x%04x) != 0)", SSW_WD); // check 'wide' bit for read + read32("vdt3", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 9 << 1); // read dibh/l + addNextFormattedControlFlow("else"); + read16("vdt3", SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 10 << 1); // read dibl only + addEndControlFlow(); + addEndControlFlow(); + + read16(null, SSW_CR | SSW_S | SSW_D | SSW_AL, "au", 0); // read sr + addFormattedMicroInsn("sr = dib & 0x%04x", + SR_T1 | SR_T0 | SR_S | SR_M | SR_I.value | FL_C | FL_V | FL_Z | FL_N | FL_X); + addFormattedMicroInsn("dar[sp] = au + %d", 29 << 1); // update supervisor stack pointer + addFormattedMicroInsn("sp = spi(sr)"); // update stack pointer index + + addFormattedMicroInsn("au = vat1"); // restore at + addFormattedMicroInsn("at = vat2"); // restore au + addFormattedMicroInsn("aob = vat3"); // restore aob + addFormattedMicroInsn("dob = vdt2"); // restore dob + addFormattedMicroInsn("dib = vdt3"); // restore dib + addFormattedMicroInsn("tvn = (vdt1 >> 14) & 0x3fc"); // restore tvn + addFormattedMicroInsn("sswi = (sswi & ~0x%04x) | ((vdt1 >> 16) & 0x%04x)", SR_T1 | SR_T0 | SSWI_EAFH, + SR_T1 | SR_T0 | SSWI_EAFH); + addFormattedMicroInsn("ssw = (ssw & 0x%04x) | ((vdt1 ^ ~0x%04x) & 0x%04x)", SSW_RS.value | SSW_HL.value, SSW_RR, + SSW_MASK & ~SSW_BR); + + // if last 32 bits access has only 16 bits transfered + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0x%04x)", SSW_RR | SSW_32 | SSW_WD, SSW_RR | SSW_32); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) != 0)", SSW_RW); + addFormattedMicroInsn("mpc = (ssw & 0x%04x) == 0x%04x ? bevtf32 : bevtr32", SSW_D | SSW_P, SSW_P); + addNextFormattedControlFlow("else"); + addFormattedMicroInsn("mpc = bevtw32"); + addEndControlFlow(); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + + addFormattedMicroInsn("break"); // resume execution to nmpc + } + + private void op_rtr_microcode() { + addState("op_rtr"); + consume(20, 5, 0); + addFormattedMicroInsn("au = dar[sp]"); // clear scan value + read32("pc", 0, "au", 1 << 1); + read16(null, SSW_AL, "au", 0 << 1); + addClearSSW(); + addFormattedMicroInsn("sr = (sr & ~0x%04x) | (dib & 0x%04x)", FL_C | FL_V | FL_Z | FL_N | FL_X, + FL_C | FL_V | FL_Z | FL_N | FL_X); + addFormattedMicroInsn("scan = 0"); // clear scan value + addFormattedMicroInsn("dar[sp] = au + 6"); // update stack pointer + addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow + microprefetch(true, null); // prefetch ir from pc and resume execution + } + + private void op_rts_microcode() { + addState("op_rts"); + consume(16, 4, 0); + addFormattedMicroInsn("au = dar[sp]"); // clear scan value + read32("pc", 0, "au"); + addClearSSW(); + addFormattedMicroInsn("scan = 0"); // clear scan value + addFormattedMicroInsn("dar[sp] = au + 4"); // update stack pointer + addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow + microprefetch(true, null); // prefetch ir from pc and resume execution + } + + private void op_reset_microcode() { + addState("op_reset"); + consume(130, 1, 0); + microprefetch(true, null); + } + + private void op_trapv_microcode() { + addState("op_trap"); + consume(38, 4, 4); + addFormattedMicroInsn("tvn = (32 + (ir & 0x000f)) << 2"); + addFormattedMicroInsn("mpc = trap0000"); // use format 2 (68020+ instruction) + addFormattedMicroInsn("continue"); // branch to trap subroutine + + addState("op_trapv"); + consume(4, 1, 0); + addBeginFormattedControlFlow("if ((sr & 0x%04x) != 0)", FL_V); + consume(40, 5, 4); + settvn(7); // set trapv exception trap + addFormattedMicroInsn("mpc = (sswi & 0x%04x) != 0 ? trap2000 : trap0000", SSWI_FMT2); + addFormattedMicroInsn("continue"); // branch to trap subroutine + addEndControlFlow(); + microprefetch(true, null); + + addState("op_trapcc"); + addBeginFormattedControlFlow("if (!testCC((ir & 0x0f00) >> 8))"); + microprefetch(true, null); // prefetch ir from pc and resume execution + addEndControlFlow(); + consume(40, 5, 4); + settvn(7); // set trapcc exception trap + addFormattedMicroInsn("mpc = trap2000"); // use format 2 (68020+ instruction) + addFormattedMicroInsn("continue"); // branch to trap subroutine + + addState("op_trapcc16"); + addFormattedMicroInsn("scan += 2"); // skip next word + addBeginFormattedControlFlow("if (!testCC((ir & 0x0f00) >> 8))"); + microprefetch(true, null); // prefetch ir from pc and resume execution + addEndControlFlow(); + consume(40, 5, 4); + settvn(7); // set trapcc exception trap + addFormattedMicroInsn("mpc = trap2000"); // use format 2 (68020+ instruction) + addFormattedMicroInsn("continue"); // branch to trap subroutine + + addState("op_trapcc32"); + addFormattedMicroInsn("scan += 4"); // skip next long word + addBeginFormattedControlFlow("if (!testCC((ir & 0x0f00) >> 8))"); + microprefetch(true, null); // prefetch ir from pc and resume execution + addEndControlFlow(); + + consume(40, 5, 4); + settvn(7); // set trapcc exception trap + addFormattedMicroInsn("mpc = trap2000"); // use format 2 (68020+ instruction) + addFormattedMicroInsn("continue"); // branch to trap subroutine + } + + private void emitStates(TypeSpec.Builder builder, Set imports) { + int count = blocks.size(); + + for (int i = 0; i < count; i++) { + MicroBlock block = blocks.get(i); + + if (block.name != null) { + FieldSpec field = null; + + if ((imports == null) || (imports.contains(block.name))) { + field = FieldSpec.builder(int.class, block.name, PROTECTED, STATIC, FINAL).initializer("$L", i) + .build(); + } else { + field = FieldSpec.builder(int.class, block.name, PRIVATE, STATIC, FINAL).initializer("$L", i) + .build(); + } + + builder.addField(field); + } + } + } + + private void emitMicrocode(MethodSpec.Builder builder) { + int count = blocks.size(); + + for (int i = 0; i < count; i++) { + blocks.get(i).emit(i, builder); + } + } + + public static TypeSpec coreType() { + TypeSpec.Builder builder = TypeSpec.classBuilder("Core").addModifiers(PUBLIC, ABSTRACT); + + builder.superclass(CoreALU.class); + + TreeMap macros = new TreeMap(); + TreeSet imports = new TreeSet(); + CoreGenerator gen = new CoreGenerator(); + + CorePLAGenerator.fillops(gen, macros); + CorePLAGenerator.corePLAType(gen, macros, imports); + + gen.emitStates(builder, imports); + + builder.addField(BKPT_EXIT.field); + builder.addField(BKPT_RPIR.field); + builder.addField(LINEA_EXIT.field); + builder.addField(LINEA_SKIP.field); + builder.addField(ILL_EXIT.field); + builder.addField(ILL_SKIP.field); + builder.addField(TRACE_EXIT.field); + builder.addField(TRACE_IGNR.field); + builder.addField(IRQ_EXIT.field); + builder.addField(IRQ_IERR.field); + builder.addField(IRQ_DFLT.field); + builder.addField(IRQ_AVEC.field); + builder.addField(IRQ_SPUR.field); + builder.addField(IRQ_IGNR.field); + + builder.addField(pc); + builder.addField(scan); + + builder.addField(alub); + builder.addField(irb); + builder.addField(ir); + builder.addField(mpc); + builder.addField(cip); + builder.addField(au); + builder.addField(at); + builder.addField(dt); + // builder.addField(aob); + // builder.addField(dob); + // builder.addField(dib); + + builder.addField(slice); + + builder.addMethod(pulse_reset_method()); + builder.addMethod(set_pending_irq_method()); + builder.addMethod(select_rte_method()); + builder.addMethod(execute_method(gen)); + builder.addMethod(fetch16_method()); + builder.addMethod(fetch32_method()); + builder.addMethod(read8_method()); + builder.addMethod(read16_method()); + builder.addMethod(read32_method()); + builder.addMethod(write8_method()); + builder.addMethod(write16_method()); + builder.addMethod(write32_method()); + builder.addMethod(handle_bkpt_method()); + builder.addMethod(handle_illegal_method()); + builder.addMethod(handle_interrupt_method()); + builder.addMethod(handle_linea_method()); + builder.addMethod(handle_reset_method()); + builder.addMethod(handle_trace_method()); + + return builder.build(); + } + + public static MethodSpec pulse_reset_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("pulse_reset"); + + builder.addModifiers(PUBLIC, FINAL); + builder.returns(void.class); + + builder.addStatement("ssw |= $N", SSW_RS.field); + + return builder.build(); + } + + public static MethodSpec set_pending_irq_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("set_pending_irq"); + + builder.addModifiers(PUBLIC, FINAL); + builder.returns(void.class).addParameter(int.class, "level"); + + /* + * sswi contains pending interrupt level. This value will be set to 0 at next + * instruction boundary + */ + builder.addStatement("level = (level << 8) & $N", SR_I.field); + builder.addStatement("$N = ($N & ~$N) | level", sswi, sswi, SR_I.field); + + return builder.build(); + } + + public static MethodSpec select_rte_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("select_rte"); + + builder.addModifiers(PRIVATE, STATIC, FINAL); + builder.returns(int.class).addParameter(int.class, "vob"); + + builder.beginControlFlow("switch((vob & 0xf000) >> 12)"); + builder.addCode("case 0:\n"); + builder.addStatement("return rte0000"); + builder.addCode("case 1:\n"); + builder.addStatement("return rte1000"); + builder.addCode("case 2:\n"); + builder.addStatement("return rte2000"); + builder.addCode("case 8:\n"); + builder.addStatement("return rte8000"); + builder.addCode("default:\n"); + builder.addStatement("return rteill"); + builder.endControlFlow(); + + return builder.build(); + } + + public static MethodSpec execute_method(CoreGenerator gen) { + MethodSpec.Builder builder = MethodSpec.methodBuilder("execute"); + + builder.addModifiers(PUBLIC, FINAL); + builder.returns(int.class).addParameter(int.class, "cycles"); + + builder.addStatement("MacroPLA decoded = MacroPLA.decode(ir)"); + builder.addStatement("int slice = Math.max(0, cycles)"); + builder.addStatement("int consumed = 0"); + + builder.beginControlFlow("if ((sswi & $N) != 0)", SSWI_PSLC.field); + builder.addStatement("slice += this.slice"); + builder.endControlFlow(); + + builder.beginControlFlow("if (slice > 0)"); + builder.addStatement("boolean exit = false"); + builder.addStatement("int sp = spi(sr)"); + builder.addStatement("int elapsed = 0"); + builder.addStatement("int nmpc = 0"); + + builder.addStatement("int hdlr = 0"); + builder.addStatement("int ipend = 0"); + builder.addStatement("int tvn = 0"); + builder.addStatement("int aob = 0"); + builder.addStatement("int dob = 0"); + builder.addStatement("int dib = 0"); + builder.addStatement("int vat1 = 0"); + builder.addStatement("int vat2 = 0"); + builder.addStatement("int vat3 = 0"); + builder.addStatement("int vdt1 = 0"); + builder.addStatement("int vdt2 = 0"); + builder.addStatement("int vdt3 = 0"); + builder.addStatement("int rx = 0"); + builder.addStatement("int ry = 0"); + builder.addStatement("int rz = 0"); + builder.addStatement("consumed = slice"); + + builder.beginControlFlow("if ((ssw & ($N | $N)) != 0)", SSW_RS.field, SSW_HL.field); + builder.addStatement("nmpc = mpc"); + builder.addStatement("mpc = halt"); + builder.endControlFlow(); + + builder.beginControlFlow("while (true)"); + builder.beginControlFlow("switch(mpc)"); + + gen.emitMicrocode(builder); + + builder.addCode("default:\n"); + builder.addStatement("mpc = dbrr"); + builder.addStatement("continue"); + + builder.endControlFlow(); + + builder.addStatement("mpc = nmpc"); + builder.addStatement("slice -= elapsed"); + builder.addStatement("elapsed = 0"); + + builder.beginControlFlow("if (exit || (slice <= 0))"); + builder.addStatement("break"); + builder.endControlFlow(); + + builder.endControlFlow(); + + builder.addStatement("consumed -= slice"); + builder.endControlFlow(); + + builder.beginControlFlow("if ((sswi & $N) != 0)", SSWI_PSLC.field); + builder.addStatement("this.slice = slice"); + builder.endControlFlow(); + + builder.addStatement("return consumed"); + + return builder.build(); + } + + public static MethodSpec fetch16_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("fetch16"); + + builder.addModifiers(PUBLIC, ABSTRACT); + builder.returns(int.class).addParameter(int.class, "aob"); + + return builder.build(); + } + + public static MethodSpec fetch32_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("fetch32"); + + builder.addModifiers(PUBLIC, ABSTRACT); + builder.returns(int.class).addParameter(int.class, "aob"); + + return builder.build(); + } + + public static MethodSpec read8_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("read8"); + + builder.addModifiers(PUBLIC, ABSTRACT); + builder.returns(byte.class).addParameter(int.class, "aob"); + + return builder.build(); + } + + public static MethodSpec read16_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("read16"); + + builder.addModifiers(PUBLIC, ABSTRACT); + builder.returns(short.class).addParameter(int.class, "aob"); + + return builder.build(); + } + + public static MethodSpec read32_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("read32"); + + builder.addModifiers(PUBLIC, ABSTRACT); + builder.returns(int.class).addParameter(int.class, "aob"); + + return builder.build(); + } + + public static MethodSpec write8_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("write8"); + + builder.addModifiers(PUBLIC, ABSTRACT); + builder.addParameter(int.class, "aob").addParameter(int.class, "dob"); + + return builder.build(); + } + + public static MethodSpec write16_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("write16"); + + builder.addModifiers(PUBLIC, ABSTRACT); + builder.addParameter(int.class, "aob").addParameter(int.class, "dob"); + + return builder.build(); + } + + public static MethodSpec write32_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("write32"); + + builder.addModifiers(PUBLIC, ABSTRACT); + builder.addParameter(int.class, "aob").addParameter(int.class, "dob"); + + return builder.build(); + } + + public static MethodSpec handle_bkpt_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("handle_bkpt"); + + builder.addModifiers(PUBLIC); + builder.returns(int.class).addParameter(int.class, "pc").addParameter(int.class, "data"); + + builder.addStatement("return 0"); + + return builder.build(); + } + + public static MethodSpec handle_linea_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("handle_linea"); + + builder.addModifiers(PUBLIC); + builder.returns(int.class).addParameter(int.class, "pc").addParameter(int.class, "data"); + + builder.addStatement("return 0"); + + return builder.build(); + } + + public static MethodSpec handle_illegal_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("handle_illegal"); + + builder.addModifiers(PUBLIC); + builder.returns(int.class).addParameter(int.class, "pc").addParameter(int.class, "ir"); + + builder.addStatement("return 0"); + + return builder.build(); + } + + public static MethodSpec handle_interrupt_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("handle_interrupt"); + + builder.addModifiers(PUBLIC); + builder.returns(int.class).addParameter(int.class, "level"); + + builder.addStatement("return $N", IRQ_DFLT.field); + + return builder.build(); + } + + public static MethodSpec handle_reset_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("handle_reset"); + + builder.addModifiers(PUBLIC); + + return builder.build(); + } + + public static MethodSpec handle_trace_method() { + MethodSpec.Builder builder = MethodSpec.methodBuilder("handle_trace"); + + builder.addModifiers(PUBLIC); + builder.returns(int.class).addParameter(int.class, "pc"); + + builder.addStatement("return 0"); + + return builder.build(); + } + + private static class FieldInt16Constant { + public final FieldSpec field; + public int value; + + public FieldInt16Constant(String name, int value) { + this.field = FieldSpec.builder(int.class, name, PUBLIC, STATIC, FINAL).initializer("$L", hex16(value)) + .build(); + this.value = value; + } + } + + private static class FieldInt32Constant { + public final FieldSpec field; + public int value; + + public FieldInt32Constant(String name, int value) { + this.field = FieldSpec.builder(int.class, name, PUBLIC, STATIC, FINAL).initializer("$L", hex32(value)) + .build(); + this.value = value; + } + } + + private static final String hex16(int value) { + return String.format("0x%04x", value & 0xffff); + } + + private static final String hex32(int value) { + return String.format("0x%08x", value); + } + + class MicroBlock { + List instructions = new ArrayList<>(); + MicroInsn sswclr = null; + String name = null; + + private MicroBlock() { + } + + public void emit(int mpc, MethodSpec.Builder builder) { + if (name == null) { + builder.addCode(String.format("case %d:\n", mpc)); + } else { + builder.addCode(String.format("case %d: /* %s */\n", mpc, name)); + } + + for (MicroInsn insn : instructions) { + insn.emit(builder); + } + } + } + + interface MicroInsn { + public void emit(MethodSpec.Builder builder); + } + + private void microprefetch(boolean resume, String eawritesize) { + if (resume) { + if (eawritesize != null) { + addFormattedMicroInsn(String.format("mpc = ea_resume_write%s", eawritesize)); + } else { + addFormattedMicroInsn("mpc = resume_prefetch"); + } + addFormattedMicroInsn("continue"); + } else { + if (eawritesize != null) { + throw new IllegalStateException(); + // addFormattedMicroInsn(String.format("nmpc = ea_write%s", eawritesize)); + // prefetchir(0, true); + // addFormattedMicroInsn("break"); + } else { + prefetchir(0, false); + } + } + } + + private void prefetchir(int fc, boolean has_nmpc) { + anyread16(null, SSW_IF | SSW_P | fc, "pc + scan", 0, has_nmpc, null); + } + + private void fetchimm16(String reg, int fc) { + anyread16(reg, SSW_DF | SSW_P | fc, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 2"); + }); + } + + private void fetchimm32(String reg, int fc) { + anyread32(reg, SSW_DF | SSW_P | fc, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 4"); + }); + } + + private void fetch16(String reg, int fc, String aob) { + anyread16(reg, SSW_DF | SSW_P | fc, aob, 0, false, null); + } + + private void fetch32(String reg, int fc, String aob) { + fetch32(reg, fc, aob, 0); + } + + private void fetch32(String reg, int fc, String aob, int off) { + anyread32(reg, SSW_DF | SSW_P | fc, aob, off, false, null); + } + + private void read8(String reg, int fc, String aob) { + read8(reg, fc, aob, 0); + } + + private void read8(String reg, int fc, String aob, int off) { + anyread8(reg, SSW_DF | SSW_D | fc, aob, off); + } + + private void read16(String reg, int fc, String aob) { + read16(reg, fc, aob, 0); + } + + private void read16(String reg, int fc, String aob, int off) { + anyread16(reg, SSW_DF | SSW_D | fc, aob, off, false, null); + } + + private void read32(String reg, int fc, String aob) { + read32(reg, fc, aob, 0); + } + + private void read32(String reg, int fc, String aob, int off) { + anyread32(reg, SSW_DF | SSW_D | fc, aob, off, false, null); + } + + private void writevob(int fc, String aob, int format, int off) { + String vob = "tvn"; + if (format != 0) { + vob = String.format("0x%04x | %s", format << 12, vob); + } + write16(fc, aob, vob, off, false); + } + + private void write8(int fc, String aob, String value, int off, boolean has_nmpc) { + fc |= SSW_RR | SSW_BY; + + boolean critical = (fc & SSW_CR) != 0; + if ((!critical) && (!has_nmpc)) { + int nstate8 = blocks.size(); + + addFormattedMicroInsn("nmpc = %d", nstate8); + } + + addFormattedMicroInsn("elapsed += 4"); + + String address = setup_busaccess(fc, aob, off); + addFormattedMicroInsn("write8(%s, dob = %s)", address, value); + check_buserror(fc, "bevt"); + + if ((!critical) && (!has_nmpc)) { + blocks.add(new MicroBlock()); + } + } + + private void write16(int fc, String aob, String value, int off, boolean has_nmpc) { + write16(fc, aob, value, off, has_nmpc, null); + } + + private void write16(int fc, String aob, String value, int off, boolean has_nmpc, Runnable post) { + fc |= SSW_RR; + + boolean critical = (fc & SSW_CR) != 0; + int nstate16 = blocks.size(); + + if ((!critical) && (!has_nmpc)) { + addFormattedMicroInsn("nmpc = %d", nstate16); + } + + addFormattedMicroInsn("elapsed += 4"); + + String address = setup_busaccess(fc, aob, off); + addFormattedMicroInsn("write16(%s, dob = %s)", address, value); + if (post != null) { + post.run(); + } + check_buserror(fc, "bevt"); + + if ((!critical) && (!has_nmpc)) { + blocks.add(new MicroBlock()); + } + } + + private void write32(int fc, String aob, String value, int off, boolean has_nmpc) { + write32(fc, aob, value, off, has_nmpc, null); + } + + private void write32(int fc, String aob, String value, int off, boolean has_nmpc, Runnable post) { + fc |= SSW_RR | SSW_32 | SSW_WD; + + boolean critical = (fc & SSW_CR) != 0; + int nstate32 = blocks.size(); + + if (critical) { + addFormattedMicroInsn("elapsed += 8"); + } else { + if (!has_nmpc) { + addFormattedMicroInsn("nmpc = %d", nstate32); + } + addFormattedMicroInsn("elapsed += 4"); + } + + String address = setup_busaccess(fc, aob, off); + addFormattedMicroInsn("write32(%s, dob = %s)", address, value); + if (post != null) { + post.run(); + } + check_buserror(fc, "bevtw32"); + + if ((!critical) && (!has_nmpc)) { + blocks.add(new MicroBlock()); + } + } + + private void anyread8(String reg, int fc, String aob, int off) { + String dib = "dib"; + + fc |= SSW_RR | SSW_RW | SSW_BY; + + boolean critical = (fc & SSW_CR) != 0; + + if (!critical) { + int nstate8 = blocks.size(); + + addFormattedMicroInsn("nmpc = %d", nstate8); + } + + addFormattedMicroInsn("elapsed += 4"); + + String address = setup_busaccess(fc, aob, off); + addFormattedMicroInsn("%s = %s(%s)", critical && (reg != null) ? reg : dib, "read8", address); + check_buserror(fc, "bevt"); + addBeginFormattedControlFlow("if ((ssw & 0x%04x) == 0x%04x)", SSW_BY | SSW_HB, SSW_BY | SSW_HB); + addFormattedMicroInsn("%s >>= 8", critical && (reg != null) ? reg : dib); + addEndControlFlow(); + + if (!critical) { + blocks.add(new MicroBlock()); + + if (reg != null) { + addFormattedMicroInsn("%s = %s", reg, dib); + } + } + } + + private void anyread16(String reg, int fc, String aob, int off, boolean has_nmpc, Runnable post) { + String dib = (fc & SSW_IF) != 0 ? "irb" : "dib"; + + fc |= SSW_RR | SSW_RW; + + boolean critical = (fc & SSW_CR) != 0; + String function = "read16"; + + if ((fc & (SSW_P | SSW_D)) == SSW_P) { + function = "fetch16"; + } + + if ((!critical) && (!has_nmpc)) { + int nstate16 = blocks.size(); + + addFormattedMicroInsn("nmpc = %d", nstate16); + } + + addFormattedMicroInsn("elapsed += 4"); + + String address = setup_busaccess(fc, aob, off); + // addFormattedMicroInsn("%s = %s(%s)", dib, function, address); + addFormattedMicroInsn("%s = %s(%s)", critical && (reg != null) ? reg : dib, function, address); + if (post != null) { + post.run(); + } + check_buserror(fc, "bevt"); + + if (!has_nmpc) { + if (!critical) { + blocks.add(new MicroBlock()); + + if (reg != null) { + addFormattedMicroInsn("%s = %s", reg, dib); + } + } + } + } + + // XXX + private void anyread32(String reg, int fc, String aob, int off, boolean has_nmpc, Runnable post) { + String dib = (fc & SSW_IF) != 0 ? "irb" : "dib"; + + fc |= SSW_RR | SSW_32 | SSW_WD | SSW_RW; + + boolean critical = (fc & SSW_CR) != 0; + String function32 = "read32"; + String berr = "bevtr32"; + + if ((fc & (SSW_P | SSW_D)) == SSW_P) { + function32 = "fetch32"; + berr = "bevtf32"; + } + + if (critical) { + addFormattedMicroInsn("elapsed += 8"); + } else { + if (!has_nmpc) { + int nstate32 = blocks.size(); + + addFormattedMicroInsn("nmpc = %d", nstate32); + } + + addFormattedMicroInsn("elapsed += 4"); + } + + String address = setup_busaccess((fc & SSW_AC) != 0 ? fc | SSW_CR : fc, aob, off); + addFormattedMicroInsn("%s = %s(%s)", critical && (reg != null) ? reg : dib, function32, address); + if (post != null) { + post.run(); + } + check_buserror(fc, berr); + + if (!has_nmpc) { + if (!critical) { + blocks.add(new MicroBlock()); + + if (reg != null) { + addFormattedMicroInsn("%s = %s", reg, dib); + } + } + } + } + + private String setup_busaccess(int fc, String aob, int off) { + boolean supervisor = (fc & SSW_S) != 0; + boolean aligned = ((aob == null) && ((off & 0x0001) == 0)) || ((fc & (SSW_AL | SSW_BY)) != 0); + + String formatted = null; + + if (aob == null) { + formatted = String.format("aob = 0x%08x", off); + } else if (off == 0) { + formatted = String.format("aob = %s", aob); + } else if (off > 0) { + formatted = String.format("aob = %s + 0x%04x", aob, off); + } else { + formatted = String.format("aob = %s - 0x%04x", aob, -off); + } + + String expr = formatted; + + if (((fc & SSW_BY) == 0) && (!aligned)) { + formatted = "aob"; + } + + if (supervisor) { + addFormattedMicroInsn("ssw = (ssw & 0x%04x) | 0x%04x", SSW_RS.value | SSW_HL.value, (fc | SSW_S) & 0xffff); + } else { + addFormattedMicroInsn("ssw = (ssw & 0x%04x) | ((sr >> 11) & 0x%04x) | 0x%04x", SSW_RS.value | SSW_HL.value, + SSW_S, fc & 0xffff); + } + + if (((fc & SSW_BY) == 0) && (!aligned)) { + addBeginFormattedControlFlow("if (((%s) & 0x000000001) != 0)", expr); + if ((fc & SSW_CR) != 0) { + /* misaligned critical transfer, signal double bus fault */ + addFormattedMicroInsn("mpc = dbrr"); + addFormattedMicroInsn("continue"); + } else { + /* misaligned transfer, signal address error */ + addFormattedMicroInsn("mpc = aerr"); + addFormattedMicroInsn("continue"); + } + addEndControlFlow(); + } + + return formatted; + } + + // XXX + private void check_buserror(int fc, String berr) { + if ((fc & SSW_CR) != 0) { + addBeginFormattedControlFlow("if ((ssw & 0x%04x) != 0)", SSW_BR | SSW_RS.value); + addFormattedMicroInsn("mpc = dbrr"); + addFormattedMicroInsn("continue"); + } else { + if (((fc & SSW_32) != 0) && ((fc & SSW_WD) != 0)) { + addBeginFormattedControlFlow("if ((ssw & 0x%04x) != 0x%04x)", SSW_WD | SSW_BR | SSW_RS.value, SSW_WD); + } else { + addBeginFormattedControlFlow("if ((ssw & 0x%04x) != 0)", SSW_BR | SSW_RS.value); + + if (((fc & SSW_WD) != 0) && ((fc & SSW_RW) != 0)) { + /* + * indicate bus handler that this transfer is part of a 32 bits read access + * (saves dibh in stackframe) + */ + addFormattedMicroInsn("ssw |= 0x%04x", SSW_WD); + } + } + addFormattedMicroInsn("mpc = %s", berr); + addFormattedMicroInsn("continue"); + } + addEndControlFlow(); + } + + private void consume(int cycles, int read, int write) { + int consumed = cycles - (read * 4) - (write * 4); + + if (consumed > 0) { + addFormattedMicroInsn("elapsed += %d", consumed); + } else if (cycles < 0) { + addFormattedMicroInsn("elapsed -= %d", -consumed); + } + } + + private void setclr16(String reg, int set, int clr) { + int eclr = clr & ~set & 0xffff; + + set &= 0xffff; + + if ((set != 0) && (eclr != 0)) { + addFormattedMicroInsn("%s = (%s & ~0x%04x) | 0x%04x", reg, reg, eclr, set); + } else if (set == 0) { + if (eclr == 0xffff) { + addFormattedMicroInsn("%s = 0x%04x", reg, 0); + } else if (eclr != 0) { + addFormattedMicroInsn("%s &= ~0x%04x", reg, eclr); + } + } else if (eclr == 0) { + if ((set & 0xffff) == 0xffff) { + addFormattedMicroInsn("%s = 0x%04x", reg, set); + } else { + addFormattedMicroInsn("%s |= 0x%04x", reg, set); + } + } + } + + private void setclr32(String reg, int set, int clr) { + int eclr = clr & ~set; + + if ((set != 0) && (eclr != 0)) { + addFormattedMicroInsn("%s = (%s & ~0x%08x) | 0x%08x", reg, reg, eclr, set); + } else if (set == 0) { + if (~eclr == 0) { + addFormattedMicroInsn("%s = 0x%08x", reg, 0); + } else if (eclr != 0) { + addFormattedMicroInsn("%s &= ~0x%08x", reg, eclr); + } + } else if (eclr == 0) { + if (set == 0xffffffff) { + addFormattedMicroInsn("%s = 0x%08x", reg, set); + } else { + addFormattedMicroInsn("%s |= 0x%08x", reg, set); + } + } + } + + private void setclr(String reg, int set, int clr) { + if (((set & 0xffff0000) == 0) && ((clr & 0xffff0000) == 0)) { + setclr16(reg, set, clr); + } else { + setclr32(reg, set, clr); + } + } + + private void settvn(int tvn) { + addFormattedMicroInsn("tvn = %d", tvn << 2); + } + + private void addState(String name) { + MicroBlock block = new MicroBlock(); + + block.name = name; + blocks.add(block); + } + + private void addMicroInsn(MicroInsn insn, boolean clrssw) { + if (blocks.isEmpty()) { + blocks.add(new MicroBlock()); + } + + MicroBlock block = blocks.get(blocks.size() - 1); + + block.instructions.add(insn); + + if (clrssw) { + block.instructions.remove(block.sswclr); + block.sswclr = insn; + } + } + + private void addFormattedMicroInsn(String expression, Object... args) { + addMicroInsn((builder) -> { + builder.addStatement(String.format(expression, args)); + }, false); + } + + private void addBeginFormattedControlFlow(String expression, Object... args) { + addMicroInsn((builder) -> { + builder.beginControlFlow(String.format(expression, args)); + }, false); + } + + private void addNextFormattedControlFlow(String expression, Object... args) { + addMicroInsn((builder) -> { + builder.nextControlFlow(String.format(expression, args)); + }, false); + } + + private void addEndControlFlow() { + addMicroInsn((builder) -> { + builder.endControlFlow(); + }, false); + } + + /** + * This SSW bits must be cleared for each transfer + */ + private static final int SSW_MASK = SSW_RR | SSW_IF | SSW_DF | SSW_RM | SSW_HB | SSW_BY | SSW_RW | SSW_32 | SSW_WD + | SSW_BR | SSW_S | SSW_P | SSW_D; + + private void addClearSSW() { + addMicroInsn((builder) -> { + builder.addStatement(String.format("ssw &= ~0x%04x", SSW_MASK)); + }, true); + } + + private void unclearSSW() { + if (!blocks.isEmpty()) { + MicroBlock block = blocks.get(blocks.size() - 1); + + block.instructions.remove(block.sswclr); + block.sswclr = null; + } + } + + public String getStateName(int address) { + MicroBlock block = blocks.get(address); + + return block.name; + } + + public int getStateAddress(String name) { + int length = blocks.size(); + for (int address = 0; address < length; address++) { + MicroBlock block = blocks.get(address); + + if (name.equals(block.name)) { + return address; + } + } + + return -1; + } + +} diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java new file mode 100644 index 0000000..6ecab69 --- /dev/null +++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java @@ -0,0 +1,1247 @@ +package miggy.cpu.genpoet; + +import static javax.lang.model.element.Modifier.FINAL; +import static javax.lang.model.element.Modifier.PRIVATE; +import static javax.lang.model.element.Modifier.PUBLIC; +import static javax.lang.model.element.Modifier.STATIC; + +import java.io.IOException; +import java.util.ArrayList; +import java.util.List; +import java.util.Map; +import java.util.Map.Entry; +import java.util.Objects; +import java.util.Set; +import java.util.TreeMap; +import java.util.TreeSet; + +import com.squareup.javapoet.ClassName; +import com.squareup.javapoet.CodeBlock; +import com.squareup.javapoet.FieldSpec; +import com.squareup.javapoet.JavaFile; +import com.squareup.javapoet.MethodSpec; +import com.squareup.javapoet.TypeSpec; + +public class CorePLAGenerator { + + private static final int EA_AIS = 0x0001; + private static final int EA_AIPS = 0x0002; + private static final int EA_PAIS = 0x0004; + private static final int EA_DAS = 0x0008; + private static final int EA_DAIS = 0x0010; + private static final int EA_ADR16 = 0x0020; + private static final int EA_ADR32 = 0x0040; + private static final int EA_DPC = 0x0080; + private static final int EA_DPCI = 0x0100; + private static final int EA_IMM = 0x0200; /* always fetched, no address */ + private static final int EA_FETCH = 0x8000; + + private static final int EA_ALL = EA_AIS | EA_AIPS | EA_PAIS | EA_DAS | EA_DAIS | EA_ADR16 | EA_ADR32 | EA_DPC + | EA_DPCI | EA_IMM; + private static final int EA_MEM = EA_ALL & (~EA_IMM); + private static final int EA_CTRL = EA_MEM & (~(EA_AIPS | EA_PAIS)); + private static final int EA_MALT = EA_MEM & (~(EA_DPC | EA_DPCI)); + + private static String move(CoreGenerator gen, String size, String src, String dst) { + return gen.gen_move(size, src, dst); + } + + private static String dyadic(CoreGenerator gen, String op, String size, String src, String dst) { + return gen.gen_dyadic(op, size, src, dst); + } + +// private static String dyadic(CoreGenerator gen, String name, String op, String size, String src, String dst, boolean update) { +// return gen.gen_dyadic(name, op, size, src, dst, update); +// } +// +// private static String dyadic(CoreGenerator gen, String op, String size, String src, String dst, boolean update) { +// return gen.gen_dyadic(op, op, size, src, dst, update); +// } + + private static String monadic(CoreGenerator gen, String op, String size, String dst) { + return gen.gen_monadic(op, size, dst); + } + + public static void fillops(CoreGenerator gen, List entries, MacroEntry[] array) { + appendOP_eas(0x0000, 0xffc0, "ori_b_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "or", "b", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "or", "b", "imm8", "ea")); + }); + appendOP_eas(0x0040, 0xffc0, "ori_w_imm16", EA_FETCH | EA_MALT, "16", dyadic(gen, "or", "w", "imm16", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "or", "w", "imm16", "ea")); + }); + appendOP_eas(0x0080, 0xffc0, "ori_l_imm32", EA_FETCH | EA_MALT, "32", dyadic(gen, "or", "l", "imm32", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, mode == 0 ? "dbrr" : dyadic(gen, "or", "l", "imm32", "ea")); + }); + + appendOP(gen, entries, array, 0x003c, 0xffff, "ori_imm8_ccr", "op_imm16", dyadic(gen, "or", "b", "imm8", "ccr"), "dbrr"); + appendOP(gen, entries, array, 0x007c, 0xffff, "ori_i16u_sr", "op_imm16", dyadic(gen, "or", "w", "imm16", "sr"), "dbrr"); + + appendOP_eas(0x0100, 0xf1c0, "btst_dd", EA_FETCH | EA_ALL, "8", dyadic(gen, "btst", "l", "dd", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", mode == 0 ? "dbrr" : dyadic(gen, "btst", "b", "dd", "ea")); + }); + + appendOP(gen, entries, array, 0x0108, 0xf1f8, "movep_w_das_dd", "ea_das16", "dbrr", "op_movepw_das_dd"); + + appendOP_eas(0x0140, 0xf1c0, "bchg_dd", EA_FETCH | EA_MALT, "8", dyadic(gen, "bchg", "l", "dd", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", mode == 0 ? "dbrr" : dyadic(gen, "bchg", "b", "dd", "ea")); + }); + + appendOP(gen, entries, array, 0x0148, 0xf1f8, "movep_l_das_dd", "ea_das32", "dbrr", "op_movepl_das_dd"); + + appendOP_eas(0x0180, 0xf1c0, "bclr_dd", EA_FETCH | EA_MALT, "8", dyadic(gen, "bclr", "l", "dd", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", mode == 0 ? "dbrr" : dyadic(gen, "bclr", "b", "dd", "ea")); + }); + + appendOP(gen, entries, array, 0x0188, 0xf1f8, "movep_w_dd_das", "ea_das16", "dbrr", "op_movepw_dd_das"); + + appendOP_eas(0x01c0, 0xf1c0, "bset_dd", EA_FETCH | EA_MALT, "8", dyadic(gen, "bset", "l", "dd", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", mode == 0 ? "dbrr" : dyadic(gen, "bset", "b", "dd", "ea")); + }); + + appendOP(gen, entries, array, 0x01c8, 0xf1f8, "movep_l_dd_das", "ea_das32", "dbrr", "op_movepl_dd_das"); + + appendOP_eas(0x0200, 0xffc0, "andi_b_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "and", "b", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "and", "b", "imm8", "ea")); + }); + appendOP_eas(0x0240, 0xffc0, "andi_w_imm16", EA_FETCH | EA_MALT, "16", dyadic(gen, "and", "w", "imm16", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "and", "w", "imm16", "ea")); + }); + appendOP_eas(0x0280, 0xffc0, "andi_l_imm32", EA_FETCH | EA_MALT, "32", dyadic(gen, "and", "l", "imm32", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, mode == 0 ? "dbrr" : dyadic(gen, "and", "l", "imm32", "ea")); + }); + + appendOP(gen, entries, array, 0x023c, 0xffff, "andi_imm8_ccr", "op_imm16", dyadic(gen, "and", "b", "imm8", "ccr"), "dbrr"); + appendOP(gen, entries, array, 0x027c, 0xffff, "andi_i16u_sr", "op_imm16", dyadic(gen, "and", "w", "imm16", "sr"), "dbrr"); + + appendOP_eas(0x0400, 0xffc0, "subi_b_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "sub", "b", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "sub", "b", "imm8", "ea")); + }); + appendOP_eas(0x0440, 0xffc0, "subi_w_imm16", EA_FETCH | EA_MALT, "16", dyadic(gen, "sub", "w", "imm16", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "sub", "w", "imm16", "ea")); + }); + appendOP_eas(0x0480, 0xffc0, "subi_l_imm32", EA_FETCH | EA_MALT, "32", dyadic(gen, "sub", "l", "imm32", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, mode == 0 ? "dbrr" : dyadic(gen, "sub", "l", "imm32", "ea")); + }); + + appendOP_eas(0x0600, 0xffc0, "addi_b_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "add", "b", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "add", "b", "imm8", "ea")); + }); + appendOP_eas(0x0640, 0xffc0, "addi_w_imm16", EA_FETCH | EA_MALT, "16", dyadic(gen, "add", "w", "imm16", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "add", "w", "imm16", "ea")); + }); + appendOP_eas(0x0680, 0xffc0, "addi_l_imm32", EA_FETCH | EA_MALT, "32", dyadic(gen, "add", "l", "imm32", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, mode == 0 ? "dbrr" : dyadic(gen, "add", "l", "imm32", "ea")); + }); + + appendOP_eas(0x0800, 0xffc0, "btst_imm8", EA_FETCH | EA_MEM, "8", dyadic(gen, "btst", "l", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "btst", "b", "imm8", "ea")); + }); + appendOP_eas(0x0840, 0xffc0, "bchg_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "bchg", "l", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "bchg", "b", "imm8", "ea")); + }); + appendOP_eas(0x0880, 0xffc0, "bclr_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "bclr", "l", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "bclr", "b", "imm8", "ea")); + }); + appendOP_eas(0x08c0, 0xffc0, "bset_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "bset", "l", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "bset", "b", "imm8", "ea")); + }); + + appendOP_eas(0x0a00, 0xffc0, "eori_b_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "eor", "b", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "eor", "b", "imm8", "ea")); + }); + appendOP_eas(0x0a40, 0xffc0, "eori_w_imm16", EA_FETCH | EA_MALT, "16", dyadic(gen, "eor", "w", "imm16", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "eor", "w", "imm16", "ea")); + }); + appendOP_eas(0x0a80, 0xffc0, "eori_l_imm32", EA_FETCH | EA_MALT, "32", dyadic(gen, "eor", "l", "imm32", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, mode == 0 ? "dbrr" : dyadic(gen, "eor", "l", "imm32", "ea")); + }); + + appendOP(gen, entries, array, 0x0a3c, 0xffff, "eori_imm8_ccr", "op_imm16", dyadic(gen, "eor", "b", "imm8", "ccr"), "dbrr"); + appendOP(gen, entries, array, 0x0a7c, 0xffff, "eori_i16u_sr", "op_imm16", dyadic(gen, "eor", "w", "imm8", "sr"), "dbrr"); + + appendOP_eas(0x0c00, 0xffc0, "cmpi_b_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "cmp", "b", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "cmp", "b", "imm8", "ea")); + }); + appendOP_eas(0x0c40, 0xffc0, "cmpi_w_imm16", EA_FETCH | EA_MALT, "16", dyadic(gen, "cmp", "w", "imm16", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "cmp", "w", "imm16", "ea")); + }); + appendOP_eas(0x0c80, 0xffc0, "cmpi_l_imm32", EA_FETCH | EA_MALT, "32", dyadic(gen, "cmp", "l", "imm32", "ds"), null, (opcode, opmask, opname, n2, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, mode == 0 ? "dbrr" : dyadic(gen, "cmp", "l", "imm32", "ea")); + }); + + appendOP_eas(0x1000, 0xf000, "move_b", EA_FETCH | EA_ALL, "8", move(gen , "b", "ds", "ea"), null, (scode, smask, sname, n1, smode) -> { + appendOP_ead(scode, smask, sname, EA_MALT, "8", move(gen , "b", "ea", "dd"), null, (opcode, opmask, opname, n3, dmode) -> { + if ((smode == 0) && (dmode == 0)) { + appendOP(gen, entries, array, opcode, opmask, opname, move(gen , "b", "ds", "dd"), "dbrr", "dbrr"); + } else if (smode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n3, n1, "dbrr"); + } else if (dmode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", n3); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, move(gen , "b", "ea", "ea"), n3); + } + }); + }); + + appendOP_eas(0x2000, 0xf000, "move_l", EA_FETCH | EA_ALL, "32", move(gen , "l", "ds", "ea"), move(gen , "l", "as", "ea"), (scode, smask, sname, n1, smode) -> { + appendOP_ead(scode, smask, sname, EA_MALT, "32", move(gen , "l", "ea", "dd"), null, (opcode, opmask, opname, n3, dmode) -> { + if ((smode == 0) && (dmode == 0)) { + appendOP(gen, entries, array, opcode, opmask, opname, move(gen , "l", (opcode & 0x38) == 8 ? "as" : "ds", "dd"), "dbrr", "dbrr"); + } else if (smode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n3, n1, "dbrr"); + } else if (dmode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", n3); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, move(gen , "l", "ea", "ea"), n3); + } + }); + }); + + appendOP_eas(0x2040, 0xf1c0, "movea_l", EA_FETCH | EA_ALL, "32", move(gen , "l", "ds", "ad"), move(gen , "l", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_ad", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", move(gen , "l", "ea", "ad")); + } + }); + + appendOP_eas(0x3000, 0xf000, "move_w", EA_FETCH | EA_ALL, "16", move(gen , "w", "ds", "ea"), move(gen , "w", "as", "ea"), (scode, smask, sname, n1, smode) -> { + appendOP_ead(scode, smask, sname, EA_MALT, "16", move(gen , "w", "ea", "dd"), null, (opcode, opmask, opname, n3, dmode) -> { + if ((smode == 0) && (dmode == 0)) { + appendOP(gen, entries, array, opcode, opmask, opname, move(gen , "w", (opcode & 0x38) == 8 ? "as" : "ds", "dd"), "dbrr", "dbrr"); + } else if (smode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n3, n1, "dbrr"); + } else if (dmode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", n3); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, move(gen , "w", "ea", "ea"), n3); + } + }); + }); + + appendOP_eas(0x3040, 0xf1c0, "movea_w", EA_FETCH | EA_ALL, "16", move(gen , "w", "ds", "ad"), move(gen , "w", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_ad", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", move(gen , "w", "ea", "ad")); + } + }); + + appendOP_eas(0x4000, 0xffc0, "negx_b", EA_FETCH | EA_MALT, "8", monadic(gen, "negx", "b", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "negx", "b", "ea")); + } + }); + appendOP_eas(0x4040, 0xffc0, "negx_w", EA_FETCH | EA_MALT, "16", monadic(gen, "negx", "w", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "negx", "w", "ea")); + } + }); + appendOP_eas(0x4080, 0xffc0, "negx_l", EA_FETCH | EA_MALT, "32", monadic(gen, "negx", "l", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "negx", "l", "ea")); + } + }); + + appendOP_eas(0x40c0, 0xffc0, "move_sr", EA_MALT, "16", move(gen , "w", "sr", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", move(gen , "w", "sr", "ea")); + } + }); + + appendOP_eas(0x4180, 0xf1c0, "chk_w", EA_FETCH | EA_ALL, "16", "op_chk_w_ds", null, (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", mode == 0 ? "dbrr" : "op_chk_w_ea"); + }); + + appendOP_eas(0x42c0, 0xffc0, "move_ccr", EA_MALT, "16", move(gen , "w", "ccr", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", move(gen , "w", "ccr", "ea")); + } + }); + + appendOP_eas(0x44c0, 0xffc0, "move", EA_FETCH | EA_ALL, "16", move(gen , "w", "ds", "ccr"), null, (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_ccr", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", move(gen , "w", "ea", "ccr")); + } + }); + + appendOP_eas(0x46c0, 0xffc0, "move", EA_FETCH | EA_ALL, "16", move(gen , "w", "ds", "sr"), null, (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_sr", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", move(gen , "w", "ea", "sr")); + } + }); + + appendOP_eas(0x41d0, 0xf1c0, "lea", EA_CTRL, "16", (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_ad", opname); + + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_lea_ea_ad"); + }); + + appendOP_eas(0x4200, 0xffc0, "clr_b", EA_MALT, "8", "op_clrb_ds", null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_clrb_ea"); + } + }); + appendOP_eas(0x4240, 0xffc0, "clr_w", EA_MALT, "16", "op_clrw_ds", null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_clrw_ea"); + } + }); + appendOP_eas(0x4280, 0xffc0, "clr_l", EA_MALT, "32", "op_clrl_ds", null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_clrl_ea"); + } + }); + + appendOP_eas(0x4400, 0xffc0, "neg_b", EA_FETCH | EA_MALT, "8", monadic(gen, "neg", "b", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "neg", "b", "ea")); + } + }); + appendOP_eas(0x4440, 0xffc0, "neg_w", EA_FETCH | EA_MALT, "16", monadic(gen, "neg", "w", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "neg", "l", "ea")); + } + }); + appendOP_eas(0x4480, 0xffc0, "neg_l", EA_FETCH | EA_MALT, "32", monadic(gen, "neg", "l", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "neg", "l", "ea")); + } + }); + + appendOP_eas(0x4600, 0xffc0, "not_b", EA_FETCH | EA_MALT, "8", monadic(gen, "not", "b", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "not", "b", "ea")); + } + }); + appendOP_eas(0x4640, 0xffc0, "not_w", EA_FETCH | EA_MALT, "16", monadic(gen, "not", "w", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "not", "w", "ea")); + } + }); + appendOP_eas(0x4680, 0xffc0, "not_l", EA_FETCH | EA_MALT, "32", monadic(gen, "not", "l", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "not", "l", "ea")); + } + }); + + appendOP_eas(0x4800, 0xffc0, "nbcd_b", EA_FETCH | EA_MALT, "8", monadic(gen, "nbcd", "b", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "nbcd", "b", "ea")); + } + }); + + appendOP(gen, entries, array, 0x4840, 0xfff8, "swap_ds", "op_swap_ds", "dbrr", "dbrr"); + + appendOP_eas(0x4850, 0xffc0, "pea", EA_CTRL, "16", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_pea"); + }); + + appendOP(gen, entries, array, 0x4880, 0xfff8, "ext_w_ds", "op_extw_ds", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x48c0, 0xfff8, "ext_l_ds", "op_extl_ds", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x49c0, 0xfff8, "extb_l_ds", "op_extbl_ds", "dbrr", "dbrr"); + + appendOP_eas(0x4a00, 0xffc0, "tst_b", EA_FETCH | EA_MALT, "8", monadic(gen, "tst", "b", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "tst", "b", "ea")); + } + }); + appendOP_eas(0x4a40, 0xffc0, "tst_w", EA_FETCH | EA_MALT, "16", monadic(gen, "tst", "w", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "tst", "w", "ea")); + } + }); + appendOP_eas(0x4a80, 0xffc0, "tst_l", EA_FETCH | EA_MALT, "32", monadic(gen, "tst", "l", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "tst", "l", "ea")); + } + }); + + appendOP(gen, entries, array, 0x4848, 0xfff8, "bkpt", "op_bkpt", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x4afc, 0xffff, "illegal", "op_illegal", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x4e40, 0xfff0, "trap_imm4", "op_trap", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x4e50, 0xfff8, "link_as_imm16", "op_imm16", "op_link_as_imm16", "dbrr"); + appendOP(gen, entries, array, 0x4808, 0xfff8, "link_as_imm32", "op_imm32", "op_link_as_imm32", "dbrr"); + appendOP(gen, entries, array, 0x4e58, 0xfff8, "unlk_as", "op_unlk_as", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x4e60, 0xfff8, "move_as_usp", "op_move_as_usp", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x4e68, 0xfff8, "move_usp_as", "op_move_usp_as", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x4e70, 0xffff, "reset", "op_reset", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x4e71, 0xffff, "nop", "op_nop", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x4e72, 0xffff, "stop_i16u", "op_imm16", "op_stop", "dbrr"); + appendOP(gen, entries, array, 0x4e73, 0xffff, "rte", "op_rte", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x4e75, 0xffff, "rts", "op_rts", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x4e76, 0xffff, "trapv", "op_trapv", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x4e77, 0xffff, "rtr", "op_rtr", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x4e7a, 0xffff, "movec_cr_rz", "op_movec_cr_rz", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x4e7b, 0xffff, "movec_rz_cr", "op_movec_rz_cr", "dbrr", "dbrr"); + + appendOP_eas(0x4e90, 0xffc0, "jsr", EA_CTRL, "16", (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s", opname); + + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_jsr"); + }); + + appendOP_eas(0x4ec0, 0xffc0, "jmp", EA_CTRL, "16", (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s", opname); + + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_jmp"); + }); + + appendOP_eas(0x5000, 0xf1c0, "addq_b_imm3", EA_FETCH | EA_MALT, "8", dyadic(gen, "add", "b", "imm3", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "b", "imm3", "ea")); + } + }); + appendOP_eas(0x5040, 0xf1c0, "addq_w_imm3", EA_FETCH | EA_MALT, "16", dyadic(gen, "add", "w", "imm3", "ds"), dyadic(gen, "add", "w", "imm3", "as"), (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "w", "imm3", "ea")); + } + }); + appendOP_eas(0x5080, 0xf1c0, "addq_l_imm3", EA_FETCH | EA_MALT, "32", dyadic(gen, "add", "l", "imm3", "ds"), dyadic(gen, "add", "l", "imm3", "as"), (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "l", "imm3", "ea")); + } + }); + + appendOP(gen, entries, array, 0x50c8, 0xf0f8, "dbcc", "op_dbcc", "dbrr", "dbrr"); + + appendOP_eas(0x5100, 0xf1c0, "subq_b_imm3", EA_FETCH | EA_MALT, "8", dyadic(gen, "sub", "b", "imm3", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "b", "imm3", "ea")); + } + }); + appendOP_eas(0x5140, 0xf1c0, "subq_w_imm3", EA_FETCH | EA_MALT, "16", dyadic(gen, "sub", "w", "imm3", "ds"), dyadic(gen, "sub", "w", "imm3", "as"), (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "w", "imm3", "ea")); + } + }); + appendOP_eas(0x5180, 0xf1c0, "subq_l_imm3", EA_FETCH | EA_MALT, "32", dyadic(gen, "sub", "l", "imm3", "ds"), dyadic(gen, "sub", "l", "imm3", "as"), (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "l", "imm3", "ea")); + } + }); + + appendOP_eas(0x50c0, 0xf0c0, "scc_b", EA_MALT, "8", "op_scc_b_ds", null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_scc_b_ea"); + } + }); + + appendOP(gen, entries, array, 0x50fa, 0xf0ff, "trapcc16", "op_trapcc16", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x50fb, 0xf0ff, "trapcc32", "op_trapcc32", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x50fc, 0xf0ff, "trapcc", "op_trapcc", "dbrr", "dbrr"); + + appendOP(gen, entries, array, 0x6000, 0xff00, "bra_rel8", "op_bra8", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x6000, 0xffff, "bra_rel16", "op_imm16", "op_bra16", "dbrr"); + appendOP(gen, entries, array, 0x60ff, 0xffff, "bra_rel32", "op_imm32", "op_bra32", "dbrr"); + appendOP(gen, entries, array, 0x6100, 0xff00, "bsr_rel8", "op_bsr8", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x6100, 0xffff, "bsr_rel16", "op_imm16", "op_bsr16", "dbrr"); + appendOP(gen, entries, array, 0x61ff, 0xffff, "bsr_rel32", "op_imm32", "op_bsr32", "dbrr"); + appendOP(gen, entries, array, 0x6000, 0xf000, "bcc_rel8", "op_bcc8", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x6000, 0xf0ff, "bcc_rel16", "op_imm16", "op_bcc16", "dbrr"); + appendOP(gen, entries, array, 0x60ff, 0xf0ff, "bcc_rel32", "op_imm32", "op_bcc32", "dbrr"); + + appendOP(gen, entries, array, 0x7000, 0xf100, "moveq_imm8o_dd", move(gen, "l", "imm8o", "dd"), "dbrr", "dbrr"); + + appendOP_eas(0x8000, 0xf1c0, "or_b", EA_FETCH | EA_ALL, "8", dyadic(gen, "or", "b", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "or", "b", "ea", "dd")); + } + }); + appendOP_eas(0x8040, 0xf1c0, "or_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "or", "w", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "or", "w", "ea", "dd")); + } + }); + appendOP_eas(0x8080, 0xf1c0, "or_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "or", "l", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "or", "l", "ea", "dd")); + } + }); + + appendOP(gen, entries, array, 0x8100, 0xf1f8, "sbcd_ds_dd", dyadic(gen, "sbcd", "b", "ds", "dd"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x8108, 0xf1f8, "sbcd_pais_paid", "ea_pais8_read", dyadic(gen, "sbcd", "b", "ea", "ea"), "ea_paid8_read"); + + appendOP_eas(0x8100, 0xf1c0, "or_b_dd", EA_FETCH | EA_MALT, "8", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "or", "b", "dd", "ea")); + }); + appendOP_eas(0x8140, 0xf1c0, "or_w_dd", EA_FETCH | EA_MALT, "16", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "or", "w", "dd", "ea")); + }); + appendOP_eas(0x8180, 0xf1c0, "or_l_dd", EA_FETCH | EA_MALT, "32", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "or", "l", "dd", "ea")); + }); + + appendOP_eas(0x9000, 0xf1c0, "sub_b", EA_FETCH | EA_ALL, "8", dyadic(gen, "sub", "b", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "b", "ea", "dd")); + } + }); + appendOP_eas(0x9040, 0xf1c0, "sub_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "sub", "w", "ds", "dd"), dyadic(gen, "sub", "w", "as", "dd"), (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "w", "ea", "dd")); + } + }); + appendOP_eas(0x9080, 0xf1c0, "sub_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "sub", "l", "ds", "dd"), dyadic(gen, "sub", "l", "as", "dd"), (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "l", "ea", "dd")); + } + }); + appendOP_eas(0x9100, 0xf1c0, "sub_b_dd", EA_FETCH | EA_MALT, "8", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "b", "dd", "ea")); + }); + appendOP_eas(0x9150, 0xf1c0, "sub_w_dd", EA_FETCH | EA_MALT, "16", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "w", "dd", "ea")); + }); + appendOP_eas(0x9190, 0xf1c0, "sub_l_dd", EA_FETCH | EA_MALT, "32", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "l", "dd", "ea")); + }); + + appendOP(gen, entries, array, 0x9100, 0xf1f8, "subx_b_ds_dd", dyadic(gen, "subx", "b", "ds", "dd"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x9108, 0xf1f8, "subx_b_pais_paid", "ea_pais8_read", dyadic(gen, "subx", "b", "ea", "ea"), + "ea_paid8_read"); + appendOP(gen, entries, array, 0x9140, 0xf1f8, "subx_w_ds_dd", dyadic(gen, "subx", "w", "ds", "dd"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x9148, 0xf1f8, "subx_w_pais_paid", "ea_pais16_read", dyadic(gen, "subx", "w", "ea", "ea"), + "ea_paid16_read"); + appendOP(gen, entries, array, 0x9180, 0xf1f8, "subx_l_ds_dd", dyadic(gen, "subx", "l", "ds", "dd"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x9188, 0xf1f8, "subx_l_pais_paid", "ea_pais32_read", dyadic(gen, "subx", "l", "ea", "ea"), "ea_paid32_read"); + + appendOP_eas(0x90c0, 0xf1c0, "suba_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "sub", "w", "ds", "ad"), dyadic(gen, "sub", "w", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_ad", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "w", "ea", "ad")); + } + }); + appendOP_eas(0x91c0, 0xf1c0, "suba_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "sub", "l", "ds", "ad"), dyadic(gen, "sub", "l", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_ad", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "l", "ea", "ad")); + } + }); + + appendOP(gen, entries, array, 0xa000, 0xf000, "linea_imm12", "op_linea", "dbrr", "dbrr"); + + appendOP_eas(0xb000, 0xf1c0, "cmp_b", EA_FETCH | EA_ALL, "8", dyadic(gen, "cmp", "b", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "cmp", "b", "ea", "dd")); + } + }); + appendOP_eas(0xb040, 0xf1c0, "cmp_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "cmp", "w", "ds", "dd"), dyadic(gen, "cmp", "w", "as", "dd"), (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "cmp", "w", "ea", "dd")); + } + }); + appendOP_eas(0xb080, 0xf1c0, "cmp_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "cmp", "l", "ds", "dd"), dyadic(gen, "cmp", "l", "as", "dd"), (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "cmp", "l", "ea", "dd")); + } + }); + + appendOP_eas(0xb0c0, 0xf1c0, "cmpa_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "cmp", "w", "ds", "ad"), dyadic(gen, "cmp", "w", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_ad", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "cmp", "w", "ea", "ad")); + } + }); + appendOP_eas(0xb1c0, 0xf1c0, "cmpa_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "cmp", "l", "ds", "ad"), dyadic(gen, "cmp", "l", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_ad", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "cmp", "l", "ea", "ad")); + } + }); + + appendOP(gen, entries, array, 0xb108, 0xf1f8, "cmpm_b_aips_aipd", "ea_aips8_read", dyadic(gen, "cmpm", "b", "ea", "ea"), "ea_aipd8_read"); + appendOP(gen, entries, array, 0xb148, 0xf1f8, "cmpm_w_aips_aipd", "ea_aips16_read", dyadic(gen, "cmpm", "w", "ea", "ea"), "ea_aipd16_read"); + appendOP(gen, entries, array, 0xb188, 0xf1f8, "cmpm_l_aips_aipd", "ea_aips32_read", dyadic(gen, "cmpm", "l", "ea", "ea"), "ea_aipd32_read"); + + appendOP_eas(0xb100, 0xf1c0, "eor_b_dd", EA_FETCH | EA_MALT, "8", dyadic(gen, "eor", "b", "dd", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "eor", "b", "dd", "ea")); + } + }); + appendOP_eas(0xb140, 0xf1c0, "eor_w_dd", EA_FETCH | EA_MALT, "16", dyadic(gen, "eor", "w", "dd", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "eor", "w", "dd", "ea")); + } + }); + appendOP_eas(0xb180, 0xf1c0, "eor_l_dd", EA_FETCH | EA_MALT, "32", dyadic(gen, "eor", "l", "dd", "ds"), null, (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "eor", "l", "dd", "ea")); + } + }); + + appendOP_eas(0xc000, 0xf1c0, "and_b", EA_FETCH | EA_ALL, "8", dyadic(gen, "and", "b", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "and", "b", "ea", "dd")); + } + }); + appendOP_eas(0xc040, 0xf1c0, "and_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "and", "w", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "and", "w", "ea", "dd")); + } + }); + appendOP_eas(0xc080, 0xf1c0, "and_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "and", "l", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "and", "l", "ea", "dd")); + } + }); + + appendOP(gen, entries, array, 0xc140, 0xf1f8, "exg_dd_ds", "op_exg_dd_ds", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xc148, 0xf1f8, "exg_ad_as", "op_exg_ad_as", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xc188, 0xf1f8, "exg_dd_as", "op_exg_dd_as", "dbrr", "dbrr"); + + appendOP_eas(0xc100, 0xf1c0, "and_b_dd", EA_FETCH | EA_MALT, "8", (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "and", "b", "dd", "ea")); + } + }); + appendOP_eas(0xc140, 0xf1c0, "and_w_dd", EA_FETCH | EA_MALT, "16", (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "and", "w", "dd", "ea")); + } + }); + appendOP_eas(0xc180, 0xf1c0, "and_l_dd", EA_FETCH | EA_MALT, "32", (opcode, opmask, opname, n1, mode) -> { + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "and", "l", "dd", "ea")); + } + }); + + appendOP(gen, entries, array, 0xc100, 0xf1f8, "abcd_ds_dd", dyadic(gen, "abcd", "b", "ds", "dd"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xc108, 0xf1f8, "abcd_pais_paid", "ea_pais8_read", dyadic(gen, "abcd", "b", "ea", "ea"), "ea_paid8_read"); + + appendOP_eas(0xd000, 0xf1c0, "add_b", EA_FETCH | EA_ALL, "8", dyadic(gen, "add", "b", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "b", "ea", "dd")); + } + }); + appendOP_eas(0xd040, 0xf1c0, "add_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "add", "w", "ds", "dd"), dyadic(gen, "add", "w", "as", "dd"), (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "w", "ea", "dd")); + } + }); + appendOP_eas(0xd080, 0xf1c0, "add_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "add", "l", "ds", "dd"), dyadic(gen, "add", "l", "as", "dd"), (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_dd", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "l", "ea", "dd")); + } + }); + appendOP_eas(0xd100, 0xf1c0, "add_b_dd", EA_FETCH | EA_MALT, "8", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "b", "dd", "ea")); + }); + appendOP_eas(0xd150, 0xf1c0, "add_w_dd", EA_FETCH | EA_MALT, "16", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "w", "dd", "ea")); + }); + appendOP_eas(0xd190, 0xf1c0, "add_l_dd", EA_FETCH | EA_MALT, "32", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "l", "dd", "ea")); + }); + + appendOP(gen, entries, array, 0xd100, 0xf1f8, "addx_b_ds_dd", dyadic(gen, "addx", "b", "ds", "dd"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xd108, 0xf1f8, "addx_b_pais_paid", "ea_pais8_read", dyadic(gen, "addx", "b", "ea", "ea"), + "ea_paid8_read"); + appendOP(gen, entries, array, 0xd140, 0xf1f8, "addx_w_ds_dd", dyadic(gen, "addx", "w", "ds", "dd"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xd148, 0xf1f8, "addx_w_pais_paid", "ea_pais16_read", dyadic(gen, "addx", "w", "ea", "ea"), + "ea_paid16_read"); + appendOP(gen, entries, array, 0xd180, 0xf1f8, "addx_l_ds_dd", dyadic(gen, "addx", "l", "ds", "dd"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xd188, 0xf1f8, "addx_l_pais_paid", "ea_pais32_read", dyadic(gen, "addx", "l", "ea", "ea"), "ea_paid32_read"); + + appendOP_eas(0xd0c0, 0xf1c0, "adda_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "add", "w", "ds", "ad"), dyadic(gen, "add", "w", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_ad", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "w", "ea", "ad")); + } + }); + appendOP_eas(0xd1c0, 0xf1c0, "adda_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "add", "l", "ds", "ad"), dyadic(gen, "add", "l", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_ad", opname); + + if (mode == 0) { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); + } else { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "l", "ea", "ad")); + } + }); + + appendOP(gen, entries, array, 0xe000, 0xf1f8, "asr_b_imm3_ds", dyadic(gen, "asr", "b", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe020, 0xf1f8, "asr_b_dd_ds", dyadic(gen, "asr", "b", "dd", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe040, 0xf1f8, "asr_w_imm3_ds", dyadic(gen, "asr", "w", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe060, 0xf1f8, "asr_w_dd_ds", dyadic(gen, "asr", "w", "dd", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe080, 0xf1f8, "asr_l_imm3_ds", dyadic(gen, "asr", "l", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe0a0, 0xf1f8, "asr_l_dd_ds", dyadic(gen, "asr", "l", "dd", "ds"), "dbrr", "dbrr"); + appendOP_eas(0xe0d0, 0xffc0, "asr", EA_FETCH | EA_MALT, "16", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "asr", "w", "ea")); + }); + + appendOP(gen, entries, array, 0xe100, 0xf1f8, "asl_b_imm3_ds", dyadic(gen, "asl", "b", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe120, 0xf1f8, "asl_b_dd_ds", dyadic(gen, "asl", "b", "dd", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe140, 0xf1f8, "asl_w_imm3_ds", dyadic(gen, "asl", "w", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe160, 0xf1f8, "asl_w_dd_ds", dyadic(gen, "asl", "w", "dd", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe180, 0xf1f8, "asl_l_imm3_ds", dyadic(gen, "asl", "l", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe1a0, 0xf1f8, "asl_l_dd_ds", dyadic(gen, "asl", "l", "dd", "ds"), "dbrr", "dbrr"); + appendOP_eas(0xe1d0, 0xffc0, "asl", EA_FETCH | EA_MALT, "16", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "asl", "w", "ea")); + }); + + appendOP(gen, entries, array, 0xe008, 0xf1f8, "lsr_b_imm3_ds", dyadic(gen, "lsr", "b", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe028, 0xf1f8, "lsr_b_dd_ds", dyadic(gen, "lsr", "b", "dd", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe048, 0xf1f8, "lsr_w_imm3_ds", dyadic(gen, "lsr", "w", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe068, 0xf1f8, "lsr_w_dd_ds", dyadic(gen, "lsr", "w", "dd", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe088, 0xf1f8, "lsr_l_imm3_ds", dyadic(gen, "lsr", "l", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe0a8, 0xf1f8, "lsr_l_dd_ds", dyadic(gen, "lsr", "l", "dd", "ds"), "dbrr", "dbrr"); + appendOP_eas(0xe2d0, 0xffc0, "lsr", EA_FETCH | EA_MALT, "16", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "lsr", "w", "ea")); + }); + + appendOP(gen, entries, array, 0xe108, 0xf1f8, "lsl_b_imm3_ds", dyadic(gen, "lsl", "b", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe128, 0xf1f8, "lsl_b_dd_ds", dyadic(gen, "lsl", "b", "dd", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe148, 0xf1f8, "lsl_w_imm3_ds", dyadic(gen, "lsl", "w", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe168, 0xf1f8, "lsl_w_dd_ds", dyadic(gen, "lsl", "w", "dd", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe188, 0xf1f8, "lsl_l_imm3_ds", dyadic(gen, "lsl", "l", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe1a8, 0xf1f8, "lsl_l_dd_ds", dyadic(gen, "lsl", "l", "dd", "ds"), "dbrr", "dbrr"); + appendOP_eas(0xe3d8, 0xffc0, "lsl", EA_FETCH | EA_MALT, "16", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "lsl", "w", "ea")); + }); + + appendOP(gen, entries, array, 0xe018, 0xf1f8, "ror_b_imm3_ds", dyadic(gen, "ror", "b", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe038, 0xf1f8, "ror_b_dd_ds", dyadic(gen, "ror", "b", "dd", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe058, 0xf1f8, "ror_w_imm3_ds", dyadic(gen, "ror", "w", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe078, 0xf1f8, "ror_w_dd_ds", dyadic(gen, "ror", "w", "dd", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe098, 0xf1f8, "ror_l_imm3_ds", dyadic(gen, "ror", "l", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe0b8, 0xf1f8, "ror_l_dd_ds", dyadic(gen, "ror", "l", "dd", "ds"), "dbrr", "dbrr"); + appendOP_eas(0xe6d0, 0xffc0, "ror", EA_FETCH | EA_MALT, "16", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "ror", "w", "ea")); + }); + + appendOP(gen, entries, array, 0xe118, 0xf1f8, "rol_b_imm3_ds", dyadic(gen, "rol", "b", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe138, 0xf1f8, "rol_b_dd_ds", dyadic(gen, "rol", "b", "dd", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe158, 0xf1f8, "rol_w_imm3_ds", dyadic(gen, "rol", "w", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe178, 0xf1f8, "rol_w_dd_ds", dyadic(gen, "rol", "w", "dd", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe198, 0xf1f8, "rol_l_imm3_ds", dyadic(gen, "rol", "l", "imm3", "ds"), "dbrr", "dbrr"); + appendOP(gen, entries, array, 0xe1b8, 0xf1f8, "rol_l_dd_ds", dyadic(gen, "rol", "l", "dd", "ds"), "dbrr", "dbrr"); + appendOP_eas(0xe7d0, 0xffc0, "rol", EA_FETCH | EA_MALT, "16", (opcode, opmask, opname, n1, mode) -> { + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "rol", "w", "ea")); + }); + + appendOP(gen, entries, array, 0xf000, 0xf000, "linef_imm12", "op_linef", "dbrr", "dbrr"); + } + + public static void main(String[] args) throws IOException { + TreeMap macros = new TreeMap(); + TreeSet imports = new TreeSet(); + + CoreGenerator gen = new CoreGenerator(); + + fillops(gen, macros); + + JavaFile.Builder builder = JavaFile.builder("miggy.cpupoet", corePLAType(gen, macros, imports)); + + for (String item : imports) { + builder.addStaticImport(ClassName.get("miggy.cpupoet", "Core"), item); + } + + JavaFile javaFile = builder.build(); + + javaFile.writeTo(System.out); + } + + protected static void fillops(CoreGenerator gen, Map macros) { + List entries = new ArrayList(); + MacroEntry[] array = new MacroEntry[0xffff + 1]; + + fillops(gen, entries, array); + + for (MacroEntry entry : entries) { + for (OPEntry op : entry.ops) { + macros.put(op, entry); + } + } + } + + protected static TypeSpec corePLAType(CoreGenerator gen, Map macros, Set imports) { + TypeSpec.Builder builder = TypeSpec.enumBuilder("MacroPLA").addModifiers(PUBLIC); + ClassName platype = ClassName.get("miggy.cpupoet", "MacroPLA"); + ClassName plaarray = ClassName.get("miggy.cpupoet", "MacroPLA[]"); + + FieldSpec opcodes = FieldSpec.builder(plaarray, "DECODER", PRIVATE, STATIC, FINAL) + .initializer("new $T[0xffff + 1]", platype).build(); + + builder.addField(FieldSpec.builder(int.class, "opcode", PUBLIC, FINAL).build()); + builder.addField(FieldSpec.builder(int.class, "opmask", PUBLIC, FINAL).build()); + builder.addField(FieldSpec.builder(int.class, "a1", PUBLIC, FINAL).build()); + builder.addField(FieldSpec.builder(int.class, "a2", PUBLIC, FINAL).build()); + builder.addField(FieldSpec.builder(int.class, "a3", PUBLIC, FINAL).build()); + + for (Entry entry : macros.entrySet()) { + OPEntry op = entry.getKey(); + MacroEntry micro = entry.getValue(); + + String a1 = gen.getStateName(micro.a1); + String a2 = gen.getStateName(micro.a2); + String a3 = gen.getStateName(micro.a3); + + if (a1 != null) { + imports.add(a1); + } + + if (a2 != null) { + imports.add(a2); + } + + if (a3 != null) { + imports.add(a3); + } + + builder.addEnumConstant(op.name, TypeSpec.anonymousClassBuilder("$L, $L, $L, $L, $L", + opcodeLiteral(op.opcode), opcodeLiteral(op.mask), a1, a2, a3).build()); + } + + MethodSpec.Builder constructor = MethodSpec.constructorBuilder(); + + constructor.addModifiers(PRIVATE); + constructor.addParameter(int.class, "opcode"); + constructor.addParameter(int.class, "opmask"); + constructor.addParameter(int.class, "a1"); + constructor.addParameter(int.class, "a2"); + constructor.addParameter(int.class, "a3"); + + constructor.addStatement("this.opcode = opcode"); + constructor.addStatement("this.opmask = opmask"); + constructor.addStatement("this.a1 = a1"); + constructor.addStatement("this.a2 = a2"); + constructor.addStatement("this.a3 = a3"); + + builder.addMethod(constructor.build()); + builder.addField(opcodes); + + CodeBlock.Builder initializer = CodeBlock.builder(); + + initializer.beginControlFlow("for (MacroPLA insn : MacroPLA.values())"); + initializer.beginControlFlow( + "for (int ir = insn.opcode & insn.opmask; ir < DECODER.length; ir = maskedIncrement(ir, insn.opmask))"); + initializer.beginControlFlow("if ((ir & insn.opmask) == insn.opcode)"); + initializer.addStatement("int bits = 0"); + initializer.beginControlFlow("if (DECODER[ir] != null)"); + initializer.addStatement("bits = Integer.bitCount(DECODER[ir].opmask)"); + initializer.endControlFlow(); + initializer.beginControlFlow("if ((bits == 0) || (Integer.bitCount(insn.opmask) > bits))"); + initializer.addStatement("DECODER[ir] = insn"); + initializer.endControlFlow(); + initializer.endControlFlow(); + initializer.endControlFlow(); + initializer.endControlFlow(); + initializer.beginControlFlow("for (int ir = 0; ir < DECODER.length; ir++)"); + initializer.beginControlFlow("if (DECODER[ir] == null)"); + initializer.addStatement("DECODER[ir] = illegal"); + initializer.endControlFlow(); + initializer.endControlFlow(); + + builder.addStaticBlock(initializer.build()); + + MethodSpec.Builder increment = MethodSpec.methodBuilder("maskedIncrement"); + + increment.addModifiers(PRIVATE, STATIC, FINAL); + increment.returns(int.class).addParameter(int.class, "value").addParameter(int.class, "mask"); + + increment.addStatement("int variableBits = ~mask"); + increment.addStatement("int base = value & mask"); + increment.addStatement("int next = mask + (value & variableBits) + 1"); + increment.addStatement("return base + (next & variableBits)"); + + builder.addMethod(increment.build()); + + MethodSpec.Builder decoder = MethodSpec.methodBuilder("decode"); + decoder.addModifiers(PUBLIC, STATIC, FINAL); + decoder.addParameter(int.class, "ir"); + decoder.returns(platype); + decoder.addStatement("return $N[ir & 0xffff]", opcodes); + + builder.addMethod(decoder.build()); + + return builder.build(); + } + + private static String opcodeLiteral(int opcode) { + return String.format("0x%04x", opcode); + } + + interface EAConsumer { + void append(int opcode, int mask, String opname, String ea, int mode); + } + + public static void appendOP_ead(int opcode, int mask, String opname, int ea, String size, String ds, String as, EAConsumer consumer) { + if (ds != null) { + consumer.append((opcode & 0xfe3f) | 0x0000, (mask & 0xfe3f) | 0x01c0, String.format("%s_dd", opname), ds, 0x0000); + } + + if (as != null) { + consumer.append((opcode & 0xfe3f) | 0x0040, (mask & 0xfe3f) | 0x01c0, String.format("%s_ad", opname), as, 0x0000); + } + + appendOP_ead(opcode, mask, opname, ea, size, consumer); + } + + public static void appendOP_ead(int opcode, int mask, String opname, int ea, String size, EAConsumer consumer) { + if ((ea & EA_AIS) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_aid%s_read" : "ea_aid%s", size); + + consumer.append((opcode & 0xfe3f) | 0x0080, (mask & 0xfe3f) | 0x01c0, String.format("%s_aid", opname), n1, EA_AIS); + } + if ((ea & EA_AIPS) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_aipd%s_read" : "ea_aipd%s", size); + + consumer.append((opcode & 0xfe3f) | 0x00c0, (mask & 0xfe3f) | 0x01c0, String.format("%s_aipd", opname), n1, EA_AIPS); + } + if ((ea & EA_PAIS) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_paid%s_read" : "ea_paid%s", size); + + consumer.append((opcode & 0xfe3f) | 0x0100, (mask & 0xfe3f) | 0x01c0, String.format("%s_paid", opname), n1, EA_PAIS); + } + if ((ea & EA_DAS) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_dad%s_read" : "ea_dad%s", size); + + consumer.append((opcode & 0xfe3f) | 0x0140, (mask & 0xfe3f) | 0x01c0, String.format("%s_dad", opname), n1, EA_DAS); + } + if ((ea & EA_DAIS) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_daid%s_read" : "ea_daid%s", size); + + consumer.append((opcode & 0xfe3f) | 0x0180, (mask & 0xfe3f) | 0x01c0, String.format("%s_daid", opname), n1, EA_DAIS); + } + if ((ea & EA_ADR16) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_adr16d%s_read" : "ea_adr16d%s", size); + + consumer.append((opcode & 0xfe3f) | 0x01c0, (mask & 0xfe3f) | 0x0fc0, String.format("%s_adr16", opname), n1, EA_ADR16); + } + if ((ea & EA_ADR32) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_adr32d%s_read" : "ea_adr32d%s", size); + + consumer.append((opcode & 0xfe3f) | 0x03c0, (mask & 0xfe3f) | 0x0fc0, String.format("%s_adr32", opname), n1, EA_ADR32); + } + } + + public static void appendOP_eas(int opcode, int mask, String opname, int ea, String size, String ds, String as, EAConsumer consumer) { + if (ds != null) { + consumer.append((opcode & 0xffc0) | 0x0000, (mask & 0xffc0) | 0x0038, String.format("%s_ds", opname), ds, 0x0000); + } + + if (as != null) { + consumer.append((opcode & 0xffc0) | 0x0008, (mask & 0xffc0) | 0x0038, String.format("%s_as", opname), as, 0x0000); + } + + appendOP_eas(opcode, mask, opname, ea, size, consumer); + } + + public static void appendOP_eas(int opcode, int mask, String opname, int ea, String size, EAConsumer consumer) { + if ((ea & EA_AIS) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_ais%s_read" : "ea_ais%s", size); + + consumer.append((opcode & 0xffc0) | 0x0010, (mask & 0xffc0) | 0x0038, String.format("%s_ais", opname), n1, EA_AIS); + } + if ((ea & EA_AIPS) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_aips%s_read" : "ea_aips%s", size); + + consumer.append((opcode & 0xffc0) | 0x0018, (mask & 0xffc0) | 0x0038, String.format("%s_aips", opname), n1, EA_AIPS); + } + if ((ea & EA_PAIS) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_pais%s_read" : "ea_pais%s", size); + + consumer.append((opcode & 0xffc0) | 0x0020, (mask & 0xffc0) | 0x0038, String.format("%s_pais", opname), n1, EA_PAIS); + } + if ((ea & EA_DAS) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_das%s_read" : "ea_das%s", size); + + consumer.append((opcode & 0xffc0) | 0x0028, (mask & 0xffc0) | 0x0038, String.format("%s_das", opname), n1, EA_DAS); + } + if ((ea & EA_DAIS) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_dais%s_read" : "ea_dais%s", size); + + consumer.append((opcode & 0xffc0) | 0x0030, (mask & 0xffc0) | 0x0038, String.format("%s_dais", opname), n1, EA_DAIS); + } + if ((ea & EA_DPC) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_dpc%s_read" : "ea_dpc%s", size); + + consumer.append((opcode & 0xffc0) | 0x003a, (mask & 0xffc0) | 0x003f, String.format("%s_dpc", opname), n1, EA_DPC); + } + if ((ea & EA_DPCI) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_dpci%s_read" : "ea_dpci%s", size); + + consumer.append((opcode & 0xffc0) | 0x003b, (mask & 0xffc0) | 0x003f, String.format("%s_dpci", opname), n1, EA_DPCI); + } + if ((ea & EA_ADR16) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_adr16s%s_read" : "ea_adr16s%s", size); + + consumer.append((opcode & 0xffc0) | 0x0038, (mask & 0xffc0) | 0x003f, String.format("%s_adr16", opname), n1, EA_ADR16); + } + if ((ea & EA_ADR32) != 0) { + String n1 = String.format((ea & EA_FETCH) != 0 ? "ea_adr32s%s_read" : "ea_adr32s%s", size); + + consumer.append((opcode & 0xffc0) | 0x0039, (mask & 0xffc0) | 0x003f, String.format("%s_adr32", opname), n1, EA_ADR32); + } + if ((ea & EA_IMM) != 0) { + String n1 = String.format("ea_imm%s_read", size); + + consumer.append((opcode & 0xffc0) | 0x003c, (mask & 0xffc0) | 0x003f, String.format("%s_imm%s", opname, size), n1, EA_IMM); + } + } + + private static final int maskedIncrement(int value, int mask) { + int variableBits = ~mask; + int base = value & mask; + int next = mask + (value & variableBits) + 1; + return base + (next & variableBits); + } + + public static void appendOP(CoreGenerator gen, List entries, MacroEntry[] array, int opcode, int mask, + String opname, String n1, String n2, String n3) { + OPEntry op = new OPEntry(opname, opcode, mask); + int a1 = gen.getStateAddress(n1); + int a2 = gen.getStateAddress(n2); + int a3 = gen.getStateAddress(n3); + + if ((a1 < 0) || (a2 < 0) || (a3 < 0)) { + throw new IllegalStateException(); + } + + for (int ir = opcode & mask; ir <= 0xffff; ir = maskedIncrement(ir, mask)) { + if ((ir & mask) == opcode) { + MacroEntry entry = new MacroEntry(a1, a2, a3); + MacroEntry found = null; + + for (int i = 0; i < entries.size(); i++) { + if (entries.get(i).equals(entry)) { + found = entry = entries.get(i); + } + } + + if (found == null) { + entries.add(entry); + } + + array[ir] = entry; + + if (!array[ir].ops.contains(op)) { + array[ir].ops.add(op); + } + } + } + } + + protected static class OPEntry implements Comparable { + private String name; + private int opcode; + private int mask; + + public OPEntry(String name, int opcode, int mask) { + this.name = name; + this.opcode = opcode & mask; + this.mask = mask; + } + + @Override + public int hashCode() { + return Objects.hash(mask, opcode); + } + + @Override + public boolean equals(Object obj) { + if (this == obj) + return true; + if (obj == null) + return false; + if (getClass() != obj.getClass()) + return false; + OPEntry other = (OPEntry) obj; + return (opcode & mask) == (other.opcode & other.mask) && mask == other.mask; + } + + @Override + public int compareTo(OPEntry o) { + int res = Integer.compare(opcode, o.opcode); + + if (res == 0) { + res = Integer.compare(Integer.bitCount(o.mask & 0xffff), Integer.bitCount(mask & 0xffff)); + } + + return res; + } + } + + protected static class MacroEntry { + private List ops = new ArrayList(); + + protected final int a1; + protected final int a2; + protected final int a3; + + public MacroEntry(int a1, int a2, int a3) { + this.a1 = a1; + this.a2 = a2; + this.a3 = a3; + } + + @Override + public int hashCode() { + return Objects.hash(a1, a2, a3); + } + + @Override + public boolean equals(Object obj) { + if (this == obj) + return true; + if (obj == null) + return false; + if (getClass() != obj.getClass()) + return false; + MacroEntry other = (MacroEntry) obj; + return a1 == other.a1 && a2 == other.a2 && a3 == other.a3; + } + } + +} diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreVerifier.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreVerifier.java new file mode 100644 index 0000000..0ac0c32 --- /dev/null +++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreVerifier.java @@ -0,0 +1,71 @@ +package miggy.cpu.genpoet; + +import java.io.BufferedReader; +import java.io.IOException; +import java.io.InputStream; +import java.io.InputStreamReader; +import java.nio.charset.StandardCharsets; +import java.util.regex.Matcher; +import java.util.regex.Pattern; + +import miggy.cpupoet.MacroPLA; + +public class CoreVerifier { + public static final Pattern OP_PATTERN2 = Pattern.compile("^(\\S+)\\s+(\\S+)\\s+([\\S.]+)\\s+([\\S.]+)\\s+(\\S+).*"); + + public static void main(String[] args) throws NumberFormatException, IOException { + InputStream res = CoreVerifier.class.getResourceAsStream("m68000.lst"); + BufferedReader in = new BufferedReader(new InputStreamReader(res, StandardCharsets.UTF_8)); + + try { + String line = null; + + while((line = in.readLine()) != null) { + Matcher matcher = OP_PATTERN2.matcher(line); + + if (matcher.find()) { + String opname = matcher.group(3); + int opcode = Integer.parseInt(matcher.group(1), 16); + int mask = Integer.parseInt(matcher.group(2), 16); + String ea1 = matcher.group(4); + String ea2 = matcher.group(5); + + StringBuilder builder = new StringBuilder(); + + builder.append(opname.replace('.', '_')); + if (!"-".equals(ea1)) { + builder.append('_'); + builder.append(ea1); + } + if (!"-".equals(ea2)) { + builder.append('_'); + builder.append(ea2); + } + + String mnemonic = builder.toString(); + boolean found = false; + + for(MacroPLA entry : MacroPLA.values()) { + if ((opcode == entry.opcode) && (mask == entry.opmask)) { + found = true; + + if (!mnemonic.equals(entry.name())) { + System.out.println(String.format("mismatch for opcode 0x%04x (mask: 0x%04x) want '%s', got '%s'", opcode, mask, mnemonic, entry.name())); + } + + break; + } + } + + if (!found) { + System.out.println(String.format("opcode '%s' 0x%04x (mask: 0x%04x) not found", mnemonic, opcode, mask)); + } + } + } + } finally { + in.close(); + } + } + + +} diff --git a/miggy-emu/src/main/java/miggy/cpupoet/Core.java b/miggy-emu/src/main/java/miggy/cpupoet/Core.java new file mode 100644 index 0000000..9d58c12 --- /dev/null +++ b/miggy-emu/src/main/java/miggy/cpupoet/Core.java @@ -0,0 +1,6932 @@ +package miggy.cpupoet; + +public abstract class Core extends CoreALU { + private static final int reset = 0; + + protected static final int dbrr = 1; + + private static final int halt = 2; + + private static final int bevtf32 = 3; + + private static final int bevtr32 = 4; + + private static final int bevtw32 = 5; + + private static final int bevt = 6; + + private static final int berr = 7; + + private static final int aerr = 8; + + private static final int trap8000 = 9; + + private static final int resume_trap8000 = 10; + + private static final int resume_berr = 11; + + private static final int trap2000 = 12; + + private static final int trapill = 13; + + private static final int trap0000 = 14; + + private static final int enter_trap0000 = 15; + + private static final int uninitialized = 17; + + private static final int interrupt = 19; + + private static final int enter_irq = 21; + + private static final int execute_trap = 22; + + private static final int resume_prefetch = 23; + + private static final int resume = 24; + + private static final int resume_notrace = 25; + + protected static final int op_stop = 26; + + private static final int op_stop_loop = 27; + + private static final int ea_resume_write8 = 28; + + private static final int ea_resume_write16 = 31; + + private static final int ea_resume_write32 = 34; + + protected static final int op_imm16 = 37; + + protected static final int op_imm32 = 39; + + protected static final int ea_aid8 = 41; + + protected static final int ea_aid16 = 42; + + protected static final int ea_aid32 = 43; + + protected static final int ea_ais8_read = 44; + + protected static final int ea_ais8 = 45; + + private static final int ea_read8 = 46; + + protected static final int ea_ais16_read = 48; + + protected static final int ea_ais16 = 49; + + private static final int ea_read16 = 50; + + protected static final int ea_ais32_read = 52; + + protected static final int ea_ais32 = 53; + + private static final int ea_read32 = 54; + + protected static final int ea_aipd8_read = 56; + + protected static final int ea_aipd8 = 57; + + protected static final int ea_aipd16_read = 58; + + protected static final int ea_aipd16 = 59; + + protected static final int ea_aipd32_read = 60; + + protected static final int ea_aipd32 = 61; + + protected static final int ea_aips8_read = 62; + + protected static final int ea_aips8 = 63; + + protected static final int ea_aips16_read = 64; + + protected static final int ea_aips16 = 65; + + protected static final int ea_aips32_read = 66; + + protected static final int ea_aips32 = 67; + + protected static final int ea_paid8_read = 68; + + protected static final int ea_paid8 = 69; + + private static final int ead_read8 = 70; + + protected static final int ea_paid16_read = 72; + + protected static final int ea_paid16 = 73; + + private static final int ead_read16 = 74; + + protected static final int ea_paid32_read = 76; + + protected static final int ea_paid32 = 77; + + private static final int ead_read32 = 78; + + protected static final int ea_pais8_read = 80; + + protected static final int ea_pais8 = 81; + + protected static final int ea_pais16_read = 82; + + protected static final int ea_pais16 = 83; + + protected static final int ea_pais32_read = 84; + + protected static final int ea_pais32 = 85; + + protected static final int ea_dad8 = 86; + + protected static final int ea_dad16 = 88; + + protected static final int ea_dad32 = 90; + + protected static final int ea_das8_read = 92; + + protected static final int ea_das8 = 93; + + protected static final int ea_das16_read = 95; + + protected static final int ea_das16 = 96; + + protected static final int ea_das32_read = 98; + + protected static final int ea_das32 = 99; + + protected static final int ea_daid8 = 101; + + private static final int ea_daid8_base = 103; + + private static final int ea_daid8_no_base = 104; + + private static final int ea_daid8_outer = 106; + + private static final int ea_daid8_fetch = 107; + + protected static final int ea_daid16 = 108; + + private static final int ea_daid16_base = 110; + + private static final int ea_daid16_no_base = 111; + + private static final int ea_daid16_outer = 113; + + private static final int ea_daid16_fetch = 114; + + protected static final int ea_daid32 = 115; + + private static final int ea_daid32_base = 117; + + private static final int ea_daid32_no_base = 118; + + private static final int ea_daid32_outer = 120; + + private static final int ea_daid32_fetch = 121; + + private static final int ea_daix_imm32 = 122; + + private static final int ea_dais_imm16 = 123; + + protected static final int ea_dais8_read = 124; + + protected static final int ea_dais8 = 125; + + private static final int ea_dais8_base = 127; + + private static final int ea_dais8_no_base = 128; + + private static final int ea_dais8_outer = 130; + + private static final int ea_dais8_fetch = 131; + + protected static final int ea_dais16_read = 132; + + protected static final int ea_dais16 = 133; + + private static final int ea_dais16_base = 135; + + private static final int ea_dais16_no_base = 136; + + private static final int ea_dais16_outer = 138; + + private static final int ea_dais16_fetch = 139; + + protected static final int ea_dais32_read = 140; + + protected static final int ea_dais32 = 141; + + private static final int ea_dais32_base = 143; + + private static final int ea_dais32_no_base = 144; + + private static final int ea_dais32_outer = 146; + + private static final int ea_dais32_fetch = 147; + + protected static final int ea_dpc8_read = 148; + + private static final int eapc_read8 = 150; + + protected static final int ea_dpc16_read = 152; + + protected static final int ea_dpc16 = 153; + + private static final int eapc_read16 = 155; + + protected static final int ea_dpc32_read = 157; + + private static final int eapc_read32 = 159; + + protected static final int ea_dpci8_read = 161; + + private static final int ea_dpci8_base = 163; + + private static final int ea_dpci8_no_base = 164; + + private static final int ea_dpci8_outer = 166; + + private static final int ea_dpci8_fetch = 167; + + protected static final int ea_dpci16_read = 168; + + protected static final int ea_dpci16 = 169; + + private static final int ea_dpci16_base = 171; + + private static final int ea_dpci16_no_base = 172; + + private static final int ea_dpci16_outer = 174; + + private static final int ea_dpci16_fetch = 175; + + protected static final int ea_dpci32_read = 176; + + private static final int ea_dpci32_base = 178; + + private static final int ea_dpci32_no_base = 179; + + private static final int ea_dpci32_outer = 181; + + private static final int ea_dpci32_fetch = 182; + + protected static final int ea_adr16d8 = 183; + + protected static final int ea_adr16d16 = 185; + + protected static final int ea_adr16d32 = 187; + + protected static final int ea_adr16s8_read = 189; + + protected static final int ea_adr16s8 = 190; + + protected static final int ea_adr16s16_read = 192; + + protected static final int ea_adr16s16 = 193; + + protected static final int ea_adr16s32_read = 195; + + protected static final int ea_adr16s32 = 196; + + protected static final int ea_adr32d8 = 198; + + protected static final int ea_adr32d16 = 199; + + protected static final int ea_adr32d32 = 200; + + protected static final int ea_adr32s8_read = 202; + + protected static final int ea_adr32s8 = 203; + + protected static final int ea_adr32s16_read = 205; + + protected static final int ea_adr32s16 = 206; + + protected static final int ea_adr32s32_read = 208; + + protected static final int ea_adr32s32 = 209; + + protected static final int ea_imm8_read = 211; + + protected static final int ea_imm16_read = 213; + + protected static final int ea_imm32_read = 215; + + protected static final int op_movepw_dd_das = 217; + + protected static final int op_movepw_das_dd = 221; + + protected static final int op_movepl_dd_das = 224; + + protected static final int op_movepl_das_dd = 230; + + protected static final int op_clrb_ds = 235; + + protected static final int op_clrw_ds = 236; + + protected static final int op_clrl_ds = 237; + + protected static final int op_clrb_ea = 238; + + protected static final int op_clrw_ea = 239; + + protected static final int op_clrl_ea = 240; + + protected static final int op_lea_ea_ad = 241; + + protected static final int op_pea = 242; + + protected static final int op_swap_ds = 244; + + protected static final int op_extw_ds = 245; + + protected static final int op_extl_ds = 246; + + protected static final int op_extbl_ds = 247; + + protected static final int op_exg_dd_ds = 248; + + protected static final int op_exg_ad_as = 249; + + protected static final int op_exg_dd_as = 250; + + protected static final int op_scc_b_ds = 251; + + protected static final int op_scc_b_ea = 252; + + protected static final int op_chk_w_ds = 253; + + protected static final int op_chk_w_ea = 254; + + protected static final int op_link_as_imm16 = 255; + + protected static final int op_link_as_imm32 = 257; + + protected static final int op_unlk_as = 259; + + protected static final int op_move_usp_as = 261; + + protected static final int op_move_as_usp = 262; + + protected static final int op_movec_cr_rz = 263; + + protected static final int op_movec_rz_cr = 265; + + private static final int op_movemw_rr_ea = 267; + + private static final int op_movemw_rr_pais = 271; + + private static final int op_moveml_rr_ea = 275; + + private static final int op_moveml_rr_pais = 279; + + private static final int op_movemw_ea_rr = 283; + + private static final int op_movemw_aisp_rr = 288; + + private static final int op_moveml_ea_rr = 293; + + private static final int op_moveml_aisp_rr = 298; + + protected static final int op_bcc8 = 303; + + protected static final int op_bra8 = 304; + + protected static final int op_bcc16 = 305; + + protected static final int op_bra16 = 306; + + protected static final int op_bcc32 = 307; + + protected static final int op_bra32 = 308; + + protected static final int op_bsr8 = 309; + + protected static final int op_bsr16 = 311; + + protected static final int op_bsr32 = 313; + + protected static final int op_dbcc = 315; + + protected static final int op_bkpt = 317; + + protected static final int op_illegal = 318; + + protected static final int op_jmp = 319; + + protected static final int op_jsr = 320; + + protected static final int op_linea = 322; + + protected static final int op_linef = 323; + + protected static final int op_nop = 324; + + protected static final int op_rte = 325; + + private static final int check_vob = 326; + + private static final int rteill = 327; + + private static final int exit_trap = 328; + + private static final int rte0000 = 329; + + private static final int rte1000 = 330; + + private static final int rte2000 = 331; + + private static final int rte8000 = 332; + + protected static final int op_rtr = 333; + + protected static final int op_rts = 336; + + protected static final int op_reset = 338; + + protected static final int op_trap = 339; + + protected static final int op_trapv = 340; + + protected static final int op_trapcc = 341; + + protected static final int op_trapcc16 = 342; + + protected static final int op_trapcc32 = 343; + + protected static final int gen_orb_dt_ds = 344; + + protected static final int gen_orb_im_ea = 345; + + protected static final int gen_orw_dt_ds = 346; + + protected static final int gen_orw_im_ea = 347; + + protected static final int gen_orl_dt_ds = 348; + + protected static final int gen_orl_im_ea = 349; + + protected static final int gen_orb_dt_ccr = 350; + + protected static final int gen_orw_dt_sr = 351; + + protected static final int gen_btstl_dd_ds = 352; + + protected static final int gen_btstb_dd_ea = 353; + + protected static final int gen_bchgl_dd_ds = 354; + + protected static final int gen_bchgb_dd_ea = 355; + + protected static final int gen_bclrl_dd_ds = 356; + + protected static final int gen_bclrb_dd_ea = 357; + + protected static final int gen_bsetl_dd_ds = 358; + + protected static final int gen_bsetb_dd_ea = 359; + + protected static final int gen_andb_dt_ds = 360; + + protected static final int gen_andb_im_ea = 361; + + protected static final int gen_andw_dt_ds = 362; + + protected static final int gen_andw_im_ea = 363; + + protected static final int gen_andl_dt_ds = 364; + + protected static final int gen_andl_im_ea = 365; + + protected static final int gen_andb_dt_ccr = 366; + + protected static final int gen_andw_dt_sr = 367; + + protected static final int gen_subb_dt_ds = 368; + + protected static final int gen_subb_im_ea = 369; + + protected static final int gen_subw_dt_ds = 370; + + protected static final int gen_subw_im_ea = 371; + + protected static final int gen_subl_dt_ds = 372; + + protected static final int gen_subl_im_ea = 373; + + protected static final int gen_addb_dt_ds = 374; + + protected static final int gen_addb_im_ea = 375; + + protected static final int gen_addw_dt_ds = 376; + + protected static final int gen_addw_im_ea = 377; + + protected static final int gen_addl_dt_ds = 378; + + protected static final int gen_addl_im_ea = 379; + + protected static final int gen_btstl_dt_ds = 380; + + protected static final int gen_btstb_im_ea = 381; + + protected static final int gen_bchgl_dt_ds = 382; + + protected static final int gen_bchgb_im_ea = 383; + + protected static final int gen_bclrl_dt_ds = 384; + + protected static final int gen_bclrb_im_ea = 385; + + protected static final int gen_bsetl_dt_ds = 386; + + protected static final int gen_bsetb_im_ea = 387; + + protected static final int gen_eorb_dt_ds = 388; + + protected static final int gen_eorb_im_ea = 389; + + protected static final int gen_eorw_dt_ds = 390; + + protected static final int gen_eorw_im_ea = 391; + + protected static final int gen_eorl_dt_ds = 392; + + protected static final int gen_eorl_im_ea = 393; + + protected static final int gen_eorb_dt_ccr = 394; + + protected static final int gen_eorw_dt_sr = 395; + + protected static final int gen_cmpb_dt_ds = 396; + + protected static final int gen_cmpb_im_ea = 397; + + protected static final int gen_cmpw_dt_ds = 398; + + protected static final int gen_cmpw_im_ea = 399; + + protected static final int gen_cmpl_dt_ds = 400; + + protected static final int gen_cmpl_im_ea = 401; + + protected static final int gen_moveb_ds_ea = 402; + + protected static final int gen_moveb_dt_dd = 403; + + protected static final int gen_moveb_ds_dd = 404; + + protected static final int gen_moveb_dt_ea = 405; + + protected static final int gen_movel_ds_ea = 406; + + protected static final int gen_movel_as_ea = 407; + + protected static final int gen_movel_dt_dd = 408; + + protected static final int gen_movel_ds_dd = 409; + + protected static final int gen_movel_as_dd = 410; + + protected static final int gen_movel_dt_ea = 411; + + protected static final int gen_movel_ds_ad = 412; + + protected static final int gen_movel_as_ad = 413; + + protected static final int gen_movel_dt_ad = 414; + + protected static final int gen_movew_ds_ea = 415; + + protected static final int gen_movew_as_ea = 416; + + protected static final int gen_movew_dt_dd = 417; + + protected static final int gen_movew_ds_dd = 418; + + protected static final int gen_movew_as_dd = 419; + + protected static final int gen_movew_dt_ea = 420; + + protected static final int gen_movew_ds_ad = 421; + + protected static final int gen_movew_as_ad = 422; + + protected static final int gen_movew_dt_ad = 423; + + protected static final int gen_negxb_ds = 424; + + protected static final int gen_negxb_ea = 425; + + protected static final int gen_negxw_ds = 426; + + protected static final int gen_negxw_ea = 427; + + protected static final int gen_negxl_ds = 428; + + protected static final int gen_negxl_ea = 429; + + protected static final int gen_movew_sr_ds = 430; + + protected static final int gen_movew_sr_ea = 431; + + protected static final int gen_movew_ccr_ds = 432; + + protected static final int gen_movew_ccr_ea = 433; + + protected static final int gen_movew_ds_ccr = 434; + + protected static final int gen_movew_dt_ccr = 435; + + protected static final int gen_movew_ds_sr = 436; + + protected static final int gen_movew_dt_sr = 437; + + protected static final int gen_negb_ds = 438; + + protected static final int gen_negb_ea = 439; + + protected static final int gen_negw_ds = 440; + + protected static final int gen_negl_ea = 441; + + protected static final int gen_negl_ds = 442; + + protected static final int gen_notb_ds = 443; + + protected static final int gen_notb_ea = 444; + + protected static final int gen_notw_ds = 445; + + protected static final int gen_notw_ea = 446; + + protected static final int gen_notl_ds = 447; + + protected static final int gen_notl_ea = 448; + + protected static final int gen_nbcdb_ds = 449; + + protected static final int gen_nbcdb_ea = 450; + + protected static final int gen_tstb_ds = 451; + + protected static final int gen_tstb_ea = 452; + + protected static final int gen_tstw_ds = 453; + + protected static final int gen_tstw_ea = 454; + + protected static final int gen_tstl_ds = 455; + + protected static final int gen_tstl_ea = 456; + + protected static final int gen_addb_ir_ds = 457; + + protected static final int gen_addb_ir_ea = 458; + + protected static final int gen_addw_ir_ds = 459; + + protected static final int gen_addw_ir_as = 460; + + protected static final int gen_addw_ir_ea = 461; + + protected static final int gen_addl_ir_ds = 462; + + protected static final int gen_addl_ir_as = 463; + + protected static final int gen_addl_ir_ea = 464; + + protected static final int gen_subb_ir_ds = 465; + + protected static final int gen_subb_ir_ea = 466; + + protected static final int gen_subw_ir_ds = 467; + + protected static final int gen_subw_ir_as = 468; + + protected static final int gen_subw_ir_ea = 469; + + protected static final int gen_subl_ir_ds = 470; + + protected static final int gen_subl_ir_as = 471; + + protected static final int gen_subl_ir_ea = 472; + + protected static final int gen_movel_im_dd = 473; + + protected static final int gen_orb_ds_dd = 474; + + protected static final int gen_orb_dt_dd = 475; + + protected static final int gen_orw_ds_dd = 476; + + protected static final int gen_orw_dt_dd = 477; + + protected static final int gen_orl_ds_dd = 478; + + protected static final int gen_orl_dt_dd = 479; + + protected static final int gen_sbcdb_ds_dd = 480; + + protected static final int gen_sbcdb_im_ea = 481; + + protected static final int gen_orb_dd_ea = 482; + + protected static final int gen_orw_dd_ea = 483; + + protected static final int gen_orl_dd_ea = 484; + + protected static final int gen_subb_ds_dd = 485; + + protected static final int gen_subb_dt_dd = 486; + + protected static final int gen_subw_ds_dd = 487; + + protected static final int gen_subw_as_dd = 488; + + protected static final int gen_subw_dt_dd = 489; + + protected static final int gen_subl_ds_dd = 490; + + protected static final int gen_subl_as_dd = 491; + + protected static final int gen_subl_dt_dd = 492; + + protected static final int gen_subb_dd_ea = 493; + + protected static final int gen_subw_dd_ea = 494; + + protected static final int gen_subl_dd_ea = 495; + + protected static final int gen_subxb_ds_dd = 496; + + protected static final int gen_subxb_im_ea = 497; + + protected static final int gen_subxw_ds_dd = 498; + + protected static final int gen_subxw_im_ea = 499; + + protected static final int gen_subxl_ds_dd = 500; + + protected static final int gen_subxl_im_ea = 501; + + protected static final int gen_subw_ds_ad = 502; + + protected static final int gen_subw_as_ad = 503; + + protected static final int gen_subw_dt_ad = 504; + + protected static final int gen_subl_ds_ad = 505; + + protected static final int gen_subl_as_ad = 506; + + protected static final int gen_subl_dt_ad = 507; + + protected static final int gen_cmpb_ds_dd = 508; + + protected static final int gen_cmpb_dt_dd = 509; + + protected static final int gen_cmpw_ds_dd = 510; + + protected static final int gen_cmpw_as_dd = 511; + + protected static final int gen_cmpw_dt_dd = 512; + + protected static final int gen_cmpl_ds_dd = 513; + + protected static final int gen_cmpl_as_dd = 514; + + protected static final int gen_cmpl_dt_dd = 515; + + protected static final int gen_cmpw_ds_ad = 516; + + protected static final int gen_cmpw_as_ad = 517; + + protected static final int gen_cmpw_dt_ad = 518; + + protected static final int gen_cmpl_ds_ad = 519; + + protected static final int gen_cmpl_as_ad = 520; + + protected static final int gen_cmpl_dt_ad = 521; + + protected static final int gen_cmpmb_im_ea = 522; + + protected static final int gen_cmpmw_im_ea = 523; + + protected static final int gen_cmpml_im_ea = 524; + + protected static final int gen_eorb_dd_ds = 525; + + protected static final int gen_eorb_dd_ea = 526; + + protected static final int gen_eorw_dd_ds = 527; + + protected static final int gen_eorw_dd_ea = 528; + + protected static final int gen_eorl_dd_ds = 529; + + protected static final int gen_eorl_dd_ea = 530; + + protected static final int gen_andb_ds_dd = 531; + + protected static final int gen_andb_dt_dd = 532; + + protected static final int gen_andw_ds_dd = 533; + + protected static final int gen_andw_dt_dd = 534; + + protected static final int gen_andl_ds_dd = 535; + + protected static final int gen_andl_dt_dd = 536; + + protected static final int gen_andb_dd_ea = 537; + + protected static final int gen_andw_dd_ea = 538; + + protected static final int gen_andl_dd_ea = 539; + + protected static final int gen_abcdb_ds_dd = 540; + + protected static final int gen_abcdb_im_ea = 541; + + protected static final int gen_addb_ds_dd = 542; + + protected static final int gen_addb_dt_dd = 543; + + protected static final int gen_addw_ds_dd = 544; + + protected static final int gen_addw_as_dd = 545; + + protected static final int gen_addw_dt_dd = 546; + + protected static final int gen_addl_ds_dd = 547; + + protected static final int gen_addl_as_dd = 548; + + protected static final int gen_addl_dt_dd = 549; + + protected static final int gen_addb_dd_ea = 550; + + protected static final int gen_addw_dd_ea = 551; + + protected static final int gen_addl_dd_ea = 552; + + protected static final int gen_addxb_ds_dd = 553; + + protected static final int gen_addxb_im_ea = 554; + + protected static final int gen_addxw_ds_dd = 555; + + protected static final int gen_addxw_im_ea = 556; + + protected static final int gen_addxl_ds_dd = 557; + + protected static final int gen_addxl_im_ea = 558; + + protected static final int gen_addw_ds_ad = 559; + + protected static final int gen_addw_as_ad = 560; + + protected static final int gen_addw_dt_ad = 561; + + protected static final int gen_addl_ds_ad = 562; + + protected static final int gen_addl_as_ad = 563; + + protected static final int gen_addl_dt_ad = 564; + + protected static final int gen_asrb_ir_ds = 565; + + protected static final int gen_asrb_dd_ds = 566; + + protected static final int gen_asrw_ir_ds = 567; + + protected static final int gen_asrw_dd_ds = 568; + + protected static final int gen_asrl_ir_ds = 569; + + protected static final int gen_asrl_dd_ds = 570; + + protected static final int gen_asrw_ea = 571; + + protected static final int gen_aslb_ir_ds = 572; + + protected static final int gen_aslb_dd_ds = 573; + + protected static final int gen_aslw_ir_ds = 574; + + protected static final int gen_aslw_dd_ds = 575; + + protected static final int gen_asll_ir_ds = 576; + + protected static final int gen_asll_dd_ds = 577; + + protected static final int gen_aslw_ea = 578; + + protected static final int gen_lsrb_ir_ds = 579; + + protected static final int gen_lsrb_dd_ds = 580; + + protected static final int gen_lsrw_ir_ds = 581; + + protected static final int gen_lsrw_dd_ds = 582; + + protected static final int gen_lsrl_ir_ds = 583; + + protected static final int gen_lsrl_dd_ds = 584; + + protected static final int gen_lsrw_ea = 585; + + protected static final int gen_lslb_ir_ds = 586; + + protected static final int gen_lslb_dd_ds = 587; + + protected static final int gen_lslw_ir_ds = 588; + + protected static final int gen_lslw_dd_ds = 589; + + protected static final int gen_lsll_ir_ds = 590; + + protected static final int gen_lsll_dd_ds = 591; + + protected static final int gen_lslw_ea = 592; + + protected static final int gen_rorb_ir_ds = 593; + + protected static final int gen_rorb_dd_ds = 594; + + protected static final int gen_rorw_ir_ds = 595; + + protected static final int gen_rorw_dd_ds = 596; + + protected static final int gen_rorl_ir_ds = 597; + + protected static final int gen_rorl_dd_ds = 598; + + protected static final int gen_rorw_ea = 599; + + protected static final int gen_rolb_ir_ds = 600; + + protected static final int gen_rolb_dd_ds = 601; + + protected static final int gen_rolw_ir_ds = 602; + + protected static final int gen_rolw_dd_ds = 603; + + protected static final int gen_roll_ir_ds = 604; + + protected static final int gen_roll_dd_ds = 605; + + protected static final int gen_rolw_ea = 606; + + public static final int BKPT_EXIT = 0x00010000; + + public static final int BKPT_RPIR = 0x00020000; + + public static final int LINEA_EXIT = 0x00010000; + + public static final int LINEA_SKIP = 0x00020000; + + public static final int ILL_EXIT = 0x00010000; + + public static final int ILL_SKIP = 0x00020000; + + public static final int TRACE_EXIT = 0x8000; + + public static final int TRACE_IGNR = 0x4000; + + public static final int IRQ_EXIT = 0x8000; + + public static final int IRQ_IERR = 0x4000; + + public static final int IRQ_DFLT = 0x0000; + + public static final int IRQ_AVEC = 0x1000; + + public static final int IRQ_SPUR = 0x2000; + + public static final int IRQ_IGNR = 0x3000; + + protected int pc; + + protected int scan; + + protected int alub; + + protected int irb; + + protected int ir; + + protected int mpc = reset; + + protected int cip; + + protected int au; + + protected int at; + + protected int dt; + + protected int slice = 0; + + public final void pulse_reset() { + ssw |= SSW_RS; + } + + public final void set_pending_irq(int level) { + level = (level << 8) & SR_I; + sswi = (sswi & ~SR_I) | level; + } + + private static final int select_rte(int vob) { + switch((vob & 0xf000) >> 12) { + case 0: + return rte0000; + case 1: + return rte1000; + case 2: + return rte2000; + case 8: + return rte8000; + default: + return rteill; + } + } + + public final int execute(int cycles) { + MacroPLA decoded = MacroPLA.decode(ir); + int slice = Math.max(0, cycles); + int consumed = 0; + if ((sswi & SSWI_PSLC) != 0) { + slice += this.slice; + } + if (slice > 0) { + boolean exit = false; + int sp = spi(sr); + int elapsed = 0; + int nmpc = 0; + int hdlr = 0; + int ipend = 0; + int tvn = 0; + int aob = 0; + int dob = 0; + int dib = 0; + int vat1 = 0; + int vat2 = 0; + int vat3 = 0; + int vdt1 = 0; + int vdt2 = 0; + int vdt3 = 0; + int rx = 0; + int ry = 0; + int rz = 0; + consumed = slice; + if ((ssw & (SSW_RS | SSW_HL)) != 0) { + nmpc = mpc; + mpc = halt; + } + while (true) { + switch(mpc) { + case 0: /* reset */ + elapsed += 16; + sr = (sr & ~0xd000) | 0x2700; + sp = spi(sr); + ssw &= ~0x0018; + sswi &= ~0xc802; + vbr = 0x00000000; + elapsed += 8; + ssw = (ssw & 0x0018) | 0x91c6; + dar[sp] = fetch32(aob = 0x00000000); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x91c6; + pc = fetch32(aob = 0x00000004); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + mpc = resume_berr; + continue; + case 1: /* dbrr */ + ssw |= 0x0008; + sswi |= 0x0002; + nmpc = halt; + case 2: /* halt */ + if ((ssw & 0x0010) != 0) { + mpc = reset; + continue; + } else if ((ssw & 0x0008) != 0) { + elapsed += Math.max(0, slice - elapsed); + } + break; + case 3: /* bevtf32 */ + if ((ssw & 0x0020) != 0) { + ssw &= ~0x0040; + mpc = berr; + continue; + } else if ((ssw & 0x0040) == 0) { + dib <<= 16; + ssw = (ssw & ~0x0080) | 0x0040; + dib |= fetch16(aob += 2) & 0xffff; + if ((ssw & 0x0030) == 0) { + mpc = nmpc; + continue; + } + } + mpc = bevt; + continue; + case 4: /* bevtr32 */ + if ((ssw & 0x0020) != 0) { + ssw &= ~0x0040; + mpc = berr; + continue; + } else if ((ssw & 0x0040) == 0) { + dib <<= 16; + ssw = (ssw & ~0x0080) | 0x0040; + dib |= read16(aob += 2) & 0xffff; + if ((ssw & 0x0030) == 0) { + mpc = nmpc; + continue; + } + } + case 5: /* bevtw32 */ + if ((ssw & 0x0020) != 0) { + ssw &= ~0x0040; + mpc = berr; + continue; + } else if ((ssw & 0x0040) == 0) { + ssw &= ~0x0080; + write16(aob += 2, dob); + if ((ssw & 0x0030) == 0) { + ssw &= ~0xbfe7; + break; + } + } + mpc = bevt; + continue; + case 6: /* bevt */ + if ((ssw & 0x0020) == 0) { + mpc = halt; + continue; + } + case 7: /* berr */ + elapsed += 6; + vdt1 = ((sswi & 0xc800) << 16) | ((tvn & 0x3fc) << 14) | ((ssw ^ ~0x8000) & 0xffdf); + tvn = 8; + mpc = trap8000; + continue; + case 8: /* aerr */ + elapsed += 6; + vdt1 = ((sswi & 0xc800) << 16) | ((tvn & 0x3fc) << 14) | ((ssw ^ ~0x8000) & 0xffdf); + tvn = 12; + case 9: /* trap8000 */ + if ((vdt1 & 0x0200) == 0) { + if ((aob & 0x000000001) != 0) { + aob -= 1; + vdt1 &= ~0x0400; + } else { + vdt1 |= 0x0400; + if ((vdt1 & 0x0100) == 0) { + dob <<= 8; + } + } + } + vat1 = at; + vat2 = au; + vat3 = aob; + vdt2 = dob; + vdt3 = dib; + sp = spi(sr | 0x2000); + au = dar[sp] - 58; + dar[sp] = au; + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + if (((aob = au) & 0x000000001) != 0) { + mpc = dbrr; + continue; + } + write16(aob, dob = sr); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x80c5; + write32(aob = au + 0x0002, dob = pc); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x80c5; + write32(aob = au + 0x000a, dob = vat3); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + if ((vdt1 & 0x0100) == 0) { + if ((vdt1 & 0x0080) == 0) { + elapsed += 8; + ssw = (ssw & 0x0018) | 0x80c5; + write32(aob = au + 0x0010, dob = vdt2); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + } else { + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + write16(aob = au + 0x0010, dob = vdt2); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + } + } else if ((vdt1 & 0x00c0) == 0x0040) { + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + write16(aob = au + 0x0012, dob = vdt3 >> 16); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + write16(aob = au + 0x0018, dob = irb); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + write16(aob = au + 0x001a, dob = nmpc); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + write16(aob = au + 0x001c, dob = scan); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x80c5; + write32(aob = au + 0x001e, dob = alub); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x80c5; + write32(aob = au + 0x0022, dob = vat1); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x80c5; + write32(aob = au + 0x0026, dob = vat2); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + write16(aob = au + 0x002e, dob = vdt1 >> 16); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + write16(aob = au + 0x0030, dob = ir); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x80c5; + write32(aob = au + 0x0032, dob = dt); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x80c5; + write32(aob = au + 0x0036, dob = cip); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + case 10: /* resume_trap8000 */ + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + write16(aob = au + 0x0006, dob = 0x8000 | tvn); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + write16(aob = au + 0x0008, dob = vdt1); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + sr = (sr & ~0xc000) | 0x2000; + sswi &= ~0xc800; + elapsed += 8; + ssw = (ssw & 0x0018) | 0x91c5; + if (((aob = tvn + vbr) & 0x000000001) != 0) { + mpc = dbrr; + continue; + } + pc = read32(aob); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + case 11: /* resume_berr */ + scan = 0; + tvn = 0; + nmpc = resume; + elapsed += 4; + ssw = (ssw & 0x0018) | 0xa106; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = dbrr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + ssw &= ~0xbfe7; + break; + case 12: /* trap2000 */ + sp = spi(sr | 0x2000); + au = dar[sp] - 12; + dar[sp] = au; + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + if (((aob = au) & 0x000000001) != 0) { + mpc = dbrr; + continue; + } + write16(aob, dob = sr); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x80c5; + write32(aob = au + 0x0002, dob = pc + scan); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + write16(aob = au + 0x0006, dob = 0x2000 | tvn); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x80c5; + write32(aob = au + 0x0008, dob = cip); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + mpc = enter_trap0000; + continue; + case 13: /* trapill */ + pc = cip; + scan = 0; + case 14: /* trap0000 */ + sp = spi(sr | 0x2000); + au = dar[sp] - 8; + dar[sp] = au; + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + if (((aob = au) & 0x000000001) != 0) { + mpc = dbrr; + continue; + } + write16(aob, dob = sr); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x80c5; + write32(aob = au + 0x0002, dob = pc + scan); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + write16(aob = au + 0x0006, dob = tvn); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + case 15: /* enter_trap0000 */ + sr = (sr & ~0xc000) | 0x2000; + sswi &= ~0xc800; + nmpc = 16; + elapsed += 4; + ssw = (ssw & 0x0018) | 0x91c5; + if (((aob = tvn + vbr) & 0x000000001) != 0) { + mpc = dbrr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 16: + pc = dib; + mpc = execute_trap; + continue; + case 17: /* uninitialized */ + tvn = 60; + nmpc = 18; + elapsed += 4; + ssw = (ssw & 0x0018) | 0x91c5; + if (((aob = tvn + vbr) & 0x000000001) != 0) { + mpc = dbrr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 18: + pc = dib; + mpc = enter_irq; + continue; + case 19: /* interrupt */ + elapsed += 10; + hdlr = handle_interrupt((sswi & 0x0700) >> 8); + exit |= (hdlr & 0x8000) != 0; + if ((hdlr & 0x3000) != 0x3000) { + sswi &= ~0x0700; + sp = spi(sr); + mpc = resume; + continue; + } else if ((hdlr & 0x3000) == 0x2000) { + tvn = 96; + } else if ((hdlr & 0x3000) == 0x1000) { + tvn = 96 + (sswi & 0x0700) >> 6; + } else if ((hdlr & 0x4000) != 0) { + tvn = 96; + } else if ((sswi & 0x0004) != 0) { + tvn = 96 + (sswi & 0x0700) >> 6; + } else { + tvn = (hdlr & 0xff) << 2; + } + sp = spi(sr | 0x2000); + au = dar[sp] - 8; + dar[sp] = au; + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + if (((aob = au) & 0x000000001) != 0) { + mpc = dbrr; + continue; + } + write16(aob, dob = sr); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x80c5; + write32(aob = au + 0x0002, dob = pc); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + sr |= 0x2000; + if ((sr & 0x1000) != 0) { + sp = spi(sr & ~0x1000); + at = dar[sp] - 8; + dar[sp] = at; + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + if (((aob = at) & 0x000000001) != 0) { + mpc = dbrr; + continue; + } + write16(aob, dob = sr); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x80c5; + write32(aob = at + 0x0002, dob = pc); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + } + sr = (sswi & 0x0700) | (sr & ~0xd700); + sswi &= ~0xcf00; + nmpc = 20; + elapsed += 4; + ssw = (ssw & 0x0018) | 0x91c5; + if (((aob = tvn + vbr) & 0x000000001) != 0) { + mpc = dbrr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 20: + pc = dib; + if (pc == 0x00000000) { + mpc = uninitialized; + continue; + } + case 21: /* enter_irq */ + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + write16(aob = au + 0x0006, dob = tvn); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + if ((sr & 0x1000) != 0) { + elapsed += 4; + ssw = (ssw & 0x0018) | 0x8005; + write16(aob = at + 0x0006, dob = 0x1000 | tvn); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + sr &= ~0x1000; + } + case 22: /* execute_trap */ + scan = 0; + tvn = 0; + case 23: /* resume_prefetch */ + nmpc = resume; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + ssw &= ~0xbfe7; + case 24: /* resume */ + if ((ssw & 0x0018) != 0) { + nmpc = resume; + mpc = halt; + continue; + } else if ((sswi & 0xc000) != 0) { + elapsed += 6; + hdlr = handle_trace(cip); + exit |= (hdlr & 0x8000) != 0; + if ((hdlr & 0x4000) == 0) { + tvn = 36; + mpc = (sswi & 0x0008) != 0 ? trap2000 : trap0000; + continue; + } + sswi &= ~0xc000; + } + case 25: /* resume_notrace */ + ipend = sswi & 0x0700; + if ((ipend == 0x0700) || ((sr & 0x0700) < ipend)) { + mpc = interrupt; + continue; + } + cip = pc + scan; + pc = cip + 2; + scan = 0; + ir = irb & 0xffff; + decoded = MacroPLA.decode(ir); + nmpc = decoded.a1; + sswi |= (sr & 0x8000); + break; + case 26: /* op_stop */ + if ((sr & 0x2000) == 0) { + elapsed += 6; + tvn = 32; + mpc = trapill; + continue; + } + sr = dt & 0xf71f; + nmpc = op_stop_loop; + case 27: /* op_stop_loop */ + if ((ssw & 0x0018) != 0) { + nmpc = op_stop_loop; + mpc = halt; + continue; + } else if ((sswi & 0xc000) != 0) { + elapsed += 6; + hdlr = handle_trace(cip); + exit |= (hdlr & 0x8000) != 0; + if ((hdlr & 0x4000) == 0) { + tvn = 36; + mpc = (sswi & 0x0008) != 0 ? trap2000 : trap0000; + continue; + } + sswi &= ~0xc000; + mpc = resume_notrace; + continue; + } + ipend = sswi & 0x0700; + if ((ipend == 0x0700) || ((sr & 0x0700) < ipend)) { + mpc = interrupt; + continue; + } + elapsed += Math.max(0, slice - elapsed); + break; + case 28: /* ea_resume_write8 */ + nmpc = 29; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 29: + nmpc = 30; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; + write8(aob = at, dob = dt); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 30: + ssw &= ~0xbfe7; + mpc = resume; + continue; + case 31: /* ea_resume_write16 */ + nmpc = 32; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 32: + nmpc = 33; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8001; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write16(aob, dob = dt); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 33: + ssw &= ~0xbfe7; + mpc = resume; + continue; + case 34: /* ea_resume_write32 */ + nmpc = 35; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 35: + nmpc = 36; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write32(aob, dob = dt); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtw32; + continue; + } + case 36: + ssw &= ~0xbfe7; + mpc = resume; + continue; + case 37: /* op_imm16 */ + nmpc = 38; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 38: + dt = dib; + nmpc = decoded.a2; + ssw &= ~0xbfe7; + break; + case 39: /* op_imm32 */ + nmpc = 40; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch32(aob); + scan += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtf32; + continue; + } + case 40: + dt = dib; + nmpc = decoded.a2; + ssw &= ~0xbfe7; + break; + case 41: /* ea_aid8 */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + at = dar[rx]; + elapsed += 2; + nmpc = decoded.a2; + break; + case 42: /* ea_aid16 */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + at = dar[rx]; + elapsed += 2; + nmpc = decoded.a3; + break; + case 43: /* ea_aid32 */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + at = dar[rx]; + elapsed += 2; + nmpc = decoded.a3; + break; + case 44: /* ea_ais8_read */ + sswi |= 0x0800; + case 45: /* ea_ais8 */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + at = dar[ry]; + if ((sswi & 0x0800) == 0) { + elapsed += 2; + nmpc = decoded.a3; + break; + } + case 46: /* ea_read8 */ + sswi &= ~0x0800; + alub = dt; + nmpc = 47; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9301; + dib = read8(aob = at); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + if ((ssw & 0x0600) == 0x0600) { + dib >>= 8; + } + case 47: + dt = dib; + ssw &= ~0xbfe7; + nmpc = decoded.a3; + break; + case 48: /* ea_ais16_read */ + sswi |= 0x0800; + case 49: /* ea_ais16 */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + at = dar[ry]; + if ((sswi & 0x0800) == 0) { + elapsed += 2; + nmpc = decoded.a3; + break; + } + case 50: /* ea_read16 */ + sswi &= ~0x0800; + alub = dt; + nmpc = 51; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9101; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 51: + dt = dib; + ssw &= ~0xbfe7; + nmpc = decoded.a3; + break; + case 52: /* ea_ais32_read */ + sswi |= 0x0800; + case 53: /* ea_ais32 */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + at = dar[ry]; + if ((sswi & 0x0800) == 0) { + elapsed += 2; + nmpc = decoded.a3; + break; + } + case 54: /* ea_read32 */ + sswi &= ~0x0800; + alub = dt; + nmpc = 55; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 55: + dt = dib; + ssw &= ~0xbfe7; + nmpc = decoded.a3; + break; + case 56: /* ea_aipd8_read */ + sswi |= 0x0800; + case 57: /* ea_aipd8 */ + rx = (ir >> 9) & 0x0007; + if (rx == 7) { + at = dar[sp]; + dar[sp] += 2; + } else { + rx |= 8; + at = dar[rx]; + dar[rx] += 1; + } + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a2; + break; + } + mpc = ead_read8; + continue; + case 58: /* ea_aipd16_read */ + sswi |= 0x0800; + case 59: /* ea_aipd16 */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + at = dar[rx]; + dar[rx] += 2; + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a2; + break; + } + mpc = ead_read16; + continue; + case 60: /* ea_aipd32_read */ + sswi |= 0x0800; + case 61: /* ea_aipd32 */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + at = dar[rx]; + dar[rx] += 4; + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a2; + break; + } + mpc = ead_read32; + continue; + case 62: /* ea_aips8_read */ + sswi |= 0x0800; + case 63: /* ea_aips8 */ + ry = ir & 0x0007; + if (ry == 7) { + at = dar[sp]; + dar[sp] += 2; + } else { + ry |= 8; + at = dar[ry]; + dar[ry] += 1; + } + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a3; + break; + } + mpc = ea_read8; + continue; + case 64: /* ea_aips16_read */ + sswi |= 0x0800; + case 65: /* ea_aips16 */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + at = dar[ry]; + dar[ry] += 2; + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a3; + break; + } + mpc = ea_read16; + continue; + case 66: /* ea_aips32_read */ + sswi |= 0x0800; + case 67: /* ea_aips32 */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + at = dar[ry]; + dar[ry] += 4; + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a3; + break; + } + mpc = ea_read32; + continue; + case 68: /* ea_paid8_read */ + sswi |= 0x0800; + case 69: /* ea_paid8 */ + rx = (ir >> 9) & 0x0007; + if (rx == 7) { + dar[sp] -= 2; + at = dar[sp]; + } else { + rx |= 8; + dar[rx] -= 1; + at = dar[rx]; + } + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a2; + break; + } + elapsed += 2; + case 70: /* ead_read8 */ + sswi &= ~0x0800; + alub = dt; + nmpc = 71; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9301; + dib = read8(aob = at); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + if ((ssw & 0x0600) == 0x0600) { + dib >>= 8; + } + case 71: + dt = dib; + ssw &= ~0xbfe7; + nmpc = decoded.a2; + break; + case 72: /* ea_paid16_read */ + sswi |= 0x0800; + case 73: /* ea_paid16 */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] -= 2; + at = dar[rx]; + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a2; + break; + } + elapsed += 2; + case 74: /* ead_read16 */ + sswi &= ~0x0800; + alub = dt; + nmpc = 75; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9101; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 75: + dt = dib; + ssw &= ~0xbfe7; + nmpc = decoded.a2; + break; + case 76: /* ea_paid32_read */ + sswi |= 0x0800; + case 77: /* ea_paid32 */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] -= 4; + at = dar[rx]; + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a2; + break; + } + elapsed += 2; + case 78: /* ead_read32 */ + sswi &= ~0x0800; + alub = dt; + nmpc = 79; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 79: + dt = dib; + ssw &= ~0xbfe7; + nmpc = decoded.a2; + break; + case 80: /* ea_pais8_read */ + sswi |= 0x0800; + case 81: /* ea_pais8 */ + ry = ir & 0x0007; + if (ry == 7) { + dar[sp] -= 2; + at = dar[sp]; + } else { + ry |= 8; + dar[ry] -= 1; + at = dar[ry]; + } + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a3; + break; + } + elapsed += 2; + mpc = ea_read8; + continue; + case 82: /* ea_pais16_read */ + sswi |= 0x0800; + case 83: /* ea_pais16 */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dar[ry] -= 2; + at = dar[ry]; + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a3; + break; + } + elapsed += 2; + mpc = ea_read16; + continue; + case 84: /* ea_pais32_read */ + sswi |= 0x0800; + case 85: /* ea_pais32 */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dar[ry] -= 4; + at = dar[ry]; + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a3; + break; + } + elapsed += 2; + mpc = ea_read32; + continue; + case 86: /* ea_dad8 */ + nmpc = 87; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 87: + at = dib; + ssw &= ~0xbfe7; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + at = ((short) at) + dar[rx]; + elapsed += 4; + nmpc = decoded.a2; + break; + case 88: /* ea_dad16 */ + nmpc = 89; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 89: + at = dib; + ssw &= ~0xbfe7; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + at = ((short) at) + dar[rx]; + elapsed += 4; + nmpc = decoded.a2; + break; + case 90: /* ea_dad32 */ + nmpc = 91; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 91: + at = dib; + ssw &= ~0xbfe7; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + at = ((short) at) + dar[rx]; + nmpc = decoded.a2; + break; + case 92: /* ea_das8_read */ + sswi |= 0x0800; + case 93: /* ea_das8 */ + nmpc = 94; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 94: + at = dib; + ssw &= ~0xbfe7; + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + at = ((short) at) + dar[ry]; + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a3; + break; + } + mpc = ea_read8; + continue; + case 95: /* ea_das16_read */ + sswi |= 0x0800; + case 96: /* ea_das16 */ + nmpc = 97; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 97: + at = dib; + ssw &= ~0xbfe7; + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + at = ((short) at) + dar[ry]; + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a3; + break; + } + mpc = ea_read16; + continue; + case 98: /* ea_das32_read */ + sswi |= 0x0800; + case 99: /* ea_das32 */ + nmpc = 100; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 100: + at = dib; + ssw &= ~0xbfe7; + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + at = ((short) at) + dar[ry]; + if ((sswi & 0x0800) == 0) { + nmpc = decoded.a3; + break; + } + mpc = ea_read32; + continue; + case 101: /* ea_daid8 */ + nmpc = 102; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 102: + ssw &= ~0xbfe7; + if ((irb & 0x0100) == 0) { + at = (byte) irb; + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + at += dt << ((irb & 0x0600) >> 9); + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + at += dar[rx]; + mpc = ea_daid8_fetch; + continue; + } + at = dt = 0; + if ((irb & 0x0040) == 0) { + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + dt <<= ((irb & 0x0600) >> 9); + } + if ((irb & 0x0080) == 0) { + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + at += dar[rx]; + } + nmpc = ea_daid8_base; + if ((irb & 0x0020) == 0) { + mpc = ea_daid8_no_base; + continue; + } else if ((irb & 0x0010) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 103: /* ea_daid8_base */ + at += dib; + ssw &= ~0xbfe7; + case 104: /* ea_daid8_no_base */ + if ((irb & 0x0004) == 0) { + at += dt; + dt = 0; + if ((irb & 0x0007) == 0) { + mpc = ea_daid8_fetch; + continue; + } + } + nmpc = 105; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 105: + at = dib; + at += dt; + ssw &= ~0xbfe7; + nmpc = ea_daid8_outer; + if ((irb & 0x0002) == 0) { + mpc = ea_daid8_fetch; + continue; + } else if ((irb & 0x0001) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 106: /* ea_daid8_outer */ + at += dib; + ssw &= ~0xbfe7; + case 107: /* ea_daid8_fetch */ + elapsed += 4; + nmpc = decoded.a2; + break; + case 108: /* ea_daid16 */ + nmpc = 109; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 109: + ssw &= ~0xbfe7; + if ((irb & 0x0100) == 0) { + at = (byte) irb; + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + at += dt << ((irb & 0x0600) >> 9); + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + at += dar[rx]; + mpc = ea_daid16_fetch; + continue; + } + at = dt = 0; + if ((irb & 0x0040) == 0) { + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + dt <<= ((irb & 0x0600) >> 9); + } + if ((irb & 0x0080) == 0) { + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + at += dar[rx]; + } + nmpc = ea_daid16_base; + if ((irb & 0x0020) == 0) { + mpc = ea_daid16_no_base; + continue; + } else if ((irb & 0x0010) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 110: /* ea_daid16_base */ + at += dib; + ssw &= ~0xbfe7; + case 111: /* ea_daid16_no_base */ + if ((irb & 0x0004) == 0) { + at += dt; + dt = 0; + if ((irb & 0x0007) == 0) { + mpc = ea_daid16_fetch; + continue; + } + } + nmpc = 112; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 112: + at = dib; + at += dt; + ssw &= ~0xbfe7; + nmpc = ea_daid16_outer; + if ((irb & 0x0002) == 0) { + mpc = ea_daid16_fetch; + continue; + } else if ((irb & 0x0001) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 113: /* ea_daid16_outer */ + at += dib; + ssw &= ~0xbfe7; + case 114: /* ea_daid16_fetch */ + elapsed += 4; + nmpc = decoded.a2; + break; + case 115: /* ea_daid32 */ + nmpc = 116; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 116: + ssw &= ~0xbfe7; + if ((irb & 0x0100) == 0) { + at = (byte) irb; + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + at += dt << ((irb & 0x0600) >> 9); + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + at += dar[rx]; + mpc = ea_daid32_fetch; + continue; + } + at = dt = 0; + if ((irb & 0x0040) == 0) { + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + dt <<= ((irb & 0x0600) >> 9); + } + if ((irb & 0x0080) == 0) { + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + at += dar[rx]; + } + nmpc = ea_daid32_base; + if ((irb & 0x0020) == 0) { + mpc = ea_daid32_no_base; + continue; + } else if ((irb & 0x0010) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 117: /* ea_daid32_base */ + at += dib; + ssw &= ~0xbfe7; + case 118: /* ea_daid32_no_base */ + if ((irb & 0x0004) == 0) { + at += dt; + dt = 0; + if ((irb & 0x0007) == 0) { + mpc = ea_daid32_fetch; + continue; + } + } + nmpc = 119; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 119: + at = dib; + at += dt; + ssw &= ~0xbfe7; + nmpc = ea_daid32_outer; + if ((irb & 0x0002) == 0) { + mpc = ea_daid32_fetch; + continue; + } else if ((irb & 0x0001) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 120: /* ea_daid32_outer */ + at += dib; + ssw &= ~0xbfe7; + case 121: /* ea_daid32_fetch */ + elapsed += 4; + nmpc = decoded.a2; + break; + case 122: /* ea_daix_imm32 */ + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; + dib = fetch32(aob = pc + scan); + scan += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtf32; + continue; + } + break; + case 123: /* ea_dais_imm16 */ + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + dib = fetch16(aob = pc + scan); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + break; + case 124: /* ea_dais8_read */ + sswi |= 0x0800; + case 125: /* ea_dais8 */ + nmpc = 126; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 126: + ssw &= ~0xbfe7; + if ((irb & 0x0100) == 0) { + at = (byte) irb; + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + at += dt << ((irb & 0x0600) >> 9); + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + at += dar[ry]; + mpc = ea_dais8_fetch; + continue; + } + at = dt = 0; + if ((irb & 0x0040) == 0) { + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + dt <<= ((irb & 0x0600) >> 9); + } + if ((irb & 0x0080) == 0) { + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + at += dar[ry]; + } + nmpc = ea_dais8_base; + if ((irb & 0x0020) == 0) { + mpc = ea_dais8_no_base; + continue; + } else if ((irb & 0x0010) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 127: /* ea_dais8_base */ + at += dib; + ssw &= ~0xbfe7; + case 128: /* ea_dais8_no_base */ + if ((irb & 0x0004) == 0) { + at += dt; + dt = 0; + if ((irb & 0x0007) == 0) { + mpc = ea_dais8_fetch; + continue; + } + } + nmpc = 129; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 129: + at = dib; + at += dt; + ssw &= ~0xbfe7; + nmpc = ea_dais8_outer; + if ((irb & 0x0002) == 0) { + mpc = ea_dais8_fetch; + continue; + } else if ((irb & 0x0001) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 130: /* ea_dais8_outer */ + at += dib; + ssw &= ~0xbfe7; + case 131: /* ea_dais8_fetch */ + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a3; + break; + } + elapsed += 2; + mpc = ea_read8; + continue; + case 132: /* ea_dais16_read */ + sswi |= 0x0800; + case 133: /* ea_dais16 */ + nmpc = 134; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 134: + ssw &= ~0xbfe7; + if ((irb & 0x0100) == 0) { + at = (byte) irb; + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + at += dt << ((irb & 0x0600) >> 9); + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + at += dar[ry]; + mpc = ea_dais16_fetch; + continue; + } + at = dt = 0; + if ((irb & 0x0040) == 0) { + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + dt <<= ((irb & 0x0600) >> 9); + } + if ((irb & 0x0080) == 0) { + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + at += dar[ry]; + } + nmpc = ea_dais16_base; + if ((irb & 0x0020) == 0) { + mpc = ea_dais16_no_base; + continue; + } else if ((irb & 0x0010) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 135: /* ea_dais16_base */ + at += dib; + ssw &= ~0xbfe7; + case 136: /* ea_dais16_no_base */ + if ((irb & 0x0004) == 0) { + at += dt; + dt = 0; + if ((irb & 0x0007) == 0) { + mpc = ea_dais16_fetch; + continue; + } + } + nmpc = 137; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 137: + at = dib; + at += dt; + ssw &= ~0xbfe7; + nmpc = ea_dais16_outer; + if ((irb & 0x0002) == 0) { + mpc = ea_dais16_fetch; + continue; + } else if ((irb & 0x0001) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 138: /* ea_dais16_outer */ + at += dib; + ssw &= ~0xbfe7; + case 139: /* ea_dais16_fetch */ + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a3; + break; + } + elapsed += 2; + mpc = ea_read16; + continue; + case 140: /* ea_dais32_read */ + sswi |= 0x0800; + case 141: /* ea_dais32 */ + nmpc = 142; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 142: + ssw &= ~0xbfe7; + if ((irb & 0x0100) == 0) { + at = (byte) irb; + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + at += dt << ((irb & 0x0600) >> 9); + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + at += dar[ry]; + mpc = ea_dais32_fetch; + continue; + } + at = dt = 0; + if ((irb & 0x0040) == 0) { + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + dt <<= ((irb & 0x0600) >> 9); + } + if ((irb & 0x0080) == 0) { + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + at += dar[ry]; + } + nmpc = ea_dais32_base; + if ((irb & 0x0020) == 0) { + mpc = ea_dais32_no_base; + continue; + } else if ((irb & 0x0010) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 143: /* ea_dais32_base */ + at += dib; + ssw &= ~0xbfe7; + case 144: /* ea_dais32_no_base */ + if ((irb & 0x0004) == 0) { + at += dt; + dt = 0; + if ((irb & 0x0007) == 0) { + mpc = ea_dais32_fetch; + continue; + } + } + nmpc = 145; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 145: + at = dib; + at += dt; + ssw &= ~0xbfe7; + nmpc = ea_dais32_outer; + if ((irb & 0x0002) == 0) { + mpc = ea_dais32_fetch; + continue; + } else if ((irb & 0x0001) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 146: /* ea_dais32_outer */ + at += dib; + ssw &= ~0xbfe7; + case 147: /* ea_dais32_fetch */ + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a3; + break; + } + elapsed += 2; + mpc = ea_read32; + continue; + case 148: /* ea_dpc8_read */ + nmpc = 149; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 149: + at = dib; + at = ((short) at) + pc; + case 150: /* eapc_read8 */ + sswi &= ~0x0800; + alub = dt; + nmpc = 151; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9302; + dib = read8(aob = at); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + if ((ssw & 0x0600) == 0x0600) { + dib >>= 8; + } + case 151: + dt = (byte) dib; + ssw &= ~0xbfe7; + nmpc = decoded.a3; + break; + case 152: /* ea_dpc16_read */ + sswi |= 0x0800; + case 153: /* ea_dpc16 */ + nmpc = 154; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 154: + at = dib; + at = ((short) at) + pc; + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a3; + break; + } + case 155: /* eapc_read16 */ + sswi &= ~0x0800; + alub = dt; + nmpc = 156; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 156: + dt = (short) dib; + ssw &= ~0xbfe7; + nmpc = decoded.a3; + break; + case 157: /* ea_dpc32_read */ + nmpc = 158; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 158: + at = dib; + at = ((short) at) + pc; + case 159: /* eapc_read32 */ + alub = dt; + nmpc = 160; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtf32; + continue; + } + case 160: + dt = dib; + ssw &= ~0xbfe7; + nmpc = decoded.a3; + break; + case 161: /* ea_dpci8_read */ + nmpc = 162; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 162: + ssw &= ~0xbfe7; + if ((irb & 0x0100) == 0) { + at = (byte) irb; + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + at += dt << ((irb & 0x0600) >> 9); + at += pc; + mpc = ea_dpci8_fetch; + continue; + } + at = dt = 0; + if ((irb & 0x0040) == 0) { + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + dt <<= ((irb & 0x0600) >> 9); + } + if ((irb & 0x0080) == 0) { + at += pc; + } + nmpc = ea_dpci8_base; + if ((irb & 0x0020) == 0) { + mpc = ea_dpci8_no_base; + continue; + } else if ((irb & 0x0010) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 163: /* ea_dpci8_base */ + at += dib; + ssw &= ~0xbfe7; + case 164: /* ea_dpci8_no_base */ + if ((irb & 0x0004) == 0) { + at += dt; + dt = 0; + if ((irb & 0x0007) == 0) { + mpc = ea_dpci8_fetch; + continue; + } + } + nmpc = 165; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 165: + at = dib; + at += dt; + ssw &= ~0xbfe7; + nmpc = ea_dpci8_outer; + if ((irb & 0x0002) == 0) { + mpc = ea_dpci8_fetch; + continue; + } else if ((irb & 0x0001) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 166: /* ea_dpci8_outer */ + at += dib; + ssw &= ~0xbfe7; + case 167: /* ea_dpci8_fetch */ + elapsed += 2; + mpc = eapc_read8; + continue; + case 168: /* ea_dpci16_read */ + sswi |= 0x0800; + case 169: /* ea_dpci16 */ + nmpc = 170; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 170: + ssw &= ~0xbfe7; + if ((irb & 0x0100) == 0) { + at = (byte) irb; + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + at += dt << ((irb & 0x0600) >> 9); + at += pc; + mpc = ea_dpci16_fetch; + continue; + } + at = dt = 0; + if ((irb & 0x0040) == 0) { + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + dt <<= ((irb & 0x0600) >> 9); + } + if ((irb & 0x0080) == 0) { + at += pc; + } + nmpc = ea_dpci16_base; + if ((irb & 0x0020) == 0) { + mpc = ea_dpci16_no_base; + continue; + } else if ((irb & 0x0010) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 171: /* ea_dpci16_base */ + at += dib; + ssw &= ~0xbfe7; + case 172: /* ea_dpci16_no_base */ + if ((irb & 0x0004) == 0) { + at += dt; + dt = 0; + if ((irb & 0x0007) == 0) { + mpc = ea_dpci16_fetch; + continue; + } + } + nmpc = 173; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 173: + at = dib; + at += dt; + ssw &= ~0xbfe7; + nmpc = ea_dpci16_outer; + if ((irb & 0x0002) == 0) { + mpc = ea_dpci16_fetch; + continue; + } else if ((irb & 0x0001) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 174: /* ea_dpci16_outer */ + at += dib; + ssw &= ~0xbfe7; + case 175: /* ea_dpci16_fetch */ + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a3; + break; + } + elapsed += 2; + mpc = eapc_read16; + continue; + case 176: /* ea_dpci32_read */ + nmpc = 177; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 177: + ssw &= ~0xbfe7; + if ((irb & 0x0100) == 0) { + at = (byte) irb; + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + at += dt << ((irb & 0x0600) >> 9); + at += pc; + mpc = ea_dpci32_fetch; + continue; + } + at = dt = 0; + if ((irb & 0x0040) == 0) { + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = (irb & 0x0800) == 0 ? (short) dar[rz] : dar[rz]; + dt <<= ((irb & 0x0600) >> 9); + } + if ((irb & 0x0080) == 0) { + at += pc; + } + nmpc = ea_dpci32_base; + if ((irb & 0x0020) == 0) { + mpc = ea_dpci32_no_base; + continue; + } else if ((irb & 0x0010) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 178: /* ea_dpci32_base */ + at += dib; + ssw &= ~0xbfe7; + case 179: /* ea_dpci32_no_base */ + if ((irb & 0x0004) == 0) { + at += dt; + dt = 0; + if ((irb & 0x0007) == 0) { + mpc = ea_dpci32_fetch; + continue; + } + } + nmpc = 180; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 180: + at = dib; + at += dt; + ssw &= ~0xbfe7; + nmpc = ea_dpci32_outer; + if ((irb & 0x0002) == 0) { + mpc = ea_dpci32_fetch; + continue; + } else if ((irb & 0x0001) == 0) { + mpc = ea_dais_imm16; + continue; + } + mpc = ea_daix_imm32; + continue; + case 181: /* ea_dpci32_outer */ + at += dib; + ssw &= ~0xbfe7; + case 182: /* ea_dpci32_fetch */ + elapsed += 2; + mpc = eapc_read32; + continue; + case 183: /* ea_adr16d8 */ + nmpc = 184; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 184: + ssw &= ~0xbfe7; + at = (short) dib; + nmpc = decoded.a2; + break; + case 185: /* ea_adr16d16 */ + nmpc = 186; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 186: + ssw &= ~0xbfe7; + at = (short) dib; + nmpc = decoded.a2; + break; + case 187: /* ea_adr16d32 */ + nmpc = 188; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 188: + ssw &= ~0xbfe7; + at = (short) dib; + nmpc = decoded.a2; + break; + case 189: /* ea_adr16s8_read */ + sswi |= 0x0800; + case 190: /* ea_adr16s8 */ + nmpc = 191; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 191: + at = (short) dib; + if ((sswi & 0x0800) == 0) { + ssw &= ~0xbfe7; + nmpc = decoded.a3; + break; + } + mpc = ea_read8; + continue; + case 192: /* ea_adr16s16_read */ + sswi |= 0x0800; + case 193: /* ea_adr16s16 */ + nmpc = 194; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 194: + at = (short) dib; + if ((sswi & 0x0800) == 0) { + ssw &= ~0xbfe7; + nmpc = decoded.a3; + break; + } + mpc = ea_read16; + continue; + case 195: /* ea_adr16s32_read */ + sswi |= 0x0800; + case 196: /* ea_adr16s32 */ + nmpc = 197; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 197: + at = (short) dib; + if ((sswi & 0x0800) == 0) { + ssw &= ~0xbfe7; + nmpc = decoded.a3; + break; + } + mpc = ea_read32; + continue; + case 198: /* ea_adr32d8 */ + case 199: /* ea_adr32d16 */ + case 200: /* ea_adr32d32 */ + nmpc = 201; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch32(aob); + scan += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtf32; + continue; + } + case 201: + at = dib; + ssw &= ~0xbfe7; + nmpc = decoded.a2; + break; + case 202: /* ea_adr32s8_read */ + sswi |= 0x0800; + case 203: /* ea_adr32s8 */ + nmpc = 204; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch32(aob); + scan += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtf32; + continue; + } + case 204: + at = dib; + if ((sswi & 0x0800) == 0) { + ssw &= ~0xbfe7; + nmpc = decoded.a3; + break; + } + mpc = ea_read8; + continue; + case 205: /* ea_adr32s16_read */ + sswi |= 0x0800; + case 206: /* ea_adr32s16 */ + nmpc = 207; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch32(aob); + scan += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtf32; + continue; + } + case 207: + at = dib; + if ((sswi & 0x0800) == 0) { + ssw &= ~0xbfe7; + nmpc = decoded.a3; + break; + } + mpc = ea_read16; + continue; + case 208: /* ea_adr32s32_read */ + sswi |= 0x0800; + case 209: /* ea_adr32s32 */ + nmpc = 210; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch32(aob); + scan += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtf32; + continue; + } + case 210: + at = dib; + if ((sswi & 0x0800) == 0) { + ssw &= ~0xbfe7; + nmpc = decoded.a3; + break; + } + mpc = ea_read32; + continue; + case 211: /* ea_imm8_read */ + nmpc = 212; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 212: + ssw &= ~0xbfe7; + dt = (byte) dib; + nmpc = decoded.a3; + break; + case 213: /* ea_imm16_read */ + nmpc = 214; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 214: + ssw &= ~0xbfe7; + dt = (short) dib; + nmpc = decoded.a3; + break; + case 215: /* ea_imm32_read */ + nmpc = 216; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch32(aob); + scan += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtf32; + continue; + } + case 216: + dt = dib; + ssw &= ~0xbfe7; + nmpc = decoded.a3; + break; + case 217: /* op_movepw_dd_das */ + rx = (ir >> 9) & 0x0007; + dt = dar[rx]; + nmpc = 218; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 218: + nmpc = 219; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; + write8(aob = at, dob = dt >> 8); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 219: + nmpc = 220; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; + write8(aob = at + 0x0002, dob = dt); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 220: + mpc = resume; + continue; + case 221: /* op_movepw_das_dd */ + rx = (ir >> 9) & 0x0007; + nmpc = 222; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9301; + dib = read8(aob = at); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + if ((ssw & 0x0600) == 0x0600) { + dib >>= 8; + } + case 222: + dt = dib; + nmpc = 223; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9301; + dib = read8(aob = at + 0x0002); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + if ((ssw & 0x0600) == 0x0600) { + dib >>= 8; + } + case 223: + dt = (dt << 8) | (dib & 0xff); + dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 224: /* op_movepl_dd_das */ + rx = (ir >> 9) & 0x0007; + dt = dar[rx]; + nmpc = 225; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 225: + nmpc = 226; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; + write8(aob = at, dob = dt >> 24); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 226: + nmpc = 227; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; + write8(aob = at + 0x0002, dob = dt >> 16); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 227: + nmpc = 228; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; + write8(aob = at + 0x0004, dob = dt >> 8); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 228: + nmpc = 229; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; + write8(aob = at + 0x0006, dob = dt); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 229: + mpc = resume; + continue; + case 230: /* op_movepl_das_dd */ + rx = (ir >> 9) & 0x0007; + nmpc = 231; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9301; + dib = read8(aob = at); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + if ((ssw & 0x0600) == 0x0600) { + dib >>= 8; + } + case 231: + dt = dib; + nmpc = 232; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9301; + dib = read8(aob = at + 0x0002); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + if ((ssw & 0x0600) == 0x0600) { + dib >>= 8; + } + case 232: + dt = (dt << 8) | (dib & 0xff); + nmpc = 233; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9301; + dib = read8(aob = at + 0x0004); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + if ((ssw & 0x0600) == 0x0600) { + dib >>= 8; + } + case 233: + dt = (dt << 8) | (dib & 0xff); + nmpc = 234; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9301; + dib = read8(aob = at + 0x0006); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + if ((ssw & 0x0600) == 0x0600) { + dib >>= 8; + } + case 234: + dt = (dt << 8) | (dib & 0xff); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 235: /* op_clrb_ds */ + ry = ir & 0x0007; + dar[ry] &= ~0xff; + mpc = resume_prefetch; + continue; + case 236: /* op_clrw_ds */ + ry = ir & 0x0007; + dar[ry] &= ~0xffff; + mpc = resume_prefetch; + continue; + case 237: /* op_clrl_ds */ + ry = ir & 0x0007; + dar[ry] = 0; + mpc = resume_prefetch; + continue; + case 238: /* op_clrb_ea */ + dt = 0; + mpc = ea_resume_write8; + continue; + case 239: /* op_clrw_ea */ + dt = 0; + mpc = ea_resume_write16; + continue; + case 240: /* op_clrl_ea */ + dt = 0; + mpc = ea_resume_write32; + continue; + case 241: /* op_lea_ea_ad */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = at; + mpc = resume_prefetch; + continue; + case 242: /* op_pea */ + au = dar[sp] - 4; + dar[sp] = au; + nmpc = 243; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; + if (((aob = au) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write32(aob, dob = at); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtw32; + continue; + } + case 243: + mpc = resume_prefetch; + continue; + case 244: /* op_swap_ds */ + ry = ir & 0x0007; + dar[ry] = (dar[ry] << 16) | (dar[ry] >>> 16); + long_tst(dar[ry]); + mpc = resume_prefetch; + continue; + case 245: /* op_extw_ds */ + ry = ir & 0x0007; + dar[ry] = (dar[ry] & ~0xffff) | (((byte) dar[ry]) & 0xffff); + word_tst(dar[ry]); + mpc = resume_prefetch; + continue; + case 246: /* op_extl_ds */ + ry = ir & 0x0007; + dar[ry] = (short) dar[ry]; + long_tst(dar[ry]); + mpc = resume_prefetch; + continue; + case 247: /* op_extbl_ds */ + ry = ir & 0x0007; + dar[ry] = (byte) dar[ry]; + long_tst(dar[ry]); + mpc = resume_prefetch; + continue; + case 248: /* op_exg_dd_ds */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dar[rx] ^= dar[ry]; + dar[ry] ^= dar[rx]; + dar[rx] ^= dar[ry]; + mpc = resume_prefetch; + continue; + case 249: /* op_exg_ad_as */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] ^= dar[ry]; + dar[ry] ^= dar[rx]; + dar[rx] ^= dar[ry]; + mpc = resume_prefetch; + continue; + case 250: /* op_exg_dd_as */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + dar[rx] ^= dar[ry]; + dar[ry] ^= dar[rx]; + dar[rx] ^= dar[ry]; + mpc = resume_prefetch; + continue; + case 251: /* op_scc_b_ds */ + ry = ir & 0x0007; + if (testCC((ir & 0x0f00) >> 8)) { + dar[ry] |= 0xff; + } else { + dar[ry] &= ~0xff; + } + mpc = resume_prefetch; + continue; + case 252: /* op_scc_b_ea */ + dt = testCC((ir & 0x0f00) >> 8) ? -1 : 0; + mpc = ea_resume_write8; + continue; + case 253: /* op_chk_w_ds */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + if (word_chk(dar[ry], dar[rx])) { + tvn = 24; + mpc = (sswi & 0x0008) != 0 ? trap2000 : trap0000; + } + mpc = resume_prefetch; + continue; + case 254: /* op_chk_w_ea */ + rx = (ir >> 9) & 0x0007; + if (word_chk(dt, dar[rx])) { + tvn = 24; + mpc = (sswi & 0x0008) != 0 ? trap2000 : trap0000; + } + mpc = resume_prefetch; + continue; + case 255: /* op_link_as_imm16 */ + au = dar[sp] - 4; + dar[sp] = au + ((short) dt); + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + nmpc = 256; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; + if (((aob = au) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write32(aob, dob = dar[ry]); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtw32; + continue; + } + case 256: + dar[ry] = au; + mpc = resume_prefetch; + continue; + case 257: /* op_link_as_imm32 */ + au = dar[sp] - 4; + dar[sp] = au + dt; + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + nmpc = 258; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; + if (((aob = au) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write32(aob, dob = dar[ry]); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtw32; + continue; + } + case 258: + dar[ry] = au; + mpc = resume_prefetch; + continue; + case 259: /* op_unlk_as */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + au = dar[ry]; + dar[sp] = au + 4; + nmpc = 260; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; + if (((aob = au) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 260: + dar[ry] = dib; + mpc = resume_prefetch; + continue; + case 261: /* op_move_usp_as */ + if ((sr & 0x2000) == 0) { + elapsed += 6; + tvn = 32; + mpc = trapill; + continue; + } + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dar[ry] = dar[15]; + mpc = resume_prefetch; + continue; + case 262: /* op_move_as_usp */ + if ((sr & 0x2000) == 0) { + elapsed += 6; + tvn = 32; + mpc = trapill; + continue; + } + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dar[15] = dar[ry]; + mpc = resume_prefetch; + continue; + case 263: /* op_movec_cr_rz */ + if ((sr & 0x2000) == 0) { + elapsed += 6; + tvn = 32; + mpc = trapill; + continue; + } + nmpc = 264; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 264: + ssw &= ~0xbfe7; + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = irb & 0x0fff; + if (dt == 0x000) { + dar[rz] = sfc; + } else if (dt == 0x001) { + dar[rz] = dfc; + } else if (dt == 0x800) { + dar[rz] = dar[15]; + } else if (dt == 0x801) { + dar[rz] = vbr; + } else if (dt == 0x803) { + dar[rz] = dar[17]; + } else if (dt == 0x804) { + dar[rz] = dar[16]; + } else { + tvn = 16; + mpc = trapill; + continue; + } + mpc = resume_prefetch; + continue; + case 265: /* op_movec_rz_cr */ + if ((sr & 0x2000) == 0) { + elapsed += 6; + tvn = 32; + mpc = trapill; + continue; + } + nmpc = 266; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 266: + ssw &= ~0xbfe7; + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = irb & 0x0fff; + if (dt == 0x000) { + sfc = dar[rz] & 0x7; + } else if (dt == 0x001) { + dfc = dar[rz] & 0x7; + } else if (dt == 0x800) { + dar[15] = dar[rz]; + } else if (dt == 0x801) { + vbr = dar[rz]; + } else if (dt == 0x803) { + dar[17] = dar[rz]; + } else if (dt == 0x804) { + dar[16] = dar[rz]; + } else { + tvn = 16; + mpc = trapill; + continue; + } + mpc = resume_prefetch; + continue; + case 267: /* op_movemw_rr_ea */ + nmpc = 268; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 268: + dt = dib; + nmpc = 269; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 269: + alub = 0; + nmpc = 270; + case 270: + if (alub >= 16) { + ssw &= ~0xbfe7; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 270; + continue; + } + rz = alub == 15 ? sp : alub; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8001; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write16(aob, dob = dar[rz]); + alub += 1; + at += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + mpc = 270; + continue; + case 271: /* op_movemw_rr_pais */ + nmpc = 272; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 272: + dt = dib; + nmpc = 273; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 273: + alub = 0; + nmpc = 274; + case 274: + if (alub >= 16) { + ssw &= ~0xbfe7; + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dar[ry] = at; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 274; + continue; + } + rz = alub == 0 ? sp : 15 - alub; + at -= 2; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8001; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write16(aob, dob = dar[rz]); + alub += 1; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + mpc = 274; + continue; + case 275: /* op_moveml_rr_ea */ + nmpc = 276; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 276: + dt = dib; + nmpc = 277; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 277: + alub = 0; + nmpc = 278; + case 278: + if (alub >= 16) { + ssw &= ~0xbfe7; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 278; + continue; + } + rz = alub == 15 ? sp : alub; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write32(aob, dob = dar[rz]); + alub += 1; + at += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtw32; + continue; + } + mpc = 278; + continue; + case 279: /* op_moveml_rr_pais */ + nmpc = 280; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 280: + dt = dib; + nmpc = 281; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 281: + alub = 0; + nmpc = 282; + case 282: + if (alub >= 16) { + ssw &= ~0xbfe7; + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dar[ry] = at; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 282; + continue; + } + rz = alub == 0 ? sp : 15 - alub; + at -= 4; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write32(aob, dob = dar[rz]); + alub += 1; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtw32; + continue; + } + mpc = 282; + continue; + case 283: /* op_movemw_ea_rr */ + nmpc = 284; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 284: + dt = dib; + nmpc = 285; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 285: + alub = 0; + nmpc = 286; + case 286: + if (alub >= 16) { + ssw &= ~0xbfe7; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 286; + continue; + } + rz = alub == 15 ? sp : alub; + nmpc = 287; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9100; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read16(aob); + alub += 1; + at += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 287: + dar[rz] = (short) dib; + mpc = 286; + continue; + case 288: /* op_movemw_aisp_rr */ + nmpc = 289; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 289: + dt = dib; + nmpc = 290; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 290: + alub = 0; + nmpc = 291; + case 291: + if (alub >= 16) { + ssw &= ~0xbfe7; + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dar[ry] = at; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 291; + continue; + } + rz = alub == 15 ? sp : alub; + nmpc = 292; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9100; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read16(aob); + alub += 1; + at += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 292: + dar[rz] = (short) dib; + mpc = 291; + continue; + case 293: /* op_moveml_ea_rr */ + nmpc = 294; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 294: + dt = dib; + nmpc = 295; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 295: + alub = 0; + nmpc = 296; + case 296: + if (alub >= 16) { + ssw &= ~0xbfe7; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 296; + continue; + } + rz = alub == 15 ? sp : alub; + nmpc = 297; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c0; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + alub += 1; + at += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 297: + dar[rz] = dib; + mpc = 296; + continue; + case 298: /* op_moveml_aisp_rr */ + nmpc = 299; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 299: + dt = dib; + nmpc = 300; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 300: + alub = 0; + nmpc = 301; + case 301: + if (alub >= 16) { + ssw &= ~0xbfe7; + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dar[ry] = at; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 301; + continue; + } + rz = alub == 15 ? sp : alub; + nmpc = 302; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c0; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + alub += 1; + at += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 302: + dar[rz] = dib; + mpc = 301; + continue; + case 303: /* op_bcc8 */ + if (!testCC((ir & 0x0f00) >> 8)) { + elapsed += 2; + mpc = resume_prefetch; + continue; + } + case 304: /* op_bra8 */ + elapsed += 2; + scan = pc + ((byte) ir); + sswi |= (sr & 0x4000); + mpc = resume_prefetch; + continue; + case 305: /* op_bcc16 */ + if (!testCC((ir & 0x0f00) >> 8)) { + elapsed += 2; + mpc = resume_prefetch; + continue; + } + case 306: /* op_bra16 */ + elapsed += 2; + scan = pc + dt; + sswi |= (sr & 0x4000); + mpc = resume_prefetch; + continue; + case 307: /* op_bcc32 */ + if (!testCC((ir & 0x0f00) >> 8)) { + elapsed += 2; + mpc = resume_prefetch; + continue; + } + case 308: /* op_bra32 */ + elapsed += 2; + scan = pc + dt; + sswi |= (sr & 0x4000); + mpc = resume_prefetch; + continue; + case 309: /* op_bsr8 */ + elapsed += 2; + au = dar[sp] - 4; + dar[sp] = au; + nmpc = 310; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; + if (((aob = au) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write32(aob, dob = pc + scan); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtw32; + continue; + } + case 310: + scan = pc + ((byte) ir); + sswi |= (sr & 0x4000); + mpc = resume_prefetch; + continue; + case 311: /* op_bsr16 */ + elapsed += 2; + au = dar[sp] - 4; + dar[sp] = au; + nmpc = 312; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; + if (((aob = au) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write32(aob, dob = pc + scan); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtw32; + continue; + } + case 312: + scan = pc + dt; + sswi |= (sr & 0x4000); + mpc = resume_prefetch; + continue; + case 313: /* op_bsr32 */ + elapsed += 2; + au = dar[sp] - 4; + dar[sp] = au; + nmpc = 314; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; + if (((aob = au) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write32(aob, dob = pc + scan); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtw32; + continue; + } + case 314: + scan = pc + dt; + sswi |= (sr & 0x4000); + mpc = resume_prefetch; + continue; + case 315: /* op_dbcc */ + if (testCC((ir & 0x0f00) >> 8)) { + elapsed += 2; + scan += 2; + mpc = resume_prefetch; + continue; + } + ry = ir & 0x0007; + dar[ry] = (dar[ry] & ~0xffff) | ((dt = ((short) dar[ry]) - 1) & 0xffff); + if (dt == -1) { + elapsed += 4; + scan += 2; + mpc = resume_prefetch; + continue; + } + nmpc = 316; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 316: + scan = dib; + elapsed += 2; + mpc = resume_prefetch; + continue; + case 317: /* op_bkpt */ + elapsed += 6; + hdlr = handle_bkpt(cip, ir & 0x0007); + exit |= (hdlr & 0x00010000) != 0; + if ((hdlr & 0x00020000) != 0) { + ir = hdlr & 0xffff; + sp = spi(sr); + decoded = MacroPLA.decode(ir); + nmpc = decoded.a1; + break; + } + tvn = 16; + mpc = trapill; + continue; + case 318: /* op_illegal */ + elapsed += 6; + hdlr = handle_illegal(cip, ir); + exit |= (hdlr & 0x00010000) != 0; + if ((hdlr & 0x00020000) != 0) { + scan += (short) hdlr; + sp = spi(sr); + mpc = resume_prefetch; + continue; + } + tvn = 16; + mpc = trapill; + continue; + case 319: /* op_jmp */ + pc = at; + scan = 0; + sswi |= (sr & 0x4000); + mpc = resume_prefetch; + continue; + case 320: /* op_jsr */ + au = dar[sp] - 4; + dar[sp] = au; + nmpc = 321; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; + if (((aob = au) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write32(aob, dob = pc + scan); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtw32; + continue; + } + case 321: + pc = at; + scan = 0; + sswi |= (sr & 0x4000); + mpc = resume_prefetch; + continue; + case 322: /* op_linea */ + elapsed += 6; + hdlr = handle_linea(cip, ir & 0x0fff); + exit |= (hdlr & 0x00010000) != 0; + if ((hdlr & 0x00020000) != 0) { + scan += (short) hdlr; + sp = spi(sr); + mpc = resume_prefetch; + continue; + } + tvn = 40; + mpc = trapill; + continue; + case 323: /* op_linef */ + elapsed += 6; + tvn = 44; + mpc = trapill; + continue; + case 324: /* op_nop */ + mpc = resume_prefetch; + continue; + case 325: /* op_rte */ + if ((sr & 0x2000) == 0) { + elapsed += 6; + tvn = 32; + mpc = trapill; + continue; + } + au = dar[sp]; + case 326: /* check_vob */ + elapsed += 4; + ssw = (ssw & 0x0018) | 0x9105; + if (((aob = au + 0x0006) & 0x000000001) != 0) { + mpc = dbrr; + continue; + } + dib = read16(aob); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + mpc = select_rte(dib); + continue; + case 327: /* rteill */ + elapsed += 6; + tvn = 56; + mpc = trapill; + continue; + case 328: /* exit_trap */ + elapsed += 8; + ssw = (ssw & 0x0018) | 0x91c5; + pc = read32(aob = au + 0x0002); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x9105; + dib = read16(aob = au); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + sr = dib & 0xf71f; + sp = spi(sr); + scan = 0; + mpc = resume_prefetch; + continue; + case 329: /* rte0000 */ + dar[sp] = au + 8; + mpc = exit_trap; + continue; + case 330: /* rte1000 */ + dar[sp] = au + 8; + au = dar[sp = spi(sr | 0x1000)]; + mpc = check_vob; + continue; + case 331: /* rte2000 */ + dar[sp] = au + 12; + mpc = exit_trap; + continue; + case 332: /* rte8000 */ + elapsed += 6; + elapsed += 8; + ssw = (ssw & 0x0018) | 0x91c5; + cip = read32(aob = au + 0x0036); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x91c5; + dt = read32(aob = au + 0x0032); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x9105; + ir = read16(aob = au + 0x0030); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + decoded = MacroPLA.decode(ir); + elapsed += 4; + ssw = (ssw & 0x0018) | 0x9105; + dib = read16(aob = au + 0x002e); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + vdt1 = dib << 16; + elapsed += 8; + ssw = (ssw & 0x0018) | 0x91c5; + vat2 = read32(aob = au + 0x0026); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x91c5; + vat1 = read32(aob = au + 0x0022); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x91c5; + alub = read32(aob = au + 0x001e); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x9105; + scan = read16(aob = au + 0x001c); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x9105; + nmpc = read16(aob = au + 0x001a); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x9105; + irb = read16(aob = au + 0x0018); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 8; + ssw = (ssw & 0x0018) | 0x91c5; + vat3 = read32(aob = au + 0x000a); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x9105; + dib = read16(aob = au + 0x0008); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + vdt1 |= dib & 0xffff; + elapsed += 8; + ssw = (ssw & 0x0018) | 0x91c5; + pc = read32(aob = au + 0x0002); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + if ((vdt1 & 0x8000) == 0) { + elapsed += 2; + if ((vdt1 & 0x0800) != 0) { + nmpc = decoded.a3; + vdt1 &= ~0xbfe7; + } else { + if ((vdt1 & 0x0100) == 0) { + if ((vdt1 & 0x0080) != 0) { + elapsed += 8; + ssw = (ssw & 0x0018) | 0x91c5; + vdt2 = read32(aob = au + 0x0010); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + } else { + elapsed += 4; + ssw = (ssw & 0x0018) | 0x9105; + vdt2 = read16(aob = au + 0x0010); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + } + } else if ((vdt1 & 0x00c0) == 0x0040) { + elapsed += 4; + ssw = (ssw & 0x0018) | 0x9105; + vdt3 = read16(aob = au + 0x0012); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + vdt3 <<= 16; + } + ssw = (ssw & 0x0018) | ((vdt1 ^ ~0x8000) & 0xbfc7); + if ((ssw & 0x0280) == 0x0200) { + if ((ssw & 0x0400) == 0) { + vat3 += 1; + } else { + ssw &= ~0x0400; + vdt2 >>= 8; + } + if ((ssw & 0x1100) == 0x1100) { + vdt3 = read8(vat3); + } else if ((ssw & 0x1100) == 0) { + write8(vat3, vdt2); + } + } else if ((vat3 & 0x000000001) != 0) { + elapsed += 6; + tvn = 12; + mpc = resume_trap8000; + continue; + } else if ((ssw & 0x0080) == 0) { + if ((ssw & 0x3100) == 0x2100) { + if ((ssw & 0x0003) == 0x0002) { + irb = fetch16(vat3); + } else { + irb = read16(vat3); + } + } else if ((ssw & 0x3140) == 0x1140) { + if ((ssw & 0x0003) == 0x0002) { + vdt3 = (vdt3 & ~0xffff) | fetch16(vat3) & 0xffff; + } else { + vdt3 = (vdt3 & ~0xffff) | read16(vat3) & 0xffff; + } + } else if ((ssw & 0x3100) == 0x1100) { + if ((ssw & 0x0003) == 0x0002) { + vdt3 = fetch16(vat3); + } else { + vdt3 = read16(vat3); + } + } else if ((ssw & 0x3100) == 0) { + write16(vat3, vdt2); + } + } else { + if ((ssw & 0x3100) == 0x2100) { + if ((ssw & 0x0003) == 0x0002) { + vdt3 = fetch32(vat3); + } else { + vdt3 = read32(vat3); + } + } else if ((ssw & 0x3100) == 0) { + write32(vat3, vdt2); + } + } + vdt1 = (vdt1 & ~0xffff) | ((ssw ^ ~0x8000) & 0xffdf); + if ((ssw & 0x0020) != 0) { + elapsed += 6; + tvn = 8; + mpc = resume_trap8000; + continue; + } + } + } else if ((vdt1 & 0x0100) != 0) { + if ((vdt1 & 0x0040) != 0) { + elapsed += 8; + ssw = (ssw & 0x0018) | 0x91c5; + vdt3 = read32(aob = au + 0x0012); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + } else { + elapsed += 4; + ssw = (ssw & 0x0018) | 0x9105; + vdt3 = read16(aob = au + 0x0014); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + } + } + elapsed += 4; + ssw = (ssw & 0x0018) | 0x9105; + dib = read16(aob = au); + if ((ssw & 0x0030) != 0) { + mpc = dbrr; + continue; + } + sr = dib & 0xf71f; + dar[sp] = au + 58; + sp = spi(sr); + au = vat1; + at = vat2; + aob = vat3; + dob = vdt2; + dib = vdt3; + tvn = (vdt1 >> 14) & 0x3fc; + sswi = (sswi & ~0xc800) | ((vdt1 >> 16) & 0xc800); + ssw = (ssw & 0x0018) | ((vdt1 ^ ~0x8000) & 0xbfc7); + if ((ssw & 0x80c0) == 0x8080) { + if ((ssw & 0x0100) != 0) { + mpc = (ssw & 0x0003) == 0x0002 ? bevtf32 : bevtr32; + } else { + mpc = bevtw32; + } + continue; + } + break; + case 333: /* op_rtr */ + au = dar[sp]; + nmpc = 334; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; + if (((aob = au + 0x0002) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 334: + pc = dib; + nmpc = 335; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9101; + dib = read16(aob = au); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 335: + ssw &= ~0xbfe7; + sr = (sr & ~0x001f) | (dib & 0x001f); + scan = 0; + dar[sp] = au + 6; + sswi |= (sr & 0x4000); + mpc = resume_prefetch; + continue; + case 336: /* op_rts */ + au = dar[sp]; + nmpc = 337; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; + if (((aob = au) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 337: + pc = dib; + ssw &= ~0xbfe7; + scan = 0; + dar[sp] = au + 4; + sswi |= (sr & 0x4000); + mpc = resume_prefetch; + continue; + case 338: /* op_reset */ + elapsed += 126; + mpc = resume_prefetch; + continue; + case 339: /* op_trap */ + elapsed += 6; + tvn = (32 + (ir & 0x000f)) << 2; + mpc = trap0000; + continue; + case 340: /* op_trapv */ + if ((sr & 0x0002) != 0) { + elapsed += 4; + tvn = 28; + mpc = (sswi & 0x0008) != 0 ? trap2000 : trap0000; + continue; + } + mpc = resume_prefetch; + continue; + case 341: /* op_trapcc */ + if (!testCC((ir & 0x0f00) >> 8)) { + mpc = resume_prefetch; + continue; + } + elapsed += 4; + tvn = 28; + mpc = trap2000; + continue; + case 342: /* op_trapcc16 */ + scan += 2; + if (!testCC((ir & 0x0f00) >> 8)) { + mpc = resume_prefetch; + continue; + } + elapsed += 4; + tvn = 28; + mpc = trap2000; + continue; + case 343: /* op_trapcc32 */ + scan += 4; + if (!testCC((ir & 0x0f00) >> 8)) { + mpc = resume_prefetch; + continue; + } + elapsed += 4; + tvn = 28; + mpc = trap2000; + continue; + case 344: /* gen_orb_dt_ds */ + ry = ir & 0x0007; + dt = byte_or(dt, dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 345: /* gen_orb_im_ea */ + dt = byte_or(alub, dt); + mpc = ea_resume_write8; + continue; + case 346: /* gen_orw_dt_ds */ + ry = ir & 0x0007; + dt = word_or(dt, dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 347: /* gen_orw_im_ea */ + dt = word_or(alub, dt); + mpc = ea_resume_write16; + continue; + case 348: /* gen_orl_dt_ds */ + ry = ir & 0x0007; + dt = long_or(dt, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 349: /* gen_orl_im_ea */ + dt = long_or(alub, dt); + mpc = ea_resume_write32; + continue; + case 350: /* gen_orb_dt_ccr */ + sr = (sr & ~0xff) | ((sr | dt) & 0x1f); + mpc = resume_prefetch; + continue; + case 351: /* gen_orw_dt_sr */ + if ((sr & 0x2000) == 0) { + elapsed += 6; + tvn = 32; + mpc = trapill; + continue; + } + sr = (sr | dt) & 0xf71f; + mpc = resume_prefetch; + continue; + case 352: /* gen_btstl_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + long_btst(dar[rx], dar[ry]); + mpc = resume_prefetch; + continue; + case 353: /* gen_btstb_dd_ea */ + rx = (ir >> 9) & 0x0007; + byte_btst(dar[rx], dt); + mpc = resume_prefetch; + continue; + case 354: /* gen_bchgl_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = long_bchg(dar[rx], dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 355: /* gen_bchgb_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = byte_bchg(dar[rx], dt); + mpc = ea_resume_write8; + continue; + case 356: /* gen_bclrl_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = long_bclr(dar[rx], dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 357: /* gen_bclrb_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = byte_bclr(dar[rx], dt); + mpc = ea_resume_write8; + continue; + case 358: /* gen_bsetl_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = long_bset(dar[rx], dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 359: /* gen_bsetb_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = byte_bset(dar[rx], dt); + mpc = ea_resume_write8; + continue; + case 360: /* gen_andb_dt_ds */ + ry = ir & 0x0007; + dt = byte_and(dt, dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 361: /* gen_andb_im_ea */ + dt = byte_and(alub, dt); + mpc = ea_resume_write8; + continue; + case 362: /* gen_andw_dt_ds */ + ry = ir & 0x0007; + dt = word_and(dt, dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 363: /* gen_andw_im_ea */ + dt = word_and(alub, dt); + mpc = ea_resume_write16; + continue; + case 364: /* gen_andl_dt_ds */ + ry = ir & 0x0007; + dt = long_and(dt, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 365: /* gen_andl_im_ea */ + dt = long_and(alub, dt); + mpc = ea_resume_write32; + continue; + case 366: /* gen_andb_dt_ccr */ + sr = (sr & ~0xff) | (sr & dt & 0x1f); + mpc = resume_prefetch; + continue; + case 367: /* gen_andw_dt_sr */ + if ((sr & 0x2000) == 0) { + elapsed += 6; + tvn = 32; + mpc = trapill; + continue; + } + sr = sr & dt; + mpc = resume_prefetch; + continue; + case 368: /* gen_subb_dt_ds */ + ry = ir & 0x0007; + dt = byte_sub(dt, dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 369: /* gen_subb_im_ea */ + dt = byte_sub(alub, dt); + mpc = ea_resume_write8; + continue; + case 370: /* gen_subw_dt_ds */ + ry = ir & 0x0007; + dt = word_sub(dt, dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 371: /* gen_subw_im_ea */ + dt = word_sub(alub, dt); + mpc = ea_resume_write16; + continue; + case 372: /* gen_subl_dt_ds */ + ry = ir & 0x0007; + dt = long_sub(dt, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 373: /* gen_subl_im_ea */ + dt = long_sub(alub, dt); + mpc = ea_resume_write32; + continue; + case 374: /* gen_addb_dt_ds */ + ry = ir & 0x0007; + dt = byte_add(dt, dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 375: /* gen_addb_im_ea */ + dt = byte_add(alub, dt); + mpc = ea_resume_write8; + continue; + case 376: /* gen_addw_dt_ds */ + ry = ir & 0x0007; + dt = word_add(dt, dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 377: /* gen_addw_im_ea */ + dt = word_add(alub, dt); + mpc = ea_resume_write16; + continue; + case 378: /* gen_addl_dt_ds */ + ry = ir & 0x0007; + dt = long_add(dt, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 379: /* gen_addl_im_ea */ + dt = long_add(alub, dt); + mpc = ea_resume_write32; + continue; + case 380: /* gen_btstl_dt_ds */ + ry = ir & 0x0007; + long_btst(dt, dar[ry]); + mpc = resume_prefetch; + continue; + case 381: /* gen_btstb_im_ea */ + byte_btst(alub, dt); + mpc = resume_prefetch; + continue; + case 382: /* gen_bchgl_dt_ds */ + ry = ir & 0x0007; + dt = long_bchg(dt, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 383: /* gen_bchgb_im_ea */ + dt = byte_bchg(alub, dt); + mpc = ea_resume_write8; + continue; + case 384: /* gen_bclrl_dt_ds */ + ry = ir & 0x0007; + dt = long_bclr(dt, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 385: /* gen_bclrb_im_ea */ + dt = byte_bclr(alub, dt); + mpc = ea_resume_write8; + continue; + case 386: /* gen_bsetl_dt_ds */ + ry = ir & 0x0007; + dt = long_bset(dt, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 387: /* gen_bsetb_im_ea */ + dt = byte_bset(alub, dt); + mpc = ea_resume_write8; + continue; + case 388: /* gen_eorb_dt_ds */ + ry = ir & 0x0007; + dt = byte_eor(dt, dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 389: /* gen_eorb_im_ea */ + dt = byte_eor(alub, dt); + mpc = ea_resume_write8; + continue; + case 390: /* gen_eorw_dt_ds */ + ry = ir & 0x0007; + dt = word_eor(dt, dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 391: /* gen_eorw_im_ea */ + dt = word_eor(alub, dt); + mpc = ea_resume_write16; + continue; + case 392: /* gen_eorl_dt_ds */ + ry = ir & 0x0007; + dt = long_eor(dt, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 393: /* gen_eorl_im_ea */ + dt = long_eor(alub, dt); + mpc = ea_resume_write32; + continue; + case 394: /* gen_eorb_dt_ccr */ + sr = (sr & ~0xff) | ((sr ^ dt) & 0x1f); + mpc = resume_prefetch; + continue; + case 395: /* gen_eorw_dt_sr */ + if ((sr & 0x2000) == 0) { + elapsed += 6; + tvn = 32; + mpc = trapill; + continue; + } + sr = (sr ^ dt) & 0xf71f; + mpc = resume_prefetch; + continue; + case 396: /* gen_cmpb_dt_ds */ + ry = ir & 0x0007; + byte_sub(dt, dar[ry]); + mpc = resume_prefetch; + continue; + case 397: /* gen_cmpb_im_ea */ + byte_sub(alub, dt); + mpc = resume_prefetch; + continue; + case 398: /* gen_cmpw_dt_ds */ + ry = ir & 0x0007; + word_sub(dt, dar[ry]); + mpc = resume_prefetch; + continue; + case 399: /* gen_cmpw_im_ea */ + word_sub(alub, dt); + mpc = resume_prefetch; + continue; + case 400: /* gen_cmpl_dt_ds */ + ry = ir & 0x0007; + long_sub(dt, dar[ry]); + mpc = resume_prefetch; + continue; + case 401: /* gen_cmpl_im_ea */ + long_sub(alub, dt); + mpc = resume_prefetch; + continue; + case 402: /* gen_moveb_ds_ea */ + ry = ir & 0x0007; + byte_tst(dar[ry]); + dt = dar[ry]; + mpc = ea_resume_write8; + continue; + case 403: /* gen_moveb_dt_dd */ + rx = (ir >> 9) & 0x0007; + byte_tst(dt); + dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 404: /* gen_moveb_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + byte_tst(dar[ry]); + dar[rx] = (dar[rx] & ~0xff) | (dar[ry] & 0xff); + mpc = resume_prefetch; + continue; + case 405: /* gen_moveb_dt_ea */ + byte_tst(dt); + mpc = ea_resume_write8; + continue; + case 406: /* gen_movel_ds_ea */ + ry = ir & 0x0007; + long_tst(dar[ry]); + dt = dar[ry]; + mpc = ea_resume_write32; + continue; + case 407: /* gen_movel_as_ea */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + long_tst(dar[ry]); + dt = dar[ry]; + mpc = ea_resume_write32; + continue; + case 408: /* gen_movel_dt_dd */ + rx = (ir >> 9) & 0x0007; + long_tst(dt); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 409: /* gen_movel_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + long_tst(dar[ry]); + dar[rx] = dar[ry]; + mpc = resume_prefetch; + continue; + case 410: /* gen_movel_as_dd */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + long_tst(dar[ry]); + dar[rx] = dar[ry]; + mpc = resume_prefetch; + continue; + case 411: /* gen_movel_dt_ea */ + long_tst(dt); + mpc = ea_resume_write32; + continue; + case 412: /* gen_movel_ds_ad */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dar[ry]; + mpc = resume_prefetch; + continue; + case 413: /* gen_movel_as_ad */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dar[ry]; + mpc = resume_prefetch; + continue; + case 414: /* gen_movel_dt_ad */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 415: /* gen_movew_ds_ea */ + ry = ir & 0x0007; + word_tst(dar[ry]); + dt = dar[ry]; + mpc = ea_resume_write16; + continue; + case 416: /* gen_movew_as_ea */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + word_tst(dar[ry]); + dt = dar[ry]; + mpc = ea_resume_write16; + continue; + case 417: /* gen_movew_dt_dd */ + rx = (ir >> 9) & 0x0007; + word_tst(dt); + dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 418: /* gen_movew_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + word_tst(dar[ry]); + dar[rx] = (dar[rx] & ~0xffff) | (dar[ry] & 0xffff); + mpc = resume_prefetch; + continue; + case 419: /* gen_movew_as_dd */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + word_tst(dar[ry]); + dar[rx] = (dar[rx] & ~0xffff) | (dar[ry] & 0xffff); + mpc = resume_prefetch; + continue; + case 420: /* gen_movew_dt_ea */ + word_tst(dt); + mpc = ea_resume_write16; + continue; + case 421: /* gen_movew_ds_ad */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = (short) dar[ry]; + mpc = resume_prefetch; + continue; + case 422: /* gen_movew_as_ad */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = (short) dar[ry]; + mpc = resume_prefetch; + continue; + case 423: /* gen_movew_dt_ad */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = (short) dt; + mpc = resume_prefetch; + continue; + case 424: /* gen_negxb_ds */ + ry = ir & 0x0007; + dt = byte_negx(dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 425: /* gen_negxb_ea */ + dt = byte_negx(dt); + mpc = ea_resume_write8; + continue; + case 426: /* gen_negxw_ds */ + ry = ir & 0x0007; + dt = word_negx(dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 427: /* gen_negxw_ea */ + dt = word_negx(dt); + mpc = ea_resume_write16; + continue; + case 428: /* gen_negxl_ds */ + ry = ir & 0x0007; + dt = long_negx(dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 429: /* gen_negxl_ea */ + dt = long_negx(dt); + mpc = ea_resume_write32; + continue; + case 430: /* gen_movew_sr_ds */ + if ((sr & 0x2000) == 0) { + elapsed += 6; + tvn = 32; + mpc = trapill; + continue; + } + ry = ir & 0x0007; + dar[ry] = (dar[ry] & ~0xffff) | (sr & 0xffff); + mpc = resume_prefetch; + continue; + case 431: /* gen_movew_sr_ea */ + if ((sr & 0x2000) == 0) { + elapsed += 6; + tvn = 32; + mpc = trapill; + continue; + } + dt = (sr & 0xf71f); + mpc = ea_resume_write16; + continue; + case 432: /* gen_movew_ccr_ds */ + ry = ir & 0x0007; + dar[ry] = (dar[ry] & ~0xffff) | (sr & 0x001f); + mpc = resume_prefetch; + continue; + case 433: /* gen_movew_ccr_ea */ + dt = (sr & 0x001f); + mpc = ea_resume_write16; + continue; + case 434: /* gen_movew_ds_ccr */ + ry = ir & 0x0007; + sr = (sr & ~0xff) | (dar[ry] & 0x001f); + mpc = resume_prefetch; + continue; + case 435: /* gen_movew_dt_ccr */ + sr = (sr & ~0xff) | (dt & 0x001f); + mpc = resume_prefetch; + continue; + case 436: /* gen_movew_ds_sr */ + if ((sr & 0x2000) == 0) { + elapsed += 6; + tvn = 32; + mpc = trapill; + continue; + } + ry = ir & 0x0007; + sr = dar[ry] & 0xf71f; + mpc = resume_prefetch; + continue; + case 437: /* gen_movew_dt_sr */ + if ((sr & 0x2000) == 0) { + elapsed += 6; + tvn = 32; + mpc = trapill; + continue; + } + sr = dt & 0xf71f; + mpc = resume_prefetch; + continue; + case 438: /* gen_negb_ds */ + ry = ir & 0x0007; + dt = byte_neg(dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 439: /* gen_negb_ea */ + dt = byte_neg(dt); + mpc = ea_resume_write8; + continue; + case 440: /* gen_negw_ds */ + ry = ir & 0x0007; + dt = word_neg(dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 441: /* gen_negl_ea */ + dt = long_neg(dt); + mpc = ea_resume_write32; + continue; + case 442: /* gen_negl_ds */ + ry = ir & 0x0007; + dt = long_neg(dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 443: /* gen_notb_ds */ + ry = ir & 0x0007; + dt = byte_not(dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 444: /* gen_notb_ea */ + dt = byte_not(dt); + mpc = ea_resume_write8; + continue; + case 445: /* gen_notw_ds */ + ry = ir & 0x0007; + dt = word_not(dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 446: /* gen_notw_ea */ + dt = word_not(dt); + mpc = ea_resume_write16; + continue; + case 447: /* gen_notl_ds */ + ry = ir & 0x0007; + dt = long_not(dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 448: /* gen_notl_ea */ + dt = long_not(dt); + mpc = ea_resume_write32; + continue; + case 449: /* gen_nbcdb_ds */ + ry = ir & 0x0007; + dt = byte_nbcd(dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 450: /* gen_nbcdb_ea */ + dt = byte_nbcd(dt); + mpc = ea_resume_write8; + continue; + case 451: /* gen_tstb_ds */ + ry = ir & 0x0007; + byte_tst(dar[ry]); + mpc = resume_prefetch; + continue; + case 452: /* gen_tstb_ea */ + byte_tst(dt); + mpc = resume_prefetch; + continue; + case 453: /* gen_tstw_ds */ + ry = ir & 0x0007; + word_tst(dar[ry]); + mpc = resume_prefetch; + continue; + case 454: /* gen_tstw_ea */ + word_tst(dt); + mpc = resume_prefetch; + continue; + case 455: /* gen_tstl_ds */ + ry = ir & 0x0007; + long_tst(dar[ry]); + mpc = resume_prefetch; + continue; + case 456: /* gen_tstl_ea */ + long_tst(dt); + mpc = resume_prefetch; + continue; + case 457: /* gen_addb_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = byte_add(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 458: /* gen_addb_ir_ea */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + dt = byte_add(alub, dt); + mpc = ea_resume_write8; + continue; + case 459: /* gen_addw_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = word_add(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 460: /* gen_addw_ir_as */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dar[ry] = dar[ry] + ((short) alub); + mpc = resume_prefetch; + continue; + case 461: /* gen_addw_ir_ea */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + dt = word_add(alub, dt); + mpc = ea_resume_write16; + continue; + case 462: /* gen_addl_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = long_add(alub, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 463: /* gen_addl_ir_as */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dar[ry] = dar[ry] + alub; + mpc = resume_prefetch; + continue; + case 464: /* gen_addl_ir_ea */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + dt = long_add(alub, dt); + mpc = ea_resume_write32; + continue; + case 465: /* gen_subb_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = byte_sub(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 466: /* gen_subb_ir_ea */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + dt = byte_sub(alub, dt); + mpc = ea_resume_write8; + continue; + case 467: /* gen_subw_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = word_sub(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 468: /* gen_subw_ir_as */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dar[ry] = dar[ry] - ((short) alub); + mpc = resume_prefetch; + continue; + case 469: /* gen_subw_ir_ea */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + dt = word_sub(alub, dt); + mpc = ea_resume_write16; + continue; + case 470: /* gen_subl_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = long_sub(alub, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 471: /* gen_subl_ir_as */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dar[ry] = dar[ry] - alub; + mpc = resume_prefetch; + continue; + case 472: /* gen_subl_ir_ea */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + dt = long_sub(alub, dt); + mpc = ea_resume_write32; + continue; + case 473: /* gen_movel_im_dd */ + dt = (byte) ir; + rx = (ir >> 9) & 0x0007; + long_tst(dt); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 474: /* gen_orb_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = byte_or(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 475: /* gen_orb_dt_dd */ + rx = (ir >> 9) & 0x0007; + dt = byte_or(dt, dar[rx]); + dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 476: /* gen_orw_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = word_or(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 477: /* gen_orw_dt_dd */ + rx = (ir >> 9) & 0x0007; + dt = word_or(dt, dar[rx]); + dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 478: /* gen_orl_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = long_or(dar[ry], dar[rx]); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 479: /* gen_orl_dt_dd */ + rx = (ir >> 9) & 0x0007; + dt = long_or(dt, dar[rx]); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 480: /* gen_sbcdb_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = byte_sbcd(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 481: /* gen_sbcdb_im_ea */ + dt = byte_sbcd(alub, dt); + mpc = ea_resume_write8; + continue; + case 482: /* gen_orb_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = byte_or(dar[rx], dt); + mpc = ea_resume_write8; + continue; + case 483: /* gen_orw_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = word_or(dar[rx], dt); + mpc = ea_resume_write16; + continue; + case 484: /* gen_orl_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = long_or(dar[rx], dt); + mpc = ea_resume_write32; + continue; + case 485: /* gen_subb_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = byte_sub(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 486: /* gen_subb_dt_dd */ + rx = (ir >> 9) & 0x0007; + dt = byte_sub(dt, dar[rx]); + dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 487: /* gen_subw_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = word_sub(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 488: /* gen_subw_as_dd */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + dt = word_sub(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 489: /* gen_subw_dt_dd */ + rx = (ir >> 9) & 0x0007; + dt = word_sub(dt, dar[rx]); + dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 490: /* gen_subl_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = long_sub(dar[ry], dar[rx]); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 491: /* gen_subl_as_dd */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + dt = long_sub(dar[ry], dar[rx]); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 492: /* gen_subl_dt_dd */ + rx = (ir >> 9) & 0x0007; + dt = long_sub(dt, dar[rx]); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 493: /* gen_subb_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = byte_sub(dar[rx], dt); + mpc = ea_resume_write8; + continue; + case 494: /* gen_subw_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = word_sub(dar[rx], dt); + mpc = ea_resume_write16; + continue; + case 495: /* gen_subl_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = long_sub(dar[rx], dt); + mpc = ea_resume_write32; + continue; + case 496: /* gen_subxb_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = byte_subx(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 497: /* gen_subxb_im_ea */ + dt = byte_subx(alub, dt); + mpc = ea_resume_write8; + continue; + case 498: /* gen_subxw_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = word_subx(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 499: /* gen_subxw_im_ea */ + dt = word_subx(alub, dt); + mpc = ea_resume_write16; + continue; + case 500: /* gen_subxl_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = long_subx(dar[ry], dar[rx]); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 501: /* gen_subxl_im_ea */ + dt = long_subx(alub, dt); + mpc = ea_resume_write32; + continue; + case 502: /* gen_subw_ds_ad */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dar[rx] - ((short) dar[ry]); + mpc = resume_prefetch; + continue; + case 503: /* gen_subw_as_ad */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dar[rx] - ((short) dar[ry]); + mpc = resume_prefetch; + continue; + case 504: /* gen_subw_dt_ad */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dar[rx] - ((short) dt); + mpc = resume_prefetch; + continue; + case 505: /* gen_subl_ds_ad */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dar[rx] - dar[ry]; + mpc = resume_prefetch; + continue; + case 506: /* gen_subl_as_ad */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dar[rx] - dar[ry]; + mpc = resume_prefetch; + continue; + case 507: /* gen_subl_dt_ad */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dar[rx] - dt; + mpc = resume_prefetch; + continue; + case 508: /* gen_cmpb_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + byte_sub(dar[ry], dar[rx]); + mpc = resume_prefetch; + continue; + case 509: /* gen_cmpb_dt_dd */ + rx = (ir >> 9) & 0x0007; + byte_sub(dt, dar[rx]); + mpc = resume_prefetch; + continue; + case 510: /* gen_cmpw_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + word_sub(dar[ry], dar[rx]); + mpc = resume_prefetch; + continue; + case 511: /* gen_cmpw_as_dd */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + word_sub(dar[ry], dar[rx]); + mpc = resume_prefetch; + continue; + case 512: /* gen_cmpw_dt_dd */ + rx = (ir >> 9) & 0x0007; + word_sub(dt, dar[rx]); + mpc = resume_prefetch; + continue; + case 513: /* gen_cmpl_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + long_sub(dar[ry], dar[rx]); + mpc = resume_prefetch; + continue; + case 514: /* gen_cmpl_as_dd */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + long_sub(dar[ry], dar[rx]); + mpc = resume_prefetch; + continue; + case 515: /* gen_cmpl_dt_dd */ + rx = (ir >> 9) & 0x0007; + long_sub(dt, dar[rx]); + mpc = resume_prefetch; + continue; + case 516: /* gen_cmpw_ds_ad */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + long_sub((short) dar[ry], dar[rx]); + mpc = resume_prefetch; + continue; + case 517: /* gen_cmpw_as_ad */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + long_sub((short) dar[ry], dar[rx]); + mpc = resume_prefetch; + continue; + case 518: /* gen_cmpw_dt_ad */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + long_sub((short) dt, dar[rx]); + mpc = resume_prefetch; + continue; + case 519: /* gen_cmpl_ds_ad */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + long_sub(dar[ry], dar[rx]); + mpc = resume_prefetch; + continue; + case 520: /* gen_cmpl_as_ad */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + long_sub(dar[ry], dar[rx]); + mpc = resume_prefetch; + continue; + case 521: /* gen_cmpl_dt_ad */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + long_sub(dt, dar[rx]); + mpc = resume_prefetch; + continue; + case 522: /* gen_cmpmb_im_ea */ + byte_sub(alub, dt); + mpc = resume_prefetch; + continue; + case 523: /* gen_cmpmw_im_ea */ + word_sub(alub, dt); + mpc = resume_prefetch; + continue; + case 524: /* gen_cmpml_im_ea */ + long_sub(alub, dt); + mpc = resume_prefetch; + continue; + case 525: /* gen_eorb_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = byte_eor(dar[rx], dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 526: /* gen_eorb_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = byte_eor(dar[rx], dt); + mpc = ea_resume_write8; + continue; + case 527: /* gen_eorw_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = word_eor(dar[rx], dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 528: /* gen_eorw_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = word_eor(dar[rx], dt); + mpc = ea_resume_write16; + continue; + case 529: /* gen_eorl_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = long_eor(dar[rx], dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 530: /* gen_eorl_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = long_eor(dar[rx], dt); + mpc = ea_resume_write32; + continue; + case 531: /* gen_andb_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = byte_and(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 532: /* gen_andb_dt_dd */ + rx = (ir >> 9) & 0x0007; + dt = byte_and(dt, dar[rx]); + dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 533: /* gen_andw_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = word_and(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 534: /* gen_andw_dt_dd */ + rx = (ir >> 9) & 0x0007; + dt = word_and(dt, dar[rx]); + dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 535: /* gen_andl_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = long_and(dar[ry], dar[rx]); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 536: /* gen_andl_dt_dd */ + rx = (ir >> 9) & 0x0007; + dt = long_and(dt, dar[rx]); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 537: /* gen_andb_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = byte_and(dar[rx], dt); + mpc = ea_resume_write8; + continue; + case 538: /* gen_andw_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = word_and(dar[rx], dt); + mpc = ea_resume_write16; + continue; + case 539: /* gen_andl_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = long_and(dar[rx], dt); + mpc = ea_resume_write32; + continue; + case 540: /* gen_abcdb_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = byte_abcd(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 541: /* gen_abcdb_im_ea */ + dt = byte_abcd(alub, dt); + mpc = ea_resume_write8; + continue; + case 542: /* gen_addb_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = byte_add(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 543: /* gen_addb_dt_dd */ + rx = (ir >> 9) & 0x0007; + dt = byte_add(dt, dar[rx]); + dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 544: /* gen_addw_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = word_add(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 545: /* gen_addw_as_dd */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + dt = word_add(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 546: /* gen_addw_dt_dd */ + rx = (ir >> 9) & 0x0007; + dt = word_add(dt, dar[rx]); + dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 547: /* gen_addl_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = long_add(dar[ry], dar[rx]); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 548: /* gen_addl_as_dd */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + dt = long_add(dar[ry], dar[rx]); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 549: /* gen_addl_dt_dd */ + rx = (ir >> 9) & 0x0007; + dt = long_add(dt, dar[rx]); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 550: /* gen_addb_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = byte_add(dar[rx], dt); + mpc = ea_resume_write8; + continue; + case 551: /* gen_addw_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = word_add(dar[rx], dt); + mpc = ea_resume_write16; + continue; + case 552: /* gen_addl_dd_ea */ + rx = (ir >> 9) & 0x0007; + dt = long_add(dar[rx], dt); + mpc = ea_resume_write32; + continue; + case 553: /* gen_addxb_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = byte_addx(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 554: /* gen_addxb_im_ea */ + dt = byte_addx(alub, dt); + mpc = ea_resume_write8; + continue; + case 555: /* gen_addxw_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = word_addx(dar[ry], dar[rx]); + dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 556: /* gen_addxw_im_ea */ + dt = word_addx(alub, dt); + mpc = ea_resume_write16; + continue; + case 557: /* gen_addxl_ds_dd */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + dt = long_addx(dar[ry], dar[rx]); + dar[rx] = dt; + mpc = resume_prefetch; + continue; + case 558: /* gen_addxl_im_ea */ + dt = long_addx(alub, dt); + mpc = ea_resume_write32; + continue; + case 559: /* gen_addw_ds_ad */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dar[rx] + ((short) dar[ry]); + mpc = resume_prefetch; + continue; + case 560: /* gen_addw_as_ad */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dar[rx] + ((short) dar[ry]); + mpc = resume_prefetch; + continue; + case 561: /* gen_addw_dt_ad */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dar[rx] + ((short) dt); + mpc = resume_prefetch; + continue; + case 562: /* gen_addl_ds_ad */ + ry = ir & 0x0007; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dar[rx] + dar[ry]; + mpc = resume_prefetch; + continue; + case 563: /* gen_addl_as_ad */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dar[rx] + dar[ry]; + mpc = resume_prefetch; + continue; + case 564: /* gen_addl_dt_ad */ + rx = (ir >> 9) & 0x0007; + rx = rx == 7 ? sp : rx | 8; + dar[rx] = dar[rx] + dt; + mpc = resume_prefetch; + continue; + case 565: /* gen_asrb_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = byte_asr(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 566: /* gen_asrb_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = byte_asr(dar[rx], dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 567: /* gen_asrw_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = word_asr(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 568: /* gen_asrw_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = word_asr(dar[rx], dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 569: /* gen_asrl_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = long_asr(alub, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 570: /* gen_asrl_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = long_asr(dar[rx], dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 571: /* gen_asrw_ea */ + dt = word_asr(1, dt); + mpc = ea_resume_write16; + continue; + case 572: /* gen_aslb_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = byte_asl(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 573: /* gen_aslb_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = byte_asl(dar[rx], dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 574: /* gen_aslw_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = word_asl(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 575: /* gen_aslw_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = word_asl(dar[rx], dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 576: /* gen_asll_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = long_asl(alub, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 577: /* gen_asll_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = long_asl(dar[rx], dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 578: /* gen_aslw_ea */ + dt = word_asl(1, dt); + mpc = ea_resume_write16; + continue; + case 579: /* gen_lsrb_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = byte_lsr(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 580: /* gen_lsrb_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = byte_lsr(dar[rx], dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 581: /* gen_lsrw_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = word_lsr(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 582: /* gen_lsrw_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = word_lsr(dar[rx], dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 583: /* gen_lsrl_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = long_lsr(alub, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 584: /* gen_lsrl_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = long_lsr(dar[rx], dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 585: /* gen_lsrw_ea */ + dt = word_lsr(1, dt); + mpc = ea_resume_write16; + continue; + case 586: /* gen_lslb_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = byte_lsl(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 587: /* gen_lslb_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = byte_lsl(dar[rx], dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 588: /* gen_lslw_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = word_lsl(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 589: /* gen_lslw_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = word_lsl(dar[rx], dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 590: /* gen_lsll_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = long_lsl(alub, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 591: /* gen_lsll_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = long_lsl(dar[rx], dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 592: /* gen_lslw_ea */ + dt = word_lsl(1, dt); + mpc = ea_resume_write16; + continue; + case 593: /* gen_rorb_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = byte_ror(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 594: /* gen_rorb_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = byte_ror(dar[rx], dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 595: /* gen_rorw_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = word_ror(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 596: /* gen_rorw_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = word_ror(dar[rx], dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 597: /* gen_rorl_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = long_ror(alub, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 598: /* gen_rorl_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = long_ror(dar[rx], dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 599: /* gen_rorw_ea */ + dt = word_ror(1, dt); + mpc = ea_resume_write16; + continue; + case 600: /* gen_rolb_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = byte_rol(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 601: /* gen_rolb_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = byte_rol(dar[rx], dar[ry]); + dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); + mpc = resume_prefetch; + continue; + case 602: /* gen_rolw_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = word_rol(alub, dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 603: /* gen_rolw_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = word_rol(dar[rx], dar[ry]); + dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); + mpc = resume_prefetch; + continue; + case 604: /* gen_roll_ir_ds */ + alub = (ir >> 9) & 0x0007; + if (alub == 0) { + alub = 8; + } + ry = ir & 0x0007; + dt = long_rol(alub, dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 605: /* gen_roll_dd_ds */ + rx = (ir >> 9) & 0x0007; + ry = ir & 0x0007; + dt = long_rol(dar[rx], dar[ry]); + dar[ry] = dt; + mpc = resume_prefetch; + continue; + case 606: /* gen_rolw_ea */ + dt = word_rol(1, dt); + mpc = ea_resume_write16; + continue; + default: + mpc = dbrr; + continue; + } + mpc = nmpc; + slice -= elapsed; + elapsed = 0; + if (exit || (slice <= 0)) { + break; + } + } + consumed -= slice; + } + if ((sswi & SSWI_PSLC) != 0) { + this.slice = slice; + } + return consumed; + } + + public abstract int fetch16(int aob); + + public abstract int fetch32(int aob); + + public abstract byte read8(int aob); + + public abstract short read16(int aob); + + public abstract int read32(int aob); + + public abstract void write8(int aob, int dob); + + public abstract void write16(int aob, int dob); + + public abstract void write32(int aob, int dob); + + public int handle_bkpt(int pc, int data) { + return 0; + } + + public int handle_illegal(int pc, int ir) { + return 0; + } + + public int handle_interrupt(int level) { + return IRQ_DFLT; + } + + public int handle_linea(int pc, int data) { + return 0; + } + + public void handle_reset() { + } + + public int handle_trace(int pc) { + return 0; + } +} diff --git a/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java b/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java new file mode 100644 index 0000000..5df5c7d --- /dev/null +++ b/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java @@ -0,0 +1,1792 @@ +package miggy.cpupoet; + +public class CoreALU { + /* + * status register privileged flags + */ + + /** + * Trace flag for all executed instructions + */ + public static final int SR_T1 = 1 << 15; + /** + * Trace flag for instruction flow changes + */ + public static final int SR_T0 = 1 << 14; + /** + * Supervisor flag + */ + public static final int SR_S = 1 << 13; + /** + * Supervisor Master flag + */ + public static final int SR_M = 1 << 12; + /** + * Interrupt level mask + */ + public static final int SR_I = 7 << 8; + + /* + * Special status word bus flags + */ + + /** + * Re-run flag: 0= processor re-run (default), 1 = software re-run. when not + * used by RTE, 1 means a read/write is running. + */ + public static final int SSW_RR = 1 << 15; + /** + * Instruction fetch to the Instruction Input Buffer. + */ + public static final int SSW_IF = 1 << 13; + /** + * Data fetch to the Data Input Buffer. + */ + public static final int SSW_DF = 1 << 12; + /** + * Read-Modify-Write cycle. + */ + public static final int SSW_RM = 1 << 11; + /** + * High byte transfer from the Data Output Buffer or to the Data Input Buffer. + */ + public static final int SSW_HB = 1 << 10; + /** + * Byte transfer flag: HB selects the high or low byte of the transfer register. + * If BY is clear, the transfer is word + */ + public static final int SSW_BY = 1 << 9; + /** + * Read/Write flag: 0 = write, 1 = read. + */ + public static final int SSW_RW = 1 << 8; + /** + * If set, indicates a 32 bits wide transfer + */ + public static final int SSW_32 = 1 << 7; + /** + * If set, indicates that 32 bits transfer has been handled by software + */ + public static final int SSW_WD = 1 << 6; + /** + * If set, indicates last transfer produced a bus error + */ + public static final int SSW_BR = 1 << 5; + /** + * If set, indicates that a reset is pending + */ + public static final int SSW_RS = 1 << 4; + /** + * If set, indicates that cpu is halted + */ + public static final int SSW_HL = 1 << 3; + /** + * If set, indicates that current access is made in supervisor (interrupt or + * master) mode + */ + public static final int SSW_S = 1 << 2; + /** + * If set, indicates that CPU is fetching a program word + */ + public static final int SSW_P = 1 << 1; + /** + * If set, indicates that CPU is fetching a data word + */ + public static final int SSW_D = 1 << 0; + + /* + * Special status word internal flags + */ + + /** + * fetch effective address after calculation + */ + public static final int SSWI_EAFH = 1 << 11; + /** + * Exit after a RMW cycle + */ + public static final int SSWI_XRMW = 1 << 4; + /** + * Enable trap format format 0x2 when applicable + */ + public static final int SSWI_FMT2 = 1 << 3; + /** + * Global interrupt auto-vectored flag + */ + public static final int SSWI_AVEC = 1 << 2; + /** + * Signal a double bus fault occurred (unrecoverable HALT state) + */ + public static final int SSWI_DERR = 1 << 1; + /** + * Persist slice (save over-runned cycles on each call to execute) and apply + * over-runned remaining cycles on each call to execute. + */ + public static final int SSWI_PSLC = 1 << 0; + + /* + * Effective address extension word + */ + + /** + * extension word register index + */ + public static final int EAX_REG = 15 << 12; + /** + * extension word index size + */ + public static final int EAX_SIZ = 1 << 11; + /** + * extension word scale + */ + public static final int EAX_SCL = 3 << 9; + /** + * extension word type + */ + public static final int EAX_EXT = 1 << 8; + /** + * extension word base register suppress + */ + public static final int EAX_BS = 1 << 7; + /** + * extension word index suppress + */ + public static final int EAX_IS = 1 << 6; + /** + * extension word base displacement size + */ + public static final int EAX_BSS = 3 << 4; + /** + * extension word index/indirect selection + */ + public static final int EAX_ISL = 7 << 0; + + + /* + * Condition code register flags + */ + + /** + * Carry + */ + public static final int FL_C = 0x01; + /** + * Overflow + */ + public static final int FL_V = 0x02; + /** + * Zero + */ + public static final int FL_Z = 0x04; + /** + * Negative + */ + public static final int FL_N = 0x08; + /** + * Extend + */ + public static final int FL_X = 0x10; + + /* + * Available conditions for 68k + */ + + /** + * True + */ + public static final int CC_T = 0x0; + /** + * False + */ + public static final int CC_F = 0x1; + /** + * High + */ + public static final int CC_HI = 0x2; + /** + * Low or same + */ + public static final int CC_LS = 0x3; + /** + * Carry clear + */ + public static final int CC_CC = 0x4; + /** + * Carry set + */ + public static final int CC_CS = 0x5; + /** + * Not equal + */ + public static final int CC_NE = 0x6; + /** + * Equal + */ + public static final int CC_EQ = 0x7; + /** + * Overflow clear + */ + public static final int CC_VC = 0x8; + /** + * Overflow set + */ + public static final int CC_VS = 0x9; + /** + * Plus + */ + public static final int CC_PL = 0xa; + /** + * Minus + */ + public static final int CC_MI = 0xb; + /** + * Greater or equal + */ + public static final int CC_GE = 0xc; + /** + * Less than + */ + public static final int CC_LT = 0xd; + /** + * Greater than + */ + public static final int CC_GT = 0xe; + /** + * Less or equal + */ + public static final int CC_LE = 0xf; + + /** + * data and address registers. container register in that order : data, address, + * usp, isp, msp + */ + protected final int[] dar = new int[18]; + + /** + * Status Register. + */ + protected int sr = 0; + /** + * Special status word. Contains information about ongoing bus, halt and reset + * states. + */ + protected int ssw = 0; + /** + * Special status word (internal). purpose of this register is to record pending + * traces and interrupts as well as global runtime flags. when saving CPU + * context, only pending stuff is saved in stack trace. + */ + protected int sswi = 0; + /** + * Vector base register + */ + protected int vbr; + /** + * Source function code + */ + protected int sfc; + /** + * Destination function code + */ + protected int dfc; + + /** + * retrieve dar index for the current stack pointer (usp, isp or msp) according + * to status register value. + * + * @param sr value of SR + * @return index of stack pointer + */ + protected static final int spi(int sr) { + int sp = 15; + if ((sr & SR_S) != 0) { + sp = (sr & SR_M) != 0 ? 17 : 16; + } + return sp; + } + + public final void setDARB(int index, int value) { + index &= 0xf; + + if (index == 0xf) { + index = spi(sr); + } + + dar[index] = (dar[index] & ~0xff) | (value & 0xff); + } + + public final byte getDARB(int index) { + index &= 0xf; + + if (index == 0xf) { + index = spi(sr); + } + + return (byte) dar[index]; + } + + public final void setDARW(int index, int value) { + index &= 0xf; + + if (index == 0xf) { + index = spi(sr); + } + + dar[index] = (dar[index] & ~0xffff) | (value & 0xffff); + } + + public final short getDARW(int index) { + index &= 0xf; + + if (index == 0xf) { + index = spi(sr); + } + + return (short) dar[index]; + } + + public final void setDARL(int index, int value) { + index &= 0xf; + + if (index == 0xf) { + index = spi(sr); + } + + dar[index] = value; + } + + public final int getDARL(int index) { + index &= 0xf; + + if (index == 0xf) { + index = spi(sr); + } + + return dar[index]; + } + + public final void setUSP(int value) { + dar[15] = value; + } + + public final int getUSP() { + return dar[15]; + } + + public final void setISP(int value) { + dar[16] = value; + } + + public final int getISP() { + return dar[16]; + } + + public final void setMSP(int value) { + dar[17] = value; + } + + public final int getMSP() { + return dar[17]; + } + + public final void setSFC(int value) { + sfc = value & 0x7; + } + + public final int getSFC() { + return sfc; + } + + public final void setDFC(int value) { + dfc = value & 0x7; + } + + public final int getDFC() { + return dfc; + } + + public final void setVBR(int value) { + vbr = value; + } + + public final int getVBR() { + return vbr; + } + + /** + * @return contents of SR register + */ + public final int getSR() { + return sr; + } + + /** + * set contents of SR register + * + * @param value value to be set. Only ALU flags are supported. Other bits are + * set as '0' + */ + public final void setSR(int value) { + int esr = (sr ^ value) & (SR_T1 | SR_T0 | SR_S | SR_M | SR_I | FL_C | FL_V | FL_Z | FL_N | FL_X); + + sr ^= esr; + } + + /** + * set or clear bits in SR. undefined bits can't be set or cleared. + * + * @param set SR bits to be set + * @param clr SR bits to be cleared + * @return new SR value + */ + public final int setclrSR(int set, int clr) { + int esr = sr & clr & (SR_T1 | SR_T0 | SR_S | SR_M | SR_I | FL_C | FL_V | FL_Z | FL_N | FL_X); + + return sr ^= esr ^ (set & (SR_T1 | SR_T0 | SR_S | SR_M | SR_I | FL_C | FL_V | FL_Z | FL_N | FL_X)); + } + + /** + * @return contents of SSW register + */ + public final int getSSW() { + return ssw; + } + + /** + * @return contents of SSWI register + */ + public final int getSSWI() { + return ssw; + } + + /** + * set or clear bits in SSW. undefined or internally handled bits can't be set + * or cleared. + * + * @param set SSW bits to be set + * @param clr SSW bits to be cleared + * @return new SSW value + */ + public final int setclrSSW(int set, int clr) { + /* RS/HL are always modifiable */ + int mask = SSW_RS | SSW_HL; + + if ((sswi & SSWI_DERR) != 0) { + /* when in double bus fault, HALT can't be cleared */ + clr &= ~SSW_HL; + } + + if ((ssw & SSW_RR) != 0) { + /* bus error may be modified if a bus transfer is running */ + mask |= SSW_BR; + + if ((ssw & SSW_32) != 0) { + /* wide access is allowed for 32 bits transfer */ + mask |= SSW_WD; + } + } + + int essw = ssw & clr & mask; + + return ssw ^= essw ^ (set & mask); + } + + /** + * set or clear bits in SSWI. undefined or internally handled bits can't be set + * or cleared. + * + * @param set SSWI bits to be set + * @param clr SSWI bits to be cleared + * @return new SSWI value + */ + public final int setclrSSWI(int set, int clr) { + int esswi = sswi & clr & (SSWI_FMT2 | SSWI_AVEC | SSWI_PSLC); + + return sswi ^= esswi ^ (set & (SSWI_FMT2 | SSWI_AVEC | SSWI_PSLC)); + } + + /** + * @return contents of CCR register + */ + public final int getCCR() { + return sr & (FL_C | FL_V | FL_Z | FL_N | FL_X); + } + + /** + * set contents of CCR register + * + * @param value value to be set. Only ALU flags are supported. Other bits are + * set as '0' + */ + public final void setCCR(int value) { + int eccr = (sr ^ value) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + + sr ^= eccr; + } + + /** + * set or clear bits in CCR. undefined bits can't be set or cleared. + * + * @param set CCR bits to be set + * @param clr CCR bits to be cleared + * @return new SR value + */ + public final int setclrCCR(int set, int clr) { + int eccr = sr & clr & (FL_C | FL_V | FL_Z | FL_N | FL_X); + + return sr ^= eccr ^ (set & (FL_C | FL_V | FL_Z | FL_N | FL_X)); + } + + /** + * check if the given condition is met using actual ALU flags. + * + * @param condition condition to be tested + * @return 'true' if condition met, 'false' otherwise. + */ + public final boolean testCC(int condition) { + return testCC(sr, condition); + } + + protected static final boolean testCC(int CCR, int condition) { + boolean result = false; + + switch (condition) { + case CC_T: + /* The T condition is always true */ + result = true; + break; + case CC_F: + /* false condition is always... false */ + result = false; + default: + break; + case CC_HI: + result = ((CCR & (FL_C | FL_Z)) == 0); + break; + case CC_LS: + result = ((CCR & (FL_C | FL_Z)) != 0); + break; + case CC_CC: + /* carry clear... check that the carry flag is not set */ + result = ((CCR & FL_C) == 0); + break; + case CC_CS: + /* carry set, check if the carry flag is set */ + result = ((CCR & FL_C) != 0); + break; + case CC_NE: + result = ((CCR & FL_Z) == 0); + break; + case CC_EQ: + /* Zero, check if the zero flag is set */ + result = ((CCR & FL_Z) != 0); + break; + case CC_VC: + result = ((CCR & FL_V) == 0); + break; + case CC_VS: + result = ((CCR & FL_V) != 0); + break; + case CC_PL: + result = ((CCR & FL_N) == 0); + break; + case CC_MI: + result = ((CCR & FL_N) != 0); + break; + case CC_GE: + CCR &= FL_N | FL_V; + + result = (CCR == 0) || (CCR == (FL_N | FL_V)); + break; + case CC_LT: + CCR &= FL_N | FL_V; + + result = (CCR == FL_N) || (CCR == FL_V); + break; + case CC_GT: + CCR &= FL_N | FL_V | FL_Z; + + result = (CCR == 0) || (CCR == (FL_N | FL_V)); + break; + case CC_LE: + CCR &= FL_N | FL_V | FL_Z; + + result = ((CCR & FL_Z) != 0) || (CCR == FL_N) || (CCR == FL_V); + break; + } + + return result; + } + + public final byte byte_abcd(int src, int dst) { + src = (byte) src; + dst = (byte) dst; + + byte br = (byte) (dst + src + ((sr & FL_X) >> 4)); + int sbr = br >>> 1; /* trick for full 32 bits bcd addition */ + int bc = (((src | dst) & ~br) | (src & dst)) & 0x88888888; + int dc = ((sbr + 0x33333333) ^ sbr) & 0x88888888; + int corf = (bc | dc) - ((bc | dc) >>> 2); + byte dr = (byte) (br + corf); + + int v = ((~br & dr) >> 30) & FL_V; + int cx = ((bc | (br & ~dr)) >> 31) & (FL_C | FL_X); + int n = (dr >> 28) & FL_N; + int z = ((dr | -dr) >> 31) & FL_Z; + + sr ^= (sr ^ (cx | v | n)) & (FL_C | FL_V | z | FL_N | FL_X); + + return dr; + } + + public final short word_abcd(int src, int dst) { + src = (short) src; + dst = (short) dst; + + short br = (short) (dst + src + ((sr & FL_X) >> 4)); + int sbr = br >>> 1; /* trick for full 32 bits bcd addition */ + int bc = (((src | dst) & ~br) | (src & dst)) & 0x88888888; + int dc = ((sbr + 0x33333333) ^ sbr) & 0x88888888; + int corf = (bc | dc) - ((bc | dc) >>> 2); + short dr = (short) (br + corf); + + int v = ((~br & dr) >> 30) & FL_V; + int cx = ((bc | (br & ~dr)) >> 31) & (FL_C | FL_X); + int n = (dr >> 28) & FL_N; + int z = ((dr | -dr) >> 31) & FL_Z; + + sr ^= (sr ^ (cx | v | n)) & (FL_C | FL_V | z | FL_N | FL_X); + + return dr; + } + + public final int long_abcd(int src, int dst) { + int br = dst + src + ((sr & FL_X) >> 4); + int sbr = br >>> 1; /* trick for full 32 bits bcd addition */ + int bc = (((src | dst) & ~br) | (src & dst)) & 0x88888888; + int dc = ((sbr + 0x33333333) ^ sbr) & 0x88888888; + int corf = (bc | dc) - ((bc | dc) >>> 2); + int dr = br + corf; + + int v = ((~br & dr) >> 30) & FL_V; + int cx = ((bc | (br & ~dr)) >> 31) & (FL_C | FL_X); + int n = (dr >> 28) & FL_N; + int z = ((dr | -dr) >> 31) & FL_Z; + + sr ^= (sr ^ (cx | v | n)) & (FL_C | FL_V | z | FL_N | FL_X); + + return dr; + } + + public final byte byte_add(int src, int dst) { + src = (byte) src; + dst = (byte) dst; + + byte res = (byte) (dst + src); + + int v = (((src ^ res) & (dst ^ res)) >> 30) & FL_V; + int cx = ((((src | dst) & ~res) | (src & dst)) >> 31) & (FL_C | FL_X); + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | v | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + + return res; + } + + public final short word_add(int src, int dst) { + src = (short) src; + dst = (short) dst; + + short res = (short) (dst + src); + + int v = (((src ^ res) & (dst ^ res)) >> 30) & FL_V; + int cx = ((((src | dst) & ~res) | (src & dst)) >> 31) & (FL_C | FL_X); + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | v | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + + return res; + } + + public final int long_add(int src, int dst) { + int res = dst + src; + + int v = (((src ^ res) & (dst ^ res)) >> 30) & FL_V; + int cx = ((((src | dst) & ~res) | (src & dst)) >> 31) & (FL_C | FL_X); + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | v | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + + return res; + } + + public final byte byte_addx(int src, int dst) { + src = (byte) src; + dst = (byte) dst; + + byte res = (byte) (dst + src + ((sr & FL_X) >> 4)); + + int v = (((src ^ res) & (dst ^ res)) >> 30) & FL_V; + int cx = ((((src | dst) & ~res) | (src & dst)) >> 31) & (FL_C | FL_X); + int n = (res >> 28) & FL_N; + int z = ((res | -res) >> 31) & FL_Z; + + sr ^= (sr ^ (cx | v | n)) & (FL_C | FL_V | z | FL_N | FL_X); + + return res; + } + + public final short word_addx(int src, int dst) { + src = (short) src; + dst = (short) dst; + + short res = (short) (dst + src + ((sr & FL_X) >> 4)); + + int v = (((src ^ res) & (dst ^ res)) >> 30) & FL_V; + int cx = ((((src | dst) & ~res) | (src & dst)) >> 31) & (FL_C | FL_X); + int n = (res >> 28) & FL_N; + int z = ((res | -res) >> 31) & FL_Z; + + sr ^= (sr ^ (cx | v | n)) & (FL_C | FL_V | z | FL_N | FL_X); + + return res; + } + + public final int long_addx(int src, int dst) { + int res = dst + src + ((sr & FL_X) >> 4); + + int v = (((src ^ res) & (dst ^ res)) >> 30) & FL_V; + int cx = ((((src | dst) & ~res) | (src & dst)) >> 31) & (FL_C | FL_X); + int n = (res >> 28) & FL_N; + int z = ((res | -res) >> 31) & FL_Z; + + sr ^= (sr ^ (cx | v | n)) & (FL_C | FL_V | z | FL_N | FL_X); + + return res; + } + + public final byte byte_and(int src, int dst) { + src = (byte) src; + dst = (byte) dst; + + byte res = (byte) (dst & src); + + res_tst(res); + + return res; + } + + public final short word_and(int src, int dst) { + src = (short) src; + dst = (short) dst; + + short res = (short) (dst & src); + + res_tst(res); + + return res; + } + + public final int long_and(int src, int dst) { + int res = dst & src; + + res_tst(res); + + return res; + } + + public final byte byte_asl(int shift, int dst) { + shift &= 0x3f; + + byte res = (byte) dst; + + if (shift > 0) { + int mask = -1 << (8 - Math.min(shift, 8)); + int vout = res & mask; + int cx = 0; + int v = (vout == 0) || (vout == mask) ? 0 : FL_V; + + if (shift <= 8) { + res <<= shift - 1; + cx = (res >> 31) & (FL_C | FL_X); + res <<= 1; + } else { + res = 0; + } + + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | v | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + } else { + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + } + + return res; + } + + public final short word_asl(int shift, int dst) { + shift &= 0x3f; + + short res = (short) dst; + + if (shift > 0) { + int mask = -1 << (16 - Math.min(shift, 16)); + int vout = res & mask; + int cx = 0; + int v = (vout == 0) || (vout == mask) ? 0 : FL_V; + + if (shift <= 16) { + res <<= shift - 1; + cx = (res >> 31) & (FL_C | FL_X); + res <<= 1; + } else { + res = 0; + } + + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | v | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + } else { + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + } + + return res; + } + + public final int long_asl(int shift, int dst) { + shift &= 0x3f; + + int res = dst; + + if (shift > 0) { + int mask = -1 << (32 - Math.min(shift, 32)); + int vout = res & mask; + int cx = 0; + int v = (vout == 0) || (vout == mask) ? 0 : FL_V; + + if (shift <= 32) { + res <<= shift - 1; + cx = (res >> 31) & (FL_C | FL_X); + res <<= 1; + } else { + res = 0; + } + + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | v | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + } else { + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + } + + return res; + } + + public final byte byte_asr(int shift, int dst) { + shift &= 0x3f; + + byte res = (byte) dst; + + if (shift > 0) { + int cx = 0; + + res >>= Math.min(shift, 8) - 1; + cx = res & FL_C; /* set carry */ + cx |= cx << 4; /* also set eXtend */ + res >>= 1; /* perform final shift */ + + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + } else { + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + } + + return res; + } + + public final short word_asr(int shift, int dst) { + shift &= 0x3f; + + short res = (short) dst; + + if (shift > 0) { + int cx = 0; + + res >>= Math.min(shift, 16) - 1; + cx = res & FL_C; /* set carry */ + cx |= cx << 4; /* also set eXtend */ + res >>= 1; /* perform final shift */ + + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + } else { + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + } + + return res; + } + + public final int long_asr(int shift, int dst) { + shift &= 0x3f; + + int res = dst; + + if (shift > 0) { + int cx = 0; + + res >>= Math.min(shift, 32) - 1; + cx = res & FL_C; /* set carry */ + cx |= cx << 4; /* also set eXtend */ + res >>= 1; /* perform final shift */ + + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + } else { + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + } + + return res; + } + + public final byte byte_bchg(int bit, int dst) { + bit &= 0x1f; + + int src = 1 << bit; + int res = dst & src & 0xff; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ z) & FL_Z; + + return (byte) (dst ^ src); + } + + public final short word_bchg(int bit, int dst) { + bit &= 0x1f; + + int src = 1 << bit; + int res = dst & src & 0xffff; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ z) & FL_Z; + + return (short) (dst ^ src); + } + + public final int long_bchg(int bit, int dst) { + bit &= 0x1f; + + int src = 1 << bit; + int res = dst & src; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ z) & FL_Z; + + return dst ^ src; + } + + public final byte byte_bclr(int bit, int dst) { + bit &= 0x1f; + + int src = 1 << bit; + int res = dst & src & 0xff; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ z) & FL_Z; + + return (byte) (dst & (~src)); + } + + public final short word_bclr(int bit, int dst) { + bit &= 0x1f; + + int src = 1 << bit; + int res = dst & src & 0xffff; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ z) & FL_Z; + + return (short) (dst & (~src)); + } + + public final int long_bclr(int bit, int dst) { + bit &= 0x1f; + + int src = 1 << bit; + int res = dst & src; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ z) & FL_Z; + + return(dst & (~src)); + } + + public final byte byte_bset(int bit, int dst) { + bit &= 0x1f; + + int src = 1 << bit; + int res = dst & src & 0xff; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ z) & FL_Z; + + return (byte) (dst | src); + } + + public final short word_bset(int bit, int dst) { + bit &= 0x1f; + + int src = 1 << bit; + int res = dst & src & 0xffff; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ z) & FL_Z; + + return (short) (dst | src); + } + + public final int long_bset(int bit, int dst) { + bit &= 0x1f; + + int src = 1 << bit; + int res = dst & src; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ z) & FL_Z; + + return dst | src; + } + + public final void byte_btst(int bit, int dst) { + bit &= 0x1f; + + int res = dst & (1 << bit) & 0xff; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ z) & FL_Z; + } + + public final void word_btst(int bit, int dst) { + bit &= 0x1f; + + int res = dst & (1 << bit) & 0xffff; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ z) & FL_Z; + } + + public final void long_btst(int bit, int dst) { + bit &= 0x1f; + + int res = dst & (1 << bit); + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ z) & FL_Z; + } + + public final boolean word_chk(int src, int dst) { + src = (short) src; + dst = (short) dst; + + int z = (~((dst | -dst) >> 31)) & FL_Z; + + if (dst < 0) { + /* set N flag and take chk trap */ + sr ^= (sr ^ (z | FL_N)) & (FL_C | FL_V | FL_Z | FL_N); + + return true; + } else if (dst > src) { + /* clear N flag and take chk trap */ + sr ^= (sr ^ z) & (FL_C | FL_V | FL_Z | FL_N); + + return true; + } + + /* leave N flag and continue execution */ + sr ^= (sr ^ z) & (FL_C | FL_V | FL_Z); + + return false; + } + + public final boolean long_chk(int src, int dst) { + int z = (~((dst | -dst) >> 31)) & FL_Z; + + if (dst < 0) { + /* set N flag and take chk trap */ + sr ^= (sr ^ (z | FL_N)) & (FL_C | FL_V | FL_Z | FL_N); + + return true; + } else if (dst > src) { + /* clear N flag and take chk trap */ + sr ^= (sr ^ z) & (FL_C | FL_V | FL_Z | FL_N); + + return true; + } + + /* leave N flag and continue execution */ + sr ^= (sr ^ z) & (FL_C | FL_V | FL_Z); + + return false; + } + + public final byte byte_eor(int src, int dst) { + src = (byte) src; + dst = (byte) dst; + + byte res = (byte) (dst ^ src); + + res_tst(res); + + return res; + } + + public final short word_eor(int src, int dst) { + src = (short) src; + dst = (short) dst; + + short res = (short) (dst ^ src); + + res_tst(res); + + return res; + } + + public final int long_eor(int src, int dst) { + int res = dst ^ src; + + res_tst(res); + + return res; + } + + public final byte byte_lsl(int shift, int dst) { + shift &= 0x3f; + + byte res = (byte) dst; + + if (shift > 0) { + int cx = 0; + + if (shift <= 8) { + res <<= shift - 1; + cx = (res >> 31) & (FL_C | FL_X); + res <<= 1; /* perform final shift */ + } else { + res = 0; + } + + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + } else { + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + } + + return res; + } + + public final short word_lsl(int shift, int dst) { + shift &= 0x3f; + + short res = (short) dst; + + if (shift > 0) { + int cx = 0; + + if (shift <= 16) { + res <<= shift - 1; + cx = (res >> 31) & (FL_C | FL_X); + res <<= 1; /* perform final shift */ + } else { + res = 0; + } + + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + } else { + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + } + + return res; + } + + public final int long_lsl(int shift, int dst) { + shift &= 0x3f; + + int res = dst; + + if (shift > 0) { + int cx = 0; + + if (shift <= 32) { + res <<= shift - 1; + cx = (res >> 31) & (FL_C | FL_X); + res <<= 1; /* perform final shift */ + } else { + res = 0; + } + + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + } else { + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + } + + return res; + } + + public final byte byte_lsr(int shift, int dst) { + shift &= 0x3f; + + int res = dst & 0xff; + + if (shift > 0) { + int cx = 0; + + if (shift <= 8) { + res >>>= shift - 1; + cx = res & FL_C; /* set carry */ + cx |= cx << 4; /* also set eXtend */ + res = (byte) (res >>> 1); /* perform final shift */ + } else { + res = 0; + } + + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + } else { + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + } + + return (byte) res; + } + + public final short word_lsr(int shift, int dst) { + shift &= 0x3f; + + int res = dst & 0xffff; + + if (shift > 0) { + int cx = 0; + + if (shift <= 16) { + res >>>= shift - 1; + cx = res & FL_C; /* set carry */ + cx |= cx << 4; /* also set eXtend */ + res = (short) (res >>> 1); /* perform final shift */ + } else { + res = 0; + } + + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + } else { + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + } + + return (short) res; + } + + public final int long_lsr(int shift, int dst) { + shift &= 0x3f; + + int res = dst; + + if (shift > 0) { + int cx = 0; + + if (shift <= 32) { + res >>>= shift - 1; + cx = res & FL_C; /* set carry */ + cx |= cx << 4; /* also set eXtend */ + res >>>= 1; /* perform final shift */ + } else { + res = 0; + } + + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + } else { + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + } + + return res; + } + + public final byte byte_nbcd(int dst) { + return byte_sbcd(dst, 0); + } + + public final short word_nbcd(int dst) { + return word_sbcd(dst, 0); + } + + public final int long_nbcd(int dst) { + return long_sbcd(dst, 0); + } + + public final byte byte_neg(int dst) { + return byte_sub(dst, 0); + } + + public final short word_neg(int dst) { + return word_sub(dst, 0); + } + + public final int long_neg(int dst) { + return long_sub(dst, 0); + } + + public final byte byte_negx(int dst) { + return byte_subx(dst, 0); + } + + public final short word_negx(int dst) { + return word_subx(dst, 0); + } + + public final int long_negx(int dst) { + return long_subx(dst, 0); + } + + public final byte byte_not(int dst) { + byte res = (byte) (~dst); + + res_tst(res); + + return res; + } + + public final short word_not(int dst) { + short res = (short) (~dst); + + res_tst(res); + + return res; + } + + public final int long_not(int dst) { + int res = (~dst); + + res_tst(res); + + return res; + } + + public final byte byte_or(int src, int dst) { + src = (byte) src; + dst = (byte) dst; + + byte res = (byte) (dst | src); + + res_tst(res); + + return res; + } + + public final short word_or(int src, int dst) { + src = (short) src; + dst = (short) dst; + + short res = (short) (dst | src); + + res_tst(res); + + return res; + } + + public final int long_or(int src, int dst) { + int res = dst | src; + + res_tst(res); + + return res; + } + + public final byte byte_rol(int shift, int dst) { + shift &= 0x3f; + + if (shift > 0) { + shift &= 7; + + byte res = (byte) ((dst << shift) | ((dst & 0xff) >>> (8 - shift))); + int c = res & FL_C; + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (c | z | n)) & (FL_C | FL_V | FL_Z | FL_N); + + return res; + } else { + byte res = (byte) dst; + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + + return res; + } + } + + public final short word_rol(int shift, int dst) { + shift &= 0x3f; + + if (shift > 0) { + shift &= 15; + + short res = (short) ((dst << shift) | ((dst & 0xffff) >>> (16 - shift))); + int c = res & FL_C; + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (c | z | n)) & (FL_C | FL_V | FL_Z | FL_N); + + return res; + } else { + short res = (short) dst; + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + + return res; + } + } + + public final int long_rol(int shift, int dst) { + shift &= 0x3f; + + if (shift > 0) { + shift &= 31; + + int res = (dst << shift) | (dst >>> (32 - shift)); + int c = res & FL_C; + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (c | z | n)) & (FL_C | FL_V | FL_Z | FL_N); + + return res; + } else { + int res = dst; + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + + return res; + } + } + + public final byte byte_ror(int shift, int dst) { + shift &= 0x3f; + + if (shift > 0) { + shift &= 7; + + byte res = (byte) ((dst << (8 - shift)) | ((dst & 0xff) >>> shift)); + int cn = (res >> 31) & (FL_N | FL_C); + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cn | z)) & (FL_C | FL_V | FL_Z | FL_N); + + return res; + } else { + byte res = (byte) dst; + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + + return res; + } + } + + public final short word_ror(int shift, int dst) { + shift &= 0x3f; + + if (shift > 0) { + shift &= 7; + + short res = (short) ((dst << (16 - shift)) | ((dst & 0xffff) >>> shift)); + int cn = (res >> 31) & (FL_N | FL_C); + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cn | z)) & (FL_C | FL_V | FL_Z | FL_N); + + return res; + } else { + short res = (short) dst; + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + + return res; + } + } + + public final int long_ror(int shift, int dst) { + shift &= 0x3f; + + if (shift > 0) { + shift &= 7; + + int res = (dst << (32 - shift)) | (dst >>> shift); + int cn = (res >> 31) & (FL_N | FL_C); + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cn | z)) & (FL_C | FL_V | FL_Z | FL_N); + + return res; + } else { + int res = dst; + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + + return res; + } + } + + public final byte byte_sbcd(int src, int dst) { + src = (byte) src; + dst = (byte) dst; + + /* compute regular binary substraction */ + byte br = (byte) (dst - src - ((sr & FL_X) >> 4)); + + /* normal carry computation */ + int bc = ((~dst & src) | (br & ~dst) | (br & src)) & 0x88888888; + int corf = bc - (bc >>> 2); + byte dr = (byte) (br - corf); + + int v = ((br & ~dr) >> 30) & FL_V; + int cx = ((bc | (~br & dr)) >> 31) & (FL_C | FL_X); + int n = (dr >> 28) & FL_N; + int z = ((dr | -dr) >> 31) & FL_Z; + + int eccr = (sr ^ (cx | v | n)) & (FL_C | FL_V | z | FL_N | FL_X); + + sr ^= eccr; + + return dr; + } + + public final short word_sbcd(int src, int dst) { + src = (short) src; + dst = (short) dst; + + /* compute regular binary substraction */ + short br = (short) (dst - src - ((sr & FL_X) >> 4)); + + /* normal carry computation */ + int bc = ((~dst & src) | (br & ~dst) | (br & src)) & 0x88888888; + int corf = bc - (bc >>> 2); + short dr = (short) (br - corf); + + int v = ((br & ~dr) >> 30) & FL_V; + int cx = ((bc | (~br & dr)) >> 31) & (FL_C | FL_X); + int n = (dr >> 28) & FL_N; + int z = ((dr | -dr) >> 31) & FL_Z; + + int eccr = (sr ^ (cx | v | n)) & (FL_C | FL_V | z | FL_N | FL_X); + + sr ^= eccr; + + return dr; + } + + public final int long_sbcd(int src, int dst) { + /* compute regular binary substraction */ + int br = dst - src - ((sr & FL_X) >> 4); + + /* normal carry computation */ + int bc = ((~dst & src) | (br & ~dst) | (br & src)) & 0x88888888; + int corf = bc - (bc >>> 2); + int dr = br - corf; + + int v = ((br & ~dr) >> 30) & FL_V; + int cx = ((bc | (~br & dr)) >> 31) & (FL_C | FL_X); + int n = (dr >> 28) & FL_N; + int z = ((dr | -dr) >> 31) & FL_Z; + + int eccr = (sr ^ (cx | v | n)) & (FL_C | FL_V | z | FL_N | FL_X); + + sr ^= eccr; + + return dr; + } + + public final byte byte_sub(int src, int dst) { + src = (byte) src; + dst = (byte) dst; + + byte res = (byte) (dst - src); + + int v = (((dst ^ src) & (dst ^ res)) >> 30) & FL_V; + int cx = ((((src | ~dst) & res) | (src & ~dst)) >> 31) & (FL_C | FL_X); + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | v | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + + return res; + } + + public final short word_sub(int src, int dst) { + src = (short) src; + dst = (short) dst; + + short res = (short) (dst - src); + + int v = (((dst ^ src) & (dst ^ res)) >> 30) & FL_V; + int cx = ((((src | ~dst) & res) | (src & ~dst)) >> 31) & (FL_C | FL_X); + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | v | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + + return res; + } + + public final int long_sub(int src, int dst) { + int res = dst - src; + + int v = (((dst ^ src) & (dst ^ res)) >> 30) & FL_V; + int cx = ((((src | ~dst) & res) | (src & ~dst)) >> 31) & (FL_C | FL_X); + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (cx | v | z | n)) & (FL_C | FL_V | FL_Z | FL_N | FL_X); + + return res; + } + + public final byte byte_subx(int src, int dst) { + src = (byte) src; + dst = (byte) dst; + + byte res = (byte) (dst - src - ((sr & FL_X) >> 4)); + + int v = (((dst ^ src) & (dst ^ res)) >> 30) & FL_V; + int cx = ((((src | ~dst) & res) | (src & ~dst)) >> 31) & (FL_C | FL_X); + int n = (res >> 28) & FL_N; + int z = ((res | -res) >> 31) & FL_Z; + + sr ^= (sr ^ (cx | v | n)) & (FL_C | FL_V | z | FL_N | FL_X); + + return res; + } + + public final short word_subx(int src, int dst) { + src = (short) src; + dst = (short) dst; + + short res = (short) (dst - src - ((sr & FL_X) >> 4)); + + int v = (((dst ^ src) & (dst ^ res)) >> 30) & FL_V; + int cx = ((((src | ~dst) & res) | (src & ~dst)) >> 31) & (FL_C | FL_X); + int n = (res >> 28) & FL_N; + int z = ((res | -res) >> 31) & FL_Z; + + sr ^= (sr ^ (cx | v | n)) & (FL_C | FL_V | z | FL_N | FL_X); + + return res; + } + + public final int long_subx(int src, int dst) { + int res = dst - src - ((sr & FL_X) >> 4); + + int v = (((dst ^ src) & (dst ^ res)) >> 30) & FL_V; + int cx = ((((src | ~dst) & res) | (src & ~dst)) >> 31) & (FL_C | FL_X); + int n = (res >> 28) & FL_N; + int z = ((res | -res) >> 31) & FL_Z; + + sr ^= (sr ^ (cx | v | n)) & (FL_C | FL_V | z | FL_N | FL_X); + + return res; + } + + public final void byte_tst(int dst) { + byte res = (byte) dst; + + res_tst(res); + } + + public final void word_tst(int dst) { + short res = (short) dst; + + res_tst(res); + } + + public final void long_tst(int dst) { + res_tst(dst); + } + + private final void res_tst(int res) { + int n = (res >> 28) & FL_N; + int z = (~((res | -res) >> 31)) & FL_Z; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + } +} diff --git a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java new file mode 100644 index 0000000..bc6e1db --- /dev/null +++ b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java @@ -0,0 +1,3019 @@ +package miggy.cpupoet; + +import static miggy.cpupoet.Core.dbrr; +import static miggy.cpupoet.Core.ea_adr16d16; +import static miggy.cpupoet.Core.ea_adr16d32; +import static miggy.cpupoet.Core.ea_adr16d8; +import static miggy.cpupoet.Core.ea_adr16s16; +import static miggy.cpupoet.Core.ea_adr16s16_read; +import static miggy.cpupoet.Core.ea_adr16s32; +import static miggy.cpupoet.Core.ea_adr16s32_read; +import static miggy.cpupoet.Core.ea_adr16s8; +import static miggy.cpupoet.Core.ea_adr16s8_read; +import static miggy.cpupoet.Core.ea_adr32d16; +import static miggy.cpupoet.Core.ea_adr32d32; +import static miggy.cpupoet.Core.ea_adr32d8; +import static miggy.cpupoet.Core.ea_adr32s16; +import static miggy.cpupoet.Core.ea_adr32s16_read; +import static miggy.cpupoet.Core.ea_adr32s32; +import static miggy.cpupoet.Core.ea_adr32s32_read; +import static miggy.cpupoet.Core.ea_adr32s8; +import static miggy.cpupoet.Core.ea_adr32s8_read; +import static miggy.cpupoet.Core.ea_aid16; +import static miggy.cpupoet.Core.ea_aid32; +import static miggy.cpupoet.Core.ea_aid8; +import static miggy.cpupoet.Core.ea_aipd16; +import static miggy.cpupoet.Core.ea_aipd16_read; +import static miggy.cpupoet.Core.ea_aipd32; +import static miggy.cpupoet.Core.ea_aipd32_read; +import static miggy.cpupoet.Core.ea_aipd8; +import static miggy.cpupoet.Core.ea_aipd8_read; +import static miggy.cpupoet.Core.ea_aips16; +import static miggy.cpupoet.Core.ea_aips16_read; +import static miggy.cpupoet.Core.ea_aips32; +import static miggy.cpupoet.Core.ea_aips32_read; +import static miggy.cpupoet.Core.ea_aips8; +import static miggy.cpupoet.Core.ea_aips8_read; +import static miggy.cpupoet.Core.ea_ais16; +import static miggy.cpupoet.Core.ea_ais16_read; +import static miggy.cpupoet.Core.ea_ais32; +import static miggy.cpupoet.Core.ea_ais32_read; +import static miggy.cpupoet.Core.ea_ais8; +import static miggy.cpupoet.Core.ea_ais8_read; +import static miggy.cpupoet.Core.ea_dad16; +import static miggy.cpupoet.Core.ea_dad32; +import static miggy.cpupoet.Core.ea_dad8; +import static miggy.cpupoet.Core.ea_daid16; +import static miggy.cpupoet.Core.ea_daid32; +import static miggy.cpupoet.Core.ea_daid8; +import static miggy.cpupoet.Core.ea_dais16; +import static miggy.cpupoet.Core.ea_dais16_read; +import static miggy.cpupoet.Core.ea_dais32; +import static miggy.cpupoet.Core.ea_dais32_read; +import static miggy.cpupoet.Core.ea_dais8; +import static miggy.cpupoet.Core.ea_dais8_read; +import static miggy.cpupoet.Core.ea_das16; +import static miggy.cpupoet.Core.ea_das16_read; +import static miggy.cpupoet.Core.ea_das32; +import static miggy.cpupoet.Core.ea_das32_read; +import static miggy.cpupoet.Core.ea_das8; +import static miggy.cpupoet.Core.ea_das8_read; +import static miggy.cpupoet.Core.ea_dpc16; +import static miggy.cpupoet.Core.ea_dpc16_read; +import static miggy.cpupoet.Core.ea_dpc32_read; +import static miggy.cpupoet.Core.ea_dpc8_read; +import static miggy.cpupoet.Core.ea_dpci16; +import static miggy.cpupoet.Core.ea_dpci16_read; +import static miggy.cpupoet.Core.ea_dpci32_read; +import static miggy.cpupoet.Core.ea_dpci8_read; +import static miggy.cpupoet.Core.ea_imm16_read; +import static miggy.cpupoet.Core.ea_imm32_read; +import static miggy.cpupoet.Core.ea_imm8_read; +import static miggy.cpupoet.Core.ea_paid16; +import static miggy.cpupoet.Core.ea_paid16_read; +import static miggy.cpupoet.Core.ea_paid32; +import static miggy.cpupoet.Core.ea_paid32_read; +import static miggy.cpupoet.Core.ea_paid8; +import static miggy.cpupoet.Core.ea_paid8_read; +import static miggy.cpupoet.Core.ea_pais16; +import static miggy.cpupoet.Core.ea_pais16_read; +import static miggy.cpupoet.Core.ea_pais32; +import static miggy.cpupoet.Core.ea_pais32_read; +import static miggy.cpupoet.Core.ea_pais8; +import static miggy.cpupoet.Core.ea_pais8_read; +import static miggy.cpupoet.Core.gen_abcdb_ds_dd; +import static miggy.cpupoet.Core.gen_abcdb_im_ea; +import static miggy.cpupoet.Core.gen_addb_dd_ea; +import static miggy.cpupoet.Core.gen_addb_ds_dd; +import static miggy.cpupoet.Core.gen_addb_dt_dd; +import static miggy.cpupoet.Core.gen_addb_dt_ds; +import static miggy.cpupoet.Core.gen_addb_im_ea; +import static miggy.cpupoet.Core.gen_addb_ir_ds; +import static miggy.cpupoet.Core.gen_addb_ir_ea; +import static miggy.cpupoet.Core.gen_addl_as_ad; +import static miggy.cpupoet.Core.gen_addl_as_dd; +import static miggy.cpupoet.Core.gen_addl_dd_ea; +import static miggy.cpupoet.Core.gen_addl_ds_ad; +import static miggy.cpupoet.Core.gen_addl_ds_dd; +import static miggy.cpupoet.Core.gen_addl_dt_ad; +import static miggy.cpupoet.Core.gen_addl_dt_dd; +import static miggy.cpupoet.Core.gen_addl_dt_ds; +import static miggy.cpupoet.Core.gen_addl_im_ea; +import static miggy.cpupoet.Core.gen_addl_ir_as; +import static miggy.cpupoet.Core.gen_addl_ir_ds; +import static miggy.cpupoet.Core.gen_addl_ir_ea; +import static miggy.cpupoet.Core.gen_addw_as_ad; +import static miggy.cpupoet.Core.gen_addw_as_dd; +import static miggy.cpupoet.Core.gen_addw_dd_ea; +import static miggy.cpupoet.Core.gen_addw_ds_ad; +import static miggy.cpupoet.Core.gen_addw_ds_dd; +import static miggy.cpupoet.Core.gen_addw_dt_ad; +import static miggy.cpupoet.Core.gen_addw_dt_dd; +import static miggy.cpupoet.Core.gen_addw_dt_ds; +import static miggy.cpupoet.Core.gen_addw_im_ea; +import static miggy.cpupoet.Core.gen_addw_ir_as; +import static miggy.cpupoet.Core.gen_addw_ir_ds; +import static miggy.cpupoet.Core.gen_addw_ir_ea; +import static miggy.cpupoet.Core.gen_addxb_ds_dd; +import static miggy.cpupoet.Core.gen_addxb_im_ea; +import static miggy.cpupoet.Core.gen_addxl_ds_dd; +import static miggy.cpupoet.Core.gen_addxl_im_ea; +import static miggy.cpupoet.Core.gen_addxw_ds_dd; +import static miggy.cpupoet.Core.gen_addxw_im_ea; +import static miggy.cpupoet.Core.gen_andb_dd_ea; +import static miggy.cpupoet.Core.gen_andb_ds_dd; +import static miggy.cpupoet.Core.gen_andb_dt_ccr; +import static miggy.cpupoet.Core.gen_andb_dt_dd; +import static miggy.cpupoet.Core.gen_andb_dt_ds; +import static miggy.cpupoet.Core.gen_andb_im_ea; +import static miggy.cpupoet.Core.gen_andl_dd_ea; +import static miggy.cpupoet.Core.gen_andl_ds_dd; +import static miggy.cpupoet.Core.gen_andl_dt_dd; +import static miggy.cpupoet.Core.gen_andl_dt_ds; +import static miggy.cpupoet.Core.gen_andl_im_ea; +import static miggy.cpupoet.Core.gen_andw_dd_ea; +import static miggy.cpupoet.Core.gen_andw_ds_dd; +import static miggy.cpupoet.Core.gen_andw_dt_dd; +import static miggy.cpupoet.Core.gen_andw_dt_ds; +import static miggy.cpupoet.Core.gen_andw_dt_sr; +import static miggy.cpupoet.Core.gen_andw_im_ea; +import static miggy.cpupoet.Core.gen_aslb_dd_ds; +import static miggy.cpupoet.Core.gen_aslb_ir_ds; +import static miggy.cpupoet.Core.gen_asll_dd_ds; +import static miggy.cpupoet.Core.gen_asll_ir_ds; +import static miggy.cpupoet.Core.gen_aslw_dd_ds; +import static miggy.cpupoet.Core.gen_aslw_ea; +import static miggy.cpupoet.Core.gen_aslw_ir_ds; +import static miggy.cpupoet.Core.gen_asrb_dd_ds; +import static miggy.cpupoet.Core.gen_asrb_ir_ds; +import static miggy.cpupoet.Core.gen_asrl_dd_ds; +import static miggy.cpupoet.Core.gen_asrl_ir_ds; +import static miggy.cpupoet.Core.gen_asrw_dd_ds; +import static miggy.cpupoet.Core.gen_asrw_ea; +import static miggy.cpupoet.Core.gen_asrw_ir_ds; +import static miggy.cpupoet.Core.gen_bchgb_dd_ea; +import static miggy.cpupoet.Core.gen_bchgb_im_ea; +import static miggy.cpupoet.Core.gen_bchgl_dd_ds; +import static miggy.cpupoet.Core.gen_bchgl_dt_ds; +import static miggy.cpupoet.Core.gen_bclrb_dd_ea; +import static miggy.cpupoet.Core.gen_bclrb_im_ea; +import static miggy.cpupoet.Core.gen_bclrl_dd_ds; +import static miggy.cpupoet.Core.gen_bclrl_dt_ds; +import static miggy.cpupoet.Core.gen_bsetb_dd_ea; +import static miggy.cpupoet.Core.gen_bsetb_im_ea; +import static miggy.cpupoet.Core.gen_bsetl_dd_ds; +import static miggy.cpupoet.Core.gen_bsetl_dt_ds; +import static miggy.cpupoet.Core.gen_btstb_dd_ea; +import static miggy.cpupoet.Core.gen_btstb_im_ea; +import static miggy.cpupoet.Core.gen_btstl_dd_ds; +import static miggy.cpupoet.Core.gen_btstl_dt_ds; +import static miggy.cpupoet.Core.gen_cmpb_ds_dd; +import static miggy.cpupoet.Core.gen_cmpb_dt_dd; +import static miggy.cpupoet.Core.gen_cmpb_dt_ds; +import static miggy.cpupoet.Core.gen_cmpb_im_ea; +import static miggy.cpupoet.Core.gen_cmpl_as_ad; +import static miggy.cpupoet.Core.gen_cmpl_as_dd; +import static miggy.cpupoet.Core.gen_cmpl_ds_ad; +import static miggy.cpupoet.Core.gen_cmpl_ds_dd; +import static miggy.cpupoet.Core.gen_cmpl_dt_ad; +import static miggy.cpupoet.Core.gen_cmpl_dt_dd; +import static miggy.cpupoet.Core.gen_cmpl_dt_ds; +import static miggy.cpupoet.Core.gen_cmpl_im_ea; +import static miggy.cpupoet.Core.gen_cmpmb_im_ea; +import static miggy.cpupoet.Core.gen_cmpml_im_ea; +import static miggy.cpupoet.Core.gen_cmpmw_im_ea; +import static miggy.cpupoet.Core.gen_cmpw_as_ad; +import static miggy.cpupoet.Core.gen_cmpw_as_dd; +import static miggy.cpupoet.Core.gen_cmpw_ds_ad; +import static miggy.cpupoet.Core.gen_cmpw_ds_dd; +import static miggy.cpupoet.Core.gen_cmpw_dt_ad; +import static miggy.cpupoet.Core.gen_cmpw_dt_dd; +import static miggy.cpupoet.Core.gen_cmpw_dt_ds; +import static miggy.cpupoet.Core.gen_cmpw_im_ea; +import static miggy.cpupoet.Core.gen_eorb_dd_ds; +import static miggy.cpupoet.Core.gen_eorb_dd_ea; +import static miggy.cpupoet.Core.gen_eorb_dt_ccr; +import static miggy.cpupoet.Core.gen_eorb_dt_ds; +import static miggy.cpupoet.Core.gen_eorb_im_ea; +import static miggy.cpupoet.Core.gen_eorl_dd_ds; +import static miggy.cpupoet.Core.gen_eorl_dd_ea; +import static miggy.cpupoet.Core.gen_eorl_dt_ds; +import static miggy.cpupoet.Core.gen_eorl_im_ea; +import static miggy.cpupoet.Core.gen_eorw_dd_ds; +import static miggy.cpupoet.Core.gen_eorw_dd_ea; +import static miggy.cpupoet.Core.gen_eorw_dt_ds; +import static miggy.cpupoet.Core.gen_eorw_dt_sr; +import static miggy.cpupoet.Core.gen_eorw_im_ea; +import static miggy.cpupoet.Core.gen_lslb_dd_ds; +import static miggy.cpupoet.Core.gen_lslb_ir_ds; +import static miggy.cpupoet.Core.gen_lsll_dd_ds; +import static miggy.cpupoet.Core.gen_lsll_ir_ds; +import static miggy.cpupoet.Core.gen_lslw_dd_ds; +import static miggy.cpupoet.Core.gen_lslw_ea; +import static miggy.cpupoet.Core.gen_lslw_ir_ds; +import static miggy.cpupoet.Core.gen_lsrb_dd_ds; +import static miggy.cpupoet.Core.gen_lsrb_ir_ds; +import static miggy.cpupoet.Core.gen_lsrl_dd_ds; +import static miggy.cpupoet.Core.gen_lsrl_ir_ds; +import static miggy.cpupoet.Core.gen_lsrw_dd_ds; +import static miggy.cpupoet.Core.gen_lsrw_ea; +import static miggy.cpupoet.Core.gen_lsrw_ir_ds; +import static miggy.cpupoet.Core.gen_moveb_ds_dd; +import static miggy.cpupoet.Core.gen_moveb_ds_ea; +import static miggy.cpupoet.Core.gen_moveb_dt_dd; +import static miggy.cpupoet.Core.gen_moveb_dt_ea; +import static miggy.cpupoet.Core.gen_movel_as_ad; +import static miggy.cpupoet.Core.gen_movel_as_dd; +import static miggy.cpupoet.Core.gen_movel_as_ea; +import static miggy.cpupoet.Core.gen_movel_ds_ad; +import static miggy.cpupoet.Core.gen_movel_ds_dd; +import static miggy.cpupoet.Core.gen_movel_ds_ea; +import static miggy.cpupoet.Core.gen_movel_dt_ad; +import static miggy.cpupoet.Core.gen_movel_dt_dd; +import static miggy.cpupoet.Core.gen_movel_dt_ea; +import static miggy.cpupoet.Core.gen_movel_im_dd; +import static miggy.cpupoet.Core.gen_movew_as_ad; +import static miggy.cpupoet.Core.gen_movew_as_dd; +import static miggy.cpupoet.Core.gen_movew_as_ea; +import static miggy.cpupoet.Core.gen_movew_ccr_ds; +import static miggy.cpupoet.Core.gen_movew_ccr_ea; +import static miggy.cpupoet.Core.gen_movew_ds_ad; +import static miggy.cpupoet.Core.gen_movew_ds_ccr; +import static miggy.cpupoet.Core.gen_movew_ds_dd; +import static miggy.cpupoet.Core.gen_movew_ds_ea; +import static miggy.cpupoet.Core.gen_movew_ds_sr; +import static miggy.cpupoet.Core.gen_movew_dt_ad; +import static miggy.cpupoet.Core.gen_movew_dt_ccr; +import static miggy.cpupoet.Core.gen_movew_dt_dd; +import static miggy.cpupoet.Core.gen_movew_dt_ea; +import static miggy.cpupoet.Core.gen_movew_dt_sr; +import static miggy.cpupoet.Core.gen_movew_sr_ds; +import static miggy.cpupoet.Core.gen_movew_sr_ea; +import static miggy.cpupoet.Core.gen_nbcdb_ds; +import static miggy.cpupoet.Core.gen_nbcdb_ea; +import static miggy.cpupoet.Core.gen_negb_ds; +import static miggy.cpupoet.Core.gen_negb_ea; +import static miggy.cpupoet.Core.gen_negl_ds; +import static miggy.cpupoet.Core.gen_negl_ea; +import static miggy.cpupoet.Core.gen_negw_ds; +import static miggy.cpupoet.Core.gen_negxb_ds; +import static miggy.cpupoet.Core.gen_negxb_ea; +import static miggy.cpupoet.Core.gen_negxl_ds; +import static miggy.cpupoet.Core.gen_negxl_ea; +import static miggy.cpupoet.Core.gen_negxw_ds; +import static miggy.cpupoet.Core.gen_negxw_ea; +import static miggy.cpupoet.Core.gen_notb_ds; +import static miggy.cpupoet.Core.gen_notb_ea; +import static miggy.cpupoet.Core.gen_notl_ds; +import static miggy.cpupoet.Core.gen_notl_ea; +import static miggy.cpupoet.Core.gen_notw_ds; +import static miggy.cpupoet.Core.gen_notw_ea; +import static miggy.cpupoet.Core.gen_orb_dd_ea; +import static miggy.cpupoet.Core.gen_orb_ds_dd; +import static miggy.cpupoet.Core.gen_orb_dt_ccr; +import static miggy.cpupoet.Core.gen_orb_dt_dd; +import static miggy.cpupoet.Core.gen_orb_dt_ds; +import static miggy.cpupoet.Core.gen_orb_im_ea; +import static miggy.cpupoet.Core.gen_orl_dd_ea; +import static miggy.cpupoet.Core.gen_orl_ds_dd; +import static miggy.cpupoet.Core.gen_orl_dt_dd; +import static miggy.cpupoet.Core.gen_orl_dt_ds; +import static miggy.cpupoet.Core.gen_orl_im_ea; +import static miggy.cpupoet.Core.gen_orw_dd_ea; +import static miggy.cpupoet.Core.gen_orw_ds_dd; +import static miggy.cpupoet.Core.gen_orw_dt_dd; +import static miggy.cpupoet.Core.gen_orw_dt_ds; +import static miggy.cpupoet.Core.gen_orw_dt_sr; +import static miggy.cpupoet.Core.gen_orw_im_ea; +import static miggy.cpupoet.Core.gen_rolb_dd_ds; +import static miggy.cpupoet.Core.gen_rolb_ir_ds; +import static miggy.cpupoet.Core.gen_roll_dd_ds; +import static miggy.cpupoet.Core.gen_roll_ir_ds; +import static miggy.cpupoet.Core.gen_rolw_dd_ds; +import static miggy.cpupoet.Core.gen_rolw_ea; +import static miggy.cpupoet.Core.gen_rolw_ir_ds; +import static miggy.cpupoet.Core.gen_rorb_dd_ds; +import static miggy.cpupoet.Core.gen_rorb_ir_ds; +import static miggy.cpupoet.Core.gen_rorl_dd_ds; +import static miggy.cpupoet.Core.gen_rorl_ir_ds; +import static miggy.cpupoet.Core.gen_rorw_dd_ds; +import static miggy.cpupoet.Core.gen_rorw_ea; +import static miggy.cpupoet.Core.gen_rorw_ir_ds; +import static miggy.cpupoet.Core.gen_sbcdb_ds_dd; +import static miggy.cpupoet.Core.gen_sbcdb_im_ea; +import static miggy.cpupoet.Core.gen_subb_dd_ea; +import static miggy.cpupoet.Core.gen_subb_ds_dd; +import static miggy.cpupoet.Core.gen_subb_dt_dd; +import static miggy.cpupoet.Core.gen_subb_dt_ds; +import static miggy.cpupoet.Core.gen_subb_im_ea; +import static miggy.cpupoet.Core.gen_subb_ir_ds; +import static miggy.cpupoet.Core.gen_subb_ir_ea; +import static miggy.cpupoet.Core.gen_subl_as_ad; +import static miggy.cpupoet.Core.gen_subl_as_dd; +import static miggy.cpupoet.Core.gen_subl_dd_ea; +import static miggy.cpupoet.Core.gen_subl_ds_ad; +import static miggy.cpupoet.Core.gen_subl_ds_dd; +import static miggy.cpupoet.Core.gen_subl_dt_ad; +import static miggy.cpupoet.Core.gen_subl_dt_dd; +import static miggy.cpupoet.Core.gen_subl_dt_ds; +import static miggy.cpupoet.Core.gen_subl_im_ea; +import static miggy.cpupoet.Core.gen_subl_ir_as; +import static miggy.cpupoet.Core.gen_subl_ir_ds; +import static miggy.cpupoet.Core.gen_subl_ir_ea; +import static miggy.cpupoet.Core.gen_subw_as_ad; +import static miggy.cpupoet.Core.gen_subw_as_dd; +import static miggy.cpupoet.Core.gen_subw_dd_ea; +import static miggy.cpupoet.Core.gen_subw_ds_ad; +import static miggy.cpupoet.Core.gen_subw_ds_dd; +import static miggy.cpupoet.Core.gen_subw_dt_ad; +import static miggy.cpupoet.Core.gen_subw_dt_dd; +import static miggy.cpupoet.Core.gen_subw_dt_ds; +import static miggy.cpupoet.Core.gen_subw_im_ea; +import static miggy.cpupoet.Core.gen_subw_ir_as; +import static miggy.cpupoet.Core.gen_subw_ir_ds; +import static miggy.cpupoet.Core.gen_subw_ir_ea; +import static miggy.cpupoet.Core.gen_subxb_ds_dd; +import static miggy.cpupoet.Core.gen_subxb_im_ea; +import static miggy.cpupoet.Core.gen_subxl_ds_dd; +import static miggy.cpupoet.Core.gen_subxl_im_ea; +import static miggy.cpupoet.Core.gen_subxw_ds_dd; +import static miggy.cpupoet.Core.gen_subxw_im_ea; +import static miggy.cpupoet.Core.gen_tstb_ds; +import static miggy.cpupoet.Core.gen_tstb_ea; +import static miggy.cpupoet.Core.gen_tstl_ds; +import static miggy.cpupoet.Core.gen_tstl_ea; +import static miggy.cpupoet.Core.gen_tstw_ds; +import static miggy.cpupoet.Core.gen_tstw_ea; +import static miggy.cpupoet.Core.op_bcc16; +import static miggy.cpupoet.Core.op_bcc32; +import static miggy.cpupoet.Core.op_bcc8; +import static miggy.cpupoet.Core.op_bkpt; +import static miggy.cpupoet.Core.op_bra16; +import static miggy.cpupoet.Core.op_bra32; +import static miggy.cpupoet.Core.op_bra8; +import static miggy.cpupoet.Core.op_bsr16; +import static miggy.cpupoet.Core.op_bsr32; +import static miggy.cpupoet.Core.op_bsr8; +import static miggy.cpupoet.Core.op_chk_w_ds; +import static miggy.cpupoet.Core.op_chk_w_ea; +import static miggy.cpupoet.Core.op_clrb_ds; +import static miggy.cpupoet.Core.op_clrb_ea; +import static miggy.cpupoet.Core.op_clrl_ds; +import static miggy.cpupoet.Core.op_clrl_ea; +import static miggy.cpupoet.Core.op_clrw_ds; +import static miggy.cpupoet.Core.op_clrw_ea; +import static miggy.cpupoet.Core.op_dbcc; +import static miggy.cpupoet.Core.op_exg_ad_as; +import static miggy.cpupoet.Core.op_exg_dd_as; +import static miggy.cpupoet.Core.op_exg_dd_ds; +import static miggy.cpupoet.Core.op_extbl_ds; +import static miggy.cpupoet.Core.op_extl_ds; +import static miggy.cpupoet.Core.op_extw_ds; +import static miggy.cpupoet.Core.op_illegal; +import static miggy.cpupoet.Core.op_imm16; +import static miggy.cpupoet.Core.op_imm32; +import static miggy.cpupoet.Core.op_jmp; +import static miggy.cpupoet.Core.op_jsr; +import static miggy.cpupoet.Core.op_lea_ea_ad; +import static miggy.cpupoet.Core.op_linea; +import static miggy.cpupoet.Core.op_linef; +import static miggy.cpupoet.Core.op_link_as_imm16; +import static miggy.cpupoet.Core.op_link_as_imm32; +import static miggy.cpupoet.Core.op_move_as_usp; +import static miggy.cpupoet.Core.op_move_usp_as; +import static miggy.cpupoet.Core.op_movec_cr_rz; +import static miggy.cpupoet.Core.op_movec_rz_cr; +import static miggy.cpupoet.Core.op_movepl_das_dd; +import static miggy.cpupoet.Core.op_movepl_dd_das; +import static miggy.cpupoet.Core.op_movepw_das_dd; +import static miggy.cpupoet.Core.op_movepw_dd_das; +import static miggy.cpupoet.Core.op_nop; +import static miggy.cpupoet.Core.op_pea; +import static miggy.cpupoet.Core.op_reset; +import static miggy.cpupoet.Core.op_rte; +import static miggy.cpupoet.Core.op_rtr; +import static miggy.cpupoet.Core.op_rts; +import static miggy.cpupoet.Core.op_scc_b_ds; +import static miggy.cpupoet.Core.op_scc_b_ea; +import static miggy.cpupoet.Core.op_stop; +import static miggy.cpupoet.Core.op_swap_ds; +import static miggy.cpupoet.Core.op_trap; +import static miggy.cpupoet.Core.op_trapcc; +import static miggy.cpupoet.Core.op_trapcc16; +import static miggy.cpupoet.Core.op_trapcc32; +import static miggy.cpupoet.Core.op_trapv; +import static miggy.cpupoet.Core.op_unlk_as; + +public enum MacroPLA { + ori_b_imm8_ds(0x0000, 0xfff8, op_imm16, gen_orb_dt_ds, dbrr), + + ori_b_imm8_ais(0x0010, 0xfff8, op_imm16, ea_ais8_read, gen_orb_im_ea), + + ori_b_imm8_aips(0x0018, 0xfff8, op_imm16, ea_aips8_read, gen_orb_im_ea), + + ori_b_imm8_pais(0x0020, 0xfff8, op_imm16, ea_pais8_read, gen_orb_im_ea), + + ori_b_imm8_das(0x0028, 0xfff8, op_imm16, ea_das8_read, gen_orb_im_ea), + + ori_b_imm8_dais(0x0030, 0xfff8, op_imm16, ea_dais8_read, gen_orb_im_ea), + + ori_b_imm8_adr16(0x0038, 0xffff, op_imm16, ea_adr16s8_read, gen_orb_im_ea), + + ori_b_imm8_adr32(0x0039, 0xffff, op_imm16, ea_adr32s8_read, gen_orb_im_ea), + + ori_imm8_ccr(0x003c, 0xffff, op_imm16, gen_orb_dt_ccr, dbrr), + + ori_w_imm16_ds(0x0040, 0xfff8, op_imm16, gen_orw_dt_ds, dbrr), + + ori_w_imm16_ais(0x0050, 0xfff8, op_imm16, ea_ais16_read, gen_orw_im_ea), + + ori_w_imm16_aips(0x0058, 0xfff8, op_imm16, ea_aips16_read, gen_orw_im_ea), + + ori_w_imm16_pais(0x0060, 0xfff8, op_imm16, ea_pais16_read, gen_orw_im_ea), + + ori_w_imm16_das(0x0068, 0xfff8, op_imm16, ea_das16_read, gen_orw_im_ea), + + ori_w_imm16_dais(0x0070, 0xfff8, op_imm16, ea_dais16_read, gen_orw_im_ea), + + ori_w_imm16_adr16(0x0078, 0xffff, op_imm16, ea_adr16s16_read, gen_orw_im_ea), + + ori_w_imm16_adr32(0x0079, 0xffff, op_imm16, ea_adr32s16_read, gen_orw_im_ea), + + ori_i16u_sr(0x007c, 0xffff, op_imm16, gen_orw_dt_sr, dbrr), + + ori_l_imm32_ds(0x0080, 0xfff8, op_imm32, gen_orl_dt_ds, dbrr), + + ori_l_imm32_ais(0x0090, 0xfff8, op_imm32, ea_ais32_read, gen_orl_im_ea), + + ori_l_imm32_aips(0x0098, 0xfff8, op_imm32, ea_aips32_read, gen_orl_im_ea), + + ori_l_imm32_pais(0x00a0, 0xfff8, op_imm32, ea_pais32_read, gen_orl_im_ea), + + ori_l_imm32_das(0x00a8, 0xfff8, op_imm32, ea_das32_read, gen_orl_im_ea), + + ori_l_imm32_dais(0x00b0, 0xfff8, op_imm32, ea_dais32_read, gen_orl_im_ea), + + ori_l_imm32_adr16(0x00b8, 0xffff, op_imm32, ea_adr16s32_read, gen_orl_im_ea), + + ori_l_imm32_adr32(0x00b9, 0xffff, op_imm32, ea_adr32s32_read, gen_orl_im_ea), + + btst_dd_ds(0x0100, 0xf1f8, gen_btstl_dd_ds, dbrr, dbrr), + + movep_w_das_dd(0x0108, 0xf1f8, ea_das16, dbrr, op_movepw_das_dd), + + btst_dd_ais(0x0110, 0xf1f8, ea_ais8_read, dbrr, gen_btstb_dd_ea), + + btst_dd_aips(0x0118, 0xf1f8, ea_aips8_read, dbrr, gen_btstb_dd_ea), + + btst_dd_pais(0x0120, 0xf1f8, ea_pais8_read, dbrr, gen_btstb_dd_ea), + + btst_dd_das(0x0128, 0xf1f8, ea_das8_read, dbrr, gen_btstb_dd_ea), + + btst_dd_dais(0x0130, 0xf1f8, ea_dais8_read, dbrr, gen_btstb_dd_ea), + + btst_dd_adr16(0x0138, 0xf1ff, ea_adr16s8_read, dbrr, gen_btstb_dd_ea), + + btst_dd_adr32(0x0139, 0xf1ff, ea_adr32s8_read, dbrr, gen_btstb_dd_ea), + + btst_dd_dpc(0x013a, 0xf1ff, ea_dpc8_read, dbrr, gen_btstb_dd_ea), + + btst_dd_dpci(0x013b, 0xf1ff, ea_dpci8_read, dbrr, gen_btstb_dd_ea), + + btst_dd_imm8(0x013c, 0xf1ff, ea_imm8_read, dbrr, gen_btstb_dd_ea), + + bchg_dd_ds(0x0140, 0xf1f8, gen_bchgl_dd_ds, dbrr, dbrr), + + movep_l_das_dd(0x0148, 0xf1f8, ea_das32, dbrr, op_movepl_das_dd), + + bchg_dd_ais(0x0150, 0xf1f8, ea_ais8_read, dbrr, gen_bchgb_dd_ea), + + bchg_dd_aips(0x0158, 0xf1f8, ea_aips8_read, dbrr, gen_bchgb_dd_ea), + + bchg_dd_pais(0x0160, 0xf1f8, ea_pais8_read, dbrr, gen_bchgb_dd_ea), + + bchg_dd_das(0x0168, 0xf1f8, ea_das8_read, dbrr, gen_bchgb_dd_ea), + + bchg_dd_dais(0x0170, 0xf1f8, ea_dais8_read, dbrr, gen_bchgb_dd_ea), + + bchg_dd_adr16(0x0178, 0xf1ff, ea_adr16s8_read, dbrr, gen_bchgb_dd_ea), + + bchg_dd_adr32(0x0179, 0xf1ff, ea_adr32s8_read, dbrr, gen_bchgb_dd_ea), + + bclr_dd_ds(0x0180, 0xf1f8, gen_bclrl_dd_ds, dbrr, dbrr), + + movep_w_dd_das(0x0188, 0xf1f8, ea_das16, dbrr, op_movepw_dd_das), + + bclr_dd_ais(0x0190, 0xf1f8, ea_ais8_read, dbrr, gen_bclrb_dd_ea), + + bclr_dd_aips(0x0198, 0xf1f8, ea_aips8_read, dbrr, gen_bclrb_dd_ea), + + bclr_dd_pais(0x01a0, 0xf1f8, ea_pais8_read, dbrr, gen_bclrb_dd_ea), + + bclr_dd_das(0x01a8, 0xf1f8, ea_das8_read, dbrr, gen_bclrb_dd_ea), + + bclr_dd_dais(0x01b0, 0xf1f8, ea_dais8_read, dbrr, gen_bclrb_dd_ea), + + bclr_dd_adr16(0x01b8, 0xf1ff, ea_adr16s8_read, dbrr, gen_bclrb_dd_ea), + + bclr_dd_adr32(0x01b9, 0xf1ff, ea_adr32s8_read, dbrr, gen_bclrb_dd_ea), + + bset_dd_ds(0x01c0, 0xf1f8, gen_bsetl_dd_ds, dbrr, dbrr), + + movep_l_dd_das(0x01c8, 0xf1f8, ea_das32, dbrr, op_movepl_dd_das), + + bset_dd_ais(0x01d0, 0xf1f8, ea_ais8_read, dbrr, gen_bsetb_dd_ea), + + bset_dd_aips(0x01d8, 0xf1f8, ea_aips8_read, dbrr, gen_bsetb_dd_ea), + + bset_dd_pais(0x01e0, 0xf1f8, ea_pais8_read, dbrr, gen_bsetb_dd_ea), + + bset_dd_das(0x01e8, 0xf1f8, ea_das8_read, dbrr, gen_bsetb_dd_ea), + + bset_dd_dais(0x01f0, 0xf1f8, ea_dais8_read, dbrr, gen_bsetb_dd_ea), + + bset_dd_adr16(0x01f8, 0xf1ff, ea_adr16s8_read, dbrr, gen_bsetb_dd_ea), + + bset_dd_adr32(0x01f9, 0xf1ff, ea_adr32s8_read, dbrr, gen_bsetb_dd_ea), + + andi_b_imm8_ds(0x0200, 0xfff8, op_imm16, gen_andb_dt_ds, dbrr), + + andi_b_imm8_ais(0x0210, 0xfff8, op_imm16, ea_ais8_read, gen_andb_im_ea), + + andi_b_imm8_aips(0x0218, 0xfff8, op_imm16, ea_aips8_read, gen_andb_im_ea), + + andi_b_imm8_pais(0x0220, 0xfff8, op_imm16, ea_pais8_read, gen_andb_im_ea), + + andi_b_imm8_das(0x0228, 0xfff8, op_imm16, ea_das8_read, gen_andb_im_ea), + + andi_b_imm8_dais(0x0230, 0xfff8, op_imm16, ea_dais8_read, gen_andb_im_ea), + + andi_b_imm8_adr16(0x0238, 0xffff, op_imm16, ea_adr16s8_read, gen_andb_im_ea), + + andi_b_imm8_adr32(0x0239, 0xffff, op_imm16, ea_adr32s8_read, gen_andb_im_ea), + + andi_imm8_ccr(0x023c, 0xffff, op_imm16, gen_andb_dt_ccr, dbrr), + + andi_w_imm16_ds(0x0240, 0xfff8, op_imm16, gen_andw_dt_ds, dbrr), + + andi_w_imm16_ais(0x0250, 0xfff8, op_imm16, ea_ais16_read, gen_andw_im_ea), + + andi_w_imm16_aips(0x0258, 0xfff8, op_imm16, ea_aips16_read, gen_andw_im_ea), + + andi_w_imm16_pais(0x0260, 0xfff8, op_imm16, ea_pais16_read, gen_andw_im_ea), + + andi_w_imm16_das(0x0268, 0xfff8, op_imm16, ea_das16_read, gen_andw_im_ea), + + andi_w_imm16_dais(0x0270, 0xfff8, op_imm16, ea_dais16_read, gen_andw_im_ea), + + andi_w_imm16_adr16(0x0278, 0xffff, op_imm16, ea_adr16s16_read, gen_andw_im_ea), + + andi_w_imm16_adr32(0x0279, 0xffff, op_imm16, ea_adr32s16_read, gen_andw_im_ea), + + andi_i16u_sr(0x027c, 0xffff, op_imm16, gen_andw_dt_sr, dbrr), + + andi_l_imm32_ds(0x0280, 0xfff8, op_imm32, gen_andl_dt_ds, dbrr), + + andi_l_imm32_ais(0x0290, 0xfff8, op_imm32, ea_ais32_read, gen_andl_im_ea), + + andi_l_imm32_aips(0x0298, 0xfff8, op_imm32, ea_aips32_read, gen_andl_im_ea), + + andi_l_imm32_pais(0x02a0, 0xfff8, op_imm32, ea_pais32_read, gen_andl_im_ea), + + andi_l_imm32_das(0x02a8, 0xfff8, op_imm32, ea_das32_read, gen_andl_im_ea), + + andi_l_imm32_dais(0x02b0, 0xfff8, op_imm32, ea_dais32_read, gen_andl_im_ea), + + andi_l_imm32_adr16(0x02b8, 0xffff, op_imm32, ea_adr16s32_read, gen_andl_im_ea), + + andi_l_imm32_adr32(0x02b9, 0xffff, op_imm32, ea_adr32s32_read, gen_andl_im_ea), + + subi_b_imm8_ds(0x0400, 0xfff8, op_imm16, gen_subb_dt_ds, dbrr), + + subi_b_imm8_ais(0x0410, 0xfff8, op_imm16, ea_ais8_read, gen_subb_im_ea), + + subi_b_imm8_aips(0x0418, 0xfff8, op_imm16, ea_aips8_read, gen_subb_im_ea), + + subi_b_imm8_pais(0x0420, 0xfff8, op_imm16, ea_pais8_read, gen_subb_im_ea), + + subi_b_imm8_das(0x0428, 0xfff8, op_imm16, ea_das8_read, gen_subb_im_ea), + + subi_b_imm8_dais(0x0430, 0xfff8, op_imm16, ea_dais8_read, gen_subb_im_ea), + + subi_b_imm8_adr16(0x0438, 0xffff, op_imm16, ea_adr16s8_read, gen_subb_im_ea), + + subi_b_imm8_adr32(0x0439, 0xffff, op_imm16, ea_adr32s8_read, gen_subb_im_ea), + + subi_w_imm16_ds(0x0440, 0xfff8, op_imm16, gen_subw_dt_ds, dbrr), + + subi_w_imm16_ais(0x0450, 0xfff8, op_imm16, ea_ais16_read, gen_subw_im_ea), + + subi_w_imm16_aips(0x0458, 0xfff8, op_imm16, ea_aips16_read, gen_subw_im_ea), + + subi_w_imm16_pais(0x0460, 0xfff8, op_imm16, ea_pais16_read, gen_subw_im_ea), + + subi_w_imm16_das(0x0468, 0xfff8, op_imm16, ea_das16_read, gen_subw_im_ea), + + subi_w_imm16_dais(0x0470, 0xfff8, op_imm16, ea_dais16_read, gen_subw_im_ea), + + subi_w_imm16_adr16(0x0478, 0xffff, op_imm16, ea_adr16s16_read, gen_subw_im_ea), + + subi_w_imm16_adr32(0x0479, 0xffff, op_imm16, ea_adr32s16_read, gen_subw_im_ea), + + subi_l_imm32_ds(0x0480, 0xfff8, op_imm32, gen_subl_dt_ds, dbrr), + + subi_l_imm32_ais(0x0490, 0xfff8, op_imm32, ea_ais32_read, gen_subl_im_ea), + + subi_l_imm32_aips(0x0498, 0xfff8, op_imm32, ea_aips32_read, gen_subl_im_ea), + + subi_l_imm32_pais(0x04a0, 0xfff8, op_imm32, ea_pais32_read, gen_subl_im_ea), + + subi_l_imm32_das(0x04a8, 0xfff8, op_imm32, ea_das32_read, gen_subl_im_ea), + + subi_l_imm32_dais(0x04b0, 0xfff8, op_imm32, ea_dais32_read, gen_subl_im_ea), + + subi_l_imm32_adr16(0x04b8, 0xffff, op_imm32, ea_adr16s32_read, gen_subl_im_ea), + + subi_l_imm32_adr32(0x04b9, 0xffff, op_imm32, ea_adr32s32_read, gen_subl_im_ea), + + addi_b_imm8_ds(0x0600, 0xfff8, op_imm16, gen_addb_dt_ds, dbrr), + + addi_b_imm8_ais(0x0610, 0xfff8, op_imm16, ea_ais8_read, gen_addb_im_ea), + + addi_b_imm8_aips(0x0618, 0xfff8, op_imm16, ea_aips8_read, gen_addb_im_ea), + + addi_b_imm8_pais(0x0620, 0xfff8, op_imm16, ea_pais8_read, gen_addb_im_ea), + + addi_b_imm8_das(0x0628, 0xfff8, op_imm16, ea_das8_read, gen_addb_im_ea), + + addi_b_imm8_dais(0x0630, 0xfff8, op_imm16, ea_dais8_read, gen_addb_im_ea), + + addi_b_imm8_adr16(0x0638, 0xffff, op_imm16, ea_adr16s8_read, gen_addb_im_ea), + + addi_b_imm8_adr32(0x0639, 0xffff, op_imm16, ea_adr32s8_read, gen_addb_im_ea), + + addi_w_imm16_ds(0x0640, 0xfff8, op_imm16, gen_addw_dt_ds, dbrr), + + addi_w_imm16_ais(0x0650, 0xfff8, op_imm16, ea_ais16_read, gen_addw_im_ea), + + addi_w_imm16_aips(0x0658, 0xfff8, op_imm16, ea_aips16_read, gen_addw_im_ea), + + addi_w_imm16_pais(0x0660, 0xfff8, op_imm16, ea_pais16_read, gen_addw_im_ea), + + addi_w_imm16_das(0x0668, 0xfff8, op_imm16, ea_das16_read, gen_addw_im_ea), + + addi_w_imm16_dais(0x0670, 0xfff8, op_imm16, ea_dais16_read, gen_addw_im_ea), + + addi_w_imm16_adr16(0x0678, 0xffff, op_imm16, ea_adr16s16_read, gen_addw_im_ea), + + addi_w_imm16_adr32(0x0679, 0xffff, op_imm16, ea_adr32s16_read, gen_addw_im_ea), + + addi_l_imm32_ds(0x0680, 0xfff8, op_imm32, gen_addl_dt_ds, dbrr), + + addi_l_imm32_ais(0x0690, 0xfff8, op_imm32, ea_ais32_read, gen_addl_im_ea), + + addi_l_imm32_aips(0x0698, 0xfff8, op_imm32, ea_aips32_read, gen_addl_im_ea), + + addi_l_imm32_pais(0x06a0, 0xfff8, op_imm32, ea_pais32_read, gen_addl_im_ea), + + addi_l_imm32_das(0x06a8, 0xfff8, op_imm32, ea_das32_read, gen_addl_im_ea), + + addi_l_imm32_dais(0x06b0, 0xfff8, op_imm32, ea_dais32_read, gen_addl_im_ea), + + addi_l_imm32_adr16(0x06b8, 0xffff, op_imm32, ea_adr16s32_read, gen_addl_im_ea), + + addi_l_imm32_adr32(0x06b9, 0xffff, op_imm32, ea_adr32s32_read, gen_addl_im_ea), + + btst_imm8_ds(0x0800, 0xfff8, op_imm16, gen_btstl_dt_ds, dbrr), + + btst_imm8_ais(0x0810, 0xfff8, op_imm16, ea_ais8_read, gen_btstb_im_ea), + + btst_imm8_aips(0x0818, 0xfff8, op_imm16, ea_aips8_read, gen_btstb_im_ea), + + btst_imm8_pais(0x0820, 0xfff8, op_imm16, ea_pais8_read, gen_btstb_im_ea), + + btst_imm8_das(0x0828, 0xfff8, op_imm16, ea_das8_read, gen_btstb_im_ea), + + btst_imm8_dais(0x0830, 0xfff8, op_imm16, ea_dais8_read, gen_btstb_im_ea), + + btst_imm8_adr16(0x0838, 0xffff, op_imm16, ea_adr16s8_read, gen_btstb_im_ea), + + btst_imm8_adr32(0x0839, 0xffff, op_imm16, ea_adr32s8_read, gen_btstb_im_ea), + + btst_imm8_dpc(0x083a, 0xffff, op_imm16, ea_dpc8_read, gen_btstb_im_ea), + + btst_imm8_dpci(0x083b, 0xffff, op_imm16, ea_dpci8_read, gen_btstb_im_ea), + + bchg_imm8_ds(0x0840, 0xfff8, op_imm16, gen_bchgl_dt_ds, dbrr), + + bchg_imm8_ais(0x0850, 0xfff8, op_imm16, ea_ais8_read, gen_bchgb_im_ea), + + bchg_imm8_aips(0x0858, 0xfff8, op_imm16, ea_aips8_read, gen_bchgb_im_ea), + + bchg_imm8_pais(0x0860, 0xfff8, op_imm16, ea_pais8_read, gen_bchgb_im_ea), + + bchg_imm8_das(0x0868, 0xfff8, op_imm16, ea_das8_read, gen_bchgb_im_ea), + + bchg_imm8_dais(0x0870, 0xfff8, op_imm16, ea_dais8_read, gen_bchgb_im_ea), + + bchg_imm8_adr16(0x0878, 0xffff, op_imm16, ea_adr16s8_read, gen_bchgb_im_ea), + + bchg_imm8_adr32(0x0879, 0xffff, op_imm16, ea_adr32s8_read, gen_bchgb_im_ea), + + bclr_imm8_ds(0x0880, 0xfff8, op_imm16, gen_bclrl_dt_ds, dbrr), + + bclr_imm8_ais(0x0890, 0xfff8, op_imm16, ea_ais8_read, gen_bclrb_im_ea), + + bclr_imm8_aips(0x0898, 0xfff8, op_imm16, ea_aips8_read, gen_bclrb_im_ea), + + bclr_imm8_pais(0x08a0, 0xfff8, op_imm16, ea_pais8_read, gen_bclrb_im_ea), + + bclr_imm8_das(0x08a8, 0xfff8, op_imm16, ea_das8_read, gen_bclrb_im_ea), + + bclr_imm8_dais(0x08b0, 0xfff8, op_imm16, ea_dais8_read, gen_bclrb_im_ea), + + bclr_imm8_adr16(0x08b8, 0xffff, op_imm16, ea_adr16s8_read, gen_bclrb_im_ea), + + bclr_imm8_adr32(0x08b9, 0xffff, op_imm16, ea_adr32s8_read, gen_bclrb_im_ea), + + bset_imm8_ds(0x08c0, 0xfff8, op_imm16, gen_bsetl_dt_ds, dbrr), + + bset_imm8_ais(0x08d0, 0xfff8, op_imm16, ea_ais8_read, gen_bsetb_im_ea), + + bset_imm8_aips(0x08d8, 0xfff8, op_imm16, ea_aips8_read, gen_bsetb_im_ea), + + bset_imm8_pais(0x08e0, 0xfff8, op_imm16, ea_pais8_read, gen_bsetb_im_ea), + + bset_imm8_das(0x08e8, 0xfff8, op_imm16, ea_das8_read, gen_bsetb_im_ea), + + bset_imm8_dais(0x08f0, 0xfff8, op_imm16, ea_dais8_read, gen_bsetb_im_ea), + + bset_imm8_adr16(0x08f8, 0xffff, op_imm16, ea_adr16s8_read, gen_bsetb_im_ea), + + bset_imm8_adr32(0x08f9, 0xffff, op_imm16, ea_adr32s8_read, gen_bsetb_im_ea), + + eori_b_imm8_ds(0x0a00, 0xfff8, op_imm16, gen_eorb_dt_ds, dbrr), + + eori_b_imm8_ais(0x0a10, 0xfff8, op_imm16, ea_ais8_read, gen_eorb_im_ea), + + eori_b_imm8_aips(0x0a18, 0xfff8, op_imm16, ea_aips8_read, gen_eorb_im_ea), + + eori_b_imm8_pais(0x0a20, 0xfff8, op_imm16, ea_pais8_read, gen_eorb_im_ea), + + eori_b_imm8_das(0x0a28, 0xfff8, op_imm16, ea_das8_read, gen_eorb_im_ea), + + eori_b_imm8_dais(0x0a30, 0xfff8, op_imm16, ea_dais8_read, gen_eorb_im_ea), + + eori_b_imm8_adr16(0x0a38, 0xffff, op_imm16, ea_adr16s8_read, gen_eorb_im_ea), + + eori_b_imm8_adr32(0x0a39, 0xffff, op_imm16, ea_adr32s8_read, gen_eorb_im_ea), + + eori_imm8_ccr(0x0a3c, 0xffff, op_imm16, gen_eorb_dt_ccr, dbrr), + + eori_w_imm16_ds(0x0a40, 0xfff8, op_imm16, gen_eorw_dt_ds, dbrr), + + eori_w_imm16_ais(0x0a50, 0xfff8, op_imm16, ea_ais16_read, gen_eorw_im_ea), + + eori_w_imm16_aips(0x0a58, 0xfff8, op_imm16, ea_aips16_read, gen_eorw_im_ea), + + eori_w_imm16_pais(0x0a60, 0xfff8, op_imm16, ea_pais16_read, gen_eorw_im_ea), + + eori_w_imm16_das(0x0a68, 0xfff8, op_imm16, ea_das16_read, gen_eorw_im_ea), + + eori_w_imm16_dais(0x0a70, 0xfff8, op_imm16, ea_dais16_read, gen_eorw_im_ea), + + eori_w_imm16_adr16(0x0a78, 0xffff, op_imm16, ea_adr16s16_read, gen_eorw_im_ea), + + eori_w_imm16_adr32(0x0a79, 0xffff, op_imm16, ea_adr32s16_read, gen_eorw_im_ea), + + eori_i16u_sr(0x0a7c, 0xffff, op_imm16, gen_eorw_dt_sr, dbrr), + + eori_l_imm32_ds(0x0a80, 0xfff8, op_imm32, gen_eorl_dt_ds, dbrr), + + eori_l_imm32_ais(0x0a90, 0xfff8, op_imm32, ea_ais32_read, gen_eorl_im_ea), + + eori_l_imm32_aips(0x0a98, 0xfff8, op_imm32, ea_aips32_read, gen_eorl_im_ea), + + eori_l_imm32_pais(0x0aa0, 0xfff8, op_imm32, ea_pais32_read, gen_eorl_im_ea), + + eori_l_imm32_das(0x0aa8, 0xfff8, op_imm32, ea_das32_read, gen_eorl_im_ea), + + eori_l_imm32_dais(0x0ab0, 0xfff8, op_imm32, ea_dais32_read, gen_eorl_im_ea), + + eori_l_imm32_adr16(0x0ab8, 0xffff, op_imm32, ea_adr16s32_read, gen_eorl_im_ea), + + eori_l_imm32_adr32(0x0ab9, 0xffff, op_imm32, ea_adr32s32_read, gen_eorl_im_ea), + + cmpi_b_imm8_ds(0x0c00, 0xfff8, op_imm16, gen_cmpb_dt_ds, dbrr), + + cmpi_b_imm8_ais(0x0c10, 0xfff8, op_imm16, ea_ais8_read, gen_cmpb_im_ea), + + cmpi_b_imm8_aips(0x0c18, 0xfff8, op_imm16, ea_aips8_read, gen_cmpb_im_ea), + + cmpi_b_imm8_pais(0x0c20, 0xfff8, op_imm16, ea_pais8_read, gen_cmpb_im_ea), + + cmpi_b_imm8_das(0x0c28, 0xfff8, op_imm16, ea_das8_read, gen_cmpb_im_ea), + + cmpi_b_imm8_dais(0x0c30, 0xfff8, op_imm16, ea_dais8_read, gen_cmpb_im_ea), + + cmpi_b_imm8_adr16(0x0c38, 0xffff, op_imm16, ea_adr16s8_read, gen_cmpb_im_ea), + + cmpi_b_imm8_adr32(0x0c39, 0xffff, op_imm16, ea_adr32s8_read, gen_cmpb_im_ea), + + cmpi_w_imm16_ds(0x0c40, 0xfff8, op_imm16, gen_cmpw_dt_ds, dbrr), + + cmpi_w_imm16_ais(0x0c50, 0xfff8, op_imm16, ea_ais16_read, gen_cmpw_im_ea), + + cmpi_w_imm16_aips(0x0c58, 0xfff8, op_imm16, ea_aips16_read, gen_cmpw_im_ea), + + cmpi_w_imm16_pais(0x0c60, 0xfff8, op_imm16, ea_pais16_read, gen_cmpw_im_ea), + + cmpi_w_imm16_das(0x0c68, 0xfff8, op_imm16, ea_das16_read, gen_cmpw_im_ea), + + cmpi_w_imm16_dais(0x0c70, 0xfff8, op_imm16, ea_dais16_read, gen_cmpw_im_ea), + + cmpi_w_imm16_adr16(0x0c78, 0xffff, op_imm16, ea_adr16s16_read, gen_cmpw_im_ea), + + cmpi_w_imm16_adr32(0x0c79, 0xffff, op_imm16, ea_adr32s16_read, gen_cmpw_im_ea), + + cmpi_l_imm32_ds(0x0c80, 0xfff8, op_imm32, gen_cmpl_dt_ds, dbrr), + + cmpi_l_imm32_ais(0x0c90, 0xfff8, op_imm32, ea_ais32_read, gen_cmpl_im_ea), + + cmpi_l_imm32_aips(0x0c98, 0xfff8, op_imm32, ea_aips32_read, gen_cmpl_im_ea), + + cmpi_l_imm32_pais(0x0ca0, 0xfff8, op_imm32, ea_pais32_read, gen_cmpl_im_ea), + + cmpi_l_imm32_das(0x0ca8, 0xfff8, op_imm32, ea_das32_read, gen_cmpl_im_ea), + + cmpi_l_imm32_dais(0x0cb0, 0xfff8, op_imm32, ea_dais32_read, gen_cmpl_im_ea), + + cmpi_l_imm32_adr16(0x0cb8, 0xffff, op_imm32, ea_adr16s32_read, gen_cmpl_im_ea), + + cmpi_l_imm32_adr32(0x0cb9, 0xffff, op_imm32, ea_adr32s32_read, gen_cmpl_im_ea), + + move_b_ds_dd(0x1000, 0xf1f8, gen_moveb_ds_dd, dbrr, dbrr), + + move_b_ais_dd(0x1010, 0xf1f8, ea_ais8_read, dbrr, gen_moveb_dt_dd), + + move_b_aips_dd(0x1018, 0xf1f8, ea_aips8_read, dbrr, gen_moveb_dt_dd), + + move_b_pais_dd(0x1020, 0xf1f8, ea_pais8_read, dbrr, gen_moveb_dt_dd), + + move_b_das_dd(0x1028, 0xf1f8, ea_das8_read, dbrr, gen_moveb_dt_dd), + + move_b_dais_dd(0x1030, 0xf1f8, ea_dais8_read, dbrr, gen_moveb_dt_dd), + + move_b_adr16_dd(0x1038, 0xf1ff, ea_adr16s8_read, dbrr, gen_moveb_dt_dd), + + move_b_adr32_dd(0x1039, 0xf1ff, ea_adr32s8_read, dbrr, gen_moveb_dt_dd), + + move_b_dpc_dd(0x103a, 0xf1ff, ea_dpc8_read, dbrr, gen_moveb_dt_dd), + + move_b_dpci_dd(0x103b, 0xf1ff, ea_dpci8_read, dbrr, gen_moveb_dt_dd), + + move_b_imm8_dd(0x103c, 0xf1ff, ea_imm8_read, dbrr, gen_moveb_dt_dd), + + move_b_ds_aid(0x1080, 0xf1f8, ea_aid8, gen_moveb_ds_ea, dbrr), + + move_b_ais_aid(0x1090, 0xf1f8, ea_ais8_read, gen_moveb_dt_ea, ea_aid8), + + move_b_aips_aid(0x1098, 0xf1f8, ea_aips8_read, gen_moveb_dt_ea, ea_aid8), + + move_b_pais_aid(0x10a0, 0xf1f8, ea_pais8_read, gen_moveb_dt_ea, ea_aid8), + + move_b_das_aid(0x10a8, 0xf1f8, ea_das8_read, gen_moveb_dt_ea, ea_aid8), + + move_b_dais_aid(0x10b0, 0xf1f8, ea_dais8_read, gen_moveb_dt_ea, ea_aid8), + + move_b_adr16_aid(0x10b8, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_ea, ea_aid8), + + move_b_adr32_aid(0x10b9, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_ea, ea_aid8), + + move_b_dpc_aid(0x10ba, 0xf1ff, ea_dpc8_read, gen_moveb_dt_ea, ea_aid8), + + move_b_dpci_aid(0x10bb, 0xf1ff, ea_dpci8_read, gen_moveb_dt_ea, ea_aid8), + + move_b_imm8_aid(0x10bc, 0xf1ff, ea_imm8_read, gen_moveb_dt_ea, ea_aid8), + + move_b_ds_aipd(0x10c0, 0xf1f8, ea_aipd8, gen_moveb_ds_ea, dbrr), + + move_b_ais_aipd(0x10d0, 0xf1f8, ea_ais8_read, gen_moveb_dt_ea, ea_aipd8), + + move_b_aips_aipd(0x10d8, 0xf1f8, ea_aips8_read, gen_moveb_dt_ea, ea_aipd8), + + move_b_pais_aipd(0x10e0, 0xf1f8, ea_pais8_read, gen_moveb_dt_ea, ea_aipd8), + + move_b_das_aipd(0x10e8, 0xf1f8, ea_das8_read, gen_moveb_dt_ea, ea_aipd8), + + move_b_dais_aipd(0x10f0, 0xf1f8, ea_dais8_read, gen_moveb_dt_ea, ea_aipd8), + + move_b_adr16_aipd(0x10f8, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_ea, ea_aipd8), + + move_b_adr32_aipd(0x10f9, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_ea, ea_aipd8), + + move_b_dpc_aipd(0x10fa, 0xf1ff, ea_dpc8_read, gen_moveb_dt_ea, ea_aipd8), + + move_b_dpci_aipd(0x10fb, 0xf1ff, ea_dpci8_read, gen_moveb_dt_ea, ea_aipd8), + + move_b_imm8_aipd(0x10fc, 0xf1ff, ea_imm8_read, gen_moveb_dt_ea, ea_aipd8), + + move_b_ds_paid(0x1100, 0xf1f8, ea_paid8, gen_moveb_ds_ea, dbrr), + + move_b_ais_paid(0x1110, 0xf1f8, ea_ais8_read, gen_moveb_dt_ea, ea_paid8), + + move_b_aips_paid(0x1118, 0xf1f8, ea_aips8_read, gen_moveb_dt_ea, ea_paid8), + + move_b_pais_paid(0x1120, 0xf1f8, ea_pais8_read, gen_moveb_dt_ea, ea_paid8), + + move_b_das_paid(0x1128, 0xf1f8, ea_das8_read, gen_moveb_dt_ea, ea_paid8), + + move_b_dais_paid(0x1130, 0xf1f8, ea_dais8_read, gen_moveb_dt_ea, ea_paid8), + + move_b_adr16_paid(0x1138, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_ea, ea_paid8), + + move_b_adr32_paid(0x1139, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_ea, ea_paid8), + + move_b_dpc_paid(0x113a, 0xf1ff, ea_dpc8_read, gen_moveb_dt_ea, ea_paid8), + + move_b_dpci_paid(0x113b, 0xf1ff, ea_dpci8_read, gen_moveb_dt_ea, ea_paid8), + + move_b_imm8_paid(0x113c, 0xf1ff, ea_imm8_read, gen_moveb_dt_ea, ea_paid8), + + move_b_ds_dad(0x1140, 0xf1f8, ea_dad8, gen_moveb_ds_ea, dbrr), + + move_b_ais_dad(0x1150, 0xf1f8, ea_ais8_read, gen_moveb_dt_ea, ea_dad8), + + move_b_aips_dad(0x1158, 0xf1f8, ea_aips8_read, gen_moveb_dt_ea, ea_dad8), + + move_b_pais_dad(0x1160, 0xf1f8, ea_pais8_read, gen_moveb_dt_ea, ea_dad8), + + move_b_das_dad(0x1168, 0xf1f8, ea_das8_read, gen_moveb_dt_ea, ea_dad8), + + move_b_dais_dad(0x1170, 0xf1f8, ea_dais8_read, gen_moveb_dt_ea, ea_dad8), + + move_b_adr16_dad(0x1178, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_ea, ea_dad8), + + move_b_adr32_dad(0x1179, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_ea, ea_dad8), + + move_b_dpc_dad(0x117a, 0xf1ff, ea_dpc8_read, gen_moveb_dt_ea, ea_dad8), + + move_b_dpci_dad(0x117b, 0xf1ff, ea_dpci8_read, gen_moveb_dt_ea, ea_dad8), + + move_b_imm8_dad(0x117c, 0xf1ff, ea_imm8_read, gen_moveb_dt_ea, ea_dad8), + + move_b_ds_daid(0x1180, 0xf1f8, ea_daid8, gen_moveb_ds_ea, dbrr), + + move_b_ais_daid(0x1190, 0xf1f8, ea_ais8_read, gen_moveb_dt_ea, ea_daid8), + + move_b_aips_daid(0x1198, 0xf1f8, ea_aips8_read, gen_moveb_dt_ea, ea_daid8), + + move_b_pais_daid(0x11a0, 0xf1f8, ea_pais8_read, gen_moveb_dt_ea, ea_daid8), + + move_b_das_daid(0x11a8, 0xf1f8, ea_das8_read, gen_moveb_dt_ea, ea_daid8), + + move_b_dais_daid(0x11b0, 0xf1f8, ea_dais8_read, gen_moveb_dt_ea, ea_daid8), + + move_b_adr16_daid(0x11b8, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_ea, ea_daid8), + + move_b_adr32_daid(0x11b9, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_ea, ea_daid8), + + move_b_dpc_daid(0x11ba, 0xf1ff, ea_dpc8_read, gen_moveb_dt_ea, ea_daid8), + + move_b_dpci_daid(0x11bb, 0xf1ff, ea_dpci8_read, gen_moveb_dt_ea, ea_daid8), + + move_b_imm8_daid(0x11bc, 0xf1ff, ea_imm8_read, gen_moveb_dt_ea, ea_daid8), + + move_b_ds_adr16(0x11c0, 0xfff8, ea_adr16d8, gen_moveb_ds_ea, dbrr), + + move_b_ais_adr16(0x11d0, 0xfff8, ea_ais8_read, gen_moveb_dt_ea, ea_adr16d8), + + move_b_aips_adr16(0x11d8, 0xfff8, ea_aips8_read, gen_moveb_dt_ea, ea_adr16d8), + + move_b_pais_adr16(0x11e0, 0xfff8, ea_pais8_read, gen_moveb_dt_ea, ea_adr16d8), + + move_b_das_adr16(0x11e8, 0xfff8, ea_das8_read, gen_moveb_dt_ea, ea_adr16d8), + + move_b_dais_adr16(0x11f0, 0xfff8, ea_dais8_read, gen_moveb_dt_ea, ea_adr16d8), + + move_b_adr16_adr16(0x11f8, 0xffff, ea_adr16s8_read, gen_moveb_dt_ea, ea_adr16d8), + + move_b_adr32_adr16(0x11f9, 0xffff, ea_adr32s8_read, gen_moveb_dt_ea, ea_adr16d8), + + move_b_dpc_adr16(0x11fa, 0xffff, ea_dpc8_read, gen_moveb_dt_ea, ea_adr16d8), + + move_b_dpci_adr16(0x11fb, 0xffff, ea_dpci8_read, gen_moveb_dt_ea, ea_adr16d8), + + move_b_imm8_adr16(0x11fc, 0xffff, ea_imm8_read, gen_moveb_dt_ea, ea_adr16d8), + + move_b_ds_adr32(0x13c0, 0xfff8, ea_adr32d8, gen_moveb_ds_ea, dbrr), + + move_b_ais_adr32(0x13d0, 0xfff8, ea_ais8_read, gen_moveb_dt_ea, ea_adr32d8), + + move_b_aips_adr32(0x13d8, 0xfff8, ea_aips8_read, gen_moveb_dt_ea, ea_adr32d8), + + move_b_pais_adr32(0x13e0, 0xfff8, ea_pais8_read, gen_moveb_dt_ea, ea_adr32d8), + + move_b_das_adr32(0x13e8, 0xfff8, ea_das8_read, gen_moveb_dt_ea, ea_adr32d8), + + move_b_dais_adr32(0x13f0, 0xfff8, ea_dais8_read, gen_moveb_dt_ea, ea_adr32d8), + + move_b_adr16_adr32(0x13f8, 0xffff, ea_adr16s8_read, gen_moveb_dt_ea, ea_adr32d8), + + move_b_adr32_adr32(0x13f9, 0xffff, ea_adr32s8_read, gen_moveb_dt_ea, ea_adr32d8), + + move_b_dpc_adr32(0x13fa, 0xffff, ea_dpc8_read, gen_moveb_dt_ea, ea_adr32d8), + + move_b_dpci_adr32(0x13fb, 0xffff, ea_dpci8_read, gen_moveb_dt_ea, ea_adr32d8), + + move_b_imm8_adr32(0x13fc, 0xffff, ea_imm8_read, gen_moveb_dt_ea, ea_adr32d8), + + move_l_ds_dd(0x2000, 0xf1f8, gen_movel_ds_dd, dbrr, dbrr), + + move_l_as_dd(0x2008, 0xf1f8, gen_movel_as_dd, dbrr, dbrr), + + move_l_ais_dd(0x2010, 0xf1f8, ea_ais32_read, dbrr, gen_movel_dt_dd), + + move_l_aips_dd(0x2018, 0xf1f8, ea_aips32_read, dbrr, gen_movel_dt_dd), + + move_l_pais_dd(0x2020, 0xf1f8, ea_pais32_read, dbrr, gen_movel_dt_dd), + + move_l_das_dd(0x2028, 0xf1f8, ea_das32_read, dbrr, gen_movel_dt_dd), + + move_l_dais_dd(0x2030, 0xf1f8, ea_dais32_read, dbrr, gen_movel_dt_dd), + + move_l_adr16_dd(0x2038, 0xf1ff, ea_adr16s32_read, dbrr, gen_movel_dt_dd), + + move_l_adr32_dd(0x2039, 0xf1ff, ea_adr32s32_read, dbrr, gen_movel_dt_dd), + + move_l_dpc_dd(0x203a, 0xf1ff, ea_dpc32_read, dbrr, gen_movel_dt_dd), + + move_l_dpci_dd(0x203b, 0xf1ff, ea_dpci32_read, dbrr, gen_movel_dt_dd), + + move_l_imm32_dd(0x203c, 0xf1ff, ea_imm32_read, dbrr, gen_movel_dt_dd), + + movea_l_ds_ad(0x2040, 0xf1f8, gen_movel_ds_ad, dbrr, dbrr), + + movea_l_as_ad(0x2048, 0xf1f8, gen_movel_as_ad, dbrr, dbrr), + + movea_l_ais_ad(0x2050, 0xf1f8, ea_ais32_read, dbrr, gen_movel_dt_ad), + + movea_l_aips_ad(0x2058, 0xf1f8, ea_aips32_read, dbrr, gen_movel_dt_ad), + + movea_l_pais_ad(0x2060, 0xf1f8, ea_pais32_read, dbrr, gen_movel_dt_ad), + + movea_l_das_ad(0x2068, 0xf1f8, ea_das32_read, dbrr, gen_movel_dt_ad), + + movea_l_dais_ad(0x2070, 0xf1f8, ea_dais32_read, dbrr, gen_movel_dt_ad), + + movea_l_adr16_ad(0x2078, 0xf1ff, ea_adr16s32_read, dbrr, gen_movel_dt_ad), + + movea_l_adr32_ad(0x2079, 0xf1ff, ea_adr32s32_read, dbrr, gen_movel_dt_ad), + + movea_l_dpc_ad(0x207a, 0xf1ff, ea_dpc32_read, dbrr, gen_movel_dt_ad), + + movea_l_dpci_ad(0x207b, 0xf1ff, ea_dpci32_read, dbrr, gen_movel_dt_ad), + + movea_l_imm32_ad(0x207c, 0xf1ff, ea_imm32_read, dbrr, gen_movel_dt_ad), + + move_l_ds_aid(0x2080, 0xf1f8, ea_aid32, gen_movel_ds_ea, dbrr), + + move_l_as_aid(0x2088, 0xf1f8, ea_aid32, gen_movel_as_ea, dbrr), + + move_l_ais_aid(0x2090, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_aid32), + + move_l_aips_aid(0x2098, 0xf1f8, ea_aips32_read, gen_movel_dt_ea, ea_aid32), + + move_l_pais_aid(0x20a0, 0xf1f8, ea_pais32_read, gen_movel_dt_ea, ea_aid32), + + move_l_das_aid(0x20a8, 0xf1f8, ea_das32_read, gen_movel_dt_ea, ea_aid32), + + move_l_dais_aid(0x20b0, 0xf1f8, ea_dais32_read, gen_movel_dt_ea, ea_aid32), + + move_l_adr16_aid(0x20b8, 0xf1ff, ea_adr16s32_read, gen_movel_dt_ea, ea_aid32), + + move_l_adr32_aid(0x20b9, 0xf1ff, ea_adr32s32_read, gen_movel_dt_ea, ea_aid32), + + move_l_dpc_aid(0x20ba, 0xf1ff, ea_dpc32_read, gen_movel_dt_ea, ea_aid32), + + move_l_dpci_aid(0x20bb, 0xf1ff, ea_dpci32_read, gen_movel_dt_ea, ea_aid32), + + move_l_imm32_aid(0x20bc, 0xf1ff, ea_imm32_read, gen_movel_dt_ea, ea_aid32), + + move_l_ds_aipd(0x20c0, 0xf1f8, ea_aipd32, gen_movel_ds_ea, dbrr), + + move_l_as_aipd(0x20c8, 0xf1f8, ea_aipd32, gen_movel_as_ea, dbrr), + + move_l_ais_aipd(0x20d0, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_aipd32), + + move_l_aips_aipd(0x20d8, 0xf1f8, ea_aips32_read, gen_movel_dt_ea, ea_aipd32), + + move_l_pais_aipd(0x20e0, 0xf1f8, ea_pais32_read, gen_movel_dt_ea, ea_aipd32), + + move_l_das_aipd(0x20e8, 0xf1f8, ea_das32_read, gen_movel_dt_ea, ea_aipd32), + + move_l_dais_aipd(0x20f0, 0xf1f8, ea_dais32_read, gen_movel_dt_ea, ea_aipd32), + + move_l_adr16_aipd(0x20f8, 0xf1ff, ea_adr16s32_read, gen_movel_dt_ea, ea_aipd32), + + move_l_adr32_aipd(0x20f9, 0xf1ff, ea_adr32s32_read, gen_movel_dt_ea, ea_aipd32), + + move_l_dpc_aipd(0x20fa, 0xf1ff, ea_dpc32_read, gen_movel_dt_ea, ea_aipd32), + + move_l_dpci_aipd(0x20fb, 0xf1ff, ea_dpci32_read, gen_movel_dt_ea, ea_aipd32), + + move_l_imm32_aipd(0x20fc, 0xf1ff, ea_imm32_read, gen_movel_dt_ea, ea_aipd32), + + move_l_ds_paid(0x2100, 0xf1f8, ea_paid32, gen_movel_ds_ea, dbrr), + + move_l_as_paid(0x2108, 0xf1f8, ea_paid32, gen_movel_as_ea, dbrr), + + move_l_ais_paid(0x2110, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_paid32), + + move_l_aips_paid(0x2118, 0xf1f8, ea_aips32_read, gen_movel_dt_ea, ea_paid32), + + move_l_pais_paid(0x2120, 0xf1f8, ea_pais32_read, gen_movel_dt_ea, ea_paid32), + + move_l_das_paid(0x2128, 0xf1f8, ea_das32_read, gen_movel_dt_ea, ea_paid32), + + move_l_dais_paid(0x2130, 0xf1f8, ea_dais32_read, gen_movel_dt_ea, ea_paid32), + + move_l_adr16_paid(0x2138, 0xf1ff, ea_adr16s32_read, gen_movel_dt_ea, ea_paid32), + + move_l_adr32_paid(0x2139, 0xf1ff, ea_adr32s32_read, gen_movel_dt_ea, ea_paid32), + + move_l_dpc_paid(0x213a, 0xf1ff, ea_dpc32_read, gen_movel_dt_ea, ea_paid32), + + move_l_dpci_paid(0x213b, 0xf1ff, ea_dpci32_read, gen_movel_dt_ea, ea_paid32), + + move_l_imm32_paid(0x213c, 0xf1ff, ea_imm32_read, gen_movel_dt_ea, ea_paid32), + + move_l_ds_dad(0x2140, 0xf1f8, ea_dad32, gen_movel_ds_ea, dbrr), + + move_l_as_dad(0x2148, 0xf1f8, ea_dad32, gen_movel_as_ea, dbrr), + + move_l_ais_dad(0x2150, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_dad32), + + move_l_aips_dad(0x2158, 0xf1f8, ea_aips32_read, gen_movel_dt_ea, ea_dad32), + + move_l_pais_dad(0x2160, 0xf1f8, ea_pais32_read, gen_movel_dt_ea, ea_dad32), + + move_l_das_dad(0x2168, 0xf1f8, ea_das32_read, gen_movel_dt_ea, ea_dad32), + + move_l_dais_dad(0x2170, 0xf1f8, ea_dais32_read, gen_movel_dt_ea, ea_dad32), + + move_l_adr16_dad(0x2178, 0xf1ff, ea_adr16s32_read, gen_movel_dt_ea, ea_dad32), + + move_l_adr32_dad(0x2179, 0xf1ff, ea_adr32s32_read, gen_movel_dt_ea, ea_dad32), + + move_l_dpc_dad(0x217a, 0xf1ff, ea_dpc32_read, gen_movel_dt_ea, ea_dad32), + + move_l_dpci_dad(0x217b, 0xf1ff, ea_dpci32_read, gen_movel_dt_ea, ea_dad32), + + move_l_imm32_dad(0x217c, 0xf1ff, ea_imm32_read, gen_movel_dt_ea, ea_dad32), + + move_l_ds_daid(0x2180, 0xf1f8, ea_daid32, gen_movel_ds_ea, dbrr), + + move_l_as_daid(0x2188, 0xf1f8, ea_daid32, gen_movel_as_ea, dbrr), + + move_l_ais_daid(0x2190, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_daid32), + + move_l_aips_daid(0x2198, 0xf1f8, ea_aips32_read, gen_movel_dt_ea, ea_daid32), + + move_l_pais_daid(0x21a0, 0xf1f8, ea_pais32_read, gen_movel_dt_ea, ea_daid32), + + move_l_das_daid(0x21a8, 0xf1f8, ea_das32_read, gen_movel_dt_ea, ea_daid32), + + move_l_dais_daid(0x21b0, 0xf1f8, ea_dais32_read, gen_movel_dt_ea, ea_daid32), + + move_l_adr16_daid(0x21b8, 0xf1ff, ea_adr16s32_read, gen_movel_dt_ea, ea_daid32), + + move_l_adr32_daid(0x21b9, 0xf1ff, ea_adr32s32_read, gen_movel_dt_ea, ea_daid32), + + move_l_dpc_daid(0x21ba, 0xf1ff, ea_dpc32_read, gen_movel_dt_ea, ea_daid32), + + move_l_dpci_daid(0x21bb, 0xf1ff, ea_dpci32_read, gen_movel_dt_ea, ea_daid32), + + move_l_imm32_daid(0x21bc, 0xf1ff, ea_imm32_read, gen_movel_dt_ea, ea_daid32), + + move_l_ds_adr16(0x21c0, 0xfff8, ea_adr16d32, gen_movel_ds_ea, dbrr), + + move_l_as_adr16(0x21c8, 0xfff8, ea_adr16d32, gen_movel_as_ea, dbrr), + + move_l_ais_adr16(0x21d0, 0xfff8, ea_ais32_read, gen_movel_dt_ea, ea_adr16d32), + + move_l_aips_adr16(0x21d8, 0xfff8, ea_aips32_read, gen_movel_dt_ea, ea_adr16d32), + + move_l_pais_adr16(0x21e0, 0xfff8, ea_pais32_read, gen_movel_dt_ea, ea_adr16d32), + + move_l_das_adr16(0x21e8, 0xfff8, ea_das32_read, gen_movel_dt_ea, ea_adr16d32), + + move_l_dais_adr16(0x21f0, 0xfff8, ea_dais32_read, gen_movel_dt_ea, ea_adr16d32), + + move_l_adr16_adr16(0x21f8, 0xffff, ea_adr16s32_read, gen_movel_dt_ea, ea_adr16d32), + + move_l_adr32_adr16(0x21f9, 0xffff, ea_adr32s32_read, gen_movel_dt_ea, ea_adr16d32), + + move_l_dpc_adr16(0x21fa, 0xffff, ea_dpc32_read, gen_movel_dt_ea, ea_adr16d32), + + move_l_dpci_adr16(0x21fb, 0xffff, ea_dpci32_read, gen_movel_dt_ea, ea_adr16d32), + + move_l_imm32_adr16(0x21fc, 0xffff, ea_imm32_read, gen_movel_dt_ea, ea_adr16d32), + + move_l_ds_adr32(0x23c0, 0xfff8, ea_adr32d32, gen_movel_ds_ea, dbrr), + + move_l_as_adr32(0x23c8, 0xfff8, ea_adr32d32, gen_movel_as_ea, dbrr), + + move_l_ais_adr32(0x23d0, 0xfff8, ea_ais32_read, gen_movel_dt_ea, ea_adr32d32), + + move_l_aips_adr32(0x23d8, 0xfff8, ea_aips32_read, gen_movel_dt_ea, ea_adr32d32), + + move_l_pais_adr32(0x23e0, 0xfff8, ea_pais32_read, gen_movel_dt_ea, ea_adr32d32), + + move_l_das_adr32(0x23e8, 0xfff8, ea_das32_read, gen_movel_dt_ea, ea_adr32d32), + + move_l_dais_adr32(0x23f0, 0xfff8, ea_dais32_read, gen_movel_dt_ea, ea_adr32d32), + + move_l_adr16_adr32(0x23f8, 0xffff, ea_adr16s32_read, gen_movel_dt_ea, ea_adr32d32), + + move_l_adr32_adr32(0x23f9, 0xffff, ea_adr32s32_read, gen_movel_dt_ea, ea_adr32d32), + + move_l_dpc_adr32(0x23fa, 0xffff, ea_dpc32_read, gen_movel_dt_ea, ea_adr32d32), + + move_l_dpci_adr32(0x23fb, 0xffff, ea_dpci32_read, gen_movel_dt_ea, ea_adr32d32), + + move_l_imm32_adr32(0x23fc, 0xffff, ea_imm32_read, gen_movel_dt_ea, ea_adr32d32), + + move_w_ds_dd(0x3000, 0xf1f8, gen_movew_ds_dd, dbrr, dbrr), + + move_w_as_dd(0x3008, 0xf1f8, gen_movew_as_dd, dbrr, dbrr), + + move_w_ais_dd(0x3010, 0xf1f8, ea_ais16_read, dbrr, gen_movew_dt_dd), + + move_w_aips_dd(0x3018, 0xf1f8, ea_aips16_read, dbrr, gen_movew_dt_dd), + + move_w_pais_dd(0x3020, 0xf1f8, ea_pais16_read, dbrr, gen_movew_dt_dd), + + move_w_das_dd(0x3028, 0xf1f8, ea_das16_read, dbrr, gen_movew_dt_dd), + + move_w_dais_dd(0x3030, 0xf1f8, ea_dais16_read, dbrr, gen_movew_dt_dd), + + move_w_adr16_dd(0x3038, 0xf1ff, ea_adr16s16_read, dbrr, gen_movew_dt_dd), + + move_w_adr32_dd(0x3039, 0xf1ff, ea_adr32s16_read, dbrr, gen_movew_dt_dd), + + move_w_dpc_dd(0x303a, 0xf1ff, ea_dpc16_read, dbrr, gen_movew_dt_dd), + + move_w_dpci_dd(0x303b, 0xf1ff, ea_dpci16_read, dbrr, gen_movew_dt_dd), + + move_w_imm16_dd(0x303c, 0xf1ff, ea_imm16_read, dbrr, gen_movew_dt_dd), + + movea_w_ds_ad(0x3040, 0xf1f8, gen_movew_ds_ad, dbrr, dbrr), + + movea_w_as_ad(0x3048, 0xf1f8, gen_movew_as_ad, dbrr, dbrr), + + movea_w_ais_ad(0x3050, 0xf1f8, ea_ais16_read, dbrr, gen_movew_dt_ad), + + movea_w_aips_ad(0x3058, 0xf1f8, ea_aips16_read, dbrr, gen_movew_dt_ad), + + movea_w_pais_ad(0x3060, 0xf1f8, ea_pais16_read, dbrr, gen_movew_dt_ad), + + movea_w_das_ad(0x3068, 0xf1f8, ea_das16_read, dbrr, gen_movew_dt_ad), + + movea_w_dais_ad(0x3070, 0xf1f8, ea_dais16_read, dbrr, gen_movew_dt_ad), + + movea_w_adr16_ad(0x3078, 0xf1ff, ea_adr16s16_read, dbrr, gen_movew_dt_ad), + + movea_w_adr32_ad(0x3079, 0xf1ff, ea_adr32s16_read, dbrr, gen_movew_dt_ad), + + movea_w_dpc_ad(0x307a, 0xf1ff, ea_dpc16_read, dbrr, gen_movew_dt_ad), + + movea_w_dpci_ad(0x307b, 0xf1ff, ea_dpci16_read, dbrr, gen_movew_dt_ad), + + movea_w_imm16_ad(0x307c, 0xf1ff, ea_imm16_read, dbrr, gen_movew_dt_ad), + + move_w_ds_aid(0x3080, 0xf1f8, ea_aid16, gen_movew_ds_ea, dbrr), + + move_w_as_aid(0x3088, 0xf1f8, ea_aid16, gen_movew_as_ea, dbrr), + + move_w_ais_aid(0x3090, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_aid16), + + move_w_aips_aid(0x3098, 0xf1f8, ea_aips16_read, gen_movew_dt_ea, ea_aid16), + + move_w_pais_aid(0x30a0, 0xf1f8, ea_pais16_read, gen_movew_dt_ea, ea_aid16), + + move_w_das_aid(0x30a8, 0xf1f8, ea_das16_read, gen_movew_dt_ea, ea_aid16), + + move_w_dais_aid(0x30b0, 0xf1f8, ea_dais16_read, gen_movew_dt_ea, ea_aid16), + + move_w_adr16_aid(0x30b8, 0xf1ff, ea_adr16s16_read, gen_movew_dt_ea, ea_aid16), + + move_w_adr32_aid(0x30b9, 0xf1ff, ea_adr32s16_read, gen_movew_dt_ea, ea_aid16), + + move_w_dpc_aid(0x30ba, 0xf1ff, ea_dpc16_read, gen_movew_dt_ea, ea_aid16), + + move_w_dpci_aid(0x30bb, 0xf1ff, ea_dpci16_read, gen_movew_dt_ea, ea_aid16), + + move_w_imm16_aid(0x30bc, 0xf1ff, ea_imm16_read, gen_movew_dt_ea, ea_aid16), + + move_w_ds_aipd(0x30c0, 0xf1f8, ea_aipd16, gen_movew_ds_ea, dbrr), + + move_w_as_aipd(0x30c8, 0xf1f8, ea_aipd16, gen_movew_as_ea, dbrr), + + move_w_ais_aipd(0x30d0, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_aipd16), + + move_w_aips_aipd(0x30d8, 0xf1f8, ea_aips16_read, gen_movew_dt_ea, ea_aipd16), + + move_w_pais_aipd(0x30e0, 0xf1f8, ea_pais16_read, gen_movew_dt_ea, ea_aipd16), + + move_w_das_aipd(0x30e8, 0xf1f8, ea_das16_read, gen_movew_dt_ea, ea_aipd16), + + move_w_dais_aipd(0x30f0, 0xf1f8, ea_dais16_read, gen_movew_dt_ea, ea_aipd16), + + move_w_adr16_aipd(0x30f8, 0xf1ff, ea_adr16s16_read, gen_movew_dt_ea, ea_aipd16), + + move_w_adr32_aipd(0x30f9, 0xf1ff, ea_adr32s16_read, gen_movew_dt_ea, ea_aipd16), + + move_w_dpc_aipd(0x30fa, 0xf1ff, ea_dpc16_read, gen_movew_dt_ea, ea_aipd16), + + move_w_dpci_aipd(0x30fb, 0xf1ff, ea_dpci16_read, gen_movew_dt_ea, ea_aipd16), + + move_w_imm16_aipd(0x30fc, 0xf1ff, ea_imm16_read, gen_movew_dt_ea, ea_aipd16), + + move_w_ds_paid(0x3100, 0xf1f8, ea_paid16, gen_movew_ds_ea, dbrr), + + move_w_as_paid(0x3108, 0xf1f8, ea_paid16, gen_movew_as_ea, dbrr), + + move_w_ais_paid(0x3110, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_paid16), + + move_w_aips_paid(0x3118, 0xf1f8, ea_aips16_read, gen_movew_dt_ea, ea_paid16), + + move_w_pais_paid(0x3120, 0xf1f8, ea_pais16_read, gen_movew_dt_ea, ea_paid16), + + move_w_das_paid(0x3128, 0xf1f8, ea_das16_read, gen_movew_dt_ea, ea_paid16), + + move_w_dais_paid(0x3130, 0xf1f8, ea_dais16_read, gen_movew_dt_ea, ea_paid16), + + move_w_adr16_paid(0x3138, 0xf1ff, ea_adr16s16_read, gen_movew_dt_ea, ea_paid16), + + move_w_adr32_paid(0x3139, 0xf1ff, ea_adr32s16_read, gen_movew_dt_ea, ea_paid16), + + move_w_dpc_paid(0x313a, 0xf1ff, ea_dpc16_read, gen_movew_dt_ea, ea_paid16), + + move_w_dpci_paid(0x313b, 0xf1ff, ea_dpci16_read, gen_movew_dt_ea, ea_paid16), + + move_w_imm16_paid(0x313c, 0xf1ff, ea_imm16_read, gen_movew_dt_ea, ea_paid16), + + move_w_ds_dad(0x3140, 0xf1f8, ea_dad16, gen_movew_ds_ea, dbrr), + + move_w_as_dad(0x3148, 0xf1f8, ea_dad16, gen_movew_as_ea, dbrr), + + move_w_ais_dad(0x3150, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_dad16), + + move_w_aips_dad(0x3158, 0xf1f8, ea_aips16_read, gen_movew_dt_ea, ea_dad16), + + move_w_pais_dad(0x3160, 0xf1f8, ea_pais16_read, gen_movew_dt_ea, ea_dad16), + + move_w_das_dad(0x3168, 0xf1f8, ea_das16_read, gen_movew_dt_ea, ea_dad16), + + move_w_dais_dad(0x3170, 0xf1f8, ea_dais16_read, gen_movew_dt_ea, ea_dad16), + + move_w_adr16_dad(0x3178, 0xf1ff, ea_adr16s16_read, gen_movew_dt_ea, ea_dad16), + + move_w_adr32_dad(0x3179, 0xf1ff, ea_adr32s16_read, gen_movew_dt_ea, ea_dad16), + + move_w_dpc_dad(0x317a, 0xf1ff, ea_dpc16_read, gen_movew_dt_ea, ea_dad16), + + move_w_dpci_dad(0x317b, 0xf1ff, ea_dpci16_read, gen_movew_dt_ea, ea_dad16), + + move_w_imm16_dad(0x317c, 0xf1ff, ea_imm16_read, gen_movew_dt_ea, ea_dad16), + + move_w_ds_daid(0x3180, 0xf1f8, ea_daid16, gen_movew_ds_ea, dbrr), + + move_w_as_daid(0x3188, 0xf1f8, ea_daid16, gen_movew_as_ea, dbrr), + + move_w_ais_daid(0x3190, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_daid16), + + move_w_aips_daid(0x3198, 0xf1f8, ea_aips16_read, gen_movew_dt_ea, ea_daid16), + + move_w_pais_daid(0x31a0, 0xf1f8, ea_pais16_read, gen_movew_dt_ea, ea_daid16), + + move_w_das_daid(0x31a8, 0xf1f8, ea_das16_read, gen_movew_dt_ea, ea_daid16), + + move_w_dais_daid(0x31b0, 0xf1f8, ea_dais16_read, gen_movew_dt_ea, ea_daid16), + + move_w_adr16_daid(0x31b8, 0xf1ff, ea_adr16s16_read, gen_movew_dt_ea, ea_daid16), + + move_w_adr32_daid(0x31b9, 0xf1ff, ea_adr32s16_read, gen_movew_dt_ea, ea_daid16), + + move_w_dpc_daid(0x31ba, 0xf1ff, ea_dpc16_read, gen_movew_dt_ea, ea_daid16), + + move_w_dpci_daid(0x31bb, 0xf1ff, ea_dpci16_read, gen_movew_dt_ea, ea_daid16), + + move_w_imm16_daid(0x31bc, 0xf1ff, ea_imm16_read, gen_movew_dt_ea, ea_daid16), + + move_w_ds_adr16(0x31c0, 0xfff8, ea_adr16d16, gen_movew_ds_ea, dbrr), + + move_w_as_adr16(0x31c8, 0xfff8, ea_adr16d16, gen_movew_as_ea, dbrr), + + move_w_ais_adr16(0x31d0, 0xfff8, ea_ais16_read, gen_movew_dt_ea, ea_adr16d16), + + move_w_aips_adr16(0x31d8, 0xfff8, ea_aips16_read, gen_movew_dt_ea, ea_adr16d16), + + move_w_pais_adr16(0x31e0, 0xfff8, ea_pais16_read, gen_movew_dt_ea, ea_adr16d16), + + move_w_das_adr16(0x31e8, 0xfff8, ea_das16_read, gen_movew_dt_ea, ea_adr16d16), + + move_w_dais_adr16(0x31f0, 0xfff8, ea_dais16_read, gen_movew_dt_ea, ea_adr16d16), + + move_w_adr16_adr16(0x31f8, 0xffff, ea_adr16s16_read, gen_movew_dt_ea, ea_adr16d16), + + move_w_adr32_adr16(0x31f9, 0xffff, ea_adr32s16_read, gen_movew_dt_ea, ea_adr16d16), + + move_w_dpc_adr16(0x31fa, 0xffff, ea_dpc16_read, gen_movew_dt_ea, ea_adr16d16), + + move_w_dpci_adr16(0x31fb, 0xffff, ea_dpci16_read, gen_movew_dt_ea, ea_adr16d16), + + move_w_imm16_adr16(0x31fc, 0xffff, ea_imm16_read, gen_movew_dt_ea, ea_adr16d16), + + move_w_ds_adr32(0x33c0, 0xfff8, ea_adr32d16, gen_movew_ds_ea, dbrr), + + move_w_as_adr32(0x33c8, 0xfff8, ea_adr32d16, gen_movew_as_ea, dbrr), + + move_w_ais_adr32(0x33d0, 0xfff8, ea_ais16_read, gen_movew_dt_ea, ea_adr32d16), + + move_w_aips_adr32(0x33d8, 0xfff8, ea_aips16_read, gen_movew_dt_ea, ea_adr32d16), + + move_w_pais_adr32(0x33e0, 0xfff8, ea_pais16_read, gen_movew_dt_ea, ea_adr32d16), + + move_w_das_adr32(0x33e8, 0xfff8, ea_das16_read, gen_movew_dt_ea, ea_adr32d16), + + move_w_dais_adr32(0x33f0, 0xfff8, ea_dais16_read, gen_movew_dt_ea, ea_adr32d16), + + move_w_adr16_adr32(0x33f8, 0xffff, ea_adr16s16_read, gen_movew_dt_ea, ea_adr32d16), + + move_w_adr32_adr32(0x33f9, 0xffff, ea_adr32s16_read, gen_movew_dt_ea, ea_adr32d16), + + move_w_dpc_adr32(0x33fa, 0xffff, ea_dpc16_read, gen_movew_dt_ea, ea_adr32d16), + + move_w_dpci_adr32(0x33fb, 0xffff, ea_dpci16_read, gen_movew_dt_ea, ea_adr32d16), + + move_w_imm16_adr32(0x33fc, 0xffff, ea_imm16_read, gen_movew_dt_ea, ea_adr32d16), + + negx_b_ds(0x4000, 0xfff8, gen_negxb_ds, dbrr, dbrr), + + negx_b_ais(0x4010, 0xfff8, ea_ais8_read, dbrr, gen_negxb_ea), + + negx_b_aips(0x4018, 0xfff8, ea_aips8_read, dbrr, gen_negxb_ea), + + negx_b_pais(0x4020, 0xfff8, ea_pais8_read, dbrr, gen_negxb_ea), + + negx_b_das(0x4028, 0xfff8, ea_das8_read, dbrr, gen_negxb_ea), + + negx_b_dais(0x4030, 0xfff8, ea_dais8_read, dbrr, gen_negxb_ea), + + negx_b_adr16(0x4038, 0xffff, ea_adr16s8_read, dbrr, gen_negxb_ea), + + negx_b_adr32(0x4039, 0xffff, ea_adr32s8_read, dbrr, gen_negxb_ea), + + negx_w_ds(0x4040, 0xfff8, gen_negxw_ds, dbrr, dbrr), + + negx_w_ais(0x4050, 0xfff8, ea_ais16_read, dbrr, gen_negxw_ea), + + negx_w_aips(0x4058, 0xfff8, ea_aips16_read, dbrr, gen_negxw_ea), + + negx_w_pais(0x4060, 0xfff8, ea_pais16_read, dbrr, gen_negxw_ea), + + negx_w_das(0x4068, 0xfff8, ea_das16_read, dbrr, gen_negxw_ea), + + negx_w_dais(0x4070, 0xfff8, ea_dais16_read, dbrr, gen_negxw_ea), + + negx_w_adr16(0x4078, 0xffff, ea_adr16s16_read, dbrr, gen_negxw_ea), + + negx_w_adr32(0x4079, 0xffff, ea_adr32s16_read, dbrr, gen_negxw_ea), + + negx_l_ds(0x4080, 0xfff8, gen_negxl_ds, dbrr, dbrr), + + negx_l_ais(0x4090, 0xfff8, ea_ais32_read, dbrr, gen_negxl_ea), + + negx_l_aips(0x4098, 0xfff8, ea_aips32_read, dbrr, gen_negxl_ea), + + negx_l_pais(0x40a0, 0xfff8, ea_pais32_read, dbrr, gen_negxl_ea), + + negx_l_das(0x40a8, 0xfff8, ea_das32_read, dbrr, gen_negxl_ea), + + negx_l_dais(0x40b0, 0xfff8, ea_dais32_read, dbrr, gen_negxl_ea), + + negx_l_adr16(0x40b8, 0xffff, ea_adr16s32_read, dbrr, gen_negxl_ea), + + negx_l_adr32(0x40b9, 0xffff, ea_adr32s32_read, dbrr, gen_negxl_ea), + + move_sr_ds(0x40c0, 0xfff8, gen_movew_sr_ds, dbrr, dbrr), + + move_sr_ais(0x40d0, 0xfff8, ea_ais16, dbrr, gen_movew_sr_ea), + + move_sr_aips(0x40d8, 0xfff8, ea_aips16, dbrr, gen_movew_sr_ea), + + move_sr_pais(0x40e0, 0xfff8, ea_pais16, dbrr, gen_movew_sr_ea), + + move_sr_das(0x40e8, 0xfff8, ea_das16, dbrr, gen_movew_sr_ea), + + move_sr_dais(0x40f0, 0xfff8, ea_dais16, dbrr, gen_movew_sr_ea), + + move_sr_adr16(0x40f8, 0xffff, ea_adr16s16, dbrr, gen_movew_sr_ea), + + move_sr_adr32(0x40f9, 0xffff, ea_adr32s16, dbrr, gen_movew_sr_ea), + + chk_w_ds_dd(0x4180, 0xf1f8, op_chk_w_ds, dbrr, dbrr), + + chk_w_ais_dd(0x4190, 0xf1f8, ea_ais16_read, dbrr, op_chk_w_ea), + + chk_w_aips_dd(0x4198, 0xf1f8, ea_aips16_read, dbrr, op_chk_w_ea), + + chk_w_pais_dd(0x41a0, 0xf1f8, ea_pais16_read, dbrr, op_chk_w_ea), + + chk_w_das_dd(0x41a8, 0xf1f8, ea_das16_read, dbrr, op_chk_w_ea), + + chk_w_dais_dd(0x41b0, 0xf1f8, ea_dais16_read, dbrr, op_chk_w_ea), + + chk_w_adr16_dd(0x41b8, 0xf1ff, ea_adr16s16_read, dbrr, op_chk_w_ea), + + chk_w_adr32_dd(0x41b9, 0xf1ff, ea_adr32s16_read, dbrr, op_chk_w_ea), + + chk_w_dpc_dd(0x41ba, 0xf1ff, ea_dpc16_read, dbrr, op_chk_w_ea), + + chk_w_dpci_dd(0x41bb, 0xf1ff, ea_dpci16_read, dbrr, op_chk_w_ea), + + chk_w_imm16_dd(0x41bc, 0xf1ff, ea_imm16_read, dbrr, op_chk_w_ea), + + lea_ais_ad(0x41d0, 0xf1f8, ea_ais16, dbrr, op_lea_ea_ad), + + lea_das_ad(0x41e8, 0xf1f8, ea_das16, dbrr, op_lea_ea_ad), + + lea_dais_ad(0x41f0, 0xf1f8, ea_dais16, dbrr, op_lea_ea_ad), + + lea_adr16_ad(0x41f8, 0xf1ff, ea_adr16s16, dbrr, op_lea_ea_ad), + + lea_adr32_ad(0x41f9, 0xf1ff, ea_adr32s16, dbrr, op_lea_ea_ad), + + lea_dpc_ad(0x41fa, 0xf1ff, ea_dpc16, dbrr, op_lea_ea_ad), + + lea_dpci_ad(0x41fb, 0xf1ff, ea_dpci16, dbrr, op_lea_ea_ad), + + clr_b_ds(0x4200, 0xfff8, op_clrb_ds, dbrr, dbrr), + + clr_b_ais(0x4210, 0xfff8, ea_ais8, dbrr, op_clrb_ea), + + clr_b_aips(0x4218, 0xfff8, ea_aips8, dbrr, op_clrb_ea), + + clr_b_pais(0x4220, 0xfff8, ea_pais8, dbrr, op_clrb_ea), + + clr_b_das(0x4228, 0xfff8, ea_das8, dbrr, op_clrb_ea), + + clr_b_dais(0x4230, 0xfff8, ea_dais8, dbrr, op_clrb_ea), + + clr_b_adr16(0x4238, 0xffff, ea_adr16s8, dbrr, op_clrb_ea), + + clr_b_adr32(0x4239, 0xffff, ea_adr32s8, dbrr, op_clrb_ea), + + clr_w_ds(0x4240, 0xfff8, op_clrw_ds, dbrr, dbrr), + + clr_w_ais(0x4250, 0xfff8, ea_ais16, dbrr, op_clrw_ea), + + clr_w_aips(0x4258, 0xfff8, ea_aips16, dbrr, op_clrw_ea), + + clr_w_pais(0x4260, 0xfff8, ea_pais16, dbrr, op_clrw_ea), + + clr_w_das(0x4268, 0xfff8, ea_das16, dbrr, op_clrw_ea), + + clr_w_dais(0x4270, 0xfff8, ea_dais16, dbrr, op_clrw_ea), + + clr_w_adr16(0x4278, 0xffff, ea_adr16s16, dbrr, op_clrw_ea), + + clr_w_adr32(0x4279, 0xffff, ea_adr32s16, dbrr, op_clrw_ea), + + clr_l_ds(0x4280, 0xfff8, op_clrl_ds, dbrr, dbrr), + + clr_l_ais(0x4290, 0xfff8, ea_ais32, dbrr, op_clrl_ea), + + clr_l_aips(0x4298, 0xfff8, ea_aips32, dbrr, op_clrl_ea), + + clr_l_pais(0x42a0, 0xfff8, ea_pais32, dbrr, op_clrl_ea), + + clr_l_das(0x42a8, 0xfff8, ea_das32, dbrr, op_clrl_ea), + + clr_l_dais(0x42b0, 0xfff8, ea_dais32, dbrr, op_clrl_ea), + + clr_l_adr16(0x42b8, 0xffff, ea_adr16s32, dbrr, op_clrl_ea), + + clr_l_adr32(0x42b9, 0xffff, ea_adr32s32, dbrr, op_clrl_ea), + + move_ccr_ds(0x42c0, 0xfff8, gen_movew_ccr_ds, dbrr, dbrr), + + move_ccr_ais(0x42d0, 0xfff8, ea_ais16, dbrr, gen_movew_ccr_ea), + + move_ccr_aips(0x42d8, 0xfff8, ea_aips16, dbrr, gen_movew_ccr_ea), + + move_ccr_pais(0x42e0, 0xfff8, ea_pais16, dbrr, gen_movew_ccr_ea), + + move_ccr_das(0x42e8, 0xfff8, ea_das16, dbrr, gen_movew_ccr_ea), + + move_ccr_dais(0x42f0, 0xfff8, ea_dais16, dbrr, gen_movew_ccr_ea), + + move_ccr_adr16(0x42f8, 0xffff, ea_adr16s16, dbrr, gen_movew_ccr_ea), + + move_ccr_adr32(0x42f9, 0xffff, ea_adr32s16, dbrr, gen_movew_ccr_ea), + + neg_b_ds(0x4400, 0xfff8, gen_negb_ds, dbrr, dbrr), + + neg_b_ais(0x4410, 0xfff8, ea_ais8_read, dbrr, gen_negb_ea), + + neg_b_aips(0x4418, 0xfff8, ea_aips8_read, dbrr, gen_negb_ea), + + neg_b_pais(0x4420, 0xfff8, ea_pais8_read, dbrr, gen_negb_ea), + + neg_b_das(0x4428, 0xfff8, ea_das8_read, dbrr, gen_negb_ea), + + neg_b_dais(0x4430, 0xfff8, ea_dais8_read, dbrr, gen_negb_ea), + + neg_b_adr16(0x4438, 0xffff, ea_adr16s8_read, dbrr, gen_negb_ea), + + neg_b_adr32(0x4439, 0xffff, ea_adr32s8_read, dbrr, gen_negb_ea), + + neg_w_ds(0x4440, 0xfff8, gen_negw_ds, dbrr, dbrr), + + neg_w_ais(0x4450, 0xfff8, ea_ais16_read, dbrr, gen_negl_ea), + + neg_w_aips(0x4458, 0xfff8, ea_aips16_read, dbrr, gen_negl_ea), + + neg_w_pais(0x4460, 0xfff8, ea_pais16_read, dbrr, gen_negl_ea), + + neg_w_das(0x4468, 0xfff8, ea_das16_read, dbrr, gen_negl_ea), + + neg_w_dais(0x4470, 0xfff8, ea_dais16_read, dbrr, gen_negl_ea), + + neg_w_adr16(0x4478, 0xffff, ea_adr16s16_read, dbrr, gen_negl_ea), + + neg_w_adr32(0x4479, 0xffff, ea_adr32s16_read, dbrr, gen_negl_ea), + + neg_l_ds(0x4480, 0xfff8, gen_negl_ds, dbrr, dbrr), + + neg_l_ais(0x4490, 0xfff8, ea_ais32_read, dbrr, gen_negl_ea), + + neg_l_aips(0x4498, 0xfff8, ea_aips32_read, dbrr, gen_negl_ea), + + neg_l_pais(0x44a0, 0xfff8, ea_pais32_read, dbrr, gen_negl_ea), + + neg_l_das(0x44a8, 0xfff8, ea_das32_read, dbrr, gen_negl_ea), + + neg_l_dais(0x44b0, 0xfff8, ea_dais32_read, dbrr, gen_negl_ea), + + neg_l_adr16(0x44b8, 0xffff, ea_adr16s32_read, dbrr, gen_negl_ea), + + neg_l_adr32(0x44b9, 0xffff, ea_adr32s32_read, dbrr, gen_negl_ea), + + move_ds_ccr(0x44c0, 0xfff8, gen_movew_ds_ccr, dbrr, dbrr), + + move_ais_ccr(0x44d0, 0xfff8, ea_ais16_read, dbrr, gen_movew_dt_ccr), + + move_aips_ccr(0x44d8, 0xfff8, ea_aips16_read, dbrr, gen_movew_dt_ccr), + + move_pais_ccr(0x44e0, 0xfff8, ea_pais16_read, dbrr, gen_movew_dt_ccr), + + move_das_ccr(0x44e8, 0xfff8, ea_das16_read, dbrr, gen_movew_dt_ccr), + + move_dais_ccr(0x44f0, 0xfff8, ea_dais16_read, dbrr, gen_movew_dt_ccr), + + move_adr16_ccr(0x44f8, 0xffff, ea_adr16s16_read, dbrr, gen_movew_dt_ccr), + + move_adr32_ccr(0x44f9, 0xffff, ea_adr32s16_read, dbrr, gen_movew_dt_ccr), + + move_dpc_ccr(0x44fa, 0xffff, ea_dpc16_read, dbrr, gen_movew_dt_ccr), + + move_dpci_ccr(0x44fb, 0xffff, ea_dpci16_read, dbrr, gen_movew_dt_ccr), + + move_imm16_ccr(0x44fc, 0xffff, ea_imm16_read, dbrr, gen_movew_dt_ccr), + + not_b_ds(0x4600, 0xfff8, gen_notb_ds, dbrr, dbrr), + + not_b_ais(0x4610, 0xfff8, ea_ais8_read, dbrr, gen_notb_ea), + + not_b_aips(0x4618, 0xfff8, ea_aips8_read, dbrr, gen_notb_ea), + + not_b_pais(0x4620, 0xfff8, ea_pais8_read, dbrr, gen_notb_ea), + + not_b_das(0x4628, 0xfff8, ea_das8_read, dbrr, gen_notb_ea), + + not_b_dais(0x4630, 0xfff8, ea_dais8_read, dbrr, gen_notb_ea), + + not_b_adr16(0x4638, 0xffff, ea_adr16s8_read, dbrr, gen_notb_ea), + + not_b_adr32(0x4639, 0xffff, ea_adr32s8_read, dbrr, gen_notb_ea), + + not_w_ds(0x4640, 0xfff8, gen_notw_ds, dbrr, dbrr), + + not_w_ais(0x4650, 0xfff8, ea_ais16_read, dbrr, gen_notw_ea), + + not_w_aips(0x4658, 0xfff8, ea_aips16_read, dbrr, gen_notw_ea), + + not_w_pais(0x4660, 0xfff8, ea_pais16_read, dbrr, gen_notw_ea), + + not_w_das(0x4668, 0xfff8, ea_das16_read, dbrr, gen_notw_ea), + + not_w_dais(0x4670, 0xfff8, ea_dais16_read, dbrr, gen_notw_ea), + + not_w_adr16(0x4678, 0xffff, ea_adr16s16_read, dbrr, gen_notw_ea), + + not_w_adr32(0x4679, 0xffff, ea_adr32s16_read, dbrr, gen_notw_ea), + + not_l_ds(0x4680, 0xfff8, gen_notl_ds, dbrr, dbrr), + + not_l_ais(0x4690, 0xfff8, ea_ais32_read, dbrr, gen_notl_ea), + + not_l_aips(0x4698, 0xfff8, ea_aips32_read, dbrr, gen_notl_ea), + + not_l_pais(0x46a0, 0xfff8, ea_pais32_read, dbrr, gen_notl_ea), + + not_l_das(0x46a8, 0xfff8, ea_das32_read, dbrr, gen_notl_ea), + + not_l_dais(0x46b0, 0xfff8, ea_dais32_read, dbrr, gen_notl_ea), + + not_l_adr16(0x46b8, 0xffff, ea_adr16s32_read, dbrr, gen_notl_ea), + + not_l_adr32(0x46b9, 0xffff, ea_adr32s32_read, dbrr, gen_notl_ea), + + move_ds_sr(0x46c0, 0xfff8, gen_movew_ds_sr, dbrr, dbrr), + + move_ais_sr(0x46d0, 0xfff8, ea_ais16_read, dbrr, gen_movew_dt_sr), + + move_aips_sr(0x46d8, 0xfff8, ea_aips16_read, dbrr, gen_movew_dt_sr), + + move_pais_sr(0x46e0, 0xfff8, ea_pais16_read, dbrr, gen_movew_dt_sr), + + move_das_sr(0x46e8, 0xfff8, ea_das16_read, dbrr, gen_movew_dt_sr), + + move_dais_sr(0x46f0, 0xfff8, ea_dais16_read, dbrr, gen_movew_dt_sr), + + move_adr16_sr(0x46f8, 0xffff, ea_adr16s16_read, dbrr, gen_movew_dt_sr), + + move_adr32_sr(0x46f9, 0xffff, ea_adr32s16_read, dbrr, gen_movew_dt_sr), + + move_dpc_sr(0x46fa, 0xffff, ea_dpc16_read, dbrr, gen_movew_dt_sr), + + move_dpci_sr(0x46fb, 0xffff, ea_dpci16_read, dbrr, gen_movew_dt_sr), + + move_imm16_sr(0x46fc, 0xffff, ea_imm16_read, dbrr, gen_movew_dt_sr), + + nbcd_b_ds(0x4800, 0xfff8, gen_nbcdb_ds, dbrr, dbrr), + + link_as_imm32(0x4808, 0xfff8, op_imm32, op_link_as_imm32, dbrr), + + nbcd_b_ais(0x4810, 0xfff8, ea_ais8_read, dbrr, gen_nbcdb_ea), + + nbcd_b_aips(0x4818, 0xfff8, ea_aips8_read, dbrr, gen_nbcdb_ea), + + nbcd_b_pais(0x4820, 0xfff8, ea_pais8_read, dbrr, gen_nbcdb_ea), + + nbcd_b_das(0x4828, 0xfff8, ea_das8_read, dbrr, gen_nbcdb_ea), + + nbcd_b_dais(0x4830, 0xfff8, ea_dais8_read, dbrr, gen_nbcdb_ea), + + nbcd_b_adr16(0x4838, 0xffff, ea_adr16s8_read, dbrr, gen_nbcdb_ea), + + nbcd_b_adr32(0x4839, 0xffff, ea_adr32s8_read, dbrr, gen_nbcdb_ea), + + swap_ds(0x4840, 0xfff8, op_swap_ds, dbrr, dbrr), + + bkpt(0x4848, 0xfff8, op_bkpt, dbrr, dbrr), + + pea_ais(0x4850, 0xfff8, ea_ais16, dbrr, op_pea), + + pea_das(0x4868, 0xfff8, ea_das16, dbrr, op_pea), + + pea_dais(0x4870, 0xfff8, ea_dais16, dbrr, op_pea), + + pea_adr16(0x4878, 0xffff, ea_adr16s16, dbrr, op_pea), + + pea_adr32(0x4879, 0xffff, ea_adr32s16, dbrr, op_pea), + + pea_dpc(0x487a, 0xffff, ea_dpc16, dbrr, op_pea), + + pea_dpci(0x487b, 0xffff, ea_dpci16, dbrr, op_pea), + + ext_w_ds(0x4880, 0xfff8, op_extw_ds, dbrr, dbrr), + + ext_l_ds(0x48c0, 0xfff8, op_extl_ds, dbrr, dbrr), + + extb_l_ds(0x49c0, 0xfff8, op_extbl_ds, dbrr, dbrr), + + tst_b_ds(0x4a00, 0xfff8, gen_tstb_ds, dbrr, dbrr), + + tst_b_ais(0x4a10, 0xfff8, ea_ais8_read, dbrr, gen_tstb_ea), + + tst_b_aips(0x4a18, 0xfff8, ea_aips8_read, dbrr, gen_tstb_ea), + + tst_b_pais(0x4a20, 0xfff8, ea_pais8_read, dbrr, gen_tstb_ea), + + tst_b_das(0x4a28, 0xfff8, ea_das8_read, dbrr, gen_tstb_ea), + + tst_b_dais(0x4a30, 0xfff8, ea_dais8_read, dbrr, gen_tstb_ea), + + tst_b_adr16(0x4a38, 0xffff, ea_adr16s8_read, dbrr, gen_tstb_ea), + + tst_b_adr32(0x4a39, 0xffff, ea_adr32s8_read, dbrr, gen_tstb_ea), + + tst_w_ds(0x4a40, 0xfff8, gen_tstw_ds, dbrr, dbrr), + + tst_w_ais(0x4a50, 0xfff8, ea_ais16_read, dbrr, gen_tstw_ea), + + tst_w_aips(0x4a58, 0xfff8, ea_aips16_read, dbrr, gen_tstw_ea), + + tst_w_pais(0x4a60, 0xfff8, ea_pais16_read, dbrr, gen_tstw_ea), + + tst_w_das(0x4a68, 0xfff8, ea_das16_read, dbrr, gen_tstw_ea), + + tst_w_dais(0x4a70, 0xfff8, ea_dais16_read, dbrr, gen_tstw_ea), + + tst_w_adr16(0x4a78, 0xffff, ea_adr16s16_read, dbrr, gen_tstw_ea), + + tst_w_adr32(0x4a79, 0xffff, ea_adr32s16_read, dbrr, gen_tstw_ea), + + tst_l_ds(0x4a80, 0xfff8, gen_tstl_ds, dbrr, dbrr), + + tst_l_ais(0x4a90, 0xfff8, ea_ais32_read, dbrr, gen_tstl_ea), + + tst_l_aips(0x4a98, 0xfff8, ea_aips32_read, dbrr, gen_tstl_ea), + + tst_l_pais(0x4aa0, 0xfff8, ea_pais32_read, dbrr, gen_tstl_ea), + + tst_l_das(0x4aa8, 0xfff8, ea_das32_read, dbrr, gen_tstl_ea), + + tst_l_dais(0x4ab0, 0xfff8, ea_dais32_read, dbrr, gen_tstl_ea), + + tst_l_adr16(0x4ab8, 0xffff, ea_adr16s32_read, dbrr, gen_tstl_ea), + + tst_l_adr32(0x4ab9, 0xffff, ea_adr32s32_read, dbrr, gen_tstl_ea), + + illegal(0x4afc, 0xffff, op_illegal, dbrr, dbrr), + + trap_imm4(0x4e40, 0xfff0, op_trap, dbrr, dbrr), + + link_as_imm16(0x4e50, 0xfff8, op_imm16, op_link_as_imm16, dbrr), + + unlk_as(0x4e58, 0xfff8, op_unlk_as, dbrr, dbrr), + + move_as_usp(0x4e60, 0xfff8, op_move_as_usp, dbrr, dbrr), + + move_usp_as(0x4e68, 0xfff8, op_move_usp_as, dbrr, dbrr), + + reset(0x4e70, 0xffff, op_reset, dbrr, dbrr), + + nop(0x4e71, 0xffff, op_nop, dbrr, dbrr), + + stop_i16u(0x4e72, 0xffff, op_imm16, op_stop, dbrr), + + rte(0x4e73, 0xffff, op_rte, dbrr, dbrr), + + rts(0x4e75, 0xffff, op_rts, dbrr, dbrr), + + trapv(0x4e76, 0xffff, op_trapv, dbrr, dbrr), + + rtr(0x4e77, 0xffff, op_rtr, dbrr, dbrr), + + movec_cr_rz(0x4e7a, 0xffff, op_movec_cr_rz, dbrr, dbrr), + + movec_rz_cr(0x4e7b, 0xffff, op_movec_rz_cr, dbrr, dbrr), + + jsr_ais(0x4e90, 0xfff8, ea_ais16, dbrr, op_jsr), + + jsr_das(0x4ea8, 0xfff8, ea_das16, dbrr, op_jsr), + + jsr_dais(0x4eb0, 0xfff8, ea_dais16, dbrr, op_jsr), + + jsr_adr16(0x4eb8, 0xffff, ea_adr16s16, dbrr, op_jsr), + + jsr_adr32(0x4eb9, 0xffff, ea_adr32s16, dbrr, op_jsr), + + jsr_dpc(0x4eba, 0xffff, ea_dpc16, dbrr, op_jsr), + + jsr_dpci(0x4ebb, 0xffff, ea_dpci16, dbrr, op_jsr), + + jmp_ais(0x4ed0, 0xfff8, ea_ais16, dbrr, op_jmp), + + jmp_das(0x4ee8, 0xfff8, ea_das16, dbrr, op_jmp), + + jmp_dais(0x4ef0, 0xfff8, ea_dais16, dbrr, op_jmp), + + jmp_adr16(0x4ef8, 0xffff, ea_adr16s16, dbrr, op_jmp), + + jmp_adr32(0x4ef9, 0xffff, ea_adr32s16, dbrr, op_jmp), + + jmp_dpc(0x4efa, 0xffff, ea_dpc16, dbrr, op_jmp), + + jmp_dpci(0x4efb, 0xffff, ea_dpci16, dbrr, op_jmp), + + addq_b_imm3_ds(0x5000, 0xf1f8, gen_addb_ir_ds, dbrr, dbrr), + + addq_b_imm3_ais(0x5010, 0xf1f8, ea_ais8_read, dbrr, gen_addb_ir_ea), + + addq_b_imm3_aips(0x5018, 0xf1f8, ea_aips8_read, dbrr, gen_addb_ir_ea), + + addq_b_imm3_pais(0x5020, 0xf1f8, ea_pais8_read, dbrr, gen_addb_ir_ea), + + addq_b_imm3_das(0x5028, 0xf1f8, ea_das8_read, dbrr, gen_addb_ir_ea), + + addq_b_imm3_dais(0x5030, 0xf1f8, ea_dais8_read, dbrr, gen_addb_ir_ea), + + addq_b_imm3_adr16(0x5038, 0xf1ff, ea_adr16s8_read, dbrr, gen_addb_ir_ea), + + addq_b_imm3_adr32(0x5039, 0xf1ff, ea_adr32s8_read, dbrr, gen_addb_ir_ea), + + addq_w_imm3_ds(0x5040, 0xf1f8, gen_addw_ir_ds, dbrr, dbrr), + + addq_w_imm3_as(0x5048, 0xf1f8, gen_addw_ir_as, dbrr, dbrr), + + addq_w_imm3_ais(0x5050, 0xf1f8, ea_ais16_read, dbrr, gen_addw_ir_ea), + + addq_w_imm3_aips(0x5058, 0xf1f8, ea_aips16_read, dbrr, gen_addw_ir_ea), + + addq_w_imm3_pais(0x5060, 0xf1f8, ea_pais16_read, dbrr, gen_addw_ir_ea), + + addq_w_imm3_das(0x5068, 0xf1f8, ea_das16_read, dbrr, gen_addw_ir_ea), + + addq_w_imm3_dais(0x5070, 0xf1f8, ea_dais16_read, dbrr, gen_addw_ir_ea), + + addq_w_imm3_adr16(0x5078, 0xf1ff, ea_adr16s16_read, dbrr, gen_addw_ir_ea), + + addq_w_imm3_adr32(0x5079, 0xf1ff, ea_adr32s16_read, dbrr, gen_addw_ir_ea), + + addq_l_imm3_ds(0x5080, 0xf1f8, gen_addl_ir_ds, dbrr, dbrr), + + addq_l_imm3_as(0x5088, 0xf1f8, gen_addl_ir_as, dbrr, dbrr), + + addq_l_imm3_ais(0x5090, 0xf1f8, ea_ais32_read, dbrr, gen_addl_ir_ea), + + addq_l_imm3_aips(0x5098, 0xf1f8, ea_aips32_read, dbrr, gen_addl_ir_ea), + + addq_l_imm3_pais(0x50a0, 0xf1f8, ea_pais32_read, dbrr, gen_addl_ir_ea), + + addq_l_imm3_das(0x50a8, 0xf1f8, ea_das32_read, dbrr, gen_addl_ir_ea), + + addq_l_imm3_dais(0x50b0, 0xf1f8, ea_dais32_read, dbrr, gen_addl_ir_ea), + + addq_l_imm3_adr16(0x50b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_addl_ir_ea), + + addq_l_imm3_adr32(0x50b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_addl_ir_ea), + + scc_b_ds(0x50c0, 0xf0f8, op_scc_b_ds, dbrr, dbrr), + + dbcc(0x50c8, 0xf0f8, op_dbcc, dbrr, dbrr), + + scc_b_ais(0x50d0, 0xf0f8, ea_ais8, dbrr, op_scc_b_ea), + + scc_b_aips(0x50d8, 0xf0f8, ea_aips8, dbrr, op_scc_b_ea), + + scc_b_pais(0x50e0, 0xf0f8, ea_pais8, dbrr, op_scc_b_ea), + + scc_b_das(0x50e8, 0xf0f8, ea_das8, dbrr, op_scc_b_ea), + + scc_b_dais(0x50f0, 0xf0f8, ea_dais8, dbrr, op_scc_b_ea), + + scc_b_adr16(0x50f8, 0xf0ff, ea_adr16s8, dbrr, op_scc_b_ea), + + scc_b_adr32(0x50f9, 0xf0ff, ea_adr32s8, dbrr, op_scc_b_ea), + + trapcc16(0x50fa, 0xf0ff, op_trapcc16, dbrr, dbrr), + + trapcc32(0x50fb, 0xf0ff, op_trapcc32, dbrr, dbrr), + + trapcc(0x50fc, 0xf0ff, op_trapcc, dbrr, dbrr), + + subq_b_imm3_ds(0x5100, 0xf1f8, gen_subb_ir_ds, dbrr, dbrr), + + subq_b_imm3_ais(0x5110, 0xf1f8, ea_ais8_read, dbrr, gen_subb_ir_ea), + + subq_b_imm3_aips(0x5118, 0xf1f8, ea_aips8_read, dbrr, gen_subb_ir_ea), + + subq_b_imm3_pais(0x5120, 0xf1f8, ea_pais8_read, dbrr, gen_subb_ir_ea), + + subq_b_imm3_das(0x5128, 0xf1f8, ea_das8_read, dbrr, gen_subb_ir_ea), + + subq_b_imm3_dais(0x5130, 0xf1f8, ea_dais8_read, dbrr, gen_subb_ir_ea), + + subq_b_imm3_adr16(0x5138, 0xf1ff, ea_adr16s8_read, dbrr, gen_subb_ir_ea), + + subq_b_imm3_adr32(0x5139, 0xf1ff, ea_adr32s8_read, dbrr, gen_subb_ir_ea), + + subq_w_imm3_ds(0x5140, 0xf1f8, gen_subw_ir_ds, dbrr, dbrr), + + subq_w_imm3_as(0x5148, 0xf1f8, gen_subw_ir_as, dbrr, dbrr), + + subq_w_imm3_ais(0x5150, 0xf1f8, ea_ais16_read, dbrr, gen_subw_ir_ea), + + subq_w_imm3_aips(0x5158, 0xf1f8, ea_aips16_read, dbrr, gen_subw_ir_ea), + + subq_w_imm3_pais(0x5160, 0xf1f8, ea_pais16_read, dbrr, gen_subw_ir_ea), + + subq_w_imm3_das(0x5168, 0xf1f8, ea_das16_read, dbrr, gen_subw_ir_ea), + + subq_w_imm3_dais(0x5170, 0xf1f8, ea_dais16_read, dbrr, gen_subw_ir_ea), + + subq_w_imm3_adr16(0x5178, 0xf1ff, ea_adr16s16_read, dbrr, gen_subw_ir_ea), + + subq_w_imm3_adr32(0x5179, 0xf1ff, ea_adr32s16_read, dbrr, gen_subw_ir_ea), + + subq_l_imm3_ds(0x5180, 0xf1f8, gen_subl_ir_ds, dbrr, dbrr), + + subq_l_imm3_as(0x5188, 0xf1f8, gen_subl_ir_as, dbrr, dbrr), + + subq_l_imm3_ais(0x5190, 0xf1f8, ea_ais32_read, dbrr, gen_subl_ir_ea), + + subq_l_imm3_aips(0x5198, 0xf1f8, ea_aips32_read, dbrr, gen_subl_ir_ea), + + subq_l_imm3_pais(0x51a0, 0xf1f8, ea_pais32_read, dbrr, gen_subl_ir_ea), + + subq_l_imm3_das(0x51a8, 0xf1f8, ea_das32_read, dbrr, gen_subl_ir_ea), + + subq_l_imm3_dais(0x51b0, 0xf1f8, ea_dais32_read, dbrr, gen_subl_ir_ea), + + subq_l_imm3_adr16(0x51b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_subl_ir_ea), + + subq_l_imm3_adr32(0x51b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_subl_ir_ea), + + bra_rel16(0x6000, 0xffff, op_imm16, op_bra16, dbrr), + + bcc_rel16(0x6000, 0xf0ff, op_imm16, op_bcc16, dbrr), + + bra_rel8(0x6000, 0xff00, op_bra8, dbrr, dbrr), + + bcc_rel8(0x6000, 0xf000, op_bcc8, dbrr, dbrr), + + bra_rel32(0x60ff, 0xffff, op_imm32, op_bra32, dbrr), + + bcc_rel32(0x60ff, 0xf0ff, op_imm32, op_bcc32, dbrr), + + bsr_rel16(0x6100, 0xffff, op_imm16, op_bsr16, dbrr), + + bsr_rel8(0x6100, 0xff00, op_bsr8, dbrr, dbrr), + + bsr_rel32(0x61ff, 0xffff, op_imm32, op_bsr32, dbrr), + + moveq_imm8o_dd(0x7000, 0xf100, gen_movel_im_dd, dbrr, dbrr), + + or_b_ds_dd(0x8000, 0xf1f8, gen_orb_ds_dd, dbrr, dbrr), + + or_b_ais_dd(0x8010, 0xf1f8, ea_ais8_read, dbrr, gen_orb_dt_dd), + + or_b_aips_dd(0x8018, 0xf1f8, ea_aips8_read, dbrr, gen_orb_dt_dd), + + or_b_pais_dd(0x8020, 0xf1f8, ea_pais8_read, dbrr, gen_orb_dt_dd), + + or_b_das_dd(0x8028, 0xf1f8, ea_das8_read, dbrr, gen_orb_dt_dd), + + or_b_dais_dd(0x8030, 0xf1f8, ea_dais8_read, dbrr, gen_orb_dt_dd), + + or_b_adr16_dd(0x8038, 0xf1ff, ea_adr16s8_read, dbrr, gen_orb_dt_dd), + + or_b_adr32_dd(0x8039, 0xf1ff, ea_adr32s8_read, dbrr, gen_orb_dt_dd), + + or_b_dpc_dd(0x803a, 0xf1ff, ea_dpc8_read, dbrr, gen_orb_dt_dd), + + or_b_dpci_dd(0x803b, 0xf1ff, ea_dpci8_read, dbrr, gen_orb_dt_dd), + + or_b_imm8_dd(0x803c, 0xf1ff, ea_imm8_read, dbrr, gen_orb_dt_dd), + + or_w_ds_dd(0x8040, 0xf1f8, gen_orw_ds_dd, dbrr, dbrr), + + or_w_ais_dd(0x8050, 0xf1f8, ea_ais16_read, dbrr, gen_orw_dt_dd), + + or_w_aips_dd(0x8058, 0xf1f8, ea_aips16_read, dbrr, gen_orw_dt_dd), + + or_w_pais_dd(0x8060, 0xf1f8, ea_pais16_read, dbrr, gen_orw_dt_dd), + + or_w_das_dd(0x8068, 0xf1f8, ea_das16_read, dbrr, gen_orw_dt_dd), + + or_w_dais_dd(0x8070, 0xf1f8, ea_dais16_read, dbrr, gen_orw_dt_dd), + + or_w_adr16_dd(0x8078, 0xf1ff, ea_adr16s16_read, dbrr, gen_orw_dt_dd), + + or_w_adr32_dd(0x8079, 0xf1ff, ea_adr32s16_read, dbrr, gen_orw_dt_dd), + + or_w_dpc_dd(0x807a, 0xf1ff, ea_dpc16_read, dbrr, gen_orw_dt_dd), + + or_w_dpci_dd(0x807b, 0xf1ff, ea_dpci16_read, dbrr, gen_orw_dt_dd), + + or_w_imm16_dd(0x807c, 0xf1ff, ea_imm16_read, dbrr, gen_orw_dt_dd), + + or_l_ds_dd(0x8080, 0xf1f8, gen_orl_ds_dd, dbrr, dbrr), + + or_l_ais_dd(0x8090, 0xf1f8, ea_ais32_read, dbrr, gen_orl_dt_dd), + + or_l_aips_dd(0x8098, 0xf1f8, ea_aips32_read, dbrr, gen_orl_dt_dd), + + or_l_pais_dd(0x80a0, 0xf1f8, ea_pais32_read, dbrr, gen_orl_dt_dd), + + or_l_das_dd(0x80a8, 0xf1f8, ea_das32_read, dbrr, gen_orl_dt_dd), + + or_l_dais_dd(0x80b0, 0xf1f8, ea_dais32_read, dbrr, gen_orl_dt_dd), + + or_l_adr16_dd(0x80b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_orl_dt_dd), + + or_l_adr32_dd(0x80b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_orl_dt_dd), + + or_l_dpc_dd(0x80ba, 0xf1ff, ea_dpc32_read, dbrr, gen_orl_dt_dd), + + or_l_dpci_dd(0x80bb, 0xf1ff, ea_dpci32_read, dbrr, gen_orl_dt_dd), + + or_l_imm32_dd(0x80bc, 0xf1ff, ea_imm32_read, dbrr, gen_orl_dt_dd), + + sbcd_ds_dd(0x8100, 0xf1f8, gen_sbcdb_ds_dd, dbrr, dbrr), + + sbcd_pais_paid(0x8108, 0xf1f8, ea_pais8_read, gen_sbcdb_im_ea, ea_paid8_read), + + or_b_dd_ais(0x8110, 0xf1f8, ea_ais8_read, dbrr, gen_orb_dd_ea), + + or_b_dd_aips(0x8118, 0xf1f8, ea_aips8_read, dbrr, gen_orb_dd_ea), + + or_b_dd_pais(0x8120, 0xf1f8, ea_pais8_read, dbrr, gen_orb_dd_ea), + + or_b_dd_das(0x8128, 0xf1f8, ea_das8_read, dbrr, gen_orb_dd_ea), + + or_b_dd_dais(0x8130, 0xf1f8, ea_dais8_read, dbrr, gen_orb_dd_ea), + + or_b_dd_adr16(0x8138, 0xf1ff, ea_adr16s8_read, dbrr, gen_orb_dd_ea), + + or_b_dd_adr32(0x8139, 0xf1ff, ea_adr32s8_read, dbrr, gen_orb_dd_ea), + + or_w_dd_ais(0x8150, 0xf1f8, ea_ais16_read, dbrr, gen_orw_dd_ea), + + or_w_dd_aips(0x8158, 0xf1f8, ea_aips16_read, dbrr, gen_orw_dd_ea), + + or_w_dd_pais(0x8160, 0xf1f8, ea_pais16_read, dbrr, gen_orw_dd_ea), + + or_w_dd_das(0x8168, 0xf1f8, ea_das16_read, dbrr, gen_orw_dd_ea), + + or_w_dd_dais(0x8170, 0xf1f8, ea_dais16_read, dbrr, gen_orw_dd_ea), + + or_w_dd_adr16(0x8178, 0xf1ff, ea_adr16s16_read, dbrr, gen_orw_dd_ea), + + or_w_dd_adr32(0x8179, 0xf1ff, ea_adr32s16_read, dbrr, gen_orw_dd_ea), + + or_l_dd_ais(0x8190, 0xf1f8, ea_ais32_read, dbrr, gen_orl_dd_ea), + + or_l_dd_aips(0x8198, 0xf1f8, ea_aips32_read, dbrr, gen_orl_dd_ea), + + or_l_dd_pais(0x81a0, 0xf1f8, ea_pais32_read, dbrr, gen_orl_dd_ea), + + or_l_dd_das(0x81a8, 0xf1f8, ea_das32_read, dbrr, gen_orl_dd_ea), + + or_l_dd_dais(0x81b0, 0xf1f8, ea_dais32_read, dbrr, gen_orl_dd_ea), + + or_l_dd_adr16(0x81b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_orl_dd_ea), + + or_l_dd_adr32(0x81b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_orl_dd_ea), + + sub_b_ds_dd(0x9000, 0xf1f8, gen_subb_ds_dd, dbrr, dbrr), + + sub_b_ais_dd(0x9010, 0xf1f8, ea_ais8_read, dbrr, gen_subb_dt_dd), + + sub_b_aips_dd(0x9018, 0xf1f8, ea_aips8_read, dbrr, gen_subb_dt_dd), + + sub_b_pais_dd(0x9020, 0xf1f8, ea_pais8_read, dbrr, gen_subb_dt_dd), + + sub_b_das_dd(0x9028, 0xf1f8, ea_das8_read, dbrr, gen_subb_dt_dd), + + sub_b_dais_dd(0x9030, 0xf1f8, ea_dais8_read, dbrr, gen_subb_dt_dd), + + sub_b_adr16_dd(0x9038, 0xf1ff, ea_adr16s8_read, dbrr, gen_subb_dt_dd), + + sub_b_adr32_dd(0x9039, 0xf1ff, ea_adr32s8_read, dbrr, gen_subb_dt_dd), + + sub_b_dpc_dd(0x903a, 0xf1ff, ea_dpc8_read, dbrr, gen_subb_dt_dd), + + sub_b_dpci_dd(0x903b, 0xf1ff, ea_dpci8_read, dbrr, gen_subb_dt_dd), + + sub_b_imm8_dd(0x903c, 0xf1ff, ea_imm8_read, dbrr, gen_subb_dt_dd), + + sub_w_ds_dd(0x9040, 0xf1f8, gen_subw_ds_dd, dbrr, dbrr), + + sub_w_as_dd(0x9048, 0xf1f8, gen_subw_as_dd, dbrr, dbrr), + + sub_w_ais_dd(0x9050, 0xf1f8, ea_ais16_read, dbrr, gen_subw_dt_dd), + + sub_w_aips_dd(0x9058, 0xf1f8, ea_aips16_read, dbrr, gen_subw_dt_dd), + + sub_w_pais_dd(0x9060, 0xf1f8, ea_pais16_read, dbrr, gen_subw_dt_dd), + + sub_w_das_dd(0x9068, 0xf1f8, ea_das16_read, dbrr, gen_subw_dt_dd), + + sub_w_dais_dd(0x9070, 0xf1f8, ea_dais16_read, dbrr, gen_subw_dt_dd), + + sub_w_adr16_dd(0x9078, 0xf1ff, ea_adr16s16_read, dbrr, gen_subw_dt_dd), + + sub_w_adr32_dd(0x9079, 0xf1ff, ea_adr32s16_read, dbrr, gen_subw_dt_dd), + + sub_w_dpc_dd(0x907a, 0xf1ff, ea_dpc16_read, dbrr, gen_subw_dt_dd), + + sub_w_dpci_dd(0x907b, 0xf1ff, ea_dpci16_read, dbrr, gen_subw_dt_dd), + + sub_w_imm16_dd(0x907c, 0xf1ff, ea_imm16_read, dbrr, gen_subw_dt_dd), + + sub_l_ds_dd(0x9080, 0xf1f8, gen_subl_ds_dd, dbrr, dbrr), + + sub_l_as_dd(0x9088, 0xf1f8, gen_subl_as_dd, dbrr, dbrr), + + sub_l_ais_dd(0x9090, 0xf1f8, ea_ais32_read, dbrr, gen_subl_dt_dd), + + sub_l_aips_dd(0x9098, 0xf1f8, ea_aips32_read, dbrr, gen_subl_dt_dd), + + sub_l_pais_dd(0x90a0, 0xf1f8, ea_pais32_read, dbrr, gen_subl_dt_dd), + + sub_l_das_dd(0x90a8, 0xf1f8, ea_das32_read, dbrr, gen_subl_dt_dd), + + sub_l_dais_dd(0x90b0, 0xf1f8, ea_dais32_read, dbrr, gen_subl_dt_dd), + + sub_l_adr16_dd(0x90b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_subl_dt_dd), + + sub_l_adr32_dd(0x90b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_subl_dt_dd), + + sub_l_dpc_dd(0x90ba, 0xf1ff, ea_dpc32_read, dbrr, gen_subl_dt_dd), + + sub_l_dpci_dd(0x90bb, 0xf1ff, ea_dpci32_read, dbrr, gen_subl_dt_dd), + + sub_l_imm32_dd(0x90bc, 0xf1ff, ea_imm32_read, dbrr, gen_subl_dt_dd), + + suba_w_ds_ad(0x90c0, 0xf1f8, gen_subw_ds_ad, dbrr, dbrr), + + suba_w_as_ad(0x90c8, 0xf1f8, gen_subw_as_ad, dbrr, dbrr), + + suba_w_ais_ad(0x90d0, 0xf1f8, ea_ais16_read, dbrr, gen_subw_dt_ad), + + suba_w_aips_ad(0x90d8, 0xf1f8, ea_aips16_read, dbrr, gen_subw_dt_ad), + + suba_w_pais_ad(0x90e0, 0xf1f8, ea_pais16_read, dbrr, gen_subw_dt_ad), + + suba_w_das_ad(0x90e8, 0xf1f8, ea_das16_read, dbrr, gen_subw_dt_ad), + + suba_w_dais_ad(0x90f0, 0xf1f8, ea_dais16_read, dbrr, gen_subw_dt_ad), + + suba_w_adr16_ad(0x90f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_subw_dt_ad), + + suba_w_adr32_ad(0x90f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_subw_dt_ad), + + suba_w_dpc_ad(0x90fa, 0xf1ff, ea_dpc16_read, dbrr, gen_subw_dt_ad), + + suba_w_dpci_ad(0x90fb, 0xf1ff, ea_dpci16_read, dbrr, gen_subw_dt_ad), + + suba_w_imm16_ad(0x90fc, 0xf1ff, ea_imm16_read, dbrr, gen_subw_dt_ad), + + subx_b_ds_dd(0x9100, 0xf1f8, gen_subxb_ds_dd, dbrr, dbrr), + + subx_b_pais_paid(0x9108, 0xf1f8, ea_pais8_read, gen_subxb_im_ea, ea_paid8_read), + + sub_b_dd_ais(0x9110, 0xf1f8, ea_ais8_read, dbrr, gen_subb_dd_ea), + + sub_b_dd_aips(0x9118, 0xf1f8, ea_aips8_read, dbrr, gen_subb_dd_ea), + + sub_b_dd_pais(0x9120, 0xf1f8, ea_pais8_read, dbrr, gen_subb_dd_ea), + + sub_b_dd_das(0x9128, 0xf1f8, ea_das8_read, dbrr, gen_subb_dd_ea), + + sub_b_dd_dais(0x9130, 0xf1f8, ea_dais8_read, dbrr, gen_subb_dd_ea), + + sub_b_dd_adr16(0x9138, 0xf1ff, ea_adr16s8_read, dbrr, gen_subb_dd_ea), + + sub_b_dd_adr32(0x9139, 0xf1ff, ea_adr32s8_read, dbrr, gen_subb_dd_ea), + + subx_w_ds_dd(0x9140, 0xf1f8, gen_subxw_ds_dd, dbrr, dbrr), + + subx_w_pais_paid(0x9148, 0xf1f8, ea_pais16_read, gen_subxw_im_ea, ea_paid16_read), + + sub_w_dd_ais(0x9150, 0xf1f8, ea_ais16_read, dbrr, gen_subw_dd_ea), + + sub_w_dd_aips(0x9158, 0xf1f8, ea_aips16_read, dbrr, gen_subw_dd_ea), + + sub_w_dd_pais(0x9160, 0xf1f8, ea_pais16_read, dbrr, gen_subw_dd_ea), + + sub_w_dd_das(0x9168, 0xf1f8, ea_das16_read, dbrr, gen_subw_dd_ea), + + sub_w_dd_dais(0x9170, 0xf1f8, ea_dais16_read, dbrr, gen_subw_dd_ea), + + sub_w_dd_adr16(0x9178, 0xf1ff, ea_adr16s16_read, dbrr, gen_subw_dd_ea), + + sub_w_dd_adr32(0x9179, 0xf1ff, ea_adr32s16_read, dbrr, gen_subw_dd_ea), + + subx_l_ds_dd(0x9180, 0xf1f8, gen_subxl_ds_dd, dbrr, dbrr), + + subx_l_pais_paid(0x9188, 0xf1f8, ea_pais32_read, gen_subxl_im_ea, ea_paid32_read), + + sub_l_dd_ais(0x9190, 0xf1f8, ea_ais32_read, dbrr, gen_subl_dd_ea), + + sub_l_dd_aips(0x9198, 0xf1f8, ea_aips32_read, dbrr, gen_subl_dd_ea), + + sub_l_dd_pais(0x91a0, 0xf1f8, ea_pais32_read, dbrr, gen_subl_dd_ea), + + sub_l_dd_das(0x91a8, 0xf1f8, ea_das32_read, dbrr, gen_subl_dd_ea), + + sub_l_dd_dais(0x91b0, 0xf1f8, ea_dais32_read, dbrr, gen_subl_dd_ea), + + sub_l_dd_adr16(0x91b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_subl_dd_ea), + + sub_l_dd_adr32(0x91b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_subl_dd_ea), + + suba_l_ds_ad(0x91c0, 0xf1f8, gen_subl_ds_ad, dbrr, dbrr), + + suba_l_as_ad(0x91c8, 0xf1f8, gen_subl_as_ad, dbrr, dbrr), + + suba_l_ais_ad(0x91d0, 0xf1f8, ea_ais32_read, dbrr, gen_subl_dt_ad), + + suba_l_aips_ad(0x91d8, 0xf1f8, ea_aips32_read, dbrr, gen_subl_dt_ad), + + suba_l_pais_ad(0x91e0, 0xf1f8, ea_pais32_read, dbrr, gen_subl_dt_ad), + + suba_l_das_ad(0x91e8, 0xf1f8, ea_das32_read, dbrr, gen_subl_dt_ad), + + suba_l_dais_ad(0x91f0, 0xf1f8, ea_dais32_read, dbrr, gen_subl_dt_ad), + + suba_l_adr16_ad(0x91f8, 0xf1ff, ea_adr16s32_read, dbrr, gen_subl_dt_ad), + + suba_l_adr32_ad(0x91f9, 0xf1ff, ea_adr32s32_read, dbrr, gen_subl_dt_ad), + + suba_l_dpc_ad(0x91fa, 0xf1ff, ea_dpc32_read, dbrr, gen_subl_dt_ad), + + suba_l_dpci_ad(0x91fb, 0xf1ff, ea_dpci32_read, dbrr, gen_subl_dt_ad), + + suba_l_imm32_ad(0x91fc, 0xf1ff, ea_imm32_read, dbrr, gen_subl_dt_ad), + + linea_imm12(0xa000, 0xf000, op_linea, dbrr, dbrr), + + cmp_b_ds_dd(0xb000, 0xf1f8, gen_cmpb_ds_dd, dbrr, dbrr), + + cmp_b_ais_dd(0xb010, 0xf1f8, ea_ais8_read, dbrr, gen_cmpb_dt_dd), + + cmp_b_aips_dd(0xb018, 0xf1f8, ea_aips8_read, dbrr, gen_cmpb_dt_dd), + + cmp_b_pais_dd(0xb020, 0xf1f8, ea_pais8_read, dbrr, gen_cmpb_dt_dd), + + cmp_b_das_dd(0xb028, 0xf1f8, ea_das8_read, dbrr, gen_cmpb_dt_dd), + + cmp_b_dais_dd(0xb030, 0xf1f8, ea_dais8_read, dbrr, gen_cmpb_dt_dd), + + cmp_b_adr16_dd(0xb038, 0xf1ff, ea_adr16s8_read, dbrr, gen_cmpb_dt_dd), + + cmp_b_adr32_dd(0xb039, 0xf1ff, ea_adr32s8_read, dbrr, gen_cmpb_dt_dd), + + cmp_b_dpc_dd(0xb03a, 0xf1ff, ea_dpc8_read, dbrr, gen_cmpb_dt_dd), + + cmp_b_dpci_dd(0xb03b, 0xf1ff, ea_dpci8_read, dbrr, gen_cmpb_dt_dd), + + cmp_b_imm8_dd(0xb03c, 0xf1ff, ea_imm8_read, dbrr, gen_cmpb_dt_dd), + + cmp_w_ds_dd(0xb040, 0xf1f8, gen_cmpw_ds_dd, dbrr, dbrr), + + cmp_w_as_dd(0xb048, 0xf1f8, gen_cmpw_as_dd, dbrr, dbrr), + + cmp_w_ais_dd(0xb050, 0xf1f8, ea_ais16_read, dbrr, gen_cmpw_dt_dd), + + cmp_w_aips_dd(0xb058, 0xf1f8, ea_aips16_read, dbrr, gen_cmpw_dt_dd), + + cmp_w_pais_dd(0xb060, 0xf1f8, ea_pais16_read, dbrr, gen_cmpw_dt_dd), + + cmp_w_das_dd(0xb068, 0xf1f8, ea_das16_read, dbrr, gen_cmpw_dt_dd), + + cmp_w_dais_dd(0xb070, 0xf1f8, ea_dais16_read, dbrr, gen_cmpw_dt_dd), + + cmp_w_adr16_dd(0xb078, 0xf1ff, ea_adr16s16_read, dbrr, gen_cmpw_dt_dd), + + cmp_w_adr32_dd(0xb079, 0xf1ff, ea_adr32s16_read, dbrr, gen_cmpw_dt_dd), + + cmp_w_dpc_dd(0xb07a, 0xf1ff, ea_dpc16_read, dbrr, gen_cmpw_dt_dd), + + cmp_w_dpci_dd(0xb07b, 0xf1ff, ea_dpci16_read, dbrr, gen_cmpw_dt_dd), + + cmp_w_imm16_dd(0xb07c, 0xf1ff, ea_imm16_read, dbrr, gen_cmpw_dt_dd), + + cmp_l_ds_dd(0xb080, 0xf1f8, gen_cmpl_ds_dd, dbrr, dbrr), + + cmp_l_as_dd(0xb088, 0xf1f8, gen_cmpl_as_dd, dbrr, dbrr), + + cmp_l_ais_dd(0xb090, 0xf1f8, ea_ais32_read, dbrr, gen_cmpl_dt_dd), + + cmp_l_aips_dd(0xb098, 0xf1f8, ea_aips32_read, dbrr, gen_cmpl_dt_dd), + + cmp_l_pais_dd(0xb0a0, 0xf1f8, ea_pais32_read, dbrr, gen_cmpl_dt_dd), + + cmp_l_das_dd(0xb0a8, 0xf1f8, ea_das32_read, dbrr, gen_cmpl_dt_dd), + + cmp_l_dais_dd(0xb0b0, 0xf1f8, ea_dais32_read, dbrr, gen_cmpl_dt_dd), + + cmp_l_adr16_dd(0xb0b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_cmpl_dt_dd), + + cmp_l_adr32_dd(0xb0b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_cmpl_dt_dd), + + cmp_l_dpc_dd(0xb0ba, 0xf1ff, ea_dpc32_read, dbrr, gen_cmpl_dt_dd), + + cmp_l_dpci_dd(0xb0bb, 0xf1ff, ea_dpci32_read, dbrr, gen_cmpl_dt_dd), + + cmp_l_imm32_dd(0xb0bc, 0xf1ff, ea_imm32_read, dbrr, gen_cmpl_dt_dd), + + cmpa_w_ds_ad(0xb0c0, 0xf1f8, gen_cmpw_ds_ad, dbrr, dbrr), + + cmpa_w_as_ad(0xb0c8, 0xf1f8, gen_cmpw_as_ad, dbrr, dbrr), + + cmpa_w_ais_ad(0xb0d0, 0xf1f8, ea_ais16_read, dbrr, gen_cmpw_dt_ad), + + cmpa_w_aips_ad(0xb0d8, 0xf1f8, ea_aips16_read, dbrr, gen_cmpw_dt_ad), + + cmpa_w_pais_ad(0xb0e0, 0xf1f8, ea_pais16_read, dbrr, gen_cmpw_dt_ad), + + cmpa_w_das_ad(0xb0e8, 0xf1f8, ea_das16_read, dbrr, gen_cmpw_dt_ad), + + cmpa_w_dais_ad(0xb0f0, 0xf1f8, ea_dais16_read, dbrr, gen_cmpw_dt_ad), + + cmpa_w_adr16_ad(0xb0f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_cmpw_dt_ad), + + cmpa_w_adr32_ad(0xb0f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_cmpw_dt_ad), + + cmpa_w_dpc_ad(0xb0fa, 0xf1ff, ea_dpc16_read, dbrr, gen_cmpw_dt_ad), + + cmpa_w_dpci_ad(0xb0fb, 0xf1ff, ea_dpci16_read, dbrr, gen_cmpw_dt_ad), + + cmpa_w_imm16_ad(0xb0fc, 0xf1ff, ea_imm16_read, dbrr, gen_cmpw_dt_ad), + + eor_b_dd_ds(0xb100, 0xf1f8, gen_eorb_dd_ds, dbrr, dbrr), + + cmpm_b_aips_aipd(0xb108, 0xf1f8, ea_aips8_read, gen_cmpmb_im_ea, ea_aipd8_read), + + eor_b_dd_ais(0xb110, 0xf1f8, ea_ais8_read, dbrr, gen_eorb_dd_ea), + + eor_b_dd_aips(0xb118, 0xf1f8, ea_aips8_read, dbrr, gen_eorb_dd_ea), + + eor_b_dd_pais(0xb120, 0xf1f8, ea_pais8_read, dbrr, gen_eorb_dd_ea), + + eor_b_dd_das(0xb128, 0xf1f8, ea_das8_read, dbrr, gen_eorb_dd_ea), + + eor_b_dd_dais(0xb130, 0xf1f8, ea_dais8_read, dbrr, gen_eorb_dd_ea), + + eor_b_dd_adr16(0xb138, 0xf1ff, ea_adr16s8_read, dbrr, gen_eorb_dd_ea), + + eor_b_dd_adr32(0xb139, 0xf1ff, ea_adr32s8_read, dbrr, gen_eorb_dd_ea), + + eor_w_dd_ds(0xb140, 0xf1f8, gen_eorw_dd_ds, dbrr, dbrr), + + cmpm_w_aips_aipd(0xb148, 0xf1f8, ea_aips16_read, gen_cmpmw_im_ea, ea_aipd16_read), + + eor_w_dd_ais(0xb150, 0xf1f8, ea_ais16_read, dbrr, gen_eorw_dd_ea), + + eor_w_dd_aips(0xb158, 0xf1f8, ea_aips16_read, dbrr, gen_eorw_dd_ea), + + eor_w_dd_pais(0xb160, 0xf1f8, ea_pais16_read, dbrr, gen_eorw_dd_ea), + + eor_w_dd_das(0xb168, 0xf1f8, ea_das16_read, dbrr, gen_eorw_dd_ea), + + eor_w_dd_dais(0xb170, 0xf1f8, ea_dais16_read, dbrr, gen_eorw_dd_ea), + + eor_w_dd_adr16(0xb178, 0xf1ff, ea_adr16s16_read, dbrr, gen_eorw_dd_ea), + + eor_w_dd_adr32(0xb179, 0xf1ff, ea_adr32s16_read, dbrr, gen_eorw_dd_ea), + + eor_l_dd_ds(0xb180, 0xf1f8, gen_eorl_dd_ds, dbrr, dbrr), + + cmpm_l_aips_aipd(0xb188, 0xf1f8, ea_aips32_read, gen_cmpml_im_ea, ea_aipd32_read), + + eor_l_dd_ais(0xb190, 0xf1f8, ea_ais32_read, dbrr, gen_eorl_dd_ea), + + eor_l_dd_aips(0xb198, 0xf1f8, ea_aips32_read, dbrr, gen_eorl_dd_ea), + + eor_l_dd_pais(0xb1a0, 0xf1f8, ea_pais32_read, dbrr, gen_eorl_dd_ea), + + eor_l_dd_das(0xb1a8, 0xf1f8, ea_das32_read, dbrr, gen_eorl_dd_ea), + + eor_l_dd_dais(0xb1b0, 0xf1f8, ea_dais32_read, dbrr, gen_eorl_dd_ea), + + eor_l_dd_adr16(0xb1b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_eorl_dd_ea), + + eor_l_dd_adr32(0xb1b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_eorl_dd_ea), + + cmpa_l_ds_ad(0xb1c0, 0xf1f8, gen_cmpl_ds_ad, dbrr, dbrr), + + cmpa_l_as_ad(0xb1c8, 0xf1f8, gen_cmpl_as_ad, dbrr, dbrr), + + cmpa_l_ais_ad(0xb1d0, 0xf1f8, ea_ais32_read, dbrr, gen_cmpl_dt_ad), + + cmpa_l_aips_ad(0xb1d8, 0xf1f8, ea_aips32_read, dbrr, gen_cmpl_dt_ad), + + cmpa_l_pais_ad(0xb1e0, 0xf1f8, ea_pais32_read, dbrr, gen_cmpl_dt_ad), + + cmpa_l_das_ad(0xb1e8, 0xf1f8, ea_das32_read, dbrr, gen_cmpl_dt_ad), + + cmpa_l_dais_ad(0xb1f0, 0xf1f8, ea_dais32_read, dbrr, gen_cmpl_dt_ad), + + cmpa_l_adr16_ad(0xb1f8, 0xf1ff, ea_adr16s32_read, dbrr, gen_cmpl_dt_ad), + + cmpa_l_adr32_ad(0xb1f9, 0xf1ff, ea_adr32s32_read, dbrr, gen_cmpl_dt_ad), + + cmpa_l_dpc_ad(0xb1fa, 0xf1ff, ea_dpc32_read, dbrr, gen_cmpl_dt_ad), + + cmpa_l_dpci_ad(0xb1fb, 0xf1ff, ea_dpci32_read, dbrr, gen_cmpl_dt_ad), + + cmpa_l_imm32_ad(0xb1fc, 0xf1ff, ea_imm32_read, dbrr, gen_cmpl_dt_ad), + + and_b_ds_dd(0xc000, 0xf1f8, gen_andb_ds_dd, dbrr, dbrr), + + and_b_ais_dd(0xc010, 0xf1f8, ea_ais8_read, dbrr, gen_andb_dt_dd), + + and_b_aips_dd(0xc018, 0xf1f8, ea_aips8_read, dbrr, gen_andb_dt_dd), + + and_b_pais_dd(0xc020, 0xf1f8, ea_pais8_read, dbrr, gen_andb_dt_dd), + + and_b_das_dd(0xc028, 0xf1f8, ea_das8_read, dbrr, gen_andb_dt_dd), + + and_b_dais_dd(0xc030, 0xf1f8, ea_dais8_read, dbrr, gen_andb_dt_dd), + + and_b_adr16_dd(0xc038, 0xf1ff, ea_adr16s8_read, dbrr, gen_andb_dt_dd), + + and_b_adr32_dd(0xc039, 0xf1ff, ea_adr32s8_read, dbrr, gen_andb_dt_dd), + + and_b_dpc_dd(0xc03a, 0xf1ff, ea_dpc8_read, dbrr, gen_andb_dt_dd), + + and_b_dpci_dd(0xc03b, 0xf1ff, ea_dpci8_read, dbrr, gen_andb_dt_dd), + + and_b_imm8_dd(0xc03c, 0xf1ff, ea_imm8_read, dbrr, gen_andb_dt_dd), + + and_w_ds_dd(0xc040, 0xf1f8, gen_andw_ds_dd, dbrr, dbrr), + + and_w_ais_dd(0xc050, 0xf1f8, ea_ais16_read, dbrr, gen_andw_dt_dd), + + and_w_aips_dd(0xc058, 0xf1f8, ea_aips16_read, dbrr, gen_andw_dt_dd), + + and_w_pais_dd(0xc060, 0xf1f8, ea_pais16_read, dbrr, gen_andw_dt_dd), + + and_w_das_dd(0xc068, 0xf1f8, ea_das16_read, dbrr, gen_andw_dt_dd), + + and_w_dais_dd(0xc070, 0xf1f8, ea_dais16_read, dbrr, gen_andw_dt_dd), + + and_w_adr16_dd(0xc078, 0xf1ff, ea_adr16s16_read, dbrr, gen_andw_dt_dd), + + and_w_adr32_dd(0xc079, 0xf1ff, ea_adr32s16_read, dbrr, gen_andw_dt_dd), + + and_w_dpc_dd(0xc07a, 0xf1ff, ea_dpc16_read, dbrr, gen_andw_dt_dd), + + and_w_dpci_dd(0xc07b, 0xf1ff, ea_dpci16_read, dbrr, gen_andw_dt_dd), + + and_w_imm16_dd(0xc07c, 0xf1ff, ea_imm16_read, dbrr, gen_andw_dt_dd), + + and_l_ds_dd(0xc080, 0xf1f8, gen_andl_ds_dd, dbrr, dbrr), + + and_l_ais_dd(0xc090, 0xf1f8, ea_ais32_read, dbrr, gen_andl_dt_dd), + + and_l_aips_dd(0xc098, 0xf1f8, ea_aips32_read, dbrr, gen_andl_dt_dd), + + and_l_pais_dd(0xc0a0, 0xf1f8, ea_pais32_read, dbrr, gen_andl_dt_dd), + + and_l_das_dd(0xc0a8, 0xf1f8, ea_das32_read, dbrr, gen_andl_dt_dd), + + and_l_dais_dd(0xc0b0, 0xf1f8, ea_dais32_read, dbrr, gen_andl_dt_dd), + + and_l_adr16_dd(0xc0b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_andl_dt_dd), + + and_l_adr32_dd(0xc0b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_andl_dt_dd), + + and_l_dpc_dd(0xc0ba, 0xf1ff, ea_dpc32_read, dbrr, gen_andl_dt_dd), + + and_l_dpci_dd(0xc0bb, 0xf1ff, ea_dpci32_read, dbrr, gen_andl_dt_dd), + + and_l_imm32_dd(0xc0bc, 0xf1ff, ea_imm32_read, dbrr, gen_andl_dt_dd), + + abcd_ds_dd(0xc100, 0xf1f8, gen_abcdb_ds_dd, dbrr, dbrr), + + abcd_pais_paid(0xc108, 0xf1f8, ea_pais8_read, gen_abcdb_im_ea, ea_paid8_read), + + and_b_dd_ais(0xc110, 0xf1f8, ea_ais8_read, dbrr, gen_andb_dd_ea), + + and_b_dd_aips(0xc118, 0xf1f8, ea_aips8_read, dbrr, gen_andb_dd_ea), + + and_b_dd_pais(0xc120, 0xf1f8, ea_pais8_read, dbrr, gen_andb_dd_ea), + + and_b_dd_das(0xc128, 0xf1f8, ea_das8_read, dbrr, gen_andb_dd_ea), + + and_b_dd_dais(0xc130, 0xf1f8, ea_dais8_read, dbrr, gen_andb_dd_ea), + + and_b_dd_adr16(0xc138, 0xf1ff, ea_adr16s8_read, dbrr, gen_andb_dd_ea), + + and_b_dd_adr32(0xc139, 0xf1ff, ea_adr32s8_read, dbrr, gen_andb_dd_ea), + + exg_dd_ds(0xc140, 0xf1f8, op_exg_dd_ds, dbrr, dbrr), + + exg_ad_as(0xc148, 0xf1f8, op_exg_ad_as, dbrr, dbrr), + + and_w_dd_ais(0xc150, 0xf1f8, ea_ais16_read, dbrr, gen_andw_dd_ea), + + and_w_dd_aips(0xc158, 0xf1f8, ea_aips16_read, dbrr, gen_andw_dd_ea), + + and_w_dd_pais(0xc160, 0xf1f8, ea_pais16_read, dbrr, gen_andw_dd_ea), + + and_w_dd_das(0xc168, 0xf1f8, ea_das16_read, dbrr, gen_andw_dd_ea), + + and_w_dd_dais(0xc170, 0xf1f8, ea_dais16_read, dbrr, gen_andw_dd_ea), + + and_w_dd_adr16(0xc178, 0xf1ff, ea_adr16s16_read, dbrr, gen_andw_dd_ea), + + and_w_dd_adr32(0xc179, 0xf1ff, ea_adr32s16_read, dbrr, gen_andw_dd_ea), + + exg_dd_as(0xc188, 0xf1f8, op_exg_dd_as, dbrr, dbrr), + + and_l_dd_ais(0xc190, 0xf1f8, ea_ais32_read, dbrr, gen_andl_dd_ea), + + and_l_dd_aips(0xc198, 0xf1f8, ea_aips32_read, dbrr, gen_andl_dd_ea), + + and_l_dd_pais(0xc1a0, 0xf1f8, ea_pais32_read, dbrr, gen_andl_dd_ea), + + and_l_dd_das(0xc1a8, 0xf1f8, ea_das32_read, dbrr, gen_andl_dd_ea), + + and_l_dd_dais(0xc1b0, 0xf1f8, ea_dais32_read, dbrr, gen_andl_dd_ea), + + and_l_dd_adr16(0xc1b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_andl_dd_ea), + + and_l_dd_adr32(0xc1b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_andl_dd_ea), + + add_b_ds_dd(0xd000, 0xf1f8, gen_addb_ds_dd, dbrr, dbrr), + + add_b_ais_dd(0xd010, 0xf1f8, ea_ais8_read, dbrr, gen_addb_dt_dd), + + add_b_aips_dd(0xd018, 0xf1f8, ea_aips8_read, dbrr, gen_addb_dt_dd), + + add_b_pais_dd(0xd020, 0xf1f8, ea_pais8_read, dbrr, gen_addb_dt_dd), + + add_b_das_dd(0xd028, 0xf1f8, ea_das8_read, dbrr, gen_addb_dt_dd), + + add_b_dais_dd(0xd030, 0xf1f8, ea_dais8_read, dbrr, gen_addb_dt_dd), + + add_b_adr16_dd(0xd038, 0xf1ff, ea_adr16s8_read, dbrr, gen_addb_dt_dd), + + add_b_adr32_dd(0xd039, 0xf1ff, ea_adr32s8_read, dbrr, gen_addb_dt_dd), + + add_b_dpc_dd(0xd03a, 0xf1ff, ea_dpc8_read, dbrr, gen_addb_dt_dd), + + add_b_dpci_dd(0xd03b, 0xf1ff, ea_dpci8_read, dbrr, gen_addb_dt_dd), + + add_b_imm8_dd(0xd03c, 0xf1ff, ea_imm8_read, dbrr, gen_addb_dt_dd), + + add_w_ds_dd(0xd040, 0xf1f8, gen_addw_ds_dd, dbrr, dbrr), + + add_w_as_dd(0xd048, 0xf1f8, gen_addw_as_dd, dbrr, dbrr), + + add_w_ais_dd(0xd050, 0xf1f8, ea_ais16_read, dbrr, gen_addw_dt_dd), + + add_w_aips_dd(0xd058, 0xf1f8, ea_aips16_read, dbrr, gen_addw_dt_dd), + + add_w_pais_dd(0xd060, 0xf1f8, ea_pais16_read, dbrr, gen_addw_dt_dd), + + add_w_das_dd(0xd068, 0xf1f8, ea_das16_read, dbrr, gen_addw_dt_dd), + + add_w_dais_dd(0xd070, 0xf1f8, ea_dais16_read, dbrr, gen_addw_dt_dd), + + add_w_adr16_dd(0xd078, 0xf1ff, ea_adr16s16_read, dbrr, gen_addw_dt_dd), + + add_w_adr32_dd(0xd079, 0xf1ff, ea_adr32s16_read, dbrr, gen_addw_dt_dd), + + add_w_dpc_dd(0xd07a, 0xf1ff, ea_dpc16_read, dbrr, gen_addw_dt_dd), + + add_w_dpci_dd(0xd07b, 0xf1ff, ea_dpci16_read, dbrr, gen_addw_dt_dd), + + add_w_imm16_dd(0xd07c, 0xf1ff, ea_imm16_read, dbrr, gen_addw_dt_dd), + + add_l_ds_dd(0xd080, 0xf1f8, gen_addl_ds_dd, dbrr, dbrr), + + add_l_as_dd(0xd088, 0xf1f8, gen_addl_as_dd, dbrr, dbrr), + + add_l_ais_dd(0xd090, 0xf1f8, ea_ais32_read, dbrr, gen_addl_dt_dd), + + add_l_aips_dd(0xd098, 0xf1f8, ea_aips32_read, dbrr, gen_addl_dt_dd), + + add_l_pais_dd(0xd0a0, 0xf1f8, ea_pais32_read, dbrr, gen_addl_dt_dd), + + add_l_das_dd(0xd0a8, 0xf1f8, ea_das32_read, dbrr, gen_addl_dt_dd), + + add_l_dais_dd(0xd0b0, 0xf1f8, ea_dais32_read, dbrr, gen_addl_dt_dd), + + add_l_adr16_dd(0xd0b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_addl_dt_dd), + + add_l_adr32_dd(0xd0b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_addl_dt_dd), + + add_l_dpc_dd(0xd0ba, 0xf1ff, ea_dpc32_read, dbrr, gen_addl_dt_dd), + + add_l_dpci_dd(0xd0bb, 0xf1ff, ea_dpci32_read, dbrr, gen_addl_dt_dd), + + add_l_imm32_dd(0xd0bc, 0xf1ff, ea_imm32_read, dbrr, gen_addl_dt_dd), + + adda_w_ds_ad(0xd0c0, 0xf1f8, gen_addw_ds_ad, dbrr, dbrr), + + adda_w_as_ad(0xd0c8, 0xf1f8, gen_addw_as_ad, dbrr, dbrr), + + adda_w_ais_ad(0xd0d0, 0xf1f8, ea_ais16_read, dbrr, gen_addw_dt_ad), + + adda_w_aips_ad(0xd0d8, 0xf1f8, ea_aips16_read, dbrr, gen_addw_dt_ad), + + adda_w_pais_ad(0xd0e0, 0xf1f8, ea_pais16_read, dbrr, gen_addw_dt_ad), + + adda_w_das_ad(0xd0e8, 0xf1f8, ea_das16_read, dbrr, gen_addw_dt_ad), + + adda_w_dais_ad(0xd0f0, 0xf1f8, ea_dais16_read, dbrr, gen_addw_dt_ad), + + adda_w_adr16_ad(0xd0f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_addw_dt_ad), + + adda_w_adr32_ad(0xd0f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_addw_dt_ad), + + adda_w_dpc_ad(0xd0fa, 0xf1ff, ea_dpc16_read, dbrr, gen_addw_dt_ad), + + adda_w_dpci_ad(0xd0fb, 0xf1ff, ea_dpci16_read, dbrr, gen_addw_dt_ad), + + adda_w_imm16_ad(0xd0fc, 0xf1ff, ea_imm16_read, dbrr, gen_addw_dt_ad), + + addx_b_ds_dd(0xd100, 0xf1f8, gen_addxb_ds_dd, dbrr, dbrr), + + addx_b_pais_paid(0xd108, 0xf1f8, ea_pais8_read, gen_addxb_im_ea, ea_paid8_read), + + add_b_dd_ais(0xd110, 0xf1f8, ea_ais8_read, dbrr, gen_addb_dd_ea), + + add_b_dd_aips(0xd118, 0xf1f8, ea_aips8_read, dbrr, gen_addb_dd_ea), + + add_b_dd_pais(0xd120, 0xf1f8, ea_pais8_read, dbrr, gen_addb_dd_ea), + + add_b_dd_das(0xd128, 0xf1f8, ea_das8_read, dbrr, gen_addb_dd_ea), + + add_b_dd_dais(0xd130, 0xf1f8, ea_dais8_read, dbrr, gen_addb_dd_ea), + + add_b_dd_adr16(0xd138, 0xf1ff, ea_adr16s8_read, dbrr, gen_addb_dd_ea), + + add_b_dd_adr32(0xd139, 0xf1ff, ea_adr32s8_read, dbrr, gen_addb_dd_ea), + + addx_w_ds_dd(0xd140, 0xf1f8, gen_addxw_ds_dd, dbrr, dbrr), + + addx_w_pais_paid(0xd148, 0xf1f8, ea_pais16_read, gen_addxw_im_ea, ea_paid16_read), + + add_w_dd_ais(0xd150, 0xf1f8, ea_ais16_read, dbrr, gen_addw_dd_ea), + + add_w_dd_aips(0xd158, 0xf1f8, ea_aips16_read, dbrr, gen_addw_dd_ea), + + add_w_dd_pais(0xd160, 0xf1f8, ea_pais16_read, dbrr, gen_addw_dd_ea), + + add_w_dd_das(0xd168, 0xf1f8, ea_das16_read, dbrr, gen_addw_dd_ea), + + add_w_dd_dais(0xd170, 0xf1f8, ea_dais16_read, dbrr, gen_addw_dd_ea), + + add_w_dd_adr16(0xd178, 0xf1ff, ea_adr16s16_read, dbrr, gen_addw_dd_ea), + + add_w_dd_adr32(0xd179, 0xf1ff, ea_adr32s16_read, dbrr, gen_addw_dd_ea), + + addx_l_ds_dd(0xd180, 0xf1f8, gen_addxl_ds_dd, dbrr, dbrr), + + addx_l_pais_paid(0xd188, 0xf1f8, ea_pais32_read, gen_addxl_im_ea, ea_paid32_read), + + add_l_dd_ais(0xd190, 0xf1f8, ea_ais32_read, dbrr, gen_addl_dd_ea), + + add_l_dd_aips(0xd198, 0xf1f8, ea_aips32_read, dbrr, gen_addl_dd_ea), + + add_l_dd_pais(0xd1a0, 0xf1f8, ea_pais32_read, dbrr, gen_addl_dd_ea), + + add_l_dd_das(0xd1a8, 0xf1f8, ea_das32_read, dbrr, gen_addl_dd_ea), + + add_l_dd_dais(0xd1b0, 0xf1f8, ea_dais32_read, dbrr, gen_addl_dd_ea), + + add_l_dd_adr16(0xd1b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_addl_dd_ea), + + add_l_dd_adr32(0xd1b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_addl_dd_ea), + + adda_l_ds_ad(0xd1c0, 0xf1f8, gen_addl_ds_ad, dbrr, dbrr), + + adda_l_as_ad(0xd1c8, 0xf1f8, gen_addl_as_ad, dbrr, dbrr), + + adda_l_ais_ad(0xd1d0, 0xf1f8, ea_ais32_read, dbrr, gen_addl_dt_ad), + + adda_l_aips_ad(0xd1d8, 0xf1f8, ea_aips32_read, dbrr, gen_addl_dt_ad), + + adda_l_pais_ad(0xd1e0, 0xf1f8, ea_pais32_read, dbrr, gen_addl_dt_ad), + + adda_l_das_ad(0xd1e8, 0xf1f8, ea_das32_read, dbrr, gen_addl_dt_ad), + + adda_l_dais_ad(0xd1f0, 0xf1f8, ea_dais32_read, dbrr, gen_addl_dt_ad), + + adda_l_adr16_ad(0xd1f8, 0xf1ff, ea_adr16s32_read, dbrr, gen_addl_dt_ad), + + adda_l_adr32_ad(0xd1f9, 0xf1ff, ea_adr32s32_read, dbrr, gen_addl_dt_ad), + + adda_l_dpc_ad(0xd1fa, 0xf1ff, ea_dpc32_read, dbrr, gen_addl_dt_ad), + + adda_l_dpci_ad(0xd1fb, 0xf1ff, ea_dpci32_read, dbrr, gen_addl_dt_ad), + + adda_l_imm32_ad(0xd1fc, 0xf1ff, ea_imm32_read, dbrr, gen_addl_dt_ad), + + asr_b_imm3_ds(0xe000, 0xf1f8, gen_asrb_ir_ds, dbrr, dbrr), + + lsr_b_imm3_ds(0xe008, 0xf1f8, gen_lsrb_ir_ds, dbrr, dbrr), + + ror_b_imm3_ds(0xe018, 0xf1f8, gen_rorb_ir_ds, dbrr, dbrr), + + asr_b_dd_ds(0xe020, 0xf1f8, gen_asrb_dd_ds, dbrr, dbrr), + + lsr_b_dd_ds(0xe028, 0xf1f8, gen_lsrb_dd_ds, dbrr, dbrr), + + ror_b_dd_ds(0xe038, 0xf1f8, gen_rorb_dd_ds, dbrr, dbrr), + + asr_w_imm3_ds(0xe040, 0xf1f8, gen_asrw_ir_ds, dbrr, dbrr), + + lsr_w_imm3_ds(0xe048, 0xf1f8, gen_lsrw_ir_ds, dbrr, dbrr), + + ror_w_imm3_ds(0xe058, 0xf1f8, gen_rorw_ir_ds, dbrr, dbrr), + + asr_w_dd_ds(0xe060, 0xf1f8, gen_asrw_dd_ds, dbrr, dbrr), + + lsr_w_dd_ds(0xe068, 0xf1f8, gen_lsrw_dd_ds, dbrr, dbrr), + + ror_w_dd_ds(0xe078, 0xf1f8, gen_rorw_dd_ds, dbrr, dbrr), + + asr_l_imm3_ds(0xe080, 0xf1f8, gen_asrl_ir_ds, dbrr, dbrr), + + lsr_l_imm3_ds(0xe088, 0xf1f8, gen_lsrl_ir_ds, dbrr, dbrr), + + ror_l_imm3_ds(0xe098, 0xf1f8, gen_rorl_ir_ds, dbrr, dbrr), + + asr_l_dd_ds(0xe0a0, 0xf1f8, gen_asrl_dd_ds, dbrr, dbrr), + + lsr_l_dd_ds(0xe0a8, 0xf1f8, gen_lsrl_dd_ds, dbrr, dbrr), + + ror_l_dd_ds(0xe0b8, 0xf1f8, gen_rorl_dd_ds, dbrr, dbrr), + + asr_ais(0xe0d0, 0xfff8, ea_ais16_read, dbrr, gen_asrw_ea), + + asr_aips(0xe0d8, 0xfff8, ea_aips16_read, dbrr, gen_asrw_ea), + + asr_pais(0xe0e0, 0xfff8, ea_pais16_read, dbrr, gen_asrw_ea), + + asr_das(0xe0e8, 0xfff8, ea_das16_read, dbrr, gen_asrw_ea), + + asr_dais(0xe0f0, 0xfff8, ea_dais16_read, dbrr, gen_asrw_ea), + + asr_adr16(0xe0f8, 0xffff, ea_adr16s16_read, dbrr, gen_asrw_ea), + + asr_adr32(0xe0f9, 0xffff, ea_adr32s16_read, dbrr, gen_asrw_ea), + + asl_b_imm3_ds(0xe100, 0xf1f8, gen_aslb_ir_ds, dbrr, dbrr), + + lsl_b_imm3_ds(0xe108, 0xf1f8, gen_lslb_ir_ds, dbrr, dbrr), + + rol_b_imm3_ds(0xe118, 0xf1f8, gen_rolb_ir_ds, dbrr, dbrr), + + asl_b_dd_ds(0xe120, 0xf1f8, gen_aslb_dd_ds, dbrr, dbrr), + + lsl_b_dd_ds(0xe128, 0xf1f8, gen_lslb_dd_ds, dbrr, dbrr), + + rol_b_dd_ds(0xe138, 0xf1f8, gen_rolb_dd_ds, dbrr, dbrr), + + asl_w_imm3_ds(0xe140, 0xf1f8, gen_aslw_ir_ds, dbrr, dbrr), + + lsl_w_imm3_ds(0xe148, 0xf1f8, gen_lslw_ir_ds, dbrr, dbrr), + + rol_w_imm3_ds(0xe158, 0xf1f8, gen_rolw_ir_ds, dbrr, dbrr), + + asl_w_dd_ds(0xe160, 0xf1f8, gen_aslw_dd_ds, dbrr, dbrr), + + lsl_w_dd_ds(0xe168, 0xf1f8, gen_lslw_dd_ds, dbrr, dbrr), + + rol_w_dd_ds(0xe178, 0xf1f8, gen_rolw_dd_ds, dbrr, dbrr), + + asl_l_imm3_ds(0xe180, 0xf1f8, gen_asll_ir_ds, dbrr, dbrr), + + lsl_l_imm3_ds(0xe188, 0xf1f8, gen_lsll_ir_ds, dbrr, dbrr), + + rol_l_imm3_ds(0xe198, 0xf1f8, gen_roll_ir_ds, dbrr, dbrr), + + asl_l_dd_ds(0xe1a0, 0xf1f8, gen_asll_dd_ds, dbrr, dbrr), + + lsl_l_dd_ds(0xe1a8, 0xf1f8, gen_lsll_dd_ds, dbrr, dbrr), + + rol_l_dd_ds(0xe1b8, 0xf1f8, gen_roll_dd_ds, dbrr, dbrr), + + asl_ais(0xe1d0, 0xfff8, ea_ais16_read, dbrr, gen_aslw_ea), + + asl_aips(0xe1d8, 0xfff8, ea_aips16_read, dbrr, gen_aslw_ea), + + asl_pais(0xe1e0, 0xfff8, ea_pais16_read, dbrr, gen_aslw_ea), + + asl_das(0xe1e8, 0xfff8, ea_das16_read, dbrr, gen_aslw_ea), + + asl_dais(0xe1f0, 0xfff8, ea_dais16_read, dbrr, gen_aslw_ea), + + asl_adr16(0xe1f8, 0xffff, ea_adr16s16_read, dbrr, gen_aslw_ea), + + asl_adr32(0xe1f9, 0xffff, ea_adr32s16_read, dbrr, gen_aslw_ea), + + lsr_ais(0xe2d0, 0xfff8, ea_ais16_read, dbrr, gen_lsrw_ea), + + lsr_aips(0xe2d8, 0xfff8, ea_aips16_read, dbrr, gen_lsrw_ea), + + lsr_pais(0xe2e0, 0xfff8, ea_pais16_read, dbrr, gen_lsrw_ea), + + lsr_das(0xe2e8, 0xfff8, ea_das16_read, dbrr, gen_lsrw_ea), + + lsr_dais(0xe2f0, 0xfff8, ea_dais16_read, dbrr, gen_lsrw_ea), + + lsr_adr16(0xe2f8, 0xffff, ea_adr16s16_read, dbrr, gen_lsrw_ea), + + lsr_adr32(0xe2f9, 0xffff, ea_adr32s16_read, dbrr, gen_lsrw_ea), + + lsl_ais(0xe3d0, 0xfff8, ea_ais16_read, dbrr, gen_lslw_ea), + + lsl_aips(0xe3d8, 0xfff8, ea_aips16_read, dbrr, gen_lslw_ea), + + lsl_pais(0xe3e0, 0xfff8, ea_pais16_read, dbrr, gen_lslw_ea), + + lsl_das(0xe3e8, 0xfff8, ea_das16_read, dbrr, gen_lslw_ea), + + lsl_dais(0xe3f0, 0xfff8, ea_dais16_read, dbrr, gen_lslw_ea), + + lsl_adr16(0xe3f8, 0xffff, ea_adr16s16_read, dbrr, gen_lslw_ea), + + lsl_adr32(0xe3f9, 0xffff, ea_adr32s16_read, dbrr, gen_lslw_ea), + + ror_ais(0xe6d0, 0xfff8, ea_ais16_read, dbrr, gen_rorw_ea), + + ror_aips(0xe6d8, 0xfff8, ea_aips16_read, dbrr, gen_rorw_ea), + + ror_pais(0xe6e0, 0xfff8, ea_pais16_read, dbrr, gen_rorw_ea), + + ror_das(0xe6e8, 0xfff8, ea_das16_read, dbrr, gen_rorw_ea), + + ror_dais(0xe6f0, 0xfff8, ea_dais16_read, dbrr, gen_rorw_ea), + + ror_adr16(0xe6f8, 0xffff, ea_adr16s16_read, dbrr, gen_rorw_ea), + + ror_adr32(0xe6f9, 0xffff, ea_adr32s16_read, dbrr, gen_rorw_ea), + + rol_ais(0xe7d0, 0xfff8, ea_ais16_read, dbrr, gen_rolw_ea), + + rol_aips(0xe7d8, 0xfff8, ea_aips16_read, dbrr, gen_rolw_ea), + + rol_pais(0xe7e0, 0xfff8, ea_pais16_read, dbrr, gen_rolw_ea), + + rol_das(0xe7e8, 0xfff8, ea_das16_read, dbrr, gen_rolw_ea), + + rol_dais(0xe7f0, 0xfff8, ea_dais16_read, dbrr, gen_rolw_ea), + + rol_adr16(0xe7f8, 0xffff, ea_adr16s16_read, dbrr, gen_rolw_ea), + + rol_adr32(0xe7f9, 0xffff, ea_adr32s16_read, dbrr, gen_rolw_ea), + + linef_imm12(0xf000, 0xf000, op_linef, dbrr, dbrr); + + private static final MacroPLA[] DECODER = new MacroPLA[0xffff + 1]; + + static { + for (MacroPLA insn : MacroPLA.values()) { + for (int ir = insn.opcode & insn.opmask; ir < DECODER.length; ir = maskedIncrement(ir, insn.opmask)) { + if ((ir & insn.opmask) == insn.opcode) { + int bits = 0; + if (DECODER[ir] != null) { + bits = Integer.bitCount(DECODER[ir].opmask); + } + if ((bits == 0) || (Integer.bitCount(insn.opmask) > bits)) { + DECODER[ir] = insn; + } + } + } + } + for (int ir = 0; ir < DECODER.length; ir++) { + if (DECODER[ir] == null) { + DECODER[ir] = illegal; + } + } + } + + public final int opcode; + + public final int opmask; + + public final int a1; + + public final int a2; + + public final int a3; + + private MacroPLA(int opcode, int opmask, int a1, int a2, int a3) { + this.opcode = opcode; + this.opmask = opmask; + this.a1 = a1; + this.a2 = a2; + this.a3 = a3; + } + + private static final int maskedIncrement(int value, int mask) { + int variableBits = ~mask; + int base = value & mask; + int next = mask + (value & variableBits) + 1; + return base + (next & variableBits); + } + + public static final MacroPLA decode(int ir) { + return DECODER[ir & 0xffff]; + } +} diff --git a/miggy-emu/src/main/resources/miggy/cpu/genpoet/m68000.lst b/miggy-emu/src/main/resources/miggy/cpu/genpoet/m68000.lst new file mode 100644 index 0000000..15a802d --- /dev/null +++ b/miggy-emu/src/main/resources/miggy/cpu/genpoet/m68000.lst @@ -0,0 +1,1528 @@ +0000 fff8 ori.b imm8 ds +0010 fff8 ori.b imm8 ais +0018 fff8 ori.b imm8 aips +0020 fff8 ori.b imm8 pais +0028 fff8 ori.b imm8 das +0030 fff8 ori.b imm8 dais +0038 ffff ori.b imm8 adr16 +0039 ffff ori.b imm8 adr32 +003c ffff ori imm8 ccr +0040 fff8 ori.w imm16 ds +0050 fff8 ori.w imm16 ais +0058 fff8 ori.w imm16 aips +0060 fff8 ori.w imm16 pais +0068 fff8 ori.w imm16 das +0070 fff8 ori.w imm16 dais +0078 ffff ori.w imm16 adr16 +0079 ffff ori.w imm16 adr32 +007c ffff ori i16u sr +0080 fff8 ori.l imm32 ds +0090 fff8 ori.l imm32 ais +0098 fff8 ori.l imm32 aips +00a0 fff8 ori.l imm32 pais +00a8 fff8 ori.l imm32 das +00b0 fff8 ori.l imm32 dais +00b8 ffff ori.l imm32 adr16 +00b9 ffff ori.l imm32 adr32 +0100 f1f8 btst dd ds +0108 f1f8 movep.w das dd +0110 f1f8 btst dd ais +0118 f1f8 btst dd aips +0120 f1f8 btst dd pais +0128 f1f8 btst dd das +0130 f1f8 btst dd dais +0138 f1ff btst dd adr16 +0139 f1ff btst dd adr32 +013a f1ff btst dd dpc +013b f1ff btst dd dpci +013c f1ff btst dd imm +0140 f1f8 bchg dd ds +0148 f1f8 movep.l das dd +0150 f1f8 bchg dd ais +0158 f1f8 bchg dd aips +0160 f1f8 bchg dd pais +0168 f1f8 bchg dd das +0170 f1f8 bchg dd dais +0178 f1ff bchg dd adr16 +0179 f1ff bchg dd adr32 +0180 f1f8 bclr dd ds +0188 f1f8 movep.w dd das +0190 f1f8 bclr dd ais +0198 f1f8 bclr dd aips +01a0 f1f8 bclr dd pais +01a8 f1f8 bclr dd das +01b0 f1f8 bclr dd dais +01b8 f1ff bclr dd adr16 +01b9 f1ff bclr dd adr32 +01c0 f1f8 bset dd ds +01c8 f1f8 movep.l dd das +01d0 f1f8 bset dd ais +01d8 f1f8 bset dd aips +01e0 f1f8 bset dd pais +01e8 f1f8 bset dd das +01f0 f1f8 bset dd dais +01f8 f1ff bset dd adr16 +01f9 f1ff bset dd adr32 +0200 fff8 andi.b imm8 ds +0210 fff8 andi.b imm8 ais +0218 fff8 andi.b imm8 aips +0220 fff8 andi.b imm8 pais +0228 fff8 andi.b imm8 das +0230 fff8 andi.b imm8 dais +0238 ffff andi.b imm8 adr16 +0239 ffff andi.b imm8 adr32 +023c ffff andi imm8 ccr +0240 fff8 andi.w imm16 ds +0250 fff8 andi.w imm16 ais +0258 fff8 andi.w imm16 aips +0260 fff8 andi.w imm16 pais +0268 fff8 andi.w imm16 das +0270 fff8 andi.w imm16 dais +0278 ffff andi.w imm16 adr16 +0279 ffff andi.w imm16 adr32 +027c ffff andi i16u sr +0280 fff8 andi.l imm32 ds +0290 fff8 andi.l imm32 ais +0298 fff8 andi.l imm32 aips +02a0 fff8 andi.l imm32 pais +02a8 fff8 andi.l imm32 das +02b0 fff8 andi.l imm32 dais +02b8 ffff andi.l imm32 adr16 +02b9 ffff andi.l imm32 adr32 +0400 fff8 subi.b imm8 ds +0410 fff8 subi.b imm8 ais +0418 fff8 subi.b imm8 aips +0420 fff8 subi.b imm8 pais +0428 fff8 subi.b imm8 das +0430 fff8 subi.b imm8 dais +0438 ffff subi.b imm8 adr16 +0439 ffff subi.b imm8 adr32 +0440 fff8 subi.w imm16 ds +0450 fff8 subi.w imm16 ais +0458 fff8 subi.w imm16 aips +0460 fff8 subi.w imm16 pais +0468 fff8 subi.w imm16 das +0470 fff8 subi.w imm16 dais +0478 ffff subi.w imm16 adr16 +0479 ffff subi.w imm16 adr32 +0480 fff8 subi.l imm32 ds +0490 fff8 subi.l imm32 ais +0498 fff8 subi.l imm32 aips +04a0 fff8 subi.l imm32 pais +04a8 fff8 subi.l imm32 das +04b0 fff8 subi.l imm32 dais +04b8 ffff subi.l imm32 adr16 +04b9 ffff subi.l imm32 adr32 +0600 fff8 addi.b imm8 ds +0610 fff8 addi.b imm8 ais +0618 fff8 addi.b imm8 aips +0620 fff8 addi.b imm8 pais +0628 fff8 addi.b imm8 das +0630 fff8 addi.b imm8 dais +0638 ffff addi.b imm8 adr16 +0639 ffff addi.b imm8 adr32 +0640 fff8 addi.w imm16 ds +0650 fff8 addi.w imm16 ais +0658 fff8 addi.w imm16 aips +0660 fff8 addi.w imm16 pais +0668 fff8 addi.w imm16 das +0670 fff8 addi.w imm16 dais +0678 ffff addi.w imm16 adr16 +0679 ffff addi.w imm16 adr32 +0680 fff8 addi.l imm32 ds +0690 fff8 addi.l imm32 ais +0698 fff8 addi.l imm32 aips +06a0 fff8 addi.l imm32 pais +06a8 fff8 addi.l imm32 das +06b0 fff8 addi.l imm32 dais +06b8 ffff addi.l imm32 adr16 +06b9 ffff addi.l imm32 adr32 +0800 fff8 btst imm8 ds +0810 fff8 btst imm8 ais +0818 fff8 btst imm8 aips +0820 fff8 btst imm8 pais +0828 fff8 btst imm8 das +0830 fff8 btst imm8 dais +0838 ffff btst imm8 adr16 +0839 ffff btst imm8 adr32 +083a ffff btst imm8 dpc +083b ffff btst imm8 dpci +0840 fff8 bchg imm8 ds +0850 fff8 bchg imm8 ais +0858 fff8 bchg imm8 aips +0860 fff8 bchg imm8 pais +0868 fff8 bchg imm8 das +0870 fff8 bchg imm8 dais +0878 ffff bchg imm8 adr16 +0879 ffff bchg imm8 adr32 +0880 fff8 bclr imm8 ds +0890 fff8 bclr imm8 ais +0898 fff8 bclr imm8 aips +08a0 fff8 bclr imm8 pais +08a8 fff8 bclr imm8 das +08b0 fff8 bclr imm8 dais +08b8 ffff bclr imm8 adr16 +08b9 ffff bclr imm8 adr32 +08c0 fff8 bset imm8 ds +08d0 fff8 bset imm8 ais +08d8 fff8 bset imm8 aips +08e0 fff8 bset imm8 pais +08e8 fff8 bset imm8 das +08f0 fff8 bset imm8 dais +08f8 ffff bset imm8 adr16 +08f9 ffff bset imm8 adr32 +0a00 fff8 eori.b imm8 ds +0a10 fff8 eori.b imm8 ais +0a18 fff8 eori.b imm8 aips +0a20 fff8 eori.b imm8 pais +0a28 fff8 eori.b imm8 das +0a30 fff8 eori.b imm8 dais +0a38 ffff eori.b imm8 adr16 +0a39 ffff eori.b imm8 adr32 +0a3c ffff eori imm8 ccr +0a40 fff8 eori.w imm16 ds +0a50 fff8 eori.w imm16 ais +0a58 fff8 eori.w imm16 aips +0a60 fff8 eori.w imm16 pais +0a68 fff8 eori.w imm16 das +0a70 fff8 eori.w imm16 dais +0a78 ffff eori.w imm16 adr16 +0a79 ffff eori.w imm16 adr32 +0a7c ffff eori i16u sr +0a80 fff8 eori.l imm32 ds +0a90 fff8 eori.l imm32 ais +0a98 fff8 eori.l imm32 aips +0aa0 fff8 eori.l imm32 pais +0aa8 fff8 eori.l imm32 das +0ab0 fff8 eori.l imm32 dais +0ab8 ffff eori.l imm32 adr16 +0ab9 ffff eori.l imm32 adr32 +0c00 fff8 cmpi.b imm8 ds +0c10 fff8 cmpi.b imm8 ais +0c18 fff8 cmpi.b imm8 aips +0c20 fff8 cmpi.b imm8 pais +0c28 fff8 cmpi.b imm8 das +0c30 fff8 cmpi.b imm8 dais +0c38 ffff cmpi.b imm8 adr16 +0c39 ffff cmpi.b imm8 adr32 +0c40 fff8 cmpi.w imm16 ds +0c50 fff8 cmpi.w imm16 ais +0c58 fff8 cmpi.w imm16 aips +0c60 fff8 cmpi.w imm16 pais +0c68 fff8 cmpi.w imm16 das +0c70 fff8 cmpi.w imm16 dais +0c78 ffff cmpi.w imm16 adr16 +0c79 ffff cmpi.w imm16 adr32 +0c80 fff8 cmpi.l imm32 ds +0c90 fff8 cmpi.l imm32 ais +0c98 fff8 cmpi.l imm32 aips +0ca0 fff8 cmpi.l imm32 pais +0ca8 fff8 cmpi.l imm32 das +0cb0 fff8 cmpi.l imm32 dais +0cb8 ffff cmpi.l imm32 adr16 +0cb9 ffff cmpi.l imm32 adr32 +1000 f1f8 move.b ds dd +1010 f1f8 move.b ais dd +1018 f1f8 move.b aips dd +1020 f1f8 move.b pais dd +1028 f1f8 move.b das dd +1030 f1f8 move.b dais dd +1038 f1ff move.b adr16 dd +1039 f1ff move.b adr32 dd +103a f1ff move.b dpc dd +103b f1ff move.b dpci dd +103c f1ff move.b imm8 dd +1080 f1f8 move.b ds aid +1090 f1f8 move.b ais aid +1098 f1f8 move.b aips aid +10a0 f1f8 move.b pais aid +10a8 f1f8 move.b das aid +10b0 f1f8 move.b dais aid +10b8 f1ff move.b adr16 aid +10b9 f1ff move.b adr32 aid +10ba f1ff move.b dpc aid +10bb f1ff move.b dpci aid +10bc f1ff move.b imm8 aid +10c0 f1f8 move.b ds aipd +10d0 f1f8 move.b ais aipd +10d8 f1f8 move.b aips aipd +10e0 f1f8 move.b pais aipd +10e8 f1f8 move.b das aipd +10f0 f1f8 move.b dais aipd +10f8 f1ff move.b adr16 aipd +10f9 f1ff move.b adr32 aipd +10fa f1ff move.b dpc aipd +10fb f1ff move.b dpci aipd +10fc f1ff move.b imm8 aipd +1100 f1f8 move.b ds paid +1110 f1f8 move.b ais paid +1118 f1f8 move.b aips paid +1120 f1f8 move.b pais paid +1128 f1f8 move.b das paid +1130 f1f8 move.b dais paid +1138 f1ff move.b adr16 paid +1139 f1ff move.b adr32 paid +113a f1ff move.b dpc paid +113b f1ff move.b dpci paid +113c f1ff move.b imm8 paid +1140 f1f8 move.b ds dad +1150 f1f8 move.b ais dad +1158 f1f8 move.b aips dad +1160 f1f8 move.b pais dad +1168 f1f8 move.b das dad +1170 f1f8 move.b dais dad +1178 f1ff move.b adr16 dad +1179 f1ff move.b adr32 dad +117a f1ff move.b dpc dad +117b f1ff move.b dpci dad +117c f1ff move.b imm8 dad +1180 f1f8 move.b ds daid +1190 f1f8 move.b ais daid +1198 f1f8 move.b aips daid +11a0 f1f8 move.b pais daid +11a8 f1f8 move.b das daid +11b0 f1f8 move.b dais daid +11b8 f1ff move.b adr16 daid +11b9 f1ff move.b adr32 daid +11ba f1ff move.b dpc daid +11bb f1ff move.b dpci daid +11bc f1ff move.b imm8 daid +11c0 fff8 move.b ds adr16 +11d0 fff8 move.b ais adr16 +11d8 fff8 move.b aips adr16 +11e0 fff8 move.b pais adr16 +11e8 fff8 move.b das adr16 +11f0 fff8 move.b dais adr16 +11f8 ffff move.b adr16 adr16 +11f9 ffff move.b adr32 adr16 +11fa ffff move.b dpc adr16 +11fb ffff move.b dpci adr16 +11fc ffff move.b imm8 adr16 +13c0 fff8 move.b ds adr32 +13d0 fff8 move.b ais adr32 +13d8 fff8 move.b aips adr32 +13e0 fff8 move.b pais adr32 +13e8 fff8 move.b das adr32 +13f0 fff8 move.b dais adr32 +13f8 ffff move.b adr16 adr32 +13f9 ffff move.b adr32 adr32 +13fa ffff move.b dpc adr32 +13fb ffff move.b dpci adr32 +13fc ffff move.b imm8 adr32 +2000 f1f8 move.l ds dd +2008 f1f8 move.l as dd +2010 f1f8 move.l ais dd +2018 f1f8 move.l aips dd +2020 f1f8 move.l pais dd +2028 f1f8 move.l das dd +2030 f1f8 move.l dais dd +2038 f1ff move.l adr16 dd +2039 f1ff move.l adr32 dd +203a f1ff move.l dpc dd +203b f1ff move.l dpci dd +203c f1ff move.l imm32 dd +2040 f1f8 movea.l ds ad +2048 f1f8 movea.l as ad +2050 f1f8 movea.l ais ad +2058 f1f8 movea.l aips ad +2060 f1f8 movea.l pais ad +2068 f1f8 movea.l das ad +2070 f1f8 movea.l dais ad +2078 f1ff movea.l adr16 ad +2079 f1ff movea.l adr32 ad +207a f1ff movea.l dpc ad +207b f1ff movea.l dpci ad +207c f1ff movea.l imm32 ad +2080 f1f8 move.l ds aid +2088 f1f8 move.l as aid +2090 f1f8 move.l ais aid +2098 f1f8 move.l aips aid +20a0 f1f8 move.l pais aid +20a8 f1f8 move.l das aid +20b0 f1f8 move.l dais aid +20b8 f1ff move.l adr16 aid +20b9 f1ff move.l adr32 aid +20ba f1ff move.l dpc aid +20bb f1ff move.l dpci aid +20bc f1ff move.l imm32 aid +20c0 f1f8 move.l ds aipd +20c8 f1f8 move.l as aipd +20d0 f1f8 move.l ais aipd +20d8 f1f8 move.l aips aipd +20e0 f1f8 move.l pais aipd +20e8 f1f8 move.l das aipd +20f0 f1f8 move.l dais aipd +20f8 f1ff move.l adr16 aipd +20f9 f1ff move.l adr32 aipd +20fa f1ff move.l dpc aipd +20fb f1ff move.l dpci aipd +20fc f1ff move.l imm32 aipd +2100 f1f8 move.l ds paid +2108 f1f8 move.l as paid +2110 f1f8 move.l ais paid +2118 f1f8 move.l aips paid +2120 f1f8 move.l pais paid +2128 f1f8 move.l das paid +2130 f1f8 move.l dais paid +2138 f1ff move.l adr16 paid +2139 f1ff move.l adr32 paid +213a f1ff move.l dpc paid +213b f1ff move.l dpci paid +213c f1ff move.l imm32 paid +2140 f1f8 move.l ds dad +2148 f1f8 move.l as dad +2150 f1f8 move.l ais dad +2158 f1f8 move.l aips dad +2160 f1f8 move.l pais dad +2168 f1f8 move.l das dad +2170 f1f8 move.l dais dad +2178 f1ff move.l adr16 dad +2179 f1ff move.l adr32 dad +217a f1ff move.l dpc dad +217b f1ff move.l dpci dad +217c f1ff move.l imm32 dad +2180 f1f8 move.l ds daid +2188 f1f8 move.l as daid +2190 f1f8 move.l ais daid +2198 f1f8 move.l aips daid +21a0 f1f8 move.l pais daid +21a8 f1f8 move.l das daid +21b0 f1f8 move.l dais daid +21b8 f1ff move.l adr16 daid +21b9 f1ff move.l adr32 daid +21ba f1ff move.l dpc daid +21bb f1ff move.l dpci daid +21bc f1ff move.l imm32 daid +21c0 fff8 move.l ds adr16 +21c8 fff8 move.l as adr16 +21d0 fff8 move.l ais adr16 +21d8 fff8 move.l aips adr16 +21e0 fff8 move.l pais adr16 +21e8 fff8 move.l das adr16 +21f0 fff8 move.l dais adr16 +21f8 ffff move.l adr16 adr16 +21f9 ffff move.l adr32 adr16 +21fa ffff move.l dpc adr16 +21fb ffff move.l dpci adr16 +21fc ffff move.l imm32 adr16 +23c0 fff8 move.l ds adr32 +23c8 fff8 move.l as adr32 +23d0 fff8 move.l ais adr32 +23d8 fff8 move.l aips adr32 +23e0 fff8 move.l pais adr32 +23e8 fff8 move.l das adr32 +23f0 fff8 move.l dais adr32 +23f8 ffff move.l adr16 adr32 +23f9 ffff move.l adr32 adr32 +23fa ffff move.l dpc adr32 +23fb ffff move.l dpci adr32 +23fc ffff move.l imm32 adr32 +3000 f1f8 move.w ds dd +3008 f1f8 move.w as dd +3010 f1f8 move.w ais dd +3018 f1f8 move.w aips dd +3020 f1f8 move.w pais dd +3028 f1f8 move.w das dd +3030 f1f8 move.w dais dd +3038 f1ff move.w adr16 dd +3039 f1ff move.w adr32 dd +303a f1ff move.w dpc dd +303b f1ff move.w dpci dd +303c f1ff move.w imm16 dd +3040 f1f8 movea.w ds ad +3048 f1f8 movea.w as ad +3050 f1f8 movea.w ais ad +3058 f1f8 movea.w aips ad +3060 f1f8 movea.w pais ad +3068 f1f8 movea.w das ad +3070 f1f8 movea.w dais ad +3078 f1ff movea.w adr16 ad +3079 f1ff movea.w adr32 ad +307a f1ff movea.w dpc ad +307b f1ff movea.w dpci ad +307c f1ff movea.w imm16 ad +3080 f1f8 move.w ds aid +3088 f1f8 move.w as aid +3090 f1f8 move.w ais aid +3098 f1f8 move.w aips aid +30a0 f1f8 move.w pais aid +30a8 f1f8 move.w das aid +30b0 f1f8 move.w dais aid +30b8 f1ff move.w adr16 aid +30b9 f1ff move.w adr32 aid +30ba f1ff move.w dpc aid +30bb f1ff move.w dpci aid +30bc f1ff move.w imm16 aid +30c0 f1f8 move.w ds aipd +30c8 f1f8 move.w as aipd +30d0 f1f8 move.w ais aipd +30d8 f1f8 move.w aips aipd +30e0 f1f8 move.w pais aipd +30e8 f1f8 move.w das aipd +30f0 f1f8 move.w dais aipd +30f8 f1ff move.w adr16 aipd +30f9 f1ff move.w adr32 aipd +30fa f1ff move.w dpc aipd +30fb f1ff move.w dpci aipd +30fc f1ff move.w imm16 aipd +3100 f1f8 move.w ds paid +3108 f1f8 move.w as paid +3110 f1f8 move.w ais paid +3118 f1f8 move.w aips paid +3120 f1f8 move.w pais paid +3128 f1f8 move.w das paid +3130 f1f8 move.w dais paid +3138 f1ff move.w adr16 paid +3139 f1ff move.w adr32 paid +313a f1ff move.w dpc paid +313b f1ff move.w dpci paid +313c f1ff move.w imm16 paid +3140 f1f8 move.w ds dad +3148 f1f8 move.w as dad +3150 f1f8 move.w ais dad +3158 f1f8 move.w aips dad +3160 f1f8 move.w pais dad +3168 f1f8 move.w das dad +3170 f1f8 move.w dais dad +3178 f1ff move.w adr16 dad +3179 f1ff move.w adr32 dad +317a f1ff move.w dpc dad +317b f1ff move.w dpci dad +317c f1ff move.w imm16 dad +3180 f1f8 move.w ds daid +3188 f1f8 move.w as daid +3190 f1f8 move.w ais daid +3198 f1f8 move.w aips daid +31a0 f1f8 move.w pais daid +31a8 f1f8 move.w das daid +31b0 f1f8 move.w dais daid +31b8 f1ff move.w adr16 daid +31b9 f1ff move.w adr32 daid +31ba f1ff move.w dpc daid +31bb f1ff move.w dpci daid +31bc f1ff move.w imm16 daid +31c0 fff8 move.w ds adr16 +31c8 fff8 move.w as adr16 +31d0 fff8 move.w ais adr16 +31d8 fff8 move.w aips adr16 +31e0 fff8 move.w pais adr16 +31e8 fff8 move.w das adr16 +31f0 fff8 move.w dais adr16 +31f8 ffff move.w adr16 adr16 +31f9 ffff move.w adr32 adr16 +31fa ffff move.w dpc adr16 +31fb ffff move.w dpci adr16 +31fc ffff move.w imm16 adr16 +33c0 fff8 move.w ds adr32 +33c8 fff8 move.w as adr32 +33d0 fff8 move.w ais adr32 +33d8 fff8 move.w aips adr32 +33e0 fff8 move.w pais adr32 +33e8 fff8 move.w das adr32 +33f0 fff8 move.w dais adr32 +33f8 ffff move.w adr16 adr32 +33f9 ffff move.w adr32 adr32 +33fa ffff move.w dpc adr32 +33fb ffff move.w dpci adr32 +33fc ffff move.w imm16 adr32 +4000 fff8 negx.b ds - +4010 fff8 negx.b ais - +4018 fff8 negx.b aips - +4020 fff8 negx.b pais - +4028 fff8 negx.b das - +4030 fff8 negx.b dais - +4038 ffff negx.b adr16 - +4039 ffff negx.b adr32 - +4040 fff8 negx.w ds - +4050 fff8 negx.w ais - +4058 fff8 negx.w aips - +4060 fff8 negx.w pais - +4068 fff8 negx.w das - +4070 fff8 negx.w dais - +4078 ffff negx.w adr16 - +4079 ffff negx.w adr32 - +4080 fff8 negx.l ds - +4090 fff8 negx.l ais - +4098 fff8 negx.l aips - +40a0 fff8 negx.l pais - +40a8 fff8 negx.l das - +40b0 fff8 negx.l dais - +40b8 ffff negx.l adr16 - +40b9 ffff negx.l adr32 - +40c0 fff8 move sr ds +40d0 fff8 move sr ais +40d8 fff8 move sr aips +40e0 fff8 move sr pais +40e8 fff8 move sr das +40f0 fff8 move sr dais +40f8 ffff move sr adr16 +40f9 ffff move sr adr32 +4180 f1f8 chk.w ds dd +4190 f1f8 chk.w ais dd +4198 f1f8 chk.w aips dd +41a0 f1f8 chk.w pais dd +41a8 f1f8 chk.w das dd +41b0 f1f8 chk.w dais dd +41b8 f1ff chk.w adr16 dd +41b9 f1ff chk.w adr32 dd +41ba f1ff chk.w dpc dd +41bb f1ff chk.w dpci dd +41bc f1ff chk.w imm16 dd +41d0 f1f8 lea ais ad +41e8 f1f8 lea das ad +41f0 f1f8 lea dais ad +41f8 f1ff lea adr16 ad +41f9 f1ff lea adr32 ad +41fa f1ff lea dpc ad +41fb f1ff lea dpci ad +4200 fff8 clr.b ds - +4210 fff8 clr.b ais - +4218 fff8 clr.b aips - +4220 fff8 clr.b pais - +4228 fff8 clr.b das - +4230 fff8 clr.b dais - +4238 ffff clr.b adr16 - +4239 ffff clr.b adr32 - +4240 fff8 clr.w ds - +4250 fff8 clr.w ais - +4258 fff8 clr.w aips - +4260 fff8 clr.w pais - +4268 fff8 clr.w das - +4270 fff8 clr.w dais - +4278 ffff clr.w adr16 - +4279 ffff clr.w adr32 - +4280 fff8 clr.l ds - +4290 fff8 clr.l ais - +4298 fff8 clr.l aips - +42a0 fff8 clr.l pais - +42a8 fff8 clr.l das - +42b0 fff8 clr.l dais - +42b8 ffff clr.l adr16 - +42b9 ffff clr.l adr32 - +4400 fff8 neg.b ds - +4410 fff8 neg.b ais - +4418 fff8 neg.b aips - +4420 fff8 neg.b pais - +4428 fff8 neg.b das - +4430 fff8 neg.b dais - +4438 ffff neg.b adr16 - +4439 ffff neg.b adr32 - +4440 fff8 neg.w ds - +4450 fff8 neg.w ais - +4458 fff8 neg.w aips - +4460 fff8 neg.w pais - +4468 fff8 neg.w das - +4470 fff8 neg.w dais - +4478 ffff neg.w adr16 - +4479 ffff neg.w adr32 - +4480 fff8 neg.l ds - +4490 fff8 neg.l ais - +4498 fff8 neg.l aips - +44a0 fff8 neg.l pais - +44a8 fff8 neg.l das - +44b0 fff8 neg.l dais - +44b8 ffff neg.l adr16 - +44b9 ffff neg.l adr32 - +44c0 fff8 move ds ccr +44d0 fff8 move ais ccr +44d8 fff8 move aips ccr +44e0 fff8 move pais ccr +44e8 fff8 move das ccr +44f0 fff8 move dais ccr +44f8 ffff move adr16 ccr +44f9 ffff move adr32 ccr +44fa ffff move dpc ccr +44fb ffff move dpci ccr +44fc ffff move imm8 ccr +4600 fff8 not.b ds - +4610 fff8 not.b ais - +4618 fff8 not.b aips - +4620 fff8 not.b pais - +4628 fff8 not.b das - +4630 fff8 not.b dais - +4638 ffff not.b adr16 - +4639 ffff not.b adr32 - +4640 fff8 not.w ds - +4650 fff8 not.w ais - +4658 fff8 not.w aips - +4660 fff8 not.w pais - +4668 fff8 not.w das - +4670 fff8 not.w dais - +4678 ffff not.w adr16 - +4679 ffff not.w adr32 - +4680 fff8 not.l ds - +4690 fff8 not.l ais - +4698 fff8 not.l aips - +46a0 fff8 not.l pais - +46a8 fff8 not.l das - +46b0 fff8 not.l dais - +46b8 ffff not.l adr16 - +46b9 ffff not.l adr32 - +46c0 fff8 move ds sr +46d0 fff8 move ais sr +46d8 fff8 move aips sr +46e0 fff8 move pais sr +46e8 fff8 move das sr +46f0 fff8 move dais sr +46f8 ffff move adr16 sr +46f9 ffff move adr32 sr +46fa ffff move dpc sr +46fb ffff move dpci sr +46fc ffff move i16u sr +4800 fff8 nbcd.b ds - +4810 fff8 nbcd.b ais - +4818 fff8 nbcd.b aips - +4820 fff8 nbcd.b pais - +4828 fff8 nbcd.b das - +4830 fff8 nbcd.b dais - +4838 ffff nbcd.b adr16 - +4839 ffff nbcd.b adr32 - +4840 fff8 swap ds - +4850 fff8 pea ais - +4868 fff8 pea das - +4870 fff8 pea dais - +4878 ffff pea adr16 - +4879 ffff pea adr32 - +487a ffff pea dpc - +487b ffff pea dpci - +4880 fff8 ext.w ds - +4890 fff8 movem.w list ais +48a0 fff8 movem.w listp pais +48a8 fff8 movem.w list das +48b0 fff8 movem.w list dais +48b8 ffff movem.w list adr16 +48b9 ffff movem.w list adr32 +48c0 fff8 ext.l ds - +48d0 fff8 movem.l list ais +48e0 fff8 movem.l listp pais +48e8 fff8 movem.l list das +48f0 fff8 movem.l list dais +48f8 ffff movem.l list adr16 +48f9 ffff movem.l list adr32 +4a00 fff8 tst.b ds - +4a10 fff8 tst.b ais - +4a18 fff8 tst.b aips - +4a20 fff8 tst.b pais - +4a28 fff8 tst.b das - +4a30 fff8 tst.b dais - +4a38 ffff tst.b adr16 - +4a39 ffff tst.b adr32 - +4a40 fff8 tst.w ds - +4a50 fff8 tst.w ais - +4a58 fff8 tst.w aips - +4a60 fff8 tst.w pais - +4a68 fff8 tst.w das - +4a70 fff8 tst.w dais - +4a78 ffff tst.w adr16 - +4a79 ffff tst.w adr32 - +4a80 fff8 tst.l ds - +4a90 fff8 tst.l ais - +4a98 fff8 tst.l aips - +4aa0 fff8 tst.l pais - +4aa8 fff8 tst.l das - +4ab0 fff8 tst.l dais - +4ab8 ffff tst.l adr16 - +4ab9 ffff tst.l adr32 - +4ac0 fff8 tas ds - +4ad0 fff8 tas ais - +4ad8 fff8 tas aips - +4ae0 fff8 tas pais - +4ae8 fff8 tas das - +4af0 fff8 tas dais - +4af8 ffff tas adr16 - +4af9 ffff tas adr32 - +4afc ffff illegal - - +4c90 fff8 movem.w ais list +4c98 fff8 movem.w aips list +4ca8 fff8 movem.w das list +4cb0 fff8 movem.w dais list +4cb8 ffff movem.w adr16 list +4cb9 ffff movem.w adr32 list +4cba ffff movem.w dpc list +4cbb ffff movem.w dpci list +4cd0 fff8 movem.l ais list +4cd8 fff8 movem.l aips list +4ce8 fff8 movem.l das list +4cf0 fff8 movem.l dais list +4cf8 ffff movem.l adr16 list +4cf9 ffff movem.l adr32 list +4cfa ffff movem.l dpc list +4cfb ffff movem.l dpci list +4e40 fff0 trap imm4 - +4e50 fff8 link as imm16 +4e58 fff8 unlk as - +4e60 fff8 move as usp +4e68 fff8 move usp as +4e70 ffff reset - - +4e71 ffff nop - - +4e72 ffff stop i16u - +4e73 ffff rte - - +4e75 ffff rts - - +4e76 ffff trapv - - +4e77 ffff rtr - - +4e90 fff8 jsr ais - +4ea8 fff8 jsr das - +4eb0 fff8 jsr dais - +4eb8 ffff jsr adr16 - +4eb9 ffff jsr adr32 - +4eba ffff jsr dpc - +4ebb ffff jsr dpci - +4ed0 fff8 jmp ais - +4ee8 fff8 jmp das - +4ef0 fff8 jmp dais - +4ef8 ffff jmp adr16 - +4ef9 ffff jmp adr32 - +4efa ffff jmp dpc - +4efb ffff jmp dpci - +5000 f1f8 addq.b imm3 ds +5010 f1f8 addq.b imm3 ais +5018 f1f8 addq.b imm3 aips +5020 f1f8 addq.b imm3 pais +5028 f1f8 addq.b imm3 das +5030 f1f8 addq.b imm3 dais +5038 f1ff addq.b imm3 adr16 +5039 f1ff addq.b imm3 adr32 +5040 f1f8 addq.w imm3 ds +5048 f1f8 addq.w imm3 as +5050 f1f8 addq.w imm3 ais +5058 f1f8 addq.w imm3 aips +5060 f1f8 addq.w imm3 pais +5068 f1f8 addq.w imm3 das +5070 f1f8 addq.w imm3 dais +5078 f1ff addq.w imm3 adr16 +5079 f1ff addq.w imm3 adr32 +5080 f1f8 addq.l imm3 ds +5088 f1f8 addq.l imm3 as +5090 f1f8 addq.l imm3 ais +5098 f1f8 addq.l imm3 aips +50a0 f1f8 addq.l imm3 pais +50a8 f1f8 addq.l imm3 das +50b0 f1f8 addq.l imm3 dais +50b8 f1ff addq.l imm3 adr16 +50b9 f1ff addq.l imm3 adr32 +50c0 fff8 st ds - +50c8 fff8 dbt ds rel16 +50d0 fff8 st ais - +50d8 fff8 st aips - +50e0 fff8 st pais - +50e8 fff8 st das - +50f0 fff8 st dais - +50f8 ffff st adr16 - +50f9 ffff st adr32 - +5100 f1f8 subq.b imm3 ds +5110 f1f8 subq.b imm3 ais +5118 f1f8 subq.b imm3 aips +5120 f1f8 subq.b imm3 pais +5128 f1f8 subq.b imm3 das +5130 f1f8 subq.b imm3 dais +5138 f1ff subq.b imm3 adr16 +5139 f1ff subq.b imm3 adr32 +5140 f1f8 subq.w imm3 ds +5148 f1f8 subq.w imm3 as +5150 f1f8 subq.w imm3 ais +5158 f1f8 subq.w imm3 aips +5160 f1f8 subq.w imm3 pais +5168 f1f8 subq.w imm3 das +5170 f1f8 subq.w imm3 dais +5178 f1ff subq.w imm3 adr16 +5179 f1ff subq.w imm3 adr32 +5180 f1f8 subq.l imm3 ds +5188 f1f8 subq.l imm3 as +5190 f1f8 subq.l imm3 ais +5198 f1f8 subq.l imm3 aips +51a0 f1f8 subq.l imm3 pais +51a8 f1f8 subq.l imm3 das +51b0 f1f8 subq.l imm3 dais +51b8 f1ff subq.l imm3 adr16 +51b9 f1ff subq.l imm3 adr32 +51c0 fff8 sf ds - +51c8 fff8 dbra ds rel16 +51d0 fff8 sf ais - +51d8 fff8 sf aips - +51e0 fff8 sf pais - +51e8 fff8 sf das - +51f0 fff8 sf dais - +51f8 ffff sf adr16 - +51f9 ffff sf adr32 - +52c0 fff8 shi ds - +52c8 fff8 dbhi ds rel16 +52d0 fff8 shi ais - +52d8 fff8 shi aips - +52e0 fff8 shi pais - +52e8 fff8 shi das - +52f0 fff8 shi dais - +52f8 ffff shi adr16 - +52f9 ffff shi adr32 - +53c0 fff8 sls ds - +53c8 fff8 dbls ds rel16 +53d0 fff8 sls ais - +53d8 fff8 sls aips - +53e0 fff8 sls pais - +53e8 fff8 sls das - +53f0 fff8 sls dais - +53f8 ffff sls adr16 - +53f9 ffff sls adr32 - +54c0 fff8 scc ds - +54c8 fff8 dbcc ds rel16 +54d0 fff8 scc ais - +54d8 fff8 scc aips - +54e0 fff8 scc pais - +54e8 fff8 scc das - +54f0 fff8 scc dais - +54f8 ffff scc adr16 - +54f9 ffff scc adr32 - +55c0 fff8 scs ds - +55c8 fff8 dbcs ds rel16 +55d0 fff8 scs ais - +55d8 fff8 scs aips - +55e0 fff8 scs pais - +55e8 fff8 scs das - +55f0 fff8 scs dais - +55f8 ffff scs adr16 - +55f9 ffff scs adr32 - +56c0 fff8 sne ds - +56c8 fff8 dbne ds rel16 +56d0 fff8 sne ais - +56d8 fff8 sne aips - +56e0 fff8 sne pais - +56e8 fff8 sne das - +56f0 fff8 sne dais - +56f8 ffff sne adr16 - +56f9 ffff sne adr32 - +57c0 fff8 seq ds - +57c8 fff8 dbeq ds rel16 +57d0 fff8 seq ais - +57d8 fff8 seq aips - +57e0 fff8 seq pais - +57e8 fff8 seq das - +57f0 fff8 seq dais - +57f8 ffff seq adr16 - +57f9 ffff seq adr32 - +58c0 fff8 svc ds - +58c8 fff8 dbvc ds rel16 +58d0 fff8 svc ais - +58d8 fff8 svc aips - +58e0 fff8 svc pais - +58e8 fff8 svc das - +58f0 fff8 svc dais - +58f8 ffff svc adr16 - +58f9 ffff svc adr32 - +59c0 fff8 svs ds - +59c8 fff8 dbvs ds rel16 +59d0 fff8 svs ais - +59d8 fff8 svs aips - +59e0 fff8 svs pais - +59e8 fff8 svs das - +59f0 fff8 svs dais - +59f8 ffff svs adr16 - +59f9 ffff svs adr32 - +5ac0 fff8 spl ds - +5ac8 fff8 dbpl ds rel16 +5ad0 fff8 spl ais - +5ad8 fff8 spl aips - +5ae0 fff8 spl pais - +5ae8 fff8 spl das - +5af0 fff8 spl dais - +5af8 ffff spl adr16 - +5af9 ffff spl adr32 - +5bc0 fff8 smi ds - +5bc8 fff8 dbmi ds rel16 +5bd0 fff8 smi ais - +5bd8 fff8 smi aips - +5be0 fff8 smi pais - +5be8 fff8 smi das - +5bf0 fff8 smi dais - +5bf8 ffff smi adr16 - +5bf9 ffff smi adr32 - +5cc0 fff8 sge ds - +5cc8 fff8 dbge ds rel16 +5cd0 fff8 sge ais - +5cd8 fff8 sge aips - +5ce0 fff8 sge pais - +5ce8 fff8 sge das - +5cf0 fff8 sge dais - +5cf8 ffff sge adr16 - +5cf9 ffff sge adr32 - +5dc0 fff8 slt ds - +5dc8 fff8 dblt ds rel16 +5dd0 fff8 slt ais - +5dd8 fff8 slt aips - +5de0 fff8 slt pais - +5de8 fff8 slt das - +5df0 fff8 slt dais - +5df8 ffff slt adr16 - +5df9 ffff slt adr32 - +5ec0 fff8 sgt ds - +5ec8 fff8 dbgt ds rel16 +5ed0 fff8 sgt ais - +5ed8 fff8 sgt aips - +5ee0 fff8 sgt pais - +5ee8 fff8 sgt das - +5ef0 fff8 sgt dais - +5ef8 ffff sgt adr16 - +5ef9 ffff sgt adr32 - +5fc0 fff8 sle ds - +5fc8 fff8 dble ds rel16 +5fd0 fff8 sle ais - +5fd8 fff8 sle aips - +5fe0 fff8 sle pais - +5fe8 fff8 sle das - +5ff0 fff8 sle dais - +5ff8 ffff sle adr16 - +5ff9 ffff sle adr32 - +6000 ffff bra rel16 - +6000 ff00 bra rel8 - +6100 ffff bsr rel16 - +6100 ff00 bsr rel8 - +6200 ffff bhi rel16 - +6200 ff00 bhi rel8 - +6300 ffff bls rel16 - +6300 ff00 bls rel8 - +6400 ffff bcc rel16 - +6400 ff00 bcc rel8 - +6500 ffff bcs rel16 - +6500 ff00 bcs rel8 - +6600 ffff bne rel16 - +6600 ff00 bne rel8 - +6700 ffff beq rel16 - +6700 ff00 beq rel8 - +6800 ffff bvc rel16 - +6800 ff00 bvc rel8 - +6900 ffff bvs rel16 - +6900 ff00 bvs rel8 - +6a00 ffff bpl rel16 - +6a00 ff00 bpl rel8 - +6b00 ffff bmi rel16 - +6b00 ff00 bmi rel8 - +6c00 ffff bge rel16 - +6c00 ff00 bge rel8 - +6d00 ffff blt rel16 - +6d00 ff00 blt rel8 - +6e00 ffff bgt rel16 - +6e00 ff00 bgt rel8 - +6f00 ffff ble rel16 - +6f00 ff00 ble rel8 - +7000 f100 moveq imm8o dd +8000 f1f8 or.b ds dd +8010 f1f8 or.b ais dd +8018 f1f8 or.b aips dd +8020 f1f8 or.b pais dd +8028 f1f8 or.b das dd +8030 f1f8 or.b dais dd +8038 f1ff or.b adr16 dd +8039 f1ff or.b adr32 dd +803a f1ff or.b dpc dd +803b f1ff or.b dpci dd +803c f1ff or.b imm8 dd +8040 f1f8 or.w ds dd +8050 f1f8 or.w ais dd +8058 f1f8 or.w aips dd +8060 f1f8 or.w pais dd +8068 f1f8 or.w das dd +8070 f1f8 or.w dais dd +8078 f1ff or.w adr16 dd +8079 f1ff or.w adr32 dd +807a f1ff or.w dpc dd +807b f1ff or.w dpci dd +807c f1ff or.w imm16 dd +8080 f1f8 or.l ds dd +8090 f1f8 or.l ais dd +8098 f1f8 or.l aips dd +80a0 f1f8 or.l pais dd +80a8 f1f8 or.l das dd +80b0 f1f8 or.l dais dd +80b8 f1ff or.l adr16 dd +80b9 f1ff or.l adr32 dd +80ba f1ff or.l dpc dd +80bb f1ff or.l dpci dd +80bc f1ff or.l imm32 dd +80c0 f1f8 divu.w ds dd +80d0 f1f8 divu.w ais dd +80d8 f1f8 divu.w aips dd +80e0 f1f8 divu.w pais dd +80e8 f1f8 divu.w das dd +80f0 f1f8 divu.w dais dd +80f8 f1ff divu.w adr16 dd +80f9 f1ff divu.w adr32 dd +80fa f1ff divu.w dpc dd +80fb f1ff divu.w dpci dd +80fc f1ff divu.w imm16 dd +8100 f1f8 sbcd ds dd +8108 f1f8 sbcd pais paid +8110 f1f8 or.b dd ais +8118 f1f8 or.b dd aips +8120 f1f8 or.b dd pais +8128 f1f8 or.b dd das +8130 f1f8 or.b dd dais +8138 f1ff or.b dd adr16 +8139 f1ff or.b dd adr32 +8150 f1f8 or.w dd ais +8158 f1f8 or.w dd aips +8160 f1f8 or.w dd pais +8168 f1f8 or.w dd das +8170 f1f8 or.w dd dais +8178 f1ff or.w dd adr16 +8179 f1ff or.w dd adr32 +8190 f1f8 or.l dd ais +8198 f1f8 or.l dd aips +81a0 f1f8 or.l dd pais +81a8 f1f8 or.l dd das +81b0 f1f8 or.l dd dais +81b8 f1ff or.l dd adr16 +81b9 f1ff or.l dd adr32 +81c0 f1f8 divs.w ds dd +81d0 f1f8 divs.w ais dd +81d8 f1f8 divs.w aips dd +81e0 f1f8 divs.w pais dd +81e8 f1f8 divs.w das dd +81f0 f1f8 divs.w dais dd +81f8 f1ff divs.w adr16 dd +81f9 f1ff divs.w adr32 dd +81fa f1ff divs.w dpc dd +81fb f1ff divs.w dpci dd +81fc f1ff divs.w imm16 dd +9000 f1f8 sub.b ds dd +9010 f1f8 sub.b ais dd +9018 f1f8 sub.b aips dd +9020 f1f8 sub.b pais dd +9028 f1f8 sub.b das dd +9030 f1f8 sub.b dais dd +9038 f1ff sub.b adr16 dd +9039 f1ff sub.b adr32 dd +903a f1ff sub.b dpc dd +903b f1ff sub.b dpci dd +903c f1ff sub.b imm8 dd +9040 f1f8 sub.w ds dd +9048 f1f8 sub.w as dd +9050 f1f8 sub.w ais dd +9058 f1f8 sub.w aips dd +9060 f1f8 sub.w pais dd +9068 f1f8 sub.w das dd +9070 f1f8 sub.w dais dd +9078 f1ff sub.w adr16 dd +9079 f1ff sub.w adr32 dd +907a f1ff sub.w dpc dd +907b f1ff sub.w dpci dd +907c f1ff sub.w imm16 dd +9080 f1f8 sub.l ds dd +9088 f1f8 sub.l as dd +9090 f1f8 sub.l ais dd +9098 f1f8 sub.l aips dd +90a0 f1f8 sub.l pais dd +90a8 f1f8 sub.l das dd +90b0 f1f8 sub.l dais dd +90b8 f1ff sub.l adr16 dd +90b9 f1ff sub.l adr32 dd +90ba f1ff sub.l dpc dd +90bb f1ff sub.l dpci dd +90bc f1ff sub.l imm32 dd +90c0 f1f8 suba.w ds ad +90c8 f1f8 suba.w as ad +90d0 f1f8 suba.w ais ad +90d8 f1f8 suba.w aips ad +90e0 f1f8 suba.w pais ad +90e8 f1f8 suba.w das ad +90f0 f1f8 suba.w dais ad +90f8 f1ff suba.w adr16 ad +90f9 f1ff suba.w adr32 ad +90fa f1ff suba.w dpc ad +90fb f1ff suba.w dpci ad +90fc f1ff suba.w imm16 ad +9100 f1f8 subx.b ds dd +9108 f1f8 subx.b pais paid +9110 f1f8 sub.b dd ais +9118 f1f8 sub.b dd aips +9120 f1f8 sub.b dd pais +9128 f1f8 sub.b dd das +9130 f1f8 sub.b dd dais +9138 f1ff sub.b dd adr16 +9139 f1ff sub.b dd adr32 +9140 f1f8 subx.w ds dd +9148 f1f8 subx.w pais paid +9150 f1f8 sub.w dd ais +9158 f1f8 sub.w dd aips +9160 f1f8 sub.w dd pais +9168 f1f8 sub.w dd das +9170 f1f8 sub.w dd dais +9178 f1ff sub.w dd adr16 +9179 f1ff sub.w dd adr32 +9180 f1f8 subx.l ds dd +9188 f1f8 subx.l pais paid +9190 f1f8 sub.l dd ais +9198 f1f8 sub.l dd aips +91a0 f1f8 sub.l dd pais +91a8 f1f8 sub.l dd das +91b0 f1f8 sub.l dd dais +91b8 f1ff sub.l dd adr16 +91b9 f1ff sub.l dd adr32 +91c0 f1f8 suba.l ds ad +91c8 f1f8 suba.l as ad +91d0 f1f8 suba.l ais ad +91d8 f1f8 suba.l aips ad +91e0 f1f8 suba.l pais ad +91e8 f1f8 suba.l das ad +91f0 f1f8 suba.l dais ad +91f8 f1ff suba.l adr16 ad +91f9 f1ff suba.l adr32 ad +91fa f1ff suba.l dpc ad +91fb f1ff suba.l dpci ad +91fc f1ff suba.l imm32 ad +a000 f000 linea imm12 - +b000 f1f8 cmp.b ds dd +b010 f1f8 cmp.b ais dd +b018 f1f8 cmp.b aips dd +b020 f1f8 cmp.b pais dd +b028 f1f8 cmp.b das dd +b030 f1f8 cmp.b dais dd +b038 f1ff cmp.b adr16 dd +b039 f1ff cmp.b adr32 dd +b03a f1ff cmp.b dpc dd +b03b f1ff cmp.b dpci dd +b03c f1ff cmp.b imm8 dd +b040 f1f8 cmp.w ds dd +b048 f1f8 cmp.w as dd +b050 f1f8 cmp.w ais dd +b058 f1f8 cmp.w aips dd +b060 f1f8 cmp.w pais dd +b068 f1f8 cmp.w das dd +b070 f1f8 cmp.w dais dd +b078 f1ff cmp.w adr16 dd +b079 f1ff cmp.w adr32 dd +b07a f1ff cmp.w dpc dd +b07b f1ff cmp.w dpci dd +b07c f1ff cmp.w imm16 dd +b080 f1f8 cmp.l ds dd +b088 f1f8 cmp.l as dd +b090 f1f8 cmp.l ais dd +b098 f1f8 cmp.l aips dd +b0a0 f1f8 cmp.l pais dd +b0a8 f1f8 cmp.l das dd +b0b0 f1f8 cmp.l dais dd +b0b8 f1ff cmp.l adr16 dd +b0b9 f1ff cmp.l adr32 dd +b0ba f1ff cmp.l dpc dd +b0bb f1ff cmp.l dpci dd +b0bc f1ff cmp.l imm32 dd +b0c0 f1f8 cmpa.w ds ad +b0c8 f1f8 cmpa.w as ad +b0d0 f1f8 cmpa.w ais ad +b0d8 f1f8 cmpa.w aips ad +b0e0 f1f8 cmpa.w pais ad +b0e8 f1f8 cmpa.w das ad +b0f0 f1f8 cmpa.w dais ad +b0f8 f1ff cmpa.w adr16 ad +b0f9 f1ff cmpa.w adr32 ad +b0fa f1ff cmpa.w dpc ad +b0fb f1ff cmpa.w dpci ad +b0fc f1ff cmpa.w imm16 ad +b100 f1f8 eor.b dd ds +b108 f1f8 cmpm.b aips aipd +b110 f1f8 eor.b dd ais +b118 f1f8 eor.b dd aips +b120 f1f8 eor.b dd pais +b128 f1f8 eor.b dd das +b130 f1f8 eor.b dd dais +b138 f1ff eor.b dd adr16 +b139 f1ff eor.b dd adr32 +b140 f1f8 eor.w dd ds +b148 f1f8 cmpm.w aips aipd +b150 f1f8 eor.w dd ais +b158 f1f8 eor.w dd aips +b160 f1f8 eor.w dd pais +b168 f1f8 eor.w dd das +b170 f1f8 eor.w dd dais +b178 f1ff eor.w dd adr16 +b179 f1ff eor.w dd adr32 +b180 f1f8 eor.l dd ds +b188 f1f8 cmpm.l aips aipd +b190 f1f8 eor.l dd ais +b198 f1f8 eor.l dd aips +b1a0 f1f8 eor.l dd pais +b1a8 f1f8 eor.l dd das +b1b0 f1f8 eor.l dd dais +b1b8 f1ff eor.l dd adr16 +b1b9 f1ff eor.l dd adr32 +b1c0 f1f8 cmpa.l ds ad +b1c8 f1f8 cmpa.l as ad +b1d0 f1f8 cmpa.l ais ad +b1d8 f1f8 cmpa.l aips ad +b1e0 f1f8 cmpa.l pais ad +b1e8 f1f8 cmpa.l das ad +b1f0 f1f8 cmpa.l dais ad +b1f8 f1ff cmpa.l adr16 ad +b1f9 f1ff cmpa.l adr32 ad +b1fa f1ff cmpa.l dpc ad +b1fb f1ff cmpa.l dpci ad +b1fc f1ff cmpa.l imm32 ad +c000 f1f8 and.b ds dd +c010 f1f8 and.b ais dd +c018 f1f8 and.b aips dd +c020 f1f8 and.b pais dd +c028 f1f8 and.b das dd +c030 f1f8 and.b dais dd +c038 f1ff and.b adr16 dd +c039 f1ff and.b adr32 dd +c03a f1ff and.b dpc dd +c03b f1ff and.b dpci dd +c03c f1ff and.b imm8 dd +c040 f1f8 and.w ds dd +c050 f1f8 and.w ais dd +c058 f1f8 and.w aips dd +c060 f1f8 and.w pais dd +c068 f1f8 and.w das dd +c070 f1f8 and.w dais dd +c078 f1ff and.w adr16 dd +c079 f1ff and.w adr32 dd +c07a f1ff and.w dpc dd +c07b f1ff and.w dpci dd +c07c f1ff and.w imm16 dd +c080 f1f8 and.l ds dd +c090 f1f8 and.l ais dd +c098 f1f8 and.l aips dd +c0a0 f1f8 and.l pais dd +c0a8 f1f8 and.l das dd +c0b0 f1f8 and.l dais dd +c0b8 f1ff and.l adr16 dd +c0b9 f1ff and.l adr32 dd +c0ba f1ff and.l dpc dd +c0bb f1ff and.l dpci dd +c0bc f1ff and.l imm32 dd +c0c0 f1f8 mulu.w ds dd +c0d0 f1f8 mulu.w ais dd +c0d8 f1f8 mulu.w aips dd +c0e0 f1f8 mulu.w pais dd +c0e8 f1f8 mulu.w das dd +c0f0 f1f8 mulu.w dais dd +c0f8 f1ff mulu.w adr16 dd +c0f9 f1ff mulu.w adr32 dd +c0fa f1ff mulu.w dpc dd +c0fb f1ff mulu.w dpci dd +c0fc f1ff mulu.w imm16 dd +c100 f1f8 abcd ds dd +c108 f1f8 abcd pais paid +c110 f1f8 and.b dd ais +c118 f1f8 and.b dd aips +c120 f1f8 and.b dd pais +c128 f1f8 and.b dd das +c130 f1f8 and.b dd dais +c138 f1ff and.b dd adr16 +c139 f1ff and.b dd adr32 +c140 f1f8 exg dd ds +c148 f1f8 exg ad as +c150 f1f8 and.w dd ais +c158 f1f8 and.w dd aips +c160 f1f8 and.w dd pais +c168 f1f8 and.w dd das +c170 f1f8 and.w dd dais +c178 f1ff and.w dd adr16 +c179 f1ff and.w dd adr32 +c188 f1f8 exg dd as +c190 f1f8 and.l dd ais +c198 f1f8 and.l dd aips +c1a0 f1f8 and.l dd pais +c1a8 f1f8 and.l dd das +c1b0 f1f8 and.l dd dais +c1b8 f1ff and.l dd adr16 +c1b9 f1ff and.l dd adr32 +c1c0 f1f8 muls.w ds dd +c1d0 f1f8 muls.w ais dd +c1d8 f1f8 muls.w aips dd +c1e0 f1f8 muls.w pais dd +c1e8 f1f8 muls.w das dd +c1f0 f1f8 muls.w dais dd +c1f8 f1ff muls.w adr16 dd +c1f9 f1ff muls.w adr32 dd +c1fa f1ff muls.w dpc dd +c1fb f1ff muls.w dpci dd +c1fc f1ff muls.w imm16 dd +d000 f1f8 add.b ds dd +d010 f1f8 add.b ais dd +d018 f1f8 add.b aips dd +d020 f1f8 add.b pais dd +d028 f1f8 add.b das dd +d030 f1f8 add.b dais dd +d038 f1ff add.b adr16 dd +d039 f1ff add.b adr32 dd +d03a f1ff add.b dpc dd +d03b f1ff add.b dpci dd +d03c f1ff add.b imm8 dd +d040 f1f8 add.w ds dd +d048 f1f8 add.w as dd +d050 f1f8 add.w ais dd +d058 f1f8 add.w aips dd +d060 f1f8 add.w pais dd +d068 f1f8 add.w das dd +d070 f1f8 add.w dais dd +d078 f1ff add.w adr16 dd +d079 f1ff add.w adr32 dd +d07a f1ff add.w dpc dd +d07b f1ff add.w dpci dd +d07c f1ff add.w imm16 dd +d080 f1f8 add.l ds dd +d088 f1f8 add.l as dd +d090 f1f8 add.l ais dd +d098 f1f8 add.l aips dd +d0a0 f1f8 add.l pais dd +d0a8 f1f8 add.l das dd +d0b0 f1f8 add.l dais dd +d0b8 f1ff add.l adr16 dd +d0b9 f1ff add.l adr32 dd +d0ba f1ff add.l dpc dd +d0bb f1ff add.l dpci dd +d0bc f1ff add.l imm32 dd +d0c0 f1f8 adda.w ds ad +d0c8 f1f8 adda.w as ad +d0d0 f1f8 adda.w ais ad +d0d8 f1f8 adda.w aips ad +d0e0 f1f8 adda.w pais ad +d0e8 f1f8 adda.w das ad +d0f0 f1f8 adda.w dais ad +d0f8 f1ff adda.w adr16 ad +d0f9 f1ff adda.w adr32 ad +d0fa f1ff adda.w dpc ad +d0fb f1ff adda.w dpci ad +d0fc f1ff adda.w imm16 ad +d100 f1f8 addx.b ds dd +d108 f1f8 addx.b pais paid +d110 f1f8 add.b dd ais +d118 f1f8 add.b dd aips +d120 f1f8 add.b dd pais +d128 f1f8 add.b dd das +d130 f1f8 add.b dd dais +d138 f1ff add.b dd adr16 +d139 f1ff add.b dd adr32 +d140 f1f8 addx.w ds dd +d148 f1f8 addx.w pais paid +d150 f1f8 add.w dd ais +d158 f1f8 add.w dd aips +d160 f1f8 add.w dd pais +d168 f1f8 add.w dd das +d170 f1f8 add.w dd dais +d178 f1ff add.w dd adr16 +d179 f1ff add.w dd adr32 +d180 f1f8 addx.l ds dd +d188 f1f8 addx.l pais paid +d190 f1f8 add.l dd ais +d198 f1f8 add.l dd aips +d1a0 f1f8 add.l dd pais +d1a8 f1f8 add.l dd das +d1b0 f1f8 add.l dd dais +d1b8 f1ff add.l dd adr16 +d1b9 f1ff add.l dd adr32 +d1c0 f1f8 adda.l ds ad +d1c8 f1f8 adda.l as ad +d1d0 f1f8 adda.l ais ad +d1d8 f1f8 adda.l aips ad +d1e0 f1f8 adda.l pais ad +d1e8 f1f8 adda.l das ad +d1f0 f1f8 adda.l dais ad +d1f8 f1ff adda.l adr16 ad +d1f9 f1ff adda.l adr32 ad +d1fa f1ff adda.l dpc ad +d1fb f1ff adda.l dpci ad +d1fc f1ff adda.l imm32 ad +e000 f1f8 asr.b imm3 ds +e008 f1f8 lsr.b imm3 ds +e010 f1f8 roxr.b imm3 ds +e018 f1f8 ror.b imm3 ds +e020 f1f8 asr.b dd ds +e028 f1f8 lsr.b dd ds +e030 f1f8 roxr.b dd ds +e038 f1f8 ror.b dd ds +e040 f1f8 asr.w imm3 ds +e048 f1f8 lsr.w imm3 ds +e050 f1f8 roxr.w imm3 ds +e058 f1f8 ror.w imm3 ds +e060 f1f8 asr.w dd ds +e068 f1f8 lsr.w dd ds +e070 f1f8 roxr.w dd ds +e078 f1f8 ror.w dd ds +e080 f1f8 asr.l imm3 ds +e088 f1f8 lsr.l imm3 ds +e090 f1f8 roxr.l imm3 ds +e098 f1f8 ror.l imm3 ds +e0a0 f1f8 asr.l dd ds +e0a8 f1f8 lsr.l dd ds +e0b0 f1f8 roxr.l dd ds +e0b8 f1f8 ror.l dd ds +e0d0 fff8 asr ais - +e0d8 fff8 asr aips - +e0e0 fff8 asr pais - +e0e8 fff8 asr das - +e0f0 fff8 asr dais - +e0f8 ffff asr adr16 - +e0f9 ffff asr adr32 - +e100 f1f8 asl.b imm3 ds +e108 f1f8 lsl.b imm3 ds +e110 f1f8 roxl.b imm3 ds +e118 f1f8 rol.b imm3 ds +e120 f1f8 asl.b dd ds +e128 f1f8 lsl.b dd ds +e130 f1f8 roxl.b dd ds +e138 f1f8 rol.b dd ds +e140 f1f8 asl.w imm3 ds +e148 f1f8 lsl.w imm3 ds +e150 f1f8 roxl.w imm3 ds +e158 f1f8 rol.w imm3 ds +e160 f1f8 asl.w dd ds +e168 f1f8 lsl.w dd ds +e170 f1f8 roxl.w dd ds +e178 f1f8 rol.w dd ds +e180 f1f8 asl.l imm3 ds +e188 f1f8 lsl.l imm3 ds +e190 f1f8 roxl.l imm3 ds +e198 f1f8 rol.l imm3 ds +e1a0 f1f8 asl.l dd ds +e1a8 f1f8 lsl.l dd ds +e1b0 f1f8 roxl.l dd ds +e1b8 f1f8 rol.l dd ds +e1d0 fff8 asl ais - +e1d8 fff8 asl aips - +e1e0 fff8 asl pais - +e1e8 fff8 asl das - +e1f0 fff8 asl dais - +e1f8 ffff asl adr16 - +e1f9 ffff asl adr32 - +e2d0 fff8 lsr ais - +e2d8 fff8 lsr aips - +e2e0 fff8 lsr pais - +e2e8 fff8 lsr das - +e2f0 fff8 lsr dais - +e2f8 ffff lsr adr16 - +e2f9 ffff lsr adr32 - +e3d0 fff8 lsl ais - +e3d8 fff8 lsl aips - +e3e0 fff8 lsl pais - +e3e8 fff8 lsl das - +e3f0 fff8 lsl dais - +e3f8 ffff lsl adr16 - +e3f9 ffff lsl adr32 - +e4d0 fff8 roxr ais - +e4d8 fff8 roxr aips - +e4e0 fff8 roxr pais - +e4e8 fff8 roxr das - +e4f0 fff8 roxr dais - +e4f8 ffff roxr adr16 - +e4f9 ffff roxr adr32 - +e5d0 fff8 roxl ais - +e5d8 fff8 roxl aips - +e5e0 fff8 roxl pais - +e5e8 fff8 roxl das - +e5f0 fff8 roxl dais - +e5f8 ffff roxl adr16 - +e5f9 ffff roxl adr32 - +e6d0 fff8 ror ais - +e6d8 fff8 ror aips - +e6e0 fff8 ror pais - +e6e8 fff8 ror das - +e6f0 fff8 ror dais - +e6f8 ffff ror adr16 - +e6f9 ffff ror adr32 - +e7d0 fff8 rol ais - +e7d8 fff8 rol aips - +e7e0 fff8 rol pais - +e7e8 fff8 rol das - +e7f0 fff8 rol dais - +e7f8 ffff rol adr16 - +e7f9 ffff rol adr32 - +f000 f000 linef imm12 - diff --git a/miggy-emu/src/test/java/miggy/cpupoet/CoreTest.java b/miggy-emu/src/test/java/miggy/cpupoet/CoreTest.java new file mode 100644 index 0000000..c008716 --- /dev/null +++ b/miggy-emu/src/test/java/miggy/cpupoet/CoreTest.java @@ -0,0 +1,242 @@ +package miggy.cpupoet; + +import java.nio.ByteBuffer; +import java.nio.ByteOrder; +import java.util.HashSet; +import java.util.Set; + +public class CoreTest extends Core { + private final ByteBuffer memory; + private final Set berrs = new HashSet(); + + public static void main(String[] args) { + ResetTest test2 = new ResetTest(); + + test2.testReset(); + + CoreTest test = new CoreTest(); + + int pc = test.memory.capacity() - 0x800; + + test.setInitialSSP(0x040000); + test.setInitialPC(pc); + + test.write16(pc, 0x4848); + test.write16(pc + 2, 0x0200); + test.write16(pc + 4, 0x1234); + test.write16(pc + 6, 0x4849); + test.write32(4 << 2, 0x090000); + + //test.setclrSSWI(SSWI_XTRP | SSWI_XBRK, 0); + + test.execute(Integer.MAX_VALUE); + test.execute(Integer.MAX_VALUE); + test.execute(Integer.MAX_VALUE); + } + + public CoreTest() { + /* allocate 512 MiB */ + this.memory = ByteBuffer.allocate(512 * 1024); + + memory.order(ByteOrder.BIG_ENDIAN); + } + + public void setInitialSSP(int ssp) { + write32(0, ssp); + } + + public void setInitialPC(int ssp) { + write32(4, ssp); + } + + public Set getBErrs() { + return berrs; + } + + @Override + public int fetch16(int aob) { + return read16(aob); + } + + @Override + public int fetch32(int aob) { + return read32(aob); + } + + protected int check8(int aob) { + if (((aob & 0x7fffffff) + 1 >= memory.capacity()) || berrs.contains(aob)) { + setclrSSW(SSW_BR, 0); + + return -1; + } + + return aob; + } + + protected int check16(int aob) { + if ((aob &= 0x7fffffff) + 2 >= memory.capacity() || berrs.contains(aob)) { + setclrSSW(SSW_BR, 0); + + return -1; + } + + return aob; + } + + protected int check32(int aob) { + if ((aob &= 0x7fffffff) + 4 >= memory.capacity() || berrs.contains(aob)) { + setclrSSW(SSW_BR, 0); + + return -1; + } + + return aob; + } + + @Override + public byte read8(int aob) { + aob = check8(aob); + + return aob < 0 ? 0 : memory.get(aob); + } + + @Override + public short read16(int aob) { + aob = check16(aob); + + return aob < 0 ? 0 : memory.getShort(aob); + } + + @Override + public int read32(int aob) { + aob = check32(aob); + + return aob < 0 ? 0 : memory.getInt(aob); + } + + @Override + public void write8(int aob, int dob) { + aob = check8(aob); + + if (aob >= 0) { + memory.put(aob, (byte) dob); + } + } + + @Override + public void write16(int aob, int dob) { + aob = check16(aob); + + if (aob >= 0) { + memory.putShort(aob, (short) dob); + } + } + + @Override + public void write32(int aob, int dob) { + aob = check32(aob); + + if (aob >= 0) { + memory.putInt(aob, dob); + } + } + + @Override + public int handle_interrupt(int level) { + return IRQ_AVEC; + } + + @Override + public int handle_bkpt(int pc, int data) { + return BKPT_RPIR | BKPT_EXIT | 0x4e71; + } + + public int getPC() { + return pc; + } + + public void setPC(int pc) { + this.pc = pc; + } + + public int getScan() { + return scan; + } + + public void setScan(int scan) { + this.scan = scan; + } + + public int getAluB() { + return alub; + } + + public void setAluB(int alub) { + this.alub = alub; + } + + public int getIRB() { + return irb; + } + + public void setIRB(int irb) { + this.irb = irb; + } + + public int getIR() { + return ir; + } + + public void setIR(int ir) { + this.ir = ir; + } + + public int getMPC() { + return mpc; + } + + public void setMPC(int mpc) { + this.mpc = mpc; + } + + public int getCIP() { + return cip; + } + + public void setCIP(int cip) { + this.cip = cip; + } + + public int getAU() { + return au; + } + + public void setAU(int au) { + this.au = au; + } + + public int getAT() { + return at; + } + + public void setAT(int at) { + this.at = at; + } + + public int getDT() { + return dt; + } + + public void setDT(int dt) { + this.dt = dt; + } + + public int getSlice() { + return slice; + } + + public void setSlice(int slice) { + this.slice = slice; + } + +} diff --git a/miggy-emu/src/test/java/miggy/cpupoet/ResetTest.java b/miggy-emu/src/test/java/miggy/cpupoet/ResetTest.java new file mode 100644 index 0000000..1db3ebd --- /dev/null +++ b/miggy-emu/src/test/java/miggy/cpupoet/ResetTest.java @@ -0,0 +1,57 @@ +package miggy.cpupoet; + +import junit.framework.TestCase; + +public class ResetTest extends TestCase { + public void testReset() { + CoreTest core = new CoreTest(); + + core.setInitialSSP(0x4000); + core.setInitialPC(0x8000); + + core.write16(0x8000, 0x4849); + + core.getBErrs().add(0); + core.getBErrs().add(4); + core.getBErrs().add(0x8000); + + core.execute(50); + + assertTrue(core.getISP() != 0x4000); // isp did not fetch because of bus err + assertTrue(core.getPC() != 0x8000); + assertEquals(CoreALU.SSWI_DERR, core.getSSWI() & CoreALU.SSWI_DERR); + + core.getBErrs().remove(0); + core.execute(50); + + assertTrue(core.getISP() != 0x4000); // still not fetched because CPU is stuck on dbrr + assertTrue(core.getPC() != 0x8000); + assertEquals(CoreALU.SSWI_DERR, core.getSSWI() & CoreALU.SSWI_DERR); + + core.pulse_reset(); // now pulse reset signal + core.execute(50); + + assertTrue(core.getISP() == 0x4000); // isp fetched + assertTrue(core.getPC() != 0x8000); // but not PC + assertEquals(CoreALU.SSWI_DERR, core.getSSWI() & CoreALU.SSWI_DERR); + core.pulse_reset(); // pulse reset signal again + + core.getBErrs().remove(4); // unlock pc + core.execute(50); + + // now both fetched, but still stuck to dbrr because prefetch of irb failed + assertTrue(core.getISP() == 0x4000); + assertTrue(core.getPC() == 0x8000); + assertEquals(CoreALU.SSWI_DERR, core.getSSWI() & CoreALU.SSWI_DERR); + + core.getBErrs().remove(0x8000); + core.pulse_reset(); + core.execute(50); + + // we did exit because of breackpoint + assertTrue(core.getISP() == 0x4000); + assertTrue(core.getCIP() == 0x8000); + assertTrue(core.getPC() == 0x8002); + assertEquals(0, core.getSSWI() & CoreALU.SSWI_DERR); + } +} diff --git a/miggy-export/pom.xml b/miggy-export/pom.xml new file mode 100644 index 0000000..463796b --- /dev/null +++ b/miggy-export/pom.xml @@ -0,0 +1,34 @@ + + 4.0.0 + + miggy + miggy-root + 0.0.1-SNAPSHOT + + miggy-export + miggy-export + pom + + + + + maven-assembly-plugin + + true + + src/main/assembly/full.xml + + + + + make-assembly + package + + single + + + + + + + \ No newline at end of file diff --git a/miggy-export/src/main/assembly/full.xml b/miggy-export/src/main/assembly/full.xml new file mode 100644 index 0000000..fd50f98 --- /dev/null +++ b/miggy-export/src/main/assembly/full.xml @@ -0,0 +1,33 @@ + + full + + zip + + + false + + + + ${project.basedir}/.. + ${project.parent.name} + + + .DS_Store + .project + .pydevproject + .classpath + .settings/** + target/** + + */.DS_Store + */.project + */.pydevproject + */.classpath + */.settings/** + */target/** + + + + \ No newline at end of file diff --git a/pom.xml b/pom.xml new file mode 100644 index 0000000..aa5761b --- /dev/null +++ b/pom.xml @@ -0,0 +1,24 @@ + + 4.0.0 + miggy + miggy-root + 0.0.1-SNAPSHOT + pom + + miggy-emu + miggy-export + + + UTF-8 + 1.8 + 1.8 + + + + junit + junit + 4.13.2 + test + + + \ No newline at end of file