CPU Commit (WIP)

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Rodolphe de Saint Léger 2025-05-13 10:03:25 +02:00
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**This is a 68010 emulator**
This implementation focus on being binary compatible with code written by the 68010, adding additional features on unused bits. Care has been taken about to have same behaviour when not using/enabling additional features.
*The following changes are applied*
- flow trace mode is available (bit 14 in SR)
- interrupt/master supervisor is available (bit 12 in SR)
- 68020 effective addressing modes bits are available in the extension word.
- 68020 additional instructions are available.
- bra/bcc/bsr can use 32 bits displacement
- exception stack frame $2000 can be enabled using a specific bit in SSWI
- 32 bits access can be recovered using specific bits in SSW (will use 16 bits by default)