mirror of
https://bitbucket.org/rslr/miggy-cpu.git
synced 2026-06-12 19:16:29 +00:00
bcc32 now updates pc and not scan (which is only 16 bits wide)
This commit is contained in:
parent
5d4b8809d0
commit
620468666f
4 changed files with 2043 additions and 1981 deletions
|
|
@ -1979,16 +1979,37 @@ public class CoreGenerator {
|
||||||
|
|
||||||
public String gen_move(String size, String src, String dst) {
|
public String gen_move(String size, String src, String dst) {
|
||||||
String msrc = src;
|
String msrc = src;
|
||||||
|
String mdst = dst;
|
||||||
|
|
||||||
if ("imm8o".equals(src)) {
|
if ("imm8o".equals(src)) {
|
||||||
msrc = "im";
|
msrc = "ir";
|
||||||
} else if ("imm8".equals(src) || "imm16".equals(src) || "imm32".equals(src)) {
|
} else if ("imm8".equals(src) || "imm16".equals(src) || "imm32".equals(src)) {
|
||||||
msrc = "dt";
|
msrc = "dt";
|
||||||
|
} else if ("dd".equals(src)) {
|
||||||
|
msrc = "dx";
|
||||||
|
} else if ("ds".equals(src)) {
|
||||||
|
msrc = "dy";
|
||||||
|
} else if ("ad".equals(src)) {
|
||||||
|
msrc = "ax";
|
||||||
|
} else if ("as".equals(src)) {
|
||||||
|
msrc = "ay";
|
||||||
} else if ("ea".equals(src)) {
|
} else if ("ea".equals(src)) {
|
||||||
msrc = "dt";
|
msrc = "dt";
|
||||||
}
|
}
|
||||||
|
|
||||||
String mnemonic = String.format("gen_move%s_%s_%s", size, msrc, dst);
|
if ("dd".equals(dst)) {
|
||||||
|
mdst = "dx";
|
||||||
|
} else if ("ds".equals(dst)) {
|
||||||
|
mdst = "dy";
|
||||||
|
} else if ("ad".equals(dst)) {
|
||||||
|
mdst = "ax";
|
||||||
|
} else if ("as".equals(dst)) {
|
||||||
|
mdst = "ay";
|
||||||
|
} else if ("ea".equals(dst)) {
|
||||||
|
mdst = "dt";
|
||||||
|
}
|
||||||
|
|
||||||
|
String mnemonic = String.format("gen_move%s_%s_%s", size, msrc, mdst);
|
||||||
|
|
||||||
for(MicroBlock block : blocks) {
|
for(MicroBlock block : blocks) {
|
||||||
if (mnemonic.equals(block.name)) {
|
if (mnemonic.equals(block.name)) {
|
||||||
|
|
@ -2155,6 +2176,7 @@ public class CoreGenerator {
|
||||||
public String gen_dyadic(String name, String size, String src, String dst) {
|
public String gen_dyadic(String name, String size, String src, String dst) {
|
||||||
boolean update = true;
|
boolean update = true;
|
||||||
String msrc = src;
|
String msrc = src;
|
||||||
|
String mdst = dst;
|
||||||
String op = name;
|
String op = name;
|
||||||
|
|
||||||
if ("btst".equals(name)) {
|
if ("btst".equals(name)) {
|
||||||
|
|
@ -2168,19 +2190,39 @@ public class CoreGenerator {
|
||||||
msrc = "ir";
|
msrc = "ir";
|
||||||
} else if ("imm8".equals(src) || "imm16".equals(src) || "imm32".equals(src)) {
|
} else if ("imm8".equals(src) || "imm16".equals(src) || "imm32".equals(src)) {
|
||||||
if ("ea".equals(dst)) {
|
if ("ea".equals(dst)) {
|
||||||
msrc = "im";
|
msrc = "alub";
|
||||||
} else {
|
} else {
|
||||||
msrc = "dt";
|
msrc = "dt";
|
||||||
}
|
}
|
||||||
|
} else if ("dd".equals(src)) {
|
||||||
|
msrc = "dx";
|
||||||
|
} else if ("ds".equals(src)) {
|
||||||
|
msrc = "dy";
|
||||||
|
} else if ("ad".equals(src)) {
|
||||||
|
msrc = "ax";
|
||||||
|
} else if ("as".equals(src)) {
|
||||||
|
msrc = "ay";
|
||||||
} else if ("ea".equals(src)) {
|
} else if ("ea".equals(src)) {
|
||||||
if ("ea".equals(dst)) {
|
if ("ea".equals(dst)) {
|
||||||
msrc = "im";
|
msrc = "alub";
|
||||||
} else {
|
} else {
|
||||||
msrc = "dt";
|
msrc = "dt";
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
String mnemonic = String.format("gen_%s%s_%s_%s", name, size, msrc, dst);
|
if ("dd".equals(dst)) {
|
||||||
|
mdst = "dx";
|
||||||
|
} else if ("ds".equals(dst)) {
|
||||||
|
mdst = "dy";
|
||||||
|
} else if ("ad".equals(dst)) {
|
||||||
|
mdst = "ax";
|
||||||
|
} else if ("as".equals(dst)) {
|
||||||
|
mdst = "ay";
|
||||||
|
} else if ("ea".equals(dst)) {
|
||||||
|
mdst = "dt";
|
||||||
|
}
|
||||||
|
|
||||||
|
String mnemonic = String.format("gen_%s%s_%s_%s", name, size, msrc, mdst);
|
||||||
|
|
||||||
for(MicroBlock block : blocks) {
|
for(MicroBlock block : blocks) {
|
||||||
if (mnemonic.equals(block.name)) {
|
if (mnemonic.equals(block.name)) {
|
||||||
|
|
@ -2415,7 +2457,21 @@ public class CoreGenerator {
|
||||||
}
|
}
|
||||||
|
|
||||||
public String gen_monadic(String name, String size, String dst) {
|
public String gen_monadic(String name, String size, String dst) {
|
||||||
String mnemonic = String.format("gen_%s%s_%s", name, size, dst);
|
String mdst = dst;
|
||||||
|
|
||||||
|
if ("dd".equals(dst)) {
|
||||||
|
mdst = "dx";
|
||||||
|
} else if ("ds".equals(dst)) {
|
||||||
|
mdst = "dy";
|
||||||
|
} else if ("ad".equals(dst)) {
|
||||||
|
mdst = "ax";
|
||||||
|
} else if ("as".equals(dst)) {
|
||||||
|
mdst = "ay";
|
||||||
|
} else if ("ea".equals(dst)) {
|
||||||
|
mdst = "dt";
|
||||||
|
}
|
||||||
|
|
||||||
|
String mnemonic = String.format("gen_%s%s_%s", name, size, mdst);
|
||||||
boolean update = !"tst".equals(name);
|
boolean update = !"tst".equals(name);
|
||||||
|
|
||||||
for(MicroBlock block : blocks) {
|
for(MicroBlock block : blocks) {
|
||||||
|
|
@ -2590,7 +2646,9 @@ public class CoreGenerator {
|
||||||
addEndControlFlow();
|
addEndControlFlow();
|
||||||
anyread32("dt", SSW_DF | SSW_P, "pc + scan", 0, false, null);
|
anyread32("dt", SSW_DF | SSW_P, "pc + scan", 0, false, null);
|
||||||
consume(14, 3, 0);
|
consume(14, 3, 0);
|
||||||
addFormattedMicroInsn("scan = dt");
|
/* scan is only 16 bits wide, directly modify pc */
|
||||||
|
addFormattedMicroInsn("pc += dt");
|
||||||
|
addFormattedMicroInsn("scan = 0");
|
||||||
addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow
|
addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow
|
||||||
microprefetch(true, null); // prefetch ir from pc and resume execution
|
microprefetch(true, null); // prefetch ir from pc and resume execution
|
||||||
|
|
||||||
|
|
@ -2627,7 +2685,9 @@ public class CoreGenerator {
|
||||||
addFormattedMicroInsn("au = dar[sp] - 4");
|
addFormattedMicroInsn("au = dar[sp] - 4");
|
||||||
addFormattedMicroInsn("dar[sp] = au");
|
addFormattedMicroInsn("dar[sp] = au");
|
||||||
write32(SSW_D, "au", "pc + scan", 0, false);
|
write32(SSW_D, "au", "pc + scan", 0, false);
|
||||||
addFormattedMicroInsn("scan = dt");
|
/* scan is only 16 bits wide, directly modify pc */
|
||||||
|
addFormattedMicroInsn("pc += dt");
|
||||||
|
addFormattedMicroInsn("scan = 0");
|
||||||
addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow
|
addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow
|
||||||
microprefetch(true, null); // prefetch ir from pc and resume execution
|
microprefetch(true, null); // prefetch ir from pc and resume execution
|
||||||
|
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -44,7 +44,7 @@ public class CoreTest extends Core {
|
||||||
for (int i = 0; i < numTests; i++) {
|
for (int i = 0; i < numTests; i++) {
|
||||||
boolean skip = checkSkip(i, skips);
|
boolean skip = checkSkip(i, skips);
|
||||||
|
|
||||||
if ((i == 40) && "MOVEM.w".equals(name)) {
|
if ((i == 295) && "MOVE.w".equals(name)) {
|
||||||
toString();
|
toString();
|
||||||
}
|
}
|
||||||
executeBinTest(buffer, skip);
|
executeBinTest(buffer, skip);
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue