From 620468666f66a1fb127320a4b5ff26d10d918826 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rodolphe=20de=20Saint=20L=C3=A9ger?= Date: Tue, 20 May 2025 20:23:17 +0200 Subject: [PATCH] bcc32 now updates pc and not scan (which is only 16 bits wide) --- .../java/miggy/cpu/genpoet/CoreGenerator.java | 76 +- .../src/main/java/miggy/cpupoet/Core.java | 1054 +++--- .../src/main/java/miggy/cpupoet/MacroPLA.java | 2892 ++++++++--------- .../src/test/java/miggy/cpupoet/CoreTest.java | 2 +- 4 files changed, 2043 insertions(+), 1981 deletions(-) diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java index f6d29e0..2ce8187 100644 --- a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java +++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java @@ -1979,16 +1979,37 @@ public class CoreGenerator { public String gen_move(String size, String src, String dst) { String msrc = src; + String mdst = dst; if ("imm8o".equals(src)) { - msrc = "im"; + msrc = "ir"; } else if ("imm8".equals(src) || "imm16".equals(src) || "imm32".equals(src)) { msrc = "dt"; + } else if ("dd".equals(src)) { + msrc = "dx"; + } else if ("ds".equals(src)) { + msrc = "dy"; + } else if ("ad".equals(src)) { + msrc = "ax"; + } else if ("as".equals(src)) { + msrc = "ay"; } else if ("ea".equals(src)) { msrc = "dt"; } - String mnemonic = String.format("gen_move%s_%s_%s", size, msrc, dst); + if ("dd".equals(dst)) { + mdst = "dx"; + } else if ("ds".equals(dst)) { + mdst = "dy"; + } else if ("ad".equals(dst)) { + mdst = "ax"; + } else if ("as".equals(dst)) { + mdst = "ay"; + } else if ("ea".equals(dst)) { + mdst = "dt"; + } + + String mnemonic = String.format("gen_move%s_%s_%s", size, msrc, mdst); for(MicroBlock block : blocks) { if (mnemonic.equals(block.name)) { @@ -2155,6 +2176,7 @@ public class CoreGenerator { public String gen_dyadic(String name, String size, String src, String dst) { boolean update = true; String msrc = src; + String mdst = dst; String op = name; if ("btst".equals(name)) { @@ -2168,19 +2190,39 @@ public class CoreGenerator { msrc = "ir"; } else if ("imm8".equals(src) || "imm16".equals(src) || "imm32".equals(src)) { if ("ea".equals(dst)) { - msrc = "im"; + msrc = "alub"; } else { msrc = "dt"; } + } else if ("dd".equals(src)) { + msrc = "dx"; + } else if ("ds".equals(src)) { + msrc = "dy"; + } else if ("ad".equals(src)) { + msrc = "ax"; + } else if ("as".equals(src)) { + msrc = "ay"; } else if ("ea".equals(src)) { if ("ea".equals(dst)) { - msrc = "im"; + msrc = "alub"; } else { msrc = "dt"; } } - String mnemonic = String.format("gen_%s%s_%s_%s", name, size, msrc, dst); + if ("dd".equals(dst)) { + mdst = "dx"; + } else if ("ds".equals(dst)) { + mdst = "dy"; + } else if ("ad".equals(dst)) { + mdst = "ax"; + } else if ("as".equals(dst)) { + mdst = "ay"; + } else if ("ea".equals(dst)) { + mdst = "dt"; + } + + String mnemonic = String.format("gen_%s%s_%s_%s", name, size, msrc, mdst); for(MicroBlock block : blocks) { if (mnemonic.equals(block.name)) { @@ -2415,7 +2457,21 @@ public class CoreGenerator { } public String gen_monadic(String name, String size, String dst) { - String mnemonic = String.format("gen_%s%s_%s", name, size, dst); + String mdst = dst; + + if ("dd".equals(dst)) { + mdst = "dx"; + } else if ("ds".equals(dst)) { + mdst = "dy"; + } else if ("ad".equals(dst)) { + mdst = "ax"; + } else if ("as".equals(dst)) { + mdst = "ay"; + } else if ("ea".equals(dst)) { + mdst = "dt"; + } + + String mnemonic = String.format("gen_%s%s_%s", name, size, mdst); boolean update = !"tst".equals(name); for(MicroBlock block : blocks) { @@ -2590,7 +2646,9 @@ public class CoreGenerator { addEndControlFlow(); anyread32("dt", SSW_DF | SSW_P, "pc + scan", 0, false, null); consume(14, 3, 0); - addFormattedMicroInsn("scan = dt"); + /* scan is only 16 bits wide, directly modify pc */ + addFormattedMicroInsn("pc += dt"); + addFormattedMicroInsn("scan = 0"); addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow microprefetch(true, null); // prefetch ir from pc and resume execution @@ -2627,7 +2685,9 @@ public class CoreGenerator { addFormattedMicroInsn("au = dar[sp] - 4"); addFormattedMicroInsn("dar[sp] = au"); write32(SSW_D, "au", "pc + scan", 0, false); - addFormattedMicroInsn("scan = dt"); + /* scan is only 16 bits wide, directly modify pc */ + addFormattedMicroInsn("pc += dt"); + addFormattedMicroInsn("scan = 0"); addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow microprefetch(true, null); // prefetch ir from pc and resume execution diff --git a/miggy-emu/src/main/java/miggy/cpupoet/Core.java b/miggy-emu/src/main/java/miggy/cpupoet/Core.java index 5939e1c..9e5e469 100644 --- a/miggy-emu/src/main/java/miggy/cpupoet/Core.java +++ b/miggy-emu/src/main/java/miggy/cpupoet/Core.java @@ -463,545 +463,545 @@ public abstract class Core extends CoreALU { protected static final int op_trapcc32 = 342; - protected static final int gen_orb_dt_ds = 343; + protected static final int gen_orb_dt_dy = 343; - protected static final int gen_orb_im_ea = 344; + protected static final int gen_orb_alub_dt = 344; - protected static final int gen_orw_dt_ds = 345; + protected static final int gen_orw_dt_dy = 345; - protected static final int gen_orw_im_ea = 346; + protected static final int gen_orw_alub_dt = 346; - protected static final int gen_orl_dt_ds = 347; + protected static final int gen_orl_dt_dy = 347; - protected static final int gen_orl_im_ea = 348; + protected static final int gen_orl_alub_dt = 348; protected static final int gen_orb_dt_ccr = 349; protected static final int gen_orw_dt_sr = 350; - protected static final int gen_btstl_dd_ds = 351; + protected static final int gen_btstl_dx_dy = 351; - protected static final int gen_btstb_dd_ea = 352; + protected static final int gen_btstb_dx_dt = 352; - protected static final int gen_bchgl_dd_ds = 353; + protected static final int gen_bchgl_dx_dy = 353; - protected static final int gen_bchgb_dd_ea = 354; + protected static final int gen_bchgb_dx_dt = 354; - protected static final int gen_bclrl_dd_ds = 355; + protected static final int gen_bclrl_dx_dy = 355; - protected static final int gen_bclrb_dd_ea = 356; + protected static final int gen_bclrb_dx_dt = 356; - protected static final int gen_bsetl_dd_ds = 357; + protected static final int gen_bsetl_dx_dy = 357; - protected static final int gen_bsetb_dd_ea = 358; + protected static final int gen_bsetb_dx_dt = 358; - protected static final int gen_andb_dt_ds = 359; + protected static final int gen_andb_dt_dy = 359; - protected static final int gen_andb_im_ea = 360; + protected static final int gen_andb_alub_dt = 360; - protected static final int gen_andw_dt_ds = 361; + protected static final int gen_andw_dt_dy = 361; - protected static final int gen_andw_im_ea = 362; + protected static final int gen_andw_alub_dt = 362; - protected static final int gen_andl_dt_ds = 363; + protected static final int gen_andl_dt_dy = 363; - protected static final int gen_andl_im_ea = 364; + protected static final int gen_andl_alub_dt = 364; protected static final int gen_andb_dt_ccr = 365; protected static final int gen_andw_dt_sr = 366; - protected static final int gen_subb_dt_ds = 367; + protected static final int gen_subb_dt_dy = 367; - protected static final int gen_subb_im_ea = 368; + protected static final int gen_subb_alub_dt = 368; - protected static final int gen_subw_dt_ds = 369; + protected static final int gen_subw_dt_dy = 369; - protected static final int gen_subw_im_ea = 370; + protected static final int gen_subw_alub_dt = 370; - protected static final int gen_subl_dt_ds = 371; + protected static final int gen_subl_dt_dy = 371; - protected static final int gen_subl_im_ea = 372; + protected static final int gen_subl_alub_dt = 372; - protected static final int gen_addb_dt_ds = 373; + protected static final int gen_addb_dt_dy = 373; - protected static final int gen_addb_im_ea = 374; + protected static final int gen_addb_alub_dt = 374; - protected static final int gen_addw_dt_ds = 375; + protected static final int gen_addw_dt_dy = 375; - protected static final int gen_addw_im_ea = 376; + protected static final int gen_addw_alub_dt = 376; - protected static final int gen_addl_dt_ds = 377; + protected static final int gen_addl_dt_dy = 377; - protected static final int gen_addl_im_ea = 378; + protected static final int gen_addl_alub_dt = 378; - protected static final int gen_btstl_dt_ds = 379; + protected static final int gen_btstl_dt_dy = 379; - protected static final int gen_btstb_im_ea = 380; + protected static final int gen_btstb_alub_dt = 380; - protected static final int gen_bchgl_dt_ds = 381; + protected static final int gen_bchgl_dt_dy = 381; - protected static final int gen_bchgb_im_ea = 382; + protected static final int gen_bchgb_alub_dt = 382; - protected static final int gen_bclrl_dt_ds = 383; + protected static final int gen_bclrl_dt_dy = 383; - protected static final int gen_bclrb_im_ea = 384; + protected static final int gen_bclrb_alub_dt = 384; - protected static final int gen_bsetl_dt_ds = 385; + protected static final int gen_bsetl_dt_dy = 385; - protected static final int gen_bsetb_im_ea = 386; + protected static final int gen_bsetb_alub_dt = 386; - protected static final int gen_eorb_dt_ds = 387; + protected static final int gen_eorb_dt_dy = 387; - protected static final int gen_eorb_im_ea = 388; + protected static final int gen_eorb_alub_dt = 388; - protected static final int gen_eorw_dt_ds = 389; + protected static final int gen_eorw_dt_dy = 389; - protected static final int gen_eorw_im_ea = 390; + protected static final int gen_eorw_alub_dt = 390; - protected static final int gen_eorl_dt_ds = 391; + protected static final int gen_eorl_dt_dy = 391; - protected static final int gen_eorl_im_ea = 392; + protected static final int gen_eorl_alub_dt = 392; protected static final int gen_eorb_dt_ccr = 393; protected static final int gen_eorw_dt_sr = 394; - protected static final int gen_cmpb_dt_ds = 395; + protected static final int gen_cmpb_dt_dy = 395; - protected static final int gen_cmpb_im_ea = 396; + protected static final int gen_cmpb_alub_dt = 396; - protected static final int gen_cmpw_dt_ds = 397; + protected static final int gen_cmpw_dt_dy = 397; - protected static final int gen_cmpw_im_ea = 398; + protected static final int gen_cmpw_alub_dt = 398; - protected static final int gen_cmpl_dt_ds = 399; + protected static final int gen_cmpl_dt_dy = 399; - protected static final int gen_cmpl_im_ea = 400; + protected static final int gen_cmpl_alub_dt = 400; - protected static final int gen_moveb_ds_ea = 401; + protected static final int gen_moveb_dy_dt = 401; - protected static final int gen_moveb_dt_dd = 402; + protected static final int gen_moveb_dt_dx = 402; - protected static final int gen_moveb_ds_dd = 403; + protected static final int gen_moveb_dy_dx = 403; - protected static final int gen_moveb_dt_ea = 404; + protected static final int gen_moveb_dt_dt = 404; - protected static final int gen_movel_ds_ea = 405; + protected static final int gen_movel_dy_dt = 405; - protected static final int gen_movel_dt_ea = 406; + protected static final int gen_movel_dt_dt = 406; - protected static final int gen_movel_dt_dd = 407; + protected static final int gen_movel_dt_dx = 407; - protected static final int gen_movel_ds_dd = 408; + protected static final int gen_movel_dy_dx = 408; - protected static final int gen_movel_as_dd = 409; + protected static final int gen_movel_ay_dx = 409; - protected static final int gen_movel_ds_ad = 410; + protected static final int gen_movel_dy_ax = 410; - protected static final int gen_movel_as_ad = 411; + protected static final int gen_movel_ay_ax = 411; - protected static final int gen_movel_dt_ad = 412; + protected static final int gen_movel_dt_ax = 412; - protected static final int gen_movew_ds_ea = 413; + protected static final int gen_movew_dy_dt = 413; - protected static final int gen_movew_dt_ea = 414; + protected static final int gen_movew_dt_dt = 414; - protected static final int gen_movew_dt_dd = 415; + protected static final int gen_movew_dt_dx = 415; - protected static final int gen_movew_ds_dd = 416; + protected static final int gen_movew_dy_dx = 416; - protected static final int gen_movew_as_dd = 417; + protected static final int gen_movew_ay_dx = 417; - protected static final int gen_movew_ds_ad = 418; + protected static final int gen_movew_dy_ax = 418; - protected static final int gen_movew_as_ad = 419; + protected static final int gen_movew_ay_ax = 419; - protected static final int gen_movew_dt_ad = 420; + protected static final int gen_movew_dt_ax = 420; - protected static final int gen_negxb_ds = 421; + protected static final int gen_negxb_dy = 421; - protected static final int gen_negxb_ea = 422; + protected static final int gen_negxb_dt = 422; - protected static final int gen_negxw_ds = 423; + protected static final int gen_negxw_dy = 423; - protected static final int gen_negxw_ea = 424; + protected static final int gen_negxw_dt = 424; - protected static final int gen_negxl_ds = 425; + protected static final int gen_negxl_dy = 425; - protected static final int gen_negxl_ea = 426; + protected static final int gen_negxl_dt = 426; - protected static final int gen_movew_sr_ds = 427; + protected static final int gen_movew_sr_dy = 427; - protected static final int gen_movew_sr_ea = 428; + protected static final int gen_movew_sr_dt = 428; - protected static final int gen_movew_ccr_ds = 429; + protected static final int gen_movew_ccr_dy = 429; - protected static final int gen_movew_ccr_ea = 430; + protected static final int gen_movew_ccr_dt = 430; - protected static final int gen_movew_ds_ccr = 431; + protected static final int gen_movew_dy_ccr = 431; protected static final int gen_movew_dt_ccr = 432; - protected static final int gen_movew_ds_sr = 433; + protected static final int gen_movew_dy_sr = 433; protected static final int gen_movew_dt_sr = 434; - protected static final int gen_negb_ds = 435; + protected static final int gen_negb_dy = 435; - protected static final int gen_negb_ea = 436; + protected static final int gen_negb_dt = 436; - protected static final int gen_negw_ds = 437; + protected static final int gen_negw_dy = 437; - protected static final int gen_negw_ea = 438; + protected static final int gen_negw_dt = 438; - protected static final int gen_negl_ds = 439; + protected static final int gen_negl_dy = 439; - protected static final int gen_negl_ea = 440; + protected static final int gen_negl_dt = 440; - protected static final int gen_notb_ds = 441; + protected static final int gen_notb_dy = 441; - protected static final int gen_notb_ea = 442; + protected static final int gen_notb_dt = 442; - protected static final int gen_notw_ds = 443; + protected static final int gen_notw_dy = 443; - protected static final int gen_notw_ea = 444; + protected static final int gen_notw_dt = 444; - protected static final int gen_notl_ds = 445; + protected static final int gen_notl_dy = 445; - protected static final int gen_notl_ea = 446; + protected static final int gen_notl_dt = 446; - protected static final int gen_nbcdb_ds = 447; + protected static final int gen_nbcdb_dy = 447; - protected static final int gen_nbcdb_ea = 448; + protected static final int gen_nbcdb_dt = 448; - protected static final int gen_tstb_ds = 449; + protected static final int gen_tstb_dy = 449; - protected static final int gen_tstb_ea = 450; + protected static final int gen_tstb_dt = 450; - protected static final int gen_tstw_ds = 451; + protected static final int gen_tstw_dy = 451; - protected static final int gen_tstw_ea = 452; + protected static final int gen_tstw_dt = 452; - protected static final int gen_tstl_ds = 453; + protected static final int gen_tstl_dy = 453; - protected static final int gen_tstl_ea = 454; + protected static final int gen_tstl_dt = 454; - protected static final int gen_addb_ir_ds = 455; + protected static final int gen_addb_ir_dy = 455; - protected static final int gen_addb_ir_ea = 456; + protected static final int gen_addb_ir_dt = 456; - protected static final int gen_addw_ir_ds = 457; + protected static final int gen_addw_ir_dy = 457; - protected static final int gen_addw_ir_as = 458; + protected static final int gen_addw_ir_ay = 458; - protected static final int gen_addw_ir_ea = 459; + protected static final int gen_addw_ir_dt = 459; - protected static final int gen_addl_ir_ds = 460; + protected static final int gen_addl_ir_dy = 460; - protected static final int gen_addl_ir_as = 461; + protected static final int gen_addl_ir_ay = 461; - protected static final int gen_addl_ir_ea = 462; + protected static final int gen_addl_ir_dt = 462; - protected static final int gen_subb_ir_ds = 463; + protected static final int gen_subb_ir_dy = 463; - protected static final int gen_subb_ir_ea = 464; + protected static final int gen_subb_ir_dt = 464; - protected static final int gen_subw_ir_ds = 465; + protected static final int gen_subw_ir_dy = 465; - protected static final int gen_subw_ir_as = 466; + protected static final int gen_subw_ir_ay = 466; - protected static final int gen_subw_ir_ea = 467; + protected static final int gen_subw_ir_dt = 467; - protected static final int gen_subl_ir_ds = 468; + protected static final int gen_subl_ir_dy = 468; - protected static final int gen_subl_ir_as = 469; + protected static final int gen_subl_ir_ay = 469; - protected static final int gen_subl_ir_ea = 470; + protected static final int gen_subl_ir_dt = 470; - protected static final int gen_movel_im_dd = 471; + protected static final int gen_movel_ir_dx = 471; - protected static final int gen_orb_ds_dd = 472; + protected static final int gen_orb_dy_dx = 472; - protected static final int gen_orb_dt_dd = 473; + protected static final int gen_orb_dt_dx = 473; - protected static final int gen_orw_ds_dd = 474; + protected static final int gen_orw_dy_dx = 474; - protected static final int gen_orw_dt_dd = 475; + protected static final int gen_orw_dt_dx = 475; - protected static final int gen_orl_ds_dd = 476; + protected static final int gen_orl_dy_dx = 476; - protected static final int gen_orl_dt_dd = 477; + protected static final int gen_orl_dt_dx = 477; - protected static final int gen_sbcdb_ds_dd = 478; + protected static final int gen_sbcdb_dy_dx = 478; - protected static final int gen_sbcdb_im_ea = 479; + protected static final int gen_sbcdb_alub_dt = 479; - protected static final int gen_orb_dd_ea = 480; + protected static final int gen_orb_dx_dt = 480; - protected static final int gen_orw_dd_ea = 481; + protected static final int gen_orw_dx_dt = 481; - protected static final int gen_orl_dd_ea = 482; + protected static final int gen_orl_dx_dt = 482; - protected static final int gen_divuw_ds_dd = 483; + protected static final int gen_divuw_dy_dx = 483; - protected static final int gen_divuw_dt_dd = 484; + protected static final int gen_divuw_dt_dx = 484; - protected static final int gen_divsw_ds_dd = 485; + protected static final int gen_divsw_dy_dx = 485; - protected static final int gen_divsw_dt_dd = 486; + protected static final int gen_divsw_dt_dx = 486; - protected static final int gen_subb_ds_dd = 487; + protected static final int gen_subb_dy_dx = 487; - protected static final int gen_subb_dt_dd = 488; + protected static final int gen_subb_dt_dx = 488; - protected static final int gen_subw_ds_dd = 489; + protected static final int gen_subw_dy_dx = 489; - protected static final int gen_subw_as_dd = 490; + protected static final int gen_subw_ay_dx = 490; - protected static final int gen_subw_dt_dd = 491; + protected static final int gen_subw_dt_dx = 491; - protected static final int gen_subl_ds_dd = 492; + protected static final int gen_subl_dy_dx = 492; - protected static final int gen_subl_as_dd = 493; + protected static final int gen_subl_ay_dx = 493; - protected static final int gen_subl_dt_dd = 494; + protected static final int gen_subl_dt_dx = 494; - protected static final int gen_subb_dd_ea = 495; + protected static final int gen_subb_dx_dt = 495; - protected static final int gen_subw_dd_ea = 496; + protected static final int gen_subw_dx_dt = 496; - protected static final int gen_subl_dd_ea = 497; + protected static final int gen_subl_dx_dt = 497; - protected static final int gen_subxb_ds_dd = 498; + protected static final int gen_subxb_dy_dx = 498; - protected static final int gen_subxb_im_ea = 499; + protected static final int gen_subxb_alub_dt = 499; - protected static final int gen_subxw_ds_dd = 500; + protected static final int gen_subxw_dy_dx = 500; - protected static final int gen_subxw_im_ea = 501; + protected static final int gen_subxw_alub_dt = 501; - protected static final int gen_subxl_ds_dd = 502; + protected static final int gen_subxl_dy_dx = 502; - protected static final int gen_subxl_im_ea = 503; + protected static final int gen_subxl_alub_dt = 503; - protected static final int gen_subw_ds_ad = 504; + protected static final int gen_subw_dy_ax = 504; - protected static final int gen_subw_as_ad = 505; + protected static final int gen_subw_ay_ax = 505; - protected static final int gen_subw_dt_ad = 506; + protected static final int gen_subw_dt_ax = 506; - protected static final int gen_subl_ds_ad = 507; + protected static final int gen_subl_dy_ax = 507; - protected static final int gen_subl_as_ad = 508; + protected static final int gen_subl_ay_ax = 508; - protected static final int gen_subl_dt_ad = 509; + protected static final int gen_subl_dt_ax = 509; - protected static final int gen_cmpb_ds_dd = 510; + protected static final int gen_cmpb_dy_dx = 510; - protected static final int gen_cmpb_dt_dd = 511; + protected static final int gen_cmpb_dt_dx = 511; - protected static final int gen_cmpw_ds_dd = 512; + protected static final int gen_cmpw_dy_dx = 512; - protected static final int gen_cmpw_as_dd = 513; + protected static final int gen_cmpw_ay_dx = 513; - protected static final int gen_cmpw_dt_dd = 514; + protected static final int gen_cmpw_dt_dx = 514; - protected static final int gen_cmpl_ds_dd = 515; + protected static final int gen_cmpl_dy_dx = 515; - protected static final int gen_cmpl_as_dd = 516; + protected static final int gen_cmpl_ay_dx = 516; - protected static final int gen_cmpl_dt_dd = 517; + protected static final int gen_cmpl_dt_dx = 517; - protected static final int gen_cmpw_ds_ad = 518; + protected static final int gen_cmpw_dy_ax = 518; - protected static final int gen_cmpw_as_ad = 519; + protected static final int gen_cmpw_ay_ax = 519; - protected static final int gen_cmpw_dt_ad = 520; + protected static final int gen_cmpw_dt_ax = 520; - protected static final int gen_cmpl_ds_ad = 521; + protected static final int gen_cmpl_dy_ax = 521; - protected static final int gen_cmpl_as_ad = 522; + protected static final int gen_cmpl_ay_ax = 522; - protected static final int gen_cmpl_dt_ad = 523; + protected static final int gen_cmpl_dt_ax = 523; - protected static final int gen_cmpmb_im_ea = 524; + protected static final int gen_cmpmb_alub_dt = 524; - protected static final int gen_cmpmw_im_ea = 525; + protected static final int gen_cmpmw_alub_dt = 525; - protected static final int gen_cmpml_im_ea = 526; + protected static final int gen_cmpml_alub_dt = 526; - protected static final int gen_eorb_dd_ds = 527; + protected static final int gen_eorb_dx_dy = 527; - protected static final int gen_eorb_dd_ea = 528; + protected static final int gen_eorb_dx_dt = 528; - protected static final int gen_eorw_dd_ds = 529; + protected static final int gen_eorw_dx_dy = 529; - protected static final int gen_eorw_dd_ea = 530; + protected static final int gen_eorw_dx_dt = 530; - protected static final int gen_eorl_dd_ds = 531; + protected static final int gen_eorl_dx_dy = 531; - protected static final int gen_eorl_dd_ea = 532; + protected static final int gen_eorl_dx_dt = 532; - protected static final int gen_andb_ds_dd = 533; + protected static final int gen_andb_dy_dx = 533; - protected static final int gen_andb_dt_dd = 534; + protected static final int gen_andb_dt_dx = 534; - protected static final int gen_andw_ds_dd = 535; + protected static final int gen_andw_dy_dx = 535; - protected static final int gen_andw_dt_dd = 536; + protected static final int gen_andw_dt_dx = 536; - protected static final int gen_andl_ds_dd = 537; + protected static final int gen_andl_dy_dx = 537; - protected static final int gen_andl_dt_dd = 538; + protected static final int gen_andl_dt_dx = 538; - protected static final int gen_muluw_ds_dd = 539; + protected static final int gen_muluw_dy_dx = 539; - protected static final int gen_muluw_dt_dd = 540; + protected static final int gen_muluw_dt_dx = 540; - protected static final int gen_mulsw_ds_dd = 541; + protected static final int gen_mulsw_dy_dx = 541; - protected static final int gen_mulsw_dt_dd = 542; + protected static final int gen_mulsw_dt_dx = 542; - protected static final int gen_andb_dd_ea = 543; + protected static final int gen_andb_dx_dt = 543; - protected static final int gen_andw_dd_ea = 544; + protected static final int gen_andw_dx_dt = 544; - protected static final int gen_andl_dd_ea = 545; + protected static final int gen_andl_dx_dt = 545; - protected static final int gen_abcdb_ds_dd = 546; + protected static final int gen_abcdb_dy_dx = 546; - protected static final int gen_abcdb_im_ea = 547; + protected static final int gen_abcdb_alub_dt = 547; - protected static final int gen_addb_ds_dd = 548; + protected static final int gen_addb_dy_dx = 548; - protected static final int gen_addb_dt_dd = 549; + protected static final int gen_addb_dt_dx = 549; - protected static final int gen_addw_ds_dd = 550; + protected static final int gen_addw_dy_dx = 550; - protected static final int gen_addw_as_dd = 551; + protected static final int gen_addw_ay_dx = 551; - protected static final int gen_addw_dt_dd = 552; + protected static final int gen_addw_dt_dx = 552; - protected static final int gen_addl_ds_dd = 553; + protected static final int gen_addl_dy_dx = 553; - protected static final int gen_addl_as_dd = 554; + protected static final int gen_addl_ay_dx = 554; - protected static final int gen_addl_dt_dd = 555; + protected static final int gen_addl_dt_dx = 555; - protected static final int gen_addb_dd_ea = 556; + protected static final int gen_addb_dx_dt = 556; - protected static final int gen_addw_dd_ea = 557; + protected static final int gen_addw_dx_dt = 557; - protected static final int gen_addl_dd_ea = 558; + protected static final int gen_addl_dx_dt = 558; - protected static final int gen_addxb_ds_dd = 559; + protected static final int gen_addxb_dy_dx = 559; - protected static final int gen_addxb_im_ea = 560; + protected static final int gen_addxb_alub_dt = 560; - protected static final int gen_addxw_ds_dd = 561; + protected static final int gen_addxw_dy_dx = 561; - protected static final int gen_addxw_im_ea = 562; + protected static final int gen_addxw_alub_dt = 562; - protected static final int gen_addxl_ds_dd = 563; + protected static final int gen_addxl_dy_dx = 563; - protected static final int gen_addxl_im_ea = 564; + protected static final int gen_addxl_alub_dt = 564; - protected static final int gen_addw_ds_ad = 565; + protected static final int gen_addw_dy_ax = 565; - protected static final int gen_addw_as_ad = 566; + protected static final int gen_addw_ay_ax = 566; - protected static final int gen_addw_dt_ad = 567; + protected static final int gen_addw_dt_ax = 567; - protected static final int gen_addl_ds_ad = 568; + protected static final int gen_addl_dy_ax = 568; - protected static final int gen_addl_as_ad = 569; + protected static final int gen_addl_ay_ax = 569; - protected static final int gen_addl_dt_ad = 570; + protected static final int gen_addl_dt_ax = 570; - protected static final int gen_asrb_ir_ds = 571; + protected static final int gen_asrb_ir_dy = 571; - protected static final int gen_asrb_dd_ds = 572; + protected static final int gen_asrb_dx_dy = 572; - protected static final int gen_asrw_ir_ds = 573; + protected static final int gen_asrw_ir_dy = 573; - protected static final int gen_asrw_dd_ds = 574; + protected static final int gen_asrw_dx_dy = 574; - protected static final int gen_asrl_ir_ds = 575; + protected static final int gen_asrl_ir_dy = 575; - protected static final int gen_asrl_dd_ds = 576; + protected static final int gen_asrl_dx_dy = 576; - protected static final int gen_asrw_ea = 577; + protected static final int gen_asrw_dt = 577; - protected static final int gen_aslb_ir_ds = 578; + protected static final int gen_aslb_ir_dy = 578; - protected static final int gen_aslb_dd_ds = 579; + protected static final int gen_aslb_dx_dy = 579; - protected static final int gen_aslw_ir_ds = 580; + protected static final int gen_aslw_ir_dy = 580; - protected static final int gen_aslw_dd_ds = 581; + protected static final int gen_aslw_dx_dy = 581; - protected static final int gen_asll_ir_ds = 582; + protected static final int gen_asll_ir_dy = 582; - protected static final int gen_asll_dd_ds = 583; + protected static final int gen_asll_dx_dy = 583; - protected static final int gen_aslw_ea = 584; + protected static final int gen_aslw_dt = 584; - protected static final int gen_lsrb_ir_ds = 585; + protected static final int gen_lsrb_ir_dy = 585; - protected static final int gen_lsrb_dd_ds = 586; + protected static final int gen_lsrb_dx_dy = 586; - protected static final int gen_lsrw_ir_ds = 587; + protected static final int gen_lsrw_ir_dy = 587; - protected static final int gen_lsrw_dd_ds = 588; + protected static final int gen_lsrw_dx_dy = 588; - protected static final int gen_lsrl_ir_ds = 589; + protected static final int gen_lsrl_ir_dy = 589; - protected static final int gen_lsrl_dd_ds = 590; + protected static final int gen_lsrl_dx_dy = 590; - protected static final int gen_lsrw_ea = 591; + protected static final int gen_lsrw_dt = 591; - protected static final int gen_lslb_ir_ds = 592; + protected static final int gen_lslb_ir_dy = 592; - protected static final int gen_lslb_dd_ds = 593; + protected static final int gen_lslb_dx_dy = 593; - protected static final int gen_lslw_ir_ds = 594; + protected static final int gen_lslw_ir_dy = 594; - protected static final int gen_lslw_dd_ds = 595; + protected static final int gen_lslw_dx_dy = 595; - protected static final int gen_lsll_ir_ds = 596; + protected static final int gen_lsll_ir_dy = 596; - protected static final int gen_lsll_dd_ds = 597; + protected static final int gen_lsll_dx_dy = 597; - protected static final int gen_lslw_ea = 598; + protected static final int gen_lslw_dt = 598; - protected static final int gen_rorb_ir_ds = 599; + protected static final int gen_rorb_ir_dy = 599; - protected static final int gen_rorb_dd_ds = 600; + protected static final int gen_rorb_dx_dy = 600; - protected static final int gen_rorw_ir_ds = 601; + protected static final int gen_rorw_ir_dy = 601; - protected static final int gen_rorw_dd_ds = 602; + protected static final int gen_rorw_dx_dy = 602; - protected static final int gen_rorl_ir_ds = 603; + protected static final int gen_rorl_ir_dy = 603; - protected static final int gen_rorl_dd_ds = 604; + protected static final int gen_rorl_dx_dy = 604; - protected static final int gen_rorw_ea = 605; + protected static final int gen_rorw_dt = 605; - protected static final int gen_rolb_ir_ds = 606; + protected static final int gen_rolb_ir_dy = 606; - protected static final int gen_rolb_dd_ds = 607; + protected static final int gen_rolb_dx_dy = 607; - protected static final int gen_rolw_ir_ds = 608; + protected static final int gen_rolw_ir_dy = 608; - protected static final int gen_rolw_dd_ds = 609; + protected static final int gen_rolw_dx_dy = 609; - protected static final int gen_roll_ir_ds = 610; + protected static final int gen_roll_ir_dy = 610; - protected static final int gen_roll_dd_ds = 611; + protected static final int gen_roll_dx_dy = 611; - protected static final int gen_rolw_ea = 612; + protected static final int gen_rolw_dt = 612; public static final int BKPT_EXIT = 0x00010000; @@ -4642,7 +4642,8 @@ public abstract class Core extends CoreALU { case 305: dt = dib; elapsed += 2; - scan = dt; + pc += dt; + scan = 0; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; @@ -4739,7 +4740,8 @@ public abstract class Core extends CoreALU { continue; } case 313: - scan = dt; + pc += dt; + scan = 0; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; @@ -5253,33 +5255,33 @@ public abstract class Core extends CoreALU { tvn = 28; mpc = trap2000; continue; - case 343: /* gen_orb_dt_ds */ + case 343: /* gen_orb_dt_dy */ ry = ir & 0x0007; dt = byte_or(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 344: /* gen_orb_im_ea */ + case 344: /* gen_orb_alub_dt */ dt = byte_or(alub, dt); mpc = ea_resume_write8; continue; - case 345: /* gen_orw_dt_ds */ + case 345: /* gen_orw_dt_dy */ ry = ir & 0x0007; dt = word_or(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 346: /* gen_orw_im_ea */ + case 346: /* gen_orw_alub_dt */ dt = word_or(alub, dt); mpc = ea_resume_write16; continue; - case 347: /* gen_orl_dt_ds */ + case 347: /* gen_orl_dt_dy */ ry = ir & 0x0007; dt = long_or(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 348: /* gen_orl_im_ea */ + case 348: /* gen_orl_alub_dt */ dt = long_or(alub, dt); mpc = ea_resume_write32; continue; @@ -5297,80 +5299,80 @@ public abstract class Core extends CoreALU { sr = (sr | dt) & 0xf71f; mpc = resume_prefetch; continue; - case 351: /* gen_btstl_dd_ds */ + case 351: /* gen_btstl_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; long_btst(dar[rx], dar[ry]); mpc = resume_prefetch; continue; - case 352: /* gen_btstb_dd_ea */ + case 352: /* gen_btstb_dx_dt */ rx = (ir >> 9) & 0x0007; byte_btst(dar[rx], dt); mpc = resume_prefetch; continue; - case 353: /* gen_bchgl_dd_ds */ + case 353: /* gen_bchgl_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bchg(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 354: /* gen_bchgb_dd_ea */ + case 354: /* gen_bchgb_dx_dt */ rx = (ir >> 9) & 0x0007; dt = byte_bchg(dar[rx], dt); mpc = ea_resume_write8; continue; - case 355: /* gen_bclrl_dd_ds */ + case 355: /* gen_bclrl_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bclr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 356: /* gen_bclrb_dd_ea */ + case 356: /* gen_bclrb_dx_dt */ rx = (ir >> 9) & 0x0007; dt = byte_bclr(dar[rx], dt); mpc = ea_resume_write8; continue; - case 357: /* gen_bsetl_dd_ds */ + case 357: /* gen_bsetl_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bset(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 358: /* gen_bsetb_dd_ea */ + case 358: /* gen_bsetb_dx_dt */ rx = (ir >> 9) & 0x0007; dt = byte_bset(dar[rx], dt); mpc = ea_resume_write8; continue; - case 359: /* gen_andb_dt_ds */ + case 359: /* gen_andb_dt_dy */ ry = ir & 0x0007; dt = byte_and(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 360: /* gen_andb_im_ea */ + case 360: /* gen_andb_alub_dt */ dt = byte_and(alub, dt); mpc = ea_resume_write8; continue; - case 361: /* gen_andw_dt_ds */ + case 361: /* gen_andw_dt_dy */ ry = ir & 0x0007; dt = word_and(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 362: /* gen_andw_im_ea */ + case 362: /* gen_andw_alub_dt */ dt = word_and(alub, dt); mpc = ea_resume_write16; continue; - case 363: /* gen_andl_dt_ds */ + case 363: /* gen_andl_dt_dy */ ry = ir & 0x0007; dt = long_and(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 364: /* gen_andl_im_ea */ + case 364: /* gen_andl_alub_dt */ dt = long_and(alub, dt); mpc = ea_resume_write32; continue; @@ -5388,132 +5390,132 @@ public abstract class Core extends CoreALU { sr = sr & dt; mpc = resume_prefetch; continue; - case 367: /* gen_subb_dt_ds */ + case 367: /* gen_subb_dt_dy */ ry = ir & 0x0007; dt = byte_sub(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 368: /* gen_subb_im_ea */ + case 368: /* gen_subb_alub_dt */ dt = byte_sub(alub, dt); mpc = ea_resume_write8; continue; - case 369: /* gen_subw_dt_ds */ + case 369: /* gen_subw_dt_dy */ ry = ir & 0x0007; dt = word_sub(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 370: /* gen_subw_im_ea */ + case 370: /* gen_subw_alub_dt */ dt = word_sub(alub, dt); mpc = ea_resume_write16; continue; - case 371: /* gen_subl_dt_ds */ + case 371: /* gen_subl_dt_dy */ ry = ir & 0x0007; dt = long_sub(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 372: /* gen_subl_im_ea */ + case 372: /* gen_subl_alub_dt */ dt = long_sub(alub, dt); mpc = ea_resume_write32; continue; - case 373: /* gen_addb_dt_ds */ + case 373: /* gen_addb_dt_dy */ ry = ir & 0x0007; dt = byte_add(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 374: /* gen_addb_im_ea */ + case 374: /* gen_addb_alub_dt */ dt = byte_add(alub, dt); mpc = ea_resume_write8; continue; - case 375: /* gen_addw_dt_ds */ + case 375: /* gen_addw_dt_dy */ ry = ir & 0x0007; dt = word_add(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 376: /* gen_addw_im_ea */ + case 376: /* gen_addw_alub_dt */ dt = word_add(alub, dt); mpc = ea_resume_write16; continue; - case 377: /* gen_addl_dt_ds */ + case 377: /* gen_addl_dt_dy */ ry = ir & 0x0007; dt = long_add(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 378: /* gen_addl_im_ea */ + case 378: /* gen_addl_alub_dt */ dt = long_add(alub, dt); mpc = ea_resume_write32; continue; - case 379: /* gen_btstl_dt_ds */ + case 379: /* gen_btstl_dt_dy */ ry = ir & 0x0007; long_btst(dt, dar[ry]); mpc = resume_prefetch; continue; - case 380: /* gen_btstb_im_ea */ + case 380: /* gen_btstb_alub_dt */ byte_btst(alub, dt); mpc = resume_prefetch; continue; - case 381: /* gen_bchgl_dt_ds */ + case 381: /* gen_bchgl_dt_dy */ ry = ir & 0x0007; dt = long_bchg(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 382: /* gen_bchgb_im_ea */ + case 382: /* gen_bchgb_alub_dt */ dt = byte_bchg(alub, dt); mpc = ea_resume_write8; continue; - case 383: /* gen_bclrl_dt_ds */ + case 383: /* gen_bclrl_dt_dy */ ry = ir & 0x0007; dt = long_bclr(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 384: /* gen_bclrb_im_ea */ + case 384: /* gen_bclrb_alub_dt */ dt = byte_bclr(alub, dt); mpc = ea_resume_write8; continue; - case 385: /* gen_bsetl_dt_ds */ + case 385: /* gen_bsetl_dt_dy */ ry = ir & 0x0007; dt = long_bset(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 386: /* gen_bsetb_im_ea */ + case 386: /* gen_bsetb_alub_dt */ dt = byte_bset(alub, dt); mpc = ea_resume_write8; continue; - case 387: /* gen_eorb_dt_ds */ + case 387: /* gen_eorb_dt_dy */ ry = ir & 0x0007; dt = byte_eor(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 388: /* gen_eorb_im_ea */ + case 388: /* gen_eorb_alub_dt */ dt = byte_eor(alub, dt); mpc = ea_resume_write8; continue; - case 389: /* gen_eorw_dt_ds */ + case 389: /* gen_eorw_dt_dy */ ry = ir & 0x0007; dt = word_eor(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 390: /* gen_eorw_im_ea */ + case 390: /* gen_eorw_alub_dt */ dt = word_eor(alub, dt); mpc = ea_resume_write16; continue; - case 391: /* gen_eorl_dt_ds */ + case 391: /* gen_eorl_dt_dy */ ry = ir & 0x0007; dt = long_eor(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 392: /* gen_eorl_im_ea */ + case 392: /* gen_eorl_alub_dt */ dt = long_eor(alub, dt); mpc = ea_resume_write32; continue; @@ -5531,80 +5533,80 @@ public abstract class Core extends CoreALU { sr = (sr ^ dt) & 0xf71f; mpc = resume_prefetch; continue; - case 395: /* gen_cmpb_dt_ds */ + case 395: /* gen_cmpb_dt_dy */ ry = ir & 0x0007; byte_cmp(dt, dar[ry]); mpc = resume_prefetch; continue; - case 396: /* gen_cmpb_im_ea */ + case 396: /* gen_cmpb_alub_dt */ byte_cmp(alub, dt); mpc = resume_prefetch; continue; - case 397: /* gen_cmpw_dt_ds */ + case 397: /* gen_cmpw_dt_dy */ ry = ir & 0x0007; word_cmp(dt, dar[ry]); mpc = resume_prefetch; continue; - case 398: /* gen_cmpw_im_ea */ + case 398: /* gen_cmpw_alub_dt */ word_cmp(alub, dt); mpc = resume_prefetch; continue; - case 399: /* gen_cmpl_dt_ds */ + case 399: /* gen_cmpl_dt_dy */ ry = ir & 0x0007; long_cmp(dt, dar[ry]); mpc = resume_prefetch; continue; - case 400: /* gen_cmpl_im_ea */ + case 400: /* gen_cmpl_alub_dt */ long_cmp(alub, dt); mpc = resume_prefetch; continue; - case 401: /* gen_moveb_ds_ea */ + case 401: /* gen_moveb_dy_dt */ ry = ir & 0x0007; byte_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write8; continue; - case 402: /* gen_moveb_dt_dd */ + case 402: /* gen_moveb_dt_dx */ rx = (ir >> 9) & 0x0007; byte_tst(dt); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 403: /* gen_moveb_ds_dd */ + case 403: /* gen_moveb_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; byte_tst(dar[ry]); dar[rx] = (dar[rx] & ~0xff) | (dar[ry] & 0xff); mpc = resume_prefetch; continue; - case 404: /* gen_moveb_dt_ea */ + case 404: /* gen_moveb_dt_dt */ byte_tst(dt); mpc = ea_resume_write8; continue; - case 405: /* gen_movel_ds_ea */ + case 405: /* gen_movel_dy_dt */ ry = ir & 0x0007; long_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write32; continue; - case 406: /* gen_movel_dt_ea */ + case 406: /* gen_movel_dt_dt */ long_tst(dt); mpc = ea_resume_write32; continue; - case 407: /* gen_movel_dt_dd */ + case 407: /* gen_movel_dt_dx */ rx = (ir >> 9) & 0x0007; long_tst(dt); dar[rx] = dt; mpc = resume_prefetch; continue; - case 408: /* gen_movel_ds_dd */ + case 408: /* gen_movel_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; long_tst(dar[ry]); dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 409: /* gen_movel_as_dd */ + case 409: /* gen_movel_ay_dx */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5612,14 +5614,14 @@ public abstract class Core extends CoreALU { dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 410: /* gen_movel_ds_ad */ + case 410: /* gen_movel_dy_ax */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 411: /* gen_movel_as_ad */ + case 411: /* gen_movel_ay_ax */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5627,36 +5629,36 @@ public abstract class Core extends CoreALU { dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 412: /* gen_movel_dt_ad */ + case 412: /* gen_movel_dt_ax */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dt; mpc = resume_prefetch; continue; - case 413: /* gen_movew_ds_ea */ + case 413: /* gen_movew_dy_dt */ ry = ir & 0x0007; word_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write16; continue; - case 414: /* gen_movew_dt_ea */ + case 414: /* gen_movew_dt_dt */ word_tst(dt); mpc = ea_resume_write16; continue; - case 415: /* gen_movew_dt_dd */ + case 415: /* gen_movew_dt_dx */ rx = (ir >> 9) & 0x0007; word_tst(dt); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 416: /* gen_movew_ds_dd */ + case 416: /* gen_movew_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; word_tst(dar[ry]); dar[rx] = (dar[rx] & ~0xffff) | (dar[ry] & 0xffff); mpc = resume_prefetch; continue; - case 417: /* gen_movew_as_dd */ + case 417: /* gen_movew_ay_dx */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5664,14 +5666,14 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dar[ry] & 0xffff); mpc = resume_prefetch; continue; - case 418: /* gen_movew_ds_ad */ + case 418: /* gen_movew_dy_ax */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = (short) dar[ry]; mpc = resume_prefetch; continue; - case 419: /* gen_movew_as_ad */ + case 419: /* gen_movew_ay_ax */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5679,43 +5681,43 @@ public abstract class Core extends CoreALU { dar[rx] = (short) dar[ry]; mpc = resume_prefetch; continue; - case 420: /* gen_movew_dt_ad */ + case 420: /* gen_movew_dt_ax */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = (short) dt; mpc = resume_prefetch; continue; - case 421: /* gen_negxb_ds */ + case 421: /* gen_negxb_dy */ ry = ir & 0x0007; dt = byte_negx(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 422: /* gen_negxb_ea */ + case 422: /* gen_negxb_dt */ dt = byte_negx(dt); mpc = ea_resume_write8; continue; - case 423: /* gen_negxw_ds */ + case 423: /* gen_negxw_dy */ ry = ir & 0x0007; dt = word_negx(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 424: /* gen_negxw_ea */ + case 424: /* gen_negxw_dt */ dt = word_negx(dt); mpc = ea_resume_write16; continue; - case 425: /* gen_negxl_ds */ + case 425: /* gen_negxl_dy */ ry = ir & 0x0007; dt = long_negx(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 426: /* gen_negxl_ea */ + case 426: /* gen_negxl_dt */ dt = long_negx(dt); mpc = ea_resume_write32; continue; - case 427: /* gen_movew_sr_ds */ + case 427: /* gen_movew_sr_dy */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5726,7 +5728,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (sr & 0xffff); mpc = resume_prefetch; continue; - case 428: /* gen_movew_sr_ea */ + case 428: /* gen_movew_sr_dt */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5736,16 +5738,16 @@ public abstract class Core extends CoreALU { dt = (sr & 0xf71f); mpc = ea_resume_write16; continue; - case 429: /* gen_movew_ccr_ds */ + case 429: /* gen_movew_ccr_dy */ ry = ir & 0x0007; dar[ry] = (dar[ry] & ~0xffff) | (sr & 0x001f); mpc = resume_prefetch; continue; - case 430: /* gen_movew_ccr_ea */ + case 430: /* gen_movew_ccr_dt */ dt = (sr & 0x001f); mpc = ea_resume_write16; continue; - case 431: /* gen_movew_ds_ccr */ + case 431: /* gen_movew_dy_ccr */ ry = ir & 0x0007; sr = (sr & ~0xff) | (dar[ry] & 0x001f); mpc = resume_prefetch; @@ -5754,7 +5756,7 @@ public abstract class Core extends CoreALU { sr = (sr & ~0xff) | (dt & 0x001f); mpc = resume_prefetch; continue; - case 433: /* gen_movew_ds_sr */ + case 433: /* gen_movew_dy_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5775,104 +5777,104 @@ public abstract class Core extends CoreALU { sr = dt & 0xf71f; mpc = resume_prefetch; continue; - case 435: /* gen_negb_ds */ + case 435: /* gen_negb_dy */ ry = ir & 0x0007; dt = byte_neg(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 436: /* gen_negb_ea */ + case 436: /* gen_negb_dt */ dt = byte_neg(dt); mpc = ea_resume_write8; continue; - case 437: /* gen_negw_ds */ + case 437: /* gen_negw_dy */ ry = ir & 0x0007; dt = word_neg(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 438: /* gen_negw_ea */ + case 438: /* gen_negw_dt */ dt = word_neg(dt); mpc = ea_resume_write16; continue; - case 439: /* gen_negl_ds */ + case 439: /* gen_negl_dy */ ry = ir & 0x0007; dt = long_neg(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 440: /* gen_negl_ea */ + case 440: /* gen_negl_dt */ dt = long_neg(dt); mpc = ea_resume_write32; continue; - case 441: /* gen_notb_ds */ + case 441: /* gen_notb_dy */ ry = ir & 0x0007; dt = byte_not(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 442: /* gen_notb_ea */ + case 442: /* gen_notb_dt */ dt = byte_not(dt); mpc = ea_resume_write8; continue; - case 443: /* gen_notw_ds */ + case 443: /* gen_notw_dy */ ry = ir & 0x0007; dt = word_not(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 444: /* gen_notw_ea */ + case 444: /* gen_notw_dt */ dt = word_not(dt); mpc = ea_resume_write16; continue; - case 445: /* gen_notl_ds */ + case 445: /* gen_notl_dy */ ry = ir & 0x0007; dt = long_not(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 446: /* gen_notl_ea */ + case 446: /* gen_notl_dt */ dt = long_not(dt); mpc = ea_resume_write32; continue; - case 447: /* gen_nbcdb_ds */ + case 447: /* gen_nbcdb_dy */ ry = ir & 0x0007; dt = byte_nbcd(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 448: /* gen_nbcdb_ea */ + case 448: /* gen_nbcdb_dt */ dt = byte_nbcd(dt); mpc = ea_resume_write8; continue; - case 449: /* gen_tstb_ds */ + case 449: /* gen_tstb_dy */ ry = ir & 0x0007; byte_tst(dar[ry]); mpc = resume_prefetch; continue; - case 450: /* gen_tstb_ea */ + case 450: /* gen_tstb_dt */ byte_tst(dt); mpc = resume_prefetch; continue; - case 451: /* gen_tstw_ds */ + case 451: /* gen_tstw_dy */ ry = ir & 0x0007; word_tst(dar[ry]); mpc = resume_prefetch; continue; - case 452: /* gen_tstw_ea */ + case 452: /* gen_tstw_dt */ word_tst(dt); mpc = resume_prefetch; continue; - case 453: /* gen_tstl_ds */ + case 453: /* gen_tstl_dy */ ry = ir & 0x0007; long_tst(dar[ry]); mpc = resume_prefetch; continue; - case 454: /* gen_tstl_ea */ + case 454: /* gen_tstl_dt */ long_tst(dt); mpc = resume_prefetch; continue; - case 455: /* gen_addb_ir_ds */ + case 455: /* gen_addb_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5882,7 +5884,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 456: /* gen_addb_ir_ea */ + case 456: /* gen_addb_ir_dt */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5890,7 +5892,7 @@ public abstract class Core extends CoreALU { dt = byte_add(alub, dt); mpc = ea_resume_write8; continue; - case 457: /* gen_addw_ir_ds */ + case 457: /* gen_addw_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5900,7 +5902,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 458: /* gen_addw_ir_as */ + case 458: /* gen_addw_ir_ay */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5910,7 +5912,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] + ((short) alub); mpc = resume_prefetch; continue; - case 459: /* gen_addw_ir_ea */ + case 459: /* gen_addw_ir_dt */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5918,7 +5920,7 @@ public abstract class Core extends CoreALU { dt = word_add(alub, dt); mpc = ea_resume_write16; continue; - case 460: /* gen_addl_ir_ds */ + case 460: /* gen_addl_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5928,7 +5930,7 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 461: /* gen_addl_ir_as */ + case 461: /* gen_addl_ir_ay */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5938,7 +5940,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] + alub; mpc = resume_prefetch; continue; - case 462: /* gen_addl_ir_ea */ + case 462: /* gen_addl_ir_dt */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5946,7 +5948,7 @@ public abstract class Core extends CoreALU { dt = long_add(alub, dt); mpc = ea_resume_write32; continue; - case 463: /* gen_subb_ir_ds */ + case 463: /* gen_subb_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5956,7 +5958,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 464: /* gen_subb_ir_ea */ + case 464: /* gen_subb_ir_dt */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5964,7 +5966,7 @@ public abstract class Core extends CoreALU { dt = byte_sub(alub, dt); mpc = ea_resume_write8; continue; - case 465: /* gen_subw_ir_ds */ + case 465: /* gen_subw_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5974,7 +5976,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 466: /* gen_subw_ir_as */ + case 466: /* gen_subw_ir_ay */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5984,7 +5986,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] - ((short) alub); mpc = resume_prefetch; continue; - case 467: /* gen_subw_ir_ea */ + case 467: /* gen_subw_ir_dt */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5992,7 +5994,7 @@ public abstract class Core extends CoreALU { dt = word_sub(alub, dt); mpc = ea_resume_write16; continue; - case 468: /* gen_subl_ir_ds */ + case 468: /* gen_subl_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6002,7 +6004,7 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 469: /* gen_subl_ir_as */ + case 469: /* gen_subl_ir_ay */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6012,7 +6014,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] - alub; mpc = resume_prefetch; continue; - case 470: /* gen_subl_ir_ea */ + case 470: /* gen_subl_ir_dt */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6020,79 +6022,79 @@ public abstract class Core extends CoreALU { dt = long_sub(alub, dt); mpc = ea_resume_write32; continue; - case 471: /* gen_movel_im_dd */ + case 471: /* gen_movel_ir_dx */ dt = (byte) ir; rx = (ir >> 9) & 0x0007; long_tst(dt); dar[rx] = dt; mpc = resume_prefetch; continue; - case 472: /* gen_orb_ds_dd */ + case 472: /* gen_orb_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_or(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 473: /* gen_orb_dt_dd */ + case 473: /* gen_orb_dt_dx */ rx = (ir >> 9) & 0x0007; dt = byte_or(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 474: /* gen_orw_ds_dd */ + case 474: /* gen_orw_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_or(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 475: /* gen_orw_dt_dd */ + case 475: /* gen_orw_dt_dx */ rx = (ir >> 9) & 0x0007; dt = word_or(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 476: /* gen_orl_ds_dd */ + case 476: /* gen_orl_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_or(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 477: /* gen_orl_dt_dd */ + case 477: /* gen_orl_dt_dx */ rx = (ir >> 9) & 0x0007; dt = long_or(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 478: /* gen_sbcdb_ds_dd */ + case 478: /* gen_sbcdb_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_sbcd(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 479: /* gen_sbcdb_im_ea */ + case 479: /* gen_sbcdb_alub_dt */ dt = byte_sbcd(alub, dt); mpc = ea_resume_write8; continue; - case 480: /* gen_orb_dd_ea */ + case 480: /* gen_orb_dx_dt */ rx = (ir >> 9) & 0x0007; dt = byte_or(dar[rx], dt); mpc = ea_resume_write8; continue; - case 481: /* gen_orw_dd_ea */ + case 481: /* gen_orw_dx_dt */ rx = (ir >> 9) & 0x0007; dt = word_or(dar[rx], dt); mpc = ea_resume_write16; continue; - case 482: /* gen_orl_dd_ea */ + case 482: /* gen_orl_dx_dt */ rx = (ir >> 9) & 0x0007; dt = long_or(dar[rx], dt); mpc = ea_resume_write32; continue; - case 483: /* gen_divuw_ds_dd */ + case 483: /* gen_divuw_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; if ((dar[ry] & 0xffff) == 0) { @@ -6104,7 +6106,7 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 484: /* gen_divuw_dt_dd */ + case 484: /* gen_divuw_dt_dx */ rx = (ir >> 9) & 0x0007; if ((dt & 0xffff) == 0) { tvn = 20; @@ -6115,7 +6117,7 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 485: /* gen_divsw_ds_dd */ + case 485: /* gen_divsw_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; if ((dar[ry] & 0xffff) == 0) { @@ -6127,7 +6129,7 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 486: /* gen_divsw_dt_dd */ + case 486: /* gen_divsw_dt_dx */ rx = (ir >> 9) & 0x0007; if ((dt & 0xffff) == 0) { tvn = 20; @@ -6138,27 +6140,27 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 487: /* gen_subb_ds_dd */ + case 487: /* gen_subb_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_sub(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 488: /* gen_subb_dt_dd */ + case 488: /* gen_subb_dt_dx */ rx = (ir >> 9) & 0x0007; dt = byte_sub(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 489: /* gen_subw_ds_dd */ + case 489: /* gen_subw_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_sub(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 490: /* gen_subw_as_dd */ + case 490: /* gen_subw_ay_dx */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6166,20 +6168,20 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 491: /* gen_subw_dt_dd */ + case 491: /* gen_subw_dt_dx */ rx = (ir >> 9) & 0x0007; dt = word_sub(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 492: /* gen_subl_ds_dd */ + case 492: /* gen_subl_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_sub(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 493: /* gen_subl_as_dd */ + case 493: /* gen_subl_ay_dx */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6187,68 +6189,68 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 494: /* gen_subl_dt_dd */ + case 494: /* gen_subl_dt_dx */ rx = (ir >> 9) & 0x0007; dt = long_sub(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 495: /* gen_subb_dd_ea */ + case 495: /* gen_subb_dx_dt */ rx = (ir >> 9) & 0x0007; dt = byte_sub(dar[rx], dt); mpc = ea_resume_write8; continue; - case 496: /* gen_subw_dd_ea */ + case 496: /* gen_subw_dx_dt */ rx = (ir >> 9) & 0x0007; dt = word_sub(dar[rx], dt); mpc = ea_resume_write16; continue; - case 497: /* gen_subl_dd_ea */ + case 497: /* gen_subl_dx_dt */ rx = (ir >> 9) & 0x0007; dt = long_sub(dar[rx], dt); mpc = ea_resume_write32; continue; - case 498: /* gen_subxb_ds_dd */ + case 498: /* gen_subxb_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_subx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 499: /* gen_subxb_im_ea */ + case 499: /* gen_subxb_alub_dt */ dt = byte_subx(alub, dt); mpc = ea_resume_write8; continue; - case 500: /* gen_subxw_ds_dd */ + case 500: /* gen_subxw_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_subx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 501: /* gen_subxw_im_ea */ + case 501: /* gen_subxw_alub_dt */ dt = word_subx(alub, dt); mpc = ea_resume_write16; continue; - case 502: /* gen_subxl_ds_dd */ + case 502: /* gen_subxl_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_subx(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 503: /* gen_subxl_im_ea */ + case 503: /* gen_subxl_alub_dt */ dt = long_subx(alub, dt); mpc = ea_resume_write32; continue; - case 504: /* gen_subw_ds_ad */ + case 504: /* gen_subw_dy_ax */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - ((short) dar[ry]); mpc = resume_prefetch; continue; - case 505: /* gen_subw_as_ad */ + case 505: /* gen_subw_ay_ax */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6256,20 +6258,20 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] - ((short) dar[ry]); mpc = resume_prefetch; continue; - case 506: /* gen_subw_dt_ad */ + case 506: /* gen_subw_dt_ax */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - ((short) dt); mpc = resume_prefetch; continue; - case 507: /* gen_subl_ds_ad */ + case 507: /* gen_subl_dy_ax */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - dar[ry]; mpc = resume_prefetch; continue; - case 508: /* gen_subl_as_ad */ + case 508: /* gen_subl_ay_ax */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6277,67 +6279,67 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] - dar[ry]; mpc = resume_prefetch; continue; - case 509: /* gen_subl_dt_ad */ + case 509: /* gen_subl_dt_ax */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - dt; mpc = resume_prefetch; continue; - case 510: /* gen_cmpb_ds_dd */ + case 510: /* gen_cmpb_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; byte_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 511: /* gen_cmpb_dt_dd */ + case 511: /* gen_cmpb_dt_dx */ rx = (ir >> 9) & 0x0007; byte_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 512: /* gen_cmpw_ds_dd */ + case 512: /* gen_cmpw_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; word_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 513: /* gen_cmpw_as_dd */ + case 513: /* gen_cmpw_ay_dx */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; word_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 514: /* gen_cmpw_dt_dd */ + case 514: /* gen_cmpw_dt_dx */ rx = (ir >> 9) & 0x0007; word_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 515: /* gen_cmpl_ds_dd */ + case 515: /* gen_cmpl_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 516: /* gen_cmpl_as_dd */ + case 516: /* gen_cmpl_ay_dx */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 517: /* gen_cmpl_dt_dd */ + case 517: /* gen_cmpl_dt_dx */ rx = (ir >> 9) & 0x0007; long_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 518: /* gen_cmpw_ds_ad */ + case 518: /* gen_cmpw_dy_ax */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp((short) dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 519: /* gen_cmpw_as_ad */ + case 519: /* gen_cmpw_ay_ax */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6345,20 +6347,20 @@ public abstract class Core extends CoreALU { long_cmp((short) dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 520: /* gen_cmpw_dt_ad */ + case 520: /* gen_cmpw_dt_ax */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp((short) dt, dar[rx]); mpc = resume_prefetch; continue; - case 521: /* gen_cmpl_ds_ad */ + case 521: /* gen_cmpl_dy_ax */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 522: /* gen_cmpl_as_ad */ + case 522: /* gen_cmpl_ay_ax */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6366,172 +6368,172 @@ public abstract class Core extends CoreALU { long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 523: /* gen_cmpl_dt_ad */ + case 523: /* gen_cmpl_dt_ax */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 524: /* gen_cmpmb_im_ea */ + case 524: /* gen_cmpmb_alub_dt */ byte_cmp(alub, dt); mpc = resume_prefetch; continue; - case 525: /* gen_cmpmw_im_ea */ + case 525: /* gen_cmpmw_alub_dt */ word_cmp(alub, dt); mpc = resume_prefetch; continue; - case 526: /* gen_cmpml_im_ea */ + case 526: /* gen_cmpml_alub_dt */ long_cmp(alub, dt); mpc = resume_prefetch; continue; - case 527: /* gen_eorb_dd_ds */ + case 527: /* gen_eorb_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_eor(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 528: /* gen_eorb_dd_ea */ + case 528: /* gen_eorb_dx_dt */ rx = (ir >> 9) & 0x0007; dt = byte_eor(dar[rx], dt); mpc = ea_resume_write8; continue; - case 529: /* gen_eorw_dd_ds */ + case 529: /* gen_eorw_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_eor(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 530: /* gen_eorw_dd_ea */ + case 530: /* gen_eorw_dx_dt */ rx = (ir >> 9) & 0x0007; dt = word_eor(dar[rx], dt); mpc = ea_resume_write16; continue; - case 531: /* gen_eorl_dd_ds */ + case 531: /* gen_eorl_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_eor(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 532: /* gen_eorl_dd_ea */ + case 532: /* gen_eorl_dx_dt */ rx = (ir >> 9) & 0x0007; dt = long_eor(dar[rx], dt); mpc = ea_resume_write32; continue; - case 533: /* gen_andb_ds_dd */ + case 533: /* gen_andb_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_and(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 534: /* gen_andb_dt_dd */ + case 534: /* gen_andb_dt_dx */ rx = (ir >> 9) & 0x0007; dt = byte_and(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 535: /* gen_andw_ds_dd */ + case 535: /* gen_andw_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_and(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 536: /* gen_andw_dt_dd */ + case 536: /* gen_andw_dt_dx */ rx = (ir >> 9) & 0x0007; dt = word_and(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 537: /* gen_andl_ds_dd */ + case 537: /* gen_andl_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_and(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 538: /* gen_andl_dt_dd */ + case 538: /* gen_andl_dt_dx */ rx = (ir >> 9) & 0x0007; dt = long_and(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 539: /* gen_muluw_ds_dd */ + case 539: /* gen_muluw_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_mulu(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 540: /* gen_muluw_dt_dd */ + case 540: /* gen_muluw_dt_dx */ rx = (ir >> 9) & 0x0007; dt = word_mulu(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 541: /* gen_mulsw_ds_dd */ + case 541: /* gen_mulsw_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_muls(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 542: /* gen_mulsw_dt_dd */ + case 542: /* gen_mulsw_dt_dx */ rx = (ir >> 9) & 0x0007; dt = word_muls(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 543: /* gen_andb_dd_ea */ + case 543: /* gen_andb_dx_dt */ rx = (ir >> 9) & 0x0007; dt = byte_and(dar[rx], dt); mpc = ea_resume_write8; continue; - case 544: /* gen_andw_dd_ea */ + case 544: /* gen_andw_dx_dt */ rx = (ir >> 9) & 0x0007; dt = word_and(dar[rx], dt); mpc = ea_resume_write16; continue; - case 545: /* gen_andl_dd_ea */ + case 545: /* gen_andl_dx_dt */ rx = (ir >> 9) & 0x0007; dt = long_and(dar[rx], dt); mpc = ea_resume_write32; continue; - case 546: /* gen_abcdb_ds_dd */ + case 546: /* gen_abcdb_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_abcd(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 547: /* gen_abcdb_im_ea */ + case 547: /* gen_abcdb_alub_dt */ dt = byte_abcd(alub, dt); mpc = ea_resume_write8; continue; - case 548: /* gen_addb_ds_dd */ + case 548: /* gen_addb_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_add(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 549: /* gen_addb_dt_dd */ + case 549: /* gen_addb_dt_dx */ rx = (ir >> 9) & 0x0007; dt = byte_add(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 550: /* gen_addw_ds_dd */ + case 550: /* gen_addw_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_add(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 551: /* gen_addw_as_dd */ + case 551: /* gen_addw_ay_dx */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6539,20 +6541,20 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 552: /* gen_addw_dt_dd */ + case 552: /* gen_addw_dt_dx */ rx = (ir >> 9) & 0x0007; dt = word_add(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 553: /* gen_addl_ds_dd */ + case 553: /* gen_addl_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_add(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 554: /* gen_addl_as_dd */ + case 554: /* gen_addl_ay_dx */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6560,68 +6562,68 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 555: /* gen_addl_dt_dd */ + case 555: /* gen_addl_dt_dx */ rx = (ir >> 9) & 0x0007; dt = long_add(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 556: /* gen_addb_dd_ea */ + case 556: /* gen_addb_dx_dt */ rx = (ir >> 9) & 0x0007; dt = byte_add(dar[rx], dt); mpc = ea_resume_write8; continue; - case 557: /* gen_addw_dd_ea */ + case 557: /* gen_addw_dx_dt */ rx = (ir >> 9) & 0x0007; dt = word_add(dar[rx], dt); mpc = ea_resume_write16; continue; - case 558: /* gen_addl_dd_ea */ + case 558: /* gen_addl_dx_dt */ rx = (ir >> 9) & 0x0007; dt = long_add(dar[rx], dt); mpc = ea_resume_write32; continue; - case 559: /* gen_addxb_ds_dd */ + case 559: /* gen_addxb_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_addx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 560: /* gen_addxb_im_ea */ + case 560: /* gen_addxb_alub_dt */ dt = byte_addx(alub, dt); mpc = ea_resume_write8; continue; - case 561: /* gen_addxw_ds_dd */ + case 561: /* gen_addxw_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_addx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 562: /* gen_addxw_im_ea */ + case 562: /* gen_addxw_alub_dt */ dt = word_addx(alub, dt); mpc = ea_resume_write16; continue; - case 563: /* gen_addxl_ds_dd */ + case 563: /* gen_addxl_dy_dx */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_addx(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 564: /* gen_addxl_im_ea */ + case 564: /* gen_addxl_alub_dt */ dt = long_addx(alub, dt); mpc = ea_resume_write32; continue; - case 565: /* gen_addw_ds_ad */ + case 565: /* gen_addw_dy_ax */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + ((short) dar[ry]); mpc = resume_prefetch; continue; - case 566: /* gen_addw_as_ad */ + case 566: /* gen_addw_ay_ax */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6629,20 +6631,20 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] + ((short) dar[ry]); mpc = resume_prefetch; continue; - case 567: /* gen_addw_dt_ad */ + case 567: /* gen_addw_dt_ax */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + ((short) dt); mpc = resume_prefetch; continue; - case 568: /* gen_addl_ds_ad */ + case 568: /* gen_addl_dy_ax */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + dar[ry]; mpc = resume_prefetch; continue; - case 569: /* gen_addl_as_ad */ + case 569: /* gen_addl_ay_ax */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6650,13 +6652,13 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] + dar[ry]; mpc = resume_prefetch; continue; - case 570: /* gen_addl_dt_ad */ + case 570: /* gen_addl_dt_ax */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + dt; mpc = resume_prefetch; continue; - case 571: /* gen_asrb_ir_ds */ + case 571: /* gen_asrb_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6666,14 +6668,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 572: /* gen_asrb_dd_ds */ + case 572: /* gen_asrb_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_asr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 573: /* gen_asrw_ir_ds */ + case 573: /* gen_asrw_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6683,14 +6685,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 574: /* gen_asrw_dd_ds */ + case 574: /* gen_asrw_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_asr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 575: /* gen_asrl_ir_ds */ + case 575: /* gen_asrl_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6700,18 +6702,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 576: /* gen_asrl_dd_ds */ + case 576: /* gen_asrl_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_asr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 577: /* gen_asrw_ea */ + case 577: /* gen_asrw_dt */ dt = word_asr(1, dt); mpc = ea_resume_write16; continue; - case 578: /* gen_aslb_ir_ds */ + case 578: /* gen_aslb_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6721,14 +6723,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 579: /* gen_aslb_dd_ds */ + case 579: /* gen_aslb_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_asl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 580: /* gen_aslw_ir_ds */ + case 580: /* gen_aslw_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6738,14 +6740,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 581: /* gen_aslw_dd_ds */ + case 581: /* gen_aslw_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_asl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 582: /* gen_asll_ir_ds */ + case 582: /* gen_asll_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6755,18 +6757,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 583: /* gen_asll_dd_ds */ + case 583: /* gen_asll_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_asl(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 584: /* gen_aslw_ea */ + case 584: /* gen_aslw_dt */ dt = word_asl(1, dt); mpc = ea_resume_write16; continue; - case 585: /* gen_lsrb_ir_ds */ + case 585: /* gen_lsrb_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6776,14 +6778,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 586: /* gen_lsrb_dd_ds */ + case 586: /* gen_lsrb_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_lsr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 587: /* gen_lsrw_ir_ds */ + case 587: /* gen_lsrw_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6793,14 +6795,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 588: /* gen_lsrw_dd_ds */ + case 588: /* gen_lsrw_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_lsr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 589: /* gen_lsrl_ir_ds */ + case 589: /* gen_lsrl_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6810,18 +6812,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 590: /* gen_lsrl_dd_ds */ + case 590: /* gen_lsrl_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_lsr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 591: /* gen_lsrw_ea */ + case 591: /* gen_lsrw_dt */ dt = word_lsr(1, dt); mpc = ea_resume_write16; continue; - case 592: /* gen_lslb_ir_ds */ + case 592: /* gen_lslb_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6831,14 +6833,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 593: /* gen_lslb_dd_ds */ + case 593: /* gen_lslb_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_lsl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 594: /* gen_lslw_ir_ds */ + case 594: /* gen_lslw_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6848,14 +6850,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 595: /* gen_lslw_dd_ds */ + case 595: /* gen_lslw_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_lsl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 596: /* gen_lsll_ir_ds */ + case 596: /* gen_lsll_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6865,18 +6867,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 597: /* gen_lsll_dd_ds */ + case 597: /* gen_lsll_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_lsl(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 598: /* gen_lslw_ea */ + case 598: /* gen_lslw_dt */ dt = word_lsl(1, dt); mpc = ea_resume_write16; continue; - case 599: /* gen_rorb_ir_ds */ + case 599: /* gen_rorb_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6886,14 +6888,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 600: /* gen_rorb_dd_ds */ + case 600: /* gen_rorb_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_ror(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 601: /* gen_rorw_ir_ds */ + case 601: /* gen_rorw_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6903,14 +6905,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 602: /* gen_rorw_dd_ds */ + case 602: /* gen_rorw_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_ror(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 603: /* gen_rorl_ir_ds */ + case 603: /* gen_rorl_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6920,18 +6922,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 604: /* gen_rorl_dd_ds */ + case 604: /* gen_rorl_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_ror(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 605: /* gen_rorw_ea */ + case 605: /* gen_rorw_dt */ dt = word_ror(1, dt); mpc = ea_resume_write16; continue; - case 606: /* gen_rolb_ir_ds */ + case 606: /* gen_rolb_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6941,14 +6943,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 607: /* gen_rolb_dd_ds */ + case 607: /* gen_rolb_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_rol(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 608: /* gen_rolw_ir_ds */ + case 608: /* gen_rolw_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6958,14 +6960,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 609: /* gen_rolw_dd_ds */ + case 609: /* gen_rolw_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_rol(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 610: /* gen_roll_ir_ds */ + case 610: /* gen_roll_ir_dy */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6975,14 +6977,14 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 611: /* gen_roll_dd_ds */ + case 611: /* gen_roll_dx_dy */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_rol(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 612: /* gen_rolw_ea */ + case 612: /* gen_rolw_dt */ dt = word_rol(1, dt); mpc = ea_resume_write16; continue; diff --git a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java index 938a151..147ab76 100644 --- a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java +++ b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java @@ -84,276 +84,276 @@ import static miggy.cpupoet.Core.ea_pais32; import static miggy.cpupoet.Core.ea_pais32_read; import static miggy.cpupoet.Core.ea_pais8; import static miggy.cpupoet.Core.ea_pais8_read; -import static miggy.cpupoet.Core.gen_abcdb_ds_dd; -import static miggy.cpupoet.Core.gen_abcdb_im_ea; -import static miggy.cpupoet.Core.gen_addb_dd_ea; -import static miggy.cpupoet.Core.gen_addb_ds_dd; -import static miggy.cpupoet.Core.gen_addb_dt_dd; -import static miggy.cpupoet.Core.gen_addb_dt_ds; -import static miggy.cpupoet.Core.gen_addb_im_ea; -import static miggy.cpupoet.Core.gen_addb_ir_ds; -import static miggy.cpupoet.Core.gen_addb_ir_ea; -import static miggy.cpupoet.Core.gen_addl_as_ad; -import static miggy.cpupoet.Core.gen_addl_as_dd; -import static miggy.cpupoet.Core.gen_addl_dd_ea; -import static miggy.cpupoet.Core.gen_addl_ds_ad; -import static miggy.cpupoet.Core.gen_addl_ds_dd; -import static miggy.cpupoet.Core.gen_addl_dt_ad; -import static miggy.cpupoet.Core.gen_addl_dt_dd; -import static miggy.cpupoet.Core.gen_addl_dt_ds; -import static miggy.cpupoet.Core.gen_addl_im_ea; -import static miggy.cpupoet.Core.gen_addl_ir_as; -import static miggy.cpupoet.Core.gen_addl_ir_ds; -import static miggy.cpupoet.Core.gen_addl_ir_ea; -import static miggy.cpupoet.Core.gen_addw_as_ad; -import static miggy.cpupoet.Core.gen_addw_as_dd; -import static miggy.cpupoet.Core.gen_addw_dd_ea; -import static miggy.cpupoet.Core.gen_addw_ds_ad; -import static miggy.cpupoet.Core.gen_addw_ds_dd; -import static miggy.cpupoet.Core.gen_addw_dt_ad; -import static miggy.cpupoet.Core.gen_addw_dt_dd; -import static miggy.cpupoet.Core.gen_addw_dt_ds; -import static miggy.cpupoet.Core.gen_addw_im_ea; -import static miggy.cpupoet.Core.gen_addw_ir_as; -import static miggy.cpupoet.Core.gen_addw_ir_ds; -import static miggy.cpupoet.Core.gen_addw_ir_ea; -import static miggy.cpupoet.Core.gen_addxb_ds_dd; -import static miggy.cpupoet.Core.gen_addxb_im_ea; -import static miggy.cpupoet.Core.gen_addxl_ds_dd; -import static miggy.cpupoet.Core.gen_addxl_im_ea; -import static miggy.cpupoet.Core.gen_addxw_ds_dd; -import static miggy.cpupoet.Core.gen_addxw_im_ea; -import static miggy.cpupoet.Core.gen_andb_dd_ea; -import static miggy.cpupoet.Core.gen_andb_ds_dd; +import static miggy.cpupoet.Core.gen_abcdb_alub_dt; +import static miggy.cpupoet.Core.gen_abcdb_dy_dx; +import static miggy.cpupoet.Core.gen_addb_alub_dt; +import static miggy.cpupoet.Core.gen_addb_dt_dx; +import static miggy.cpupoet.Core.gen_addb_dt_dy; +import static miggy.cpupoet.Core.gen_addb_dx_dt; +import static miggy.cpupoet.Core.gen_addb_dy_dx; +import static miggy.cpupoet.Core.gen_addb_ir_dt; +import static miggy.cpupoet.Core.gen_addb_ir_dy; +import static miggy.cpupoet.Core.gen_addl_alub_dt; +import static miggy.cpupoet.Core.gen_addl_ay_ax; +import static miggy.cpupoet.Core.gen_addl_ay_dx; +import static miggy.cpupoet.Core.gen_addl_dt_ax; +import static miggy.cpupoet.Core.gen_addl_dt_dx; +import static miggy.cpupoet.Core.gen_addl_dt_dy; +import static miggy.cpupoet.Core.gen_addl_dx_dt; +import static miggy.cpupoet.Core.gen_addl_dy_ax; +import static miggy.cpupoet.Core.gen_addl_dy_dx; +import static miggy.cpupoet.Core.gen_addl_ir_ay; +import static miggy.cpupoet.Core.gen_addl_ir_dt; +import static miggy.cpupoet.Core.gen_addl_ir_dy; +import static miggy.cpupoet.Core.gen_addw_alub_dt; +import static miggy.cpupoet.Core.gen_addw_ay_ax; +import static miggy.cpupoet.Core.gen_addw_ay_dx; +import static miggy.cpupoet.Core.gen_addw_dt_ax; +import static miggy.cpupoet.Core.gen_addw_dt_dx; +import static miggy.cpupoet.Core.gen_addw_dt_dy; +import static miggy.cpupoet.Core.gen_addw_dx_dt; +import static miggy.cpupoet.Core.gen_addw_dy_ax; +import static miggy.cpupoet.Core.gen_addw_dy_dx; +import static miggy.cpupoet.Core.gen_addw_ir_ay; +import static miggy.cpupoet.Core.gen_addw_ir_dt; +import static miggy.cpupoet.Core.gen_addw_ir_dy; +import static miggy.cpupoet.Core.gen_addxb_alub_dt; +import static miggy.cpupoet.Core.gen_addxb_dy_dx; +import static miggy.cpupoet.Core.gen_addxl_alub_dt; +import static miggy.cpupoet.Core.gen_addxl_dy_dx; +import static miggy.cpupoet.Core.gen_addxw_alub_dt; +import static miggy.cpupoet.Core.gen_addxw_dy_dx; +import static miggy.cpupoet.Core.gen_andb_alub_dt; import static miggy.cpupoet.Core.gen_andb_dt_ccr; -import static miggy.cpupoet.Core.gen_andb_dt_dd; -import static miggy.cpupoet.Core.gen_andb_dt_ds; -import static miggy.cpupoet.Core.gen_andb_im_ea; -import static miggy.cpupoet.Core.gen_andl_dd_ea; -import static miggy.cpupoet.Core.gen_andl_ds_dd; -import static miggy.cpupoet.Core.gen_andl_dt_dd; -import static miggy.cpupoet.Core.gen_andl_dt_ds; -import static miggy.cpupoet.Core.gen_andl_im_ea; -import static miggy.cpupoet.Core.gen_andw_dd_ea; -import static miggy.cpupoet.Core.gen_andw_ds_dd; -import static miggy.cpupoet.Core.gen_andw_dt_dd; -import static miggy.cpupoet.Core.gen_andw_dt_ds; +import static miggy.cpupoet.Core.gen_andb_dt_dx; +import static miggy.cpupoet.Core.gen_andb_dt_dy; +import static miggy.cpupoet.Core.gen_andb_dx_dt; +import static miggy.cpupoet.Core.gen_andb_dy_dx; +import static miggy.cpupoet.Core.gen_andl_alub_dt; +import static miggy.cpupoet.Core.gen_andl_dt_dx; +import static miggy.cpupoet.Core.gen_andl_dt_dy; +import static miggy.cpupoet.Core.gen_andl_dx_dt; +import static miggy.cpupoet.Core.gen_andl_dy_dx; +import static miggy.cpupoet.Core.gen_andw_alub_dt; +import static miggy.cpupoet.Core.gen_andw_dt_dx; +import static miggy.cpupoet.Core.gen_andw_dt_dy; import static miggy.cpupoet.Core.gen_andw_dt_sr; -import static miggy.cpupoet.Core.gen_andw_im_ea; -import static miggy.cpupoet.Core.gen_aslb_dd_ds; -import static miggy.cpupoet.Core.gen_aslb_ir_ds; -import static miggy.cpupoet.Core.gen_asll_dd_ds; -import static miggy.cpupoet.Core.gen_asll_ir_ds; -import static miggy.cpupoet.Core.gen_aslw_dd_ds; -import static miggy.cpupoet.Core.gen_aslw_ea; -import static miggy.cpupoet.Core.gen_aslw_ir_ds; -import static miggy.cpupoet.Core.gen_asrb_dd_ds; -import static miggy.cpupoet.Core.gen_asrb_ir_ds; -import static miggy.cpupoet.Core.gen_asrl_dd_ds; -import static miggy.cpupoet.Core.gen_asrl_ir_ds; -import static miggy.cpupoet.Core.gen_asrw_dd_ds; -import static miggy.cpupoet.Core.gen_asrw_ea; -import static miggy.cpupoet.Core.gen_asrw_ir_ds; -import static miggy.cpupoet.Core.gen_bchgb_dd_ea; -import static miggy.cpupoet.Core.gen_bchgb_im_ea; -import static miggy.cpupoet.Core.gen_bchgl_dd_ds; -import static miggy.cpupoet.Core.gen_bchgl_dt_ds; -import static miggy.cpupoet.Core.gen_bclrb_dd_ea; -import static miggy.cpupoet.Core.gen_bclrb_im_ea; -import static miggy.cpupoet.Core.gen_bclrl_dd_ds; -import static miggy.cpupoet.Core.gen_bclrl_dt_ds; -import static miggy.cpupoet.Core.gen_bsetb_dd_ea; -import static miggy.cpupoet.Core.gen_bsetb_im_ea; -import static miggy.cpupoet.Core.gen_bsetl_dd_ds; -import static miggy.cpupoet.Core.gen_bsetl_dt_ds; -import static miggy.cpupoet.Core.gen_btstb_dd_ea; -import static miggy.cpupoet.Core.gen_btstb_im_ea; -import static miggy.cpupoet.Core.gen_btstl_dd_ds; -import static miggy.cpupoet.Core.gen_btstl_dt_ds; -import static miggy.cpupoet.Core.gen_cmpb_ds_dd; -import static miggy.cpupoet.Core.gen_cmpb_dt_dd; -import static miggy.cpupoet.Core.gen_cmpb_dt_ds; -import static miggy.cpupoet.Core.gen_cmpb_im_ea; -import static miggy.cpupoet.Core.gen_cmpl_as_ad; -import static miggy.cpupoet.Core.gen_cmpl_as_dd; -import static miggy.cpupoet.Core.gen_cmpl_ds_ad; -import static miggy.cpupoet.Core.gen_cmpl_ds_dd; -import static miggy.cpupoet.Core.gen_cmpl_dt_ad; -import static miggy.cpupoet.Core.gen_cmpl_dt_dd; -import static miggy.cpupoet.Core.gen_cmpl_dt_ds; -import static miggy.cpupoet.Core.gen_cmpl_im_ea; -import static miggy.cpupoet.Core.gen_cmpmb_im_ea; -import static miggy.cpupoet.Core.gen_cmpml_im_ea; -import static miggy.cpupoet.Core.gen_cmpmw_im_ea; -import static miggy.cpupoet.Core.gen_cmpw_as_ad; -import static miggy.cpupoet.Core.gen_cmpw_as_dd; -import static miggy.cpupoet.Core.gen_cmpw_ds_ad; -import static miggy.cpupoet.Core.gen_cmpw_ds_dd; -import static miggy.cpupoet.Core.gen_cmpw_dt_ad; -import static miggy.cpupoet.Core.gen_cmpw_dt_dd; -import static miggy.cpupoet.Core.gen_cmpw_dt_ds; -import static miggy.cpupoet.Core.gen_cmpw_im_ea; -import static miggy.cpupoet.Core.gen_divsw_ds_dd; -import static miggy.cpupoet.Core.gen_divsw_dt_dd; -import static miggy.cpupoet.Core.gen_divuw_ds_dd; -import static miggy.cpupoet.Core.gen_divuw_dt_dd; -import static miggy.cpupoet.Core.gen_eorb_dd_ds; -import static miggy.cpupoet.Core.gen_eorb_dd_ea; +import static miggy.cpupoet.Core.gen_andw_dx_dt; +import static miggy.cpupoet.Core.gen_andw_dy_dx; +import static miggy.cpupoet.Core.gen_aslb_dx_dy; +import static miggy.cpupoet.Core.gen_aslb_ir_dy; +import static miggy.cpupoet.Core.gen_asll_dx_dy; +import static miggy.cpupoet.Core.gen_asll_ir_dy; +import static miggy.cpupoet.Core.gen_aslw_dt; +import static miggy.cpupoet.Core.gen_aslw_dx_dy; +import static miggy.cpupoet.Core.gen_aslw_ir_dy; +import static miggy.cpupoet.Core.gen_asrb_dx_dy; +import static miggy.cpupoet.Core.gen_asrb_ir_dy; +import static miggy.cpupoet.Core.gen_asrl_dx_dy; +import static miggy.cpupoet.Core.gen_asrl_ir_dy; +import static miggy.cpupoet.Core.gen_asrw_dt; +import static miggy.cpupoet.Core.gen_asrw_dx_dy; +import static miggy.cpupoet.Core.gen_asrw_ir_dy; +import static miggy.cpupoet.Core.gen_bchgb_alub_dt; +import static miggy.cpupoet.Core.gen_bchgb_dx_dt; +import static miggy.cpupoet.Core.gen_bchgl_dt_dy; +import static miggy.cpupoet.Core.gen_bchgl_dx_dy; +import static miggy.cpupoet.Core.gen_bclrb_alub_dt; +import static miggy.cpupoet.Core.gen_bclrb_dx_dt; +import static miggy.cpupoet.Core.gen_bclrl_dt_dy; +import static miggy.cpupoet.Core.gen_bclrl_dx_dy; +import static miggy.cpupoet.Core.gen_bsetb_alub_dt; +import static miggy.cpupoet.Core.gen_bsetb_dx_dt; +import static miggy.cpupoet.Core.gen_bsetl_dt_dy; +import static miggy.cpupoet.Core.gen_bsetl_dx_dy; +import static miggy.cpupoet.Core.gen_btstb_alub_dt; +import static miggy.cpupoet.Core.gen_btstb_dx_dt; +import static miggy.cpupoet.Core.gen_btstl_dt_dy; +import static miggy.cpupoet.Core.gen_btstl_dx_dy; +import static miggy.cpupoet.Core.gen_cmpb_alub_dt; +import static miggy.cpupoet.Core.gen_cmpb_dt_dx; +import static miggy.cpupoet.Core.gen_cmpb_dt_dy; +import static miggy.cpupoet.Core.gen_cmpb_dy_dx; +import static miggy.cpupoet.Core.gen_cmpl_alub_dt; +import static miggy.cpupoet.Core.gen_cmpl_ay_ax; +import static miggy.cpupoet.Core.gen_cmpl_ay_dx; +import static miggy.cpupoet.Core.gen_cmpl_dt_ax; +import static miggy.cpupoet.Core.gen_cmpl_dt_dx; +import static miggy.cpupoet.Core.gen_cmpl_dt_dy; +import static miggy.cpupoet.Core.gen_cmpl_dy_ax; +import static miggy.cpupoet.Core.gen_cmpl_dy_dx; +import static miggy.cpupoet.Core.gen_cmpmb_alub_dt; +import static miggy.cpupoet.Core.gen_cmpml_alub_dt; +import static miggy.cpupoet.Core.gen_cmpmw_alub_dt; +import static miggy.cpupoet.Core.gen_cmpw_alub_dt; +import static miggy.cpupoet.Core.gen_cmpw_ay_ax; +import static miggy.cpupoet.Core.gen_cmpw_ay_dx; +import static miggy.cpupoet.Core.gen_cmpw_dt_ax; +import static miggy.cpupoet.Core.gen_cmpw_dt_dx; +import static miggy.cpupoet.Core.gen_cmpw_dt_dy; +import static miggy.cpupoet.Core.gen_cmpw_dy_ax; +import static miggy.cpupoet.Core.gen_cmpw_dy_dx; +import static miggy.cpupoet.Core.gen_divsw_dt_dx; +import static miggy.cpupoet.Core.gen_divsw_dy_dx; +import static miggy.cpupoet.Core.gen_divuw_dt_dx; +import static miggy.cpupoet.Core.gen_divuw_dy_dx; +import static miggy.cpupoet.Core.gen_eorb_alub_dt; import static miggy.cpupoet.Core.gen_eorb_dt_ccr; -import static miggy.cpupoet.Core.gen_eorb_dt_ds; -import static miggy.cpupoet.Core.gen_eorb_im_ea; -import static miggy.cpupoet.Core.gen_eorl_dd_ds; -import static miggy.cpupoet.Core.gen_eorl_dd_ea; -import static miggy.cpupoet.Core.gen_eorl_dt_ds; -import static miggy.cpupoet.Core.gen_eorl_im_ea; -import static miggy.cpupoet.Core.gen_eorw_dd_ds; -import static miggy.cpupoet.Core.gen_eorw_dd_ea; -import static miggy.cpupoet.Core.gen_eorw_dt_ds; +import static miggy.cpupoet.Core.gen_eorb_dt_dy; +import static miggy.cpupoet.Core.gen_eorb_dx_dt; +import static miggy.cpupoet.Core.gen_eorb_dx_dy; +import static miggy.cpupoet.Core.gen_eorl_alub_dt; +import static miggy.cpupoet.Core.gen_eorl_dt_dy; +import static miggy.cpupoet.Core.gen_eorl_dx_dt; +import static miggy.cpupoet.Core.gen_eorl_dx_dy; +import static miggy.cpupoet.Core.gen_eorw_alub_dt; +import static miggy.cpupoet.Core.gen_eorw_dt_dy; import static miggy.cpupoet.Core.gen_eorw_dt_sr; -import static miggy.cpupoet.Core.gen_eorw_im_ea; -import static miggy.cpupoet.Core.gen_lslb_dd_ds; -import static miggy.cpupoet.Core.gen_lslb_ir_ds; -import static miggy.cpupoet.Core.gen_lsll_dd_ds; -import static miggy.cpupoet.Core.gen_lsll_ir_ds; -import static miggy.cpupoet.Core.gen_lslw_dd_ds; -import static miggy.cpupoet.Core.gen_lslw_ea; -import static miggy.cpupoet.Core.gen_lslw_ir_ds; -import static miggy.cpupoet.Core.gen_lsrb_dd_ds; -import static miggy.cpupoet.Core.gen_lsrb_ir_ds; -import static miggy.cpupoet.Core.gen_lsrl_dd_ds; -import static miggy.cpupoet.Core.gen_lsrl_ir_ds; -import static miggy.cpupoet.Core.gen_lsrw_dd_ds; -import static miggy.cpupoet.Core.gen_lsrw_ea; -import static miggy.cpupoet.Core.gen_lsrw_ir_ds; -import static miggy.cpupoet.Core.gen_moveb_ds_dd; -import static miggy.cpupoet.Core.gen_moveb_ds_ea; -import static miggy.cpupoet.Core.gen_moveb_dt_dd; -import static miggy.cpupoet.Core.gen_moveb_dt_ea; -import static miggy.cpupoet.Core.gen_movel_as_ad; -import static miggy.cpupoet.Core.gen_movel_as_dd; -import static miggy.cpupoet.Core.gen_movel_ds_ad; -import static miggy.cpupoet.Core.gen_movel_ds_dd; -import static miggy.cpupoet.Core.gen_movel_ds_ea; -import static miggy.cpupoet.Core.gen_movel_dt_ad; -import static miggy.cpupoet.Core.gen_movel_dt_dd; -import static miggy.cpupoet.Core.gen_movel_dt_ea; -import static miggy.cpupoet.Core.gen_movel_im_dd; -import static miggy.cpupoet.Core.gen_movew_as_ad; -import static miggy.cpupoet.Core.gen_movew_as_dd; -import static miggy.cpupoet.Core.gen_movew_ccr_ds; -import static miggy.cpupoet.Core.gen_movew_ccr_ea; -import static miggy.cpupoet.Core.gen_movew_ds_ad; -import static miggy.cpupoet.Core.gen_movew_ds_ccr; -import static miggy.cpupoet.Core.gen_movew_ds_dd; -import static miggy.cpupoet.Core.gen_movew_ds_ea; -import static miggy.cpupoet.Core.gen_movew_ds_sr; -import static miggy.cpupoet.Core.gen_movew_dt_ad; +import static miggy.cpupoet.Core.gen_eorw_dx_dt; +import static miggy.cpupoet.Core.gen_eorw_dx_dy; +import static miggy.cpupoet.Core.gen_lslb_dx_dy; +import static miggy.cpupoet.Core.gen_lslb_ir_dy; +import static miggy.cpupoet.Core.gen_lsll_dx_dy; +import static miggy.cpupoet.Core.gen_lsll_ir_dy; +import static miggy.cpupoet.Core.gen_lslw_dt; +import static miggy.cpupoet.Core.gen_lslw_dx_dy; +import static miggy.cpupoet.Core.gen_lslw_ir_dy; +import static miggy.cpupoet.Core.gen_lsrb_dx_dy; +import static miggy.cpupoet.Core.gen_lsrb_ir_dy; +import static miggy.cpupoet.Core.gen_lsrl_dx_dy; +import static miggy.cpupoet.Core.gen_lsrl_ir_dy; +import static miggy.cpupoet.Core.gen_lsrw_dt; +import static miggy.cpupoet.Core.gen_lsrw_dx_dy; +import static miggy.cpupoet.Core.gen_lsrw_ir_dy; +import static miggy.cpupoet.Core.gen_moveb_dt_dt; +import static miggy.cpupoet.Core.gen_moveb_dt_dx; +import static miggy.cpupoet.Core.gen_moveb_dy_dt; +import static miggy.cpupoet.Core.gen_moveb_dy_dx; +import static miggy.cpupoet.Core.gen_movel_ay_ax; +import static miggy.cpupoet.Core.gen_movel_ay_dx; +import static miggy.cpupoet.Core.gen_movel_dt_ax; +import static miggy.cpupoet.Core.gen_movel_dt_dt; +import static miggy.cpupoet.Core.gen_movel_dt_dx; +import static miggy.cpupoet.Core.gen_movel_dy_ax; +import static miggy.cpupoet.Core.gen_movel_dy_dt; +import static miggy.cpupoet.Core.gen_movel_dy_dx; +import static miggy.cpupoet.Core.gen_movel_ir_dx; +import static miggy.cpupoet.Core.gen_movew_ay_ax; +import static miggy.cpupoet.Core.gen_movew_ay_dx; +import static miggy.cpupoet.Core.gen_movew_ccr_dt; +import static miggy.cpupoet.Core.gen_movew_ccr_dy; +import static miggy.cpupoet.Core.gen_movew_dt_ax; import static miggy.cpupoet.Core.gen_movew_dt_ccr; -import static miggy.cpupoet.Core.gen_movew_dt_dd; -import static miggy.cpupoet.Core.gen_movew_dt_ea; +import static miggy.cpupoet.Core.gen_movew_dt_dt; +import static miggy.cpupoet.Core.gen_movew_dt_dx; import static miggy.cpupoet.Core.gen_movew_dt_sr; -import static miggy.cpupoet.Core.gen_movew_sr_ds; -import static miggy.cpupoet.Core.gen_movew_sr_ea; -import static miggy.cpupoet.Core.gen_mulsw_ds_dd; -import static miggy.cpupoet.Core.gen_mulsw_dt_dd; -import static miggy.cpupoet.Core.gen_muluw_ds_dd; -import static miggy.cpupoet.Core.gen_muluw_dt_dd; -import static miggy.cpupoet.Core.gen_nbcdb_ds; -import static miggy.cpupoet.Core.gen_nbcdb_ea; -import static miggy.cpupoet.Core.gen_negb_ds; -import static miggy.cpupoet.Core.gen_negb_ea; -import static miggy.cpupoet.Core.gen_negl_ds; -import static miggy.cpupoet.Core.gen_negl_ea; -import static miggy.cpupoet.Core.gen_negw_ds; -import static miggy.cpupoet.Core.gen_negw_ea; -import static miggy.cpupoet.Core.gen_negxb_ds; -import static miggy.cpupoet.Core.gen_negxb_ea; -import static miggy.cpupoet.Core.gen_negxl_ds; -import static miggy.cpupoet.Core.gen_negxl_ea; -import static miggy.cpupoet.Core.gen_negxw_ds; -import static miggy.cpupoet.Core.gen_negxw_ea; -import static miggy.cpupoet.Core.gen_notb_ds; -import static miggy.cpupoet.Core.gen_notb_ea; -import static miggy.cpupoet.Core.gen_notl_ds; -import static miggy.cpupoet.Core.gen_notl_ea; -import static miggy.cpupoet.Core.gen_notw_ds; -import static miggy.cpupoet.Core.gen_notw_ea; -import static miggy.cpupoet.Core.gen_orb_dd_ea; -import static miggy.cpupoet.Core.gen_orb_ds_dd; +import static miggy.cpupoet.Core.gen_movew_dy_ax; +import static miggy.cpupoet.Core.gen_movew_dy_ccr; +import static miggy.cpupoet.Core.gen_movew_dy_dt; +import static miggy.cpupoet.Core.gen_movew_dy_dx; +import static miggy.cpupoet.Core.gen_movew_dy_sr; +import static miggy.cpupoet.Core.gen_movew_sr_dt; +import static miggy.cpupoet.Core.gen_movew_sr_dy; +import static miggy.cpupoet.Core.gen_mulsw_dt_dx; +import static miggy.cpupoet.Core.gen_mulsw_dy_dx; +import static miggy.cpupoet.Core.gen_muluw_dt_dx; +import static miggy.cpupoet.Core.gen_muluw_dy_dx; +import static miggy.cpupoet.Core.gen_nbcdb_dt; +import static miggy.cpupoet.Core.gen_nbcdb_dy; +import static miggy.cpupoet.Core.gen_negb_dt; +import static miggy.cpupoet.Core.gen_negb_dy; +import static miggy.cpupoet.Core.gen_negl_dt; +import static miggy.cpupoet.Core.gen_negl_dy; +import static miggy.cpupoet.Core.gen_negw_dt; +import static miggy.cpupoet.Core.gen_negw_dy; +import static miggy.cpupoet.Core.gen_negxb_dt; +import static miggy.cpupoet.Core.gen_negxb_dy; +import static miggy.cpupoet.Core.gen_negxl_dt; +import static miggy.cpupoet.Core.gen_negxl_dy; +import static miggy.cpupoet.Core.gen_negxw_dt; +import static miggy.cpupoet.Core.gen_negxw_dy; +import static miggy.cpupoet.Core.gen_notb_dt; +import static miggy.cpupoet.Core.gen_notb_dy; +import static miggy.cpupoet.Core.gen_notl_dt; +import static miggy.cpupoet.Core.gen_notl_dy; +import static miggy.cpupoet.Core.gen_notw_dt; +import static miggy.cpupoet.Core.gen_notw_dy; +import static miggy.cpupoet.Core.gen_orb_alub_dt; import static miggy.cpupoet.Core.gen_orb_dt_ccr; -import static miggy.cpupoet.Core.gen_orb_dt_dd; -import static miggy.cpupoet.Core.gen_orb_dt_ds; -import static miggy.cpupoet.Core.gen_orb_im_ea; -import static miggy.cpupoet.Core.gen_orl_dd_ea; -import static miggy.cpupoet.Core.gen_orl_ds_dd; -import static miggy.cpupoet.Core.gen_orl_dt_dd; -import static miggy.cpupoet.Core.gen_orl_dt_ds; -import static miggy.cpupoet.Core.gen_orl_im_ea; -import static miggy.cpupoet.Core.gen_orw_dd_ea; -import static miggy.cpupoet.Core.gen_orw_ds_dd; -import static miggy.cpupoet.Core.gen_orw_dt_dd; -import static miggy.cpupoet.Core.gen_orw_dt_ds; +import static miggy.cpupoet.Core.gen_orb_dt_dx; +import static miggy.cpupoet.Core.gen_orb_dt_dy; +import static miggy.cpupoet.Core.gen_orb_dx_dt; +import static miggy.cpupoet.Core.gen_orb_dy_dx; +import static miggy.cpupoet.Core.gen_orl_alub_dt; +import static miggy.cpupoet.Core.gen_orl_dt_dx; +import static miggy.cpupoet.Core.gen_orl_dt_dy; +import static miggy.cpupoet.Core.gen_orl_dx_dt; +import static miggy.cpupoet.Core.gen_orl_dy_dx; +import static miggy.cpupoet.Core.gen_orw_alub_dt; +import static miggy.cpupoet.Core.gen_orw_dt_dx; +import static miggy.cpupoet.Core.gen_orw_dt_dy; import static miggy.cpupoet.Core.gen_orw_dt_sr; -import static miggy.cpupoet.Core.gen_orw_im_ea; -import static miggy.cpupoet.Core.gen_rolb_dd_ds; -import static miggy.cpupoet.Core.gen_rolb_ir_ds; -import static miggy.cpupoet.Core.gen_roll_dd_ds; -import static miggy.cpupoet.Core.gen_roll_ir_ds; -import static miggy.cpupoet.Core.gen_rolw_dd_ds; -import static miggy.cpupoet.Core.gen_rolw_ea; -import static miggy.cpupoet.Core.gen_rolw_ir_ds; -import static miggy.cpupoet.Core.gen_rorb_dd_ds; -import static miggy.cpupoet.Core.gen_rorb_ir_ds; -import static miggy.cpupoet.Core.gen_rorl_dd_ds; -import static miggy.cpupoet.Core.gen_rorl_ir_ds; -import static miggy.cpupoet.Core.gen_rorw_dd_ds; -import static miggy.cpupoet.Core.gen_rorw_ea; -import static miggy.cpupoet.Core.gen_rorw_ir_ds; -import static miggy.cpupoet.Core.gen_sbcdb_ds_dd; -import static miggy.cpupoet.Core.gen_sbcdb_im_ea; -import static miggy.cpupoet.Core.gen_subb_dd_ea; -import static miggy.cpupoet.Core.gen_subb_ds_dd; -import static miggy.cpupoet.Core.gen_subb_dt_dd; -import static miggy.cpupoet.Core.gen_subb_dt_ds; -import static miggy.cpupoet.Core.gen_subb_im_ea; -import static miggy.cpupoet.Core.gen_subb_ir_ds; -import static miggy.cpupoet.Core.gen_subb_ir_ea; -import static miggy.cpupoet.Core.gen_subl_as_ad; -import static miggy.cpupoet.Core.gen_subl_as_dd; -import static miggy.cpupoet.Core.gen_subl_dd_ea; -import static miggy.cpupoet.Core.gen_subl_ds_ad; -import static miggy.cpupoet.Core.gen_subl_ds_dd; -import static miggy.cpupoet.Core.gen_subl_dt_ad; -import static miggy.cpupoet.Core.gen_subl_dt_dd; -import static miggy.cpupoet.Core.gen_subl_dt_ds; -import static miggy.cpupoet.Core.gen_subl_im_ea; -import static miggy.cpupoet.Core.gen_subl_ir_as; -import static miggy.cpupoet.Core.gen_subl_ir_ds; -import static miggy.cpupoet.Core.gen_subl_ir_ea; -import static miggy.cpupoet.Core.gen_subw_as_ad; -import static miggy.cpupoet.Core.gen_subw_as_dd; -import static miggy.cpupoet.Core.gen_subw_dd_ea; -import static miggy.cpupoet.Core.gen_subw_ds_ad; -import static miggy.cpupoet.Core.gen_subw_ds_dd; -import static miggy.cpupoet.Core.gen_subw_dt_ad; -import static miggy.cpupoet.Core.gen_subw_dt_dd; -import static miggy.cpupoet.Core.gen_subw_dt_ds; -import static miggy.cpupoet.Core.gen_subw_im_ea; -import static miggy.cpupoet.Core.gen_subw_ir_as; -import static miggy.cpupoet.Core.gen_subw_ir_ds; -import static miggy.cpupoet.Core.gen_subw_ir_ea; -import static miggy.cpupoet.Core.gen_subxb_ds_dd; -import static miggy.cpupoet.Core.gen_subxb_im_ea; -import static miggy.cpupoet.Core.gen_subxl_ds_dd; -import static miggy.cpupoet.Core.gen_subxl_im_ea; -import static miggy.cpupoet.Core.gen_subxw_ds_dd; -import static miggy.cpupoet.Core.gen_subxw_im_ea; -import static miggy.cpupoet.Core.gen_tstb_ds; -import static miggy.cpupoet.Core.gen_tstb_ea; -import static miggy.cpupoet.Core.gen_tstl_ds; -import static miggy.cpupoet.Core.gen_tstl_ea; -import static miggy.cpupoet.Core.gen_tstw_ds; -import static miggy.cpupoet.Core.gen_tstw_ea; +import static miggy.cpupoet.Core.gen_orw_dx_dt; +import static miggy.cpupoet.Core.gen_orw_dy_dx; +import static miggy.cpupoet.Core.gen_rolb_dx_dy; +import static miggy.cpupoet.Core.gen_rolb_ir_dy; +import static miggy.cpupoet.Core.gen_roll_dx_dy; +import static miggy.cpupoet.Core.gen_roll_ir_dy; +import static miggy.cpupoet.Core.gen_rolw_dt; +import static miggy.cpupoet.Core.gen_rolw_dx_dy; +import static miggy.cpupoet.Core.gen_rolw_ir_dy; +import static miggy.cpupoet.Core.gen_rorb_dx_dy; +import static miggy.cpupoet.Core.gen_rorb_ir_dy; +import static miggy.cpupoet.Core.gen_rorl_dx_dy; +import static miggy.cpupoet.Core.gen_rorl_ir_dy; +import static miggy.cpupoet.Core.gen_rorw_dt; +import static miggy.cpupoet.Core.gen_rorw_dx_dy; +import static miggy.cpupoet.Core.gen_rorw_ir_dy; +import static miggy.cpupoet.Core.gen_sbcdb_alub_dt; +import static miggy.cpupoet.Core.gen_sbcdb_dy_dx; +import static miggy.cpupoet.Core.gen_subb_alub_dt; +import static miggy.cpupoet.Core.gen_subb_dt_dx; +import static miggy.cpupoet.Core.gen_subb_dt_dy; +import static miggy.cpupoet.Core.gen_subb_dx_dt; +import static miggy.cpupoet.Core.gen_subb_dy_dx; +import static miggy.cpupoet.Core.gen_subb_ir_dt; +import static miggy.cpupoet.Core.gen_subb_ir_dy; +import static miggy.cpupoet.Core.gen_subl_alub_dt; +import static miggy.cpupoet.Core.gen_subl_ay_ax; +import static miggy.cpupoet.Core.gen_subl_ay_dx; +import static miggy.cpupoet.Core.gen_subl_dt_ax; +import static miggy.cpupoet.Core.gen_subl_dt_dx; +import static miggy.cpupoet.Core.gen_subl_dt_dy; +import static miggy.cpupoet.Core.gen_subl_dx_dt; +import static miggy.cpupoet.Core.gen_subl_dy_ax; +import static miggy.cpupoet.Core.gen_subl_dy_dx; +import static miggy.cpupoet.Core.gen_subl_ir_ay; +import static miggy.cpupoet.Core.gen_subl_ir_dt; +import static miggy.cpupoet.Core.gen_subl_ir_dy; +import static miggy.cpupoet.Core.gen_subw_alub_dt; +import static miggy.cpupoet.Core.gen_subw_ay_ax; +import static miggy.cpupoet.Core.gen_subw_ay_dx; +import static miggy.cpupoet.Core.gen_subw_dt_ax; +import static miggy.cpupoet.Core.gen_subw_dt_dx; +import static miggy.cpupoet.Core.gen_subw_dt_dy; +import static miggy.cpupoet.Core.gen_subw_dx_dt; +import static miggy.cpupoet.Core.gen_subw_dy_ax; +import static miggy.cpupoet.Core.gen_subw_dy_dx; +import static miggy.cpupoet.Core.gen_subw_ir_ay; +import static miggy.cpupoet.Core.gen_subw_ir_dt; +import static miggy.cpupoet.Core.gen_subw_ir_dy; +import static miggy.cpupoet.Core.gen_subxb_alub_dt; +import static miggy.cpupoet.Core.gen_subxb_dy_dx; +import static miggy.cpupoet.Core.gen_subxl_alub_dt; +import static miggy.cpupoet.Core.gen_subxl_dy_dx; +import static miggy.cpupoet.Core.gen_subxw_alub_dt; +import static miggy.cpupoet.Core.gen_subxw_dy_dx; +import static miggy.cpupoet.Core.gen_tstb_dt; +import static miggy.cpupoet.Core.gen_tstb_dy; +import static miggy.cpupoet.Core.gen_tstl_dt; +import static miggy.cpupoet.Core.gen_tstl_dy; +import static miggy.cpupoet.Core.gen_tstw_dt; +import static miggy.cpupoet.Core.gen_tstw_dy; import static miggy.cpupoet.Core.op_bcc16; import static miggy.cpupoet.Core.op_bcc32; import static miggy.cpupoet.Core.op_bcc8; @@ -423,1123 +423,1123 @@ import static miggy.cpupoet.Core.op_trapv; import static miggy.cpupoet.Core.op_unlk_as; public enum MacroPLA { - ori_b_imm8_ds(0x0000, 0xfff8, op_imm16, gen_orb_dt_ds, dbrr), + ori_b_imm8_ds(0x0000, 0xfff8, op_imm16, gen_orb_dt_dy, dbrr), - ori_b_imm8_ais(0x0010, 0xfff8, op_imm16, ea_ais8_read, gen_orb_im_ea), + ori_b_imm8_ais(0x0010, 0xfff8, op_imm16, ea_ais8_read, gen_orb_alub_dt), - ori_b_imm8_aips(0x0018, 0xfff8, op_imm16, ea_aips8_read, gen_orb_im_ea), + ori_b_imm8_aips(0x0018, 0xfff8, op_imm16, ea_aips8_read, gen_orb_alub_dt), - ori_b_imm8_pais(0x0020, 0xfff8, op_imm16, ea_pais8_read, gen_orb_im_ea), + ori_b_imm8_pais(0x0020, 0xfff8, op_imm16, ea_pais8_read, gen_orb_alub_dt), - ori_b_imm8_das(0x0028, 0xfff8, op_imm16, ea_das8_read, gen_orb_im_ea), + ori_b_imm8_das(0x0028, 0xfff8, op_imm16, ea_das8_read, gen_orb_alub_dt), - ori_b_imm8_dais(0x0030, 0xfff8, op_imm16, ea_dais8_read, gen_orb_im_ea), + ori_b_imm8_dais(0x0030, 0xfff8, op_imm16, ea_dais8_read, gen_orb_alub_dt), - ori_b_imm8_adr16(0x0038, 0xffff, op_imm16, ea_adr16s8_read, gen_orb_im_ea), + ori_b_imm8_adr16(0x0038, 0xffff, op_imm16, ea_adr16s8_read, gen_orb_alub_dt), - ori_b_imm8_adr32(0x0039, 0xffff, op_imm16, ea_adr32s8_read, gen_orb_im_ea), + ori_b_imm8_adr32(0x0039, 0xffff, op_imm16, ea_adr32s8_read, gen_orb_alub_dt), ori_imm8_ccr(0x003c, 0xffff, op_imm16, gen_orb_dt_ccr, dbrr), - ori_w_imm16_ds(0x0040, 0xfff8, op_imm16, gen_orw_dt_ds, dbrr), + ori_w_imm16_ds(0x0040, 0xfff8, op_imm16, gen_orw_dt_dy, dbrr), - ori_w_imm16_ais(0x0050, 0xfff8, op_imm16, ea_ais16_read, gen_orw_im_ea), + ori_w_imm16_ais(0x0050, 0xfff8, op_imm16, ea_ais16_read, gen_orw_alub_dt), - ori_w_imm16_aips(0x0058, 0xfff8, op_imm16, ea_aips16_read, gen_orw_im_ea), + ori_w_imm16_aips(0x0058, 0xfff8, op_imm16, ea_aips16_read, gen_orw_alub_dt), - ori_w_imm16_pais(0x0060, 0xfff8, op_imm16, ea_pais16_read, gen_orw_im_ea), + ori_w_imm16_pais(0x0060, 0xfff8, op_imm16, ea_pais16_read, gen_orw_alub_dt), - ori_w_imm16_das(0x0068, 0xfff8, op_imm16, ea_das16_read, gen_orw_im_ea), + ori_w_imm16_das(0x0068, 0xfff8, op_imm16, ea_das16_read, gen_orw_alub_dt), - ori_w_imm16_dais(0x0070, 0xfff8, op_imm16, ea_dais16_read, gen_orw_im_ea), + ori_w_imm16_dais(0x0070, 0xfff8, op_imm16, ea_dais16_read, gen_orw_alub_dt), - ori_w_imm16_adr16(0x0078, 0xffff, op_imm16, ea_adr16s16_read, gen_orw_im_ea), + ori_w_imm16_adr16(0x0078, 0xffff, op_imm16, ea_adr16s16_read, gen_orw_alub_dt), - ori_w_imm16_adr32(0x0079, 0xffff, op_imm16, ea_adr32s16_read, gen_orw_im_ea), + ori_w_imm16_adr32(0x0079, 0xffff, op_imm16, ea_adr32s16_read, gen_orw_alub_dt), ori_i16u_sr(0x007c, 0xffff, op_imm16, gen_orw_dt_sr, dbrr), - ori_l_imm32_ds(0x0080, 0xfff8, op_imm32, gen_orl_dt_ds, dbrr), + ori_l_imm32_ds(0x0080, 0xfff8, op_imm32, gen_orl_dt_dy, dbrr), - ori_l_imm32_ais(0x0090, 0xfff8, op_imm32, ea_ais32_read, gen_orl_im_ea), + ori_l_imm32_ais(0x0090, 0xfff8, op_imm32, ea_ais32_read, gen_orl_alub_dt), - ori_l_imm32_aips(0x0098, 0xfff8, op_imm32, ea_aips32_read, gen_orl_im_ea), + ori_l_imm32_aips(0x0098, 0xfff8, op_imm32, ea_aips32_read, gen_orl_alub_dt), - ori_l_imm32_pais(0x00a0, 0xfff8, op_imm32, ea_pais32_read, gen_orl_im_ea), + ori_l_imm32_pais(0x00a0, 0xfff8, op_imm32, ea_pais32_read, gen_orl_alub_dt), - ori_l_imm32_das(0x00a8, 0xfff8, op_imm32, ea_das32_read, gen_orl_im_ea), + ori_l_imm32_das(0x00a8, 0xfff8, op_imm32, ea_das32_read, gen_orl_alub_dt), - ori_l_imm32_dais(0x00b0, 0xfff8, op_imm32, ea_dais32_read, gen_orl_im_ea), + ori_l_imm32_dais(0x00b0, 0xfff8, op_imm32, ea_dais32_read, gen_orl_alub_dt), - ori_l_imm32_adr16(0x00b8, 0xffff, op_imm32, ea_adr16s32_read, gen_orl_im_ea), + ori_l_imm32_adr16(0x00b8, 0xffff, op_imm32, ea_adr16s32_read, gen_orl_alub_dt), - ori_l_imm32_adr32(0x00b9, 0xffff, op_imm32, ea_adr32s32_read, gen_orl_im_ea), + ori_l_imm32_adr32(0x00b9, 0xffff, op_imm32, ea_adr32s32_read, gen_orl_alub_dt), - btst_dd_ds(0x0100, 0xf1f8, gen_btstl_dd_ds, dbrr, dbrr), + btst_dd_ds(0x0100, 0xf1f8, gen_btstl_dx_dy, dbrr, dbrr), movep_w_das_dd(0x0108, 0xf1f8, ea_das16, dbrr, op_movepw_das_dd), - btst_dd_ais(0x0110, 0xf1f8, ea_ais8_read, dbrr, gen_btstb_dd_ea), + btst_dd_ais(0x0110, 0xf1f8, ea_ais8_read, dbrr, gen_btstb_dx_dt), - btst_dd_aips(0x0118, 0xf1f8, ea_aips8_read, dbrr, gen_btstb_dd_ea), + btst_dd_aips(0x0118, 0xf1f8, ea_aips8_read, dbrr, gen_btstb_dx_dt), - btst_dd_pais(0x0120, 0xf1f8, ea_pais8_read, dbrr, gen_btstb_dd_ea), + btst_dd_pais(0x0120, 0xf1f8, ea_pais8_read, dbrr, gen_btstb_dx_dt), - btst_dd_das(0x0128, 0xf1f8, ea_das8_read, dbrr, gen_btstb_dd_ea), + btst_dd_das(0x0128, 0xf1f8, ea_das8_read, dbrr, gen_btstb_dx_dt), - btst_dd_dais(0x0130, 0xf1f8, ea_dais8_read, dbrr, gen_btstb_dd_ea), + btst_dd_dais(0x0130, 0xf1f8, ea_dais8_read, dbrr, gen_btstb_dx_dt), - btst_dd_adr16(0x0138, 0xf1ff, ea_adr16s8_read, dbrr, gen_btstb_dd_ea), + btst_dd_adr16(0x0138, 0xf1ff, ea_adr16s8_read, dbrr, gen_btstb_dx_dt), - btst_dd_adr32(0x0139, 0xf1ff, ea_adr32s8_read, dbrr, gen_btstb_dd_ea), + btst_dd_adr32(0x0139, 0xf1ff, ea_adr32s8_read, dbrr, gen_btstb_dx_dt), - btst_dd_dpc(0x013a, 0xf1ff, ea_dpc8_read, dbrr, gen_btstb_dd_ea), + btst_dd_dpc(0x013a, 0xf1ff, ea_dpc8_read, dbrr, gen_btstb_dx_dt), - btst_dd_dpci(0x013b, 0xf1ff, ea_dpci8_read, dbrr, gen_btstb_dd_ea), + btst_dd_dpci(0x013b, 0xf1ff, ea_dpci8_read, dbrr, gen_btstb_dx_dt), - btst_dd_imm8(0x013c, 0xf1ff, ea_imm8_read, dbrr, gen_btstb_dd_ea), + btst_dd_imm8(0x013c, 0xf1ff, ea_imm8_read, dbrr, gen_btstb_dx_dt), - bchg_dd_ds(0x0140, 0xf1f8, gen_bchgl_dd_ds, dbrr, dbrr), + bchg_dd_ds(0x0140, 0xf1f8, gen_bchgl_dx_dy, dbrr, dbrr), movep_l_das_dd(0x0148, 0xf1f8, ea_das32, dbrr, op_movepl_das_dd), - bchg_dd_ais(0x0150, 0xf1f8, ea_ais8_read, dbrr, gen_bchgb_dd_ea), + bchg_dd_ais(0x0150, 0xf1f8, ea_ais8_read, dbrr, gen_bchgb_dx_dt), - bchg_dd_aips(0x0158, 0xf1f8, ea_aips8_read, dbrr, gen_bchgb_dd_ea), + bchg_dd_aips(0x0158, 0xf1f8, ea_aips8_read, dbrr, gen_bchgb_dx_dt), - bchg_dd_pais(0x0160, 0xf1f8, ea_pais8_read, dbrr, gen_bchgb_dd_ea), + bchg_dd_pais(0x0160, 0xf1f8, ea_pais8_read, dbrr, gen_bchgb_dx_dt), - bchg_dd_das(0x0168, 0xf1f8, ea_das8_read, dbrr, gen_bchgb_dd_ea), + bchg_dd_das(0x0168, 0xf1f8, ea_das8_read, dbrr, gen_bchgb_dx_dt), - bchg_dd_dais(0x0170, 0xf1f8, ea_dais8_read, dbrr, gen_bchgb_dd_ea), + bchg_dd_dais(0x0170, 0xf1f8, ea_dais8_read, dbrr, gen_bchgb_dx_dt), - bchg_dd_adr16(0x0178, 0xf1ff, ea_adr16s8_read, dbrr, gen_bchgb_dd_ea), + bchg_dd_adr16(0x0178, 0xf1ff, ea_adr16s8_read, dbrr, gen_bchgb_dx_dt), - bchg_dd_adr32(0x0179, 0xf1ff, ea_adr32s8_read, dbrr, gen_bchgb_dd_ea), + bchg_dd_adr32(0x0179, 0xf1ff, ea_adr32s8_read, dbrr, gen_bchgb_dx_dt), - bclr_dd_ds(0x0180, 0xf1f8, gen_bclrl_dd_ds, dbrr, dbrr), + bclr_dd_ds(0x0180, 0xf1f8, gen_bclrl_dx_dy, dbrr, dbrr), movep_w_dd_das(0x0188, 0xf1f8, ea_das16, dbrr, op_movepw_dd_das), - bclr_dd_ais(0x0190, 0xf1f8, ea_ais8_read, dbrr, gen_bclrb_dd_ea), + bclr_dd_ais(0x0190, 0xf1f8, ea_ais8_read, dbrr, gen_bclrb_dx_dt), - bclr_dd_aips(0x0198, 0xf1f8, ea_aips8_read, dbrr, gen_bclrb_dd_ea), + bclr_dd_aips(0x0198, 0xf1f8, ea_aips8_read, dbrr, gen_bclrb_dx_dt), - bclr_dd_pais(0x01a0, 0xf1f8, ea_pais8_read, dbrr, gen_bclrb_dd_ea), + bclr_dd_pais(0x01a0, 0xf1f8, ea_pais8_read, dbrr, gen_bclrb_dx_dt), - bclr_dd_das(0x01a8, 0xf1f8, ea_das8_read, dbrr, gen_bclrb_dd_ea), + bclr_dd_das(0x01a8, 0xf1f8, ea_das8_read, dbrr, gen_bclrb_dx_dt), - bclr_dd_dais(0x01b0, 0xf1f8, ea_dais8_read, dbrr, gen_bclrb_dd_ea), + bclr_dd_dais(0x01b0, 0xf1f8, ea_dais8_read, dbrr, gen_bclrb_dx_dt), - bclr_dd_adr16(0x01b8, 0xf1ff, ea_adr16s8_read, dbrr, gen_bclrb_dd_ea), + bclr_dd_adr16(0x01b8, 0xf1ff, ea_adr16s8_read, dbrr, gen_bclrb_dx_dt), - bclr_dd_adr32(0x01b9, 0xf1ff, ea_adr32s8_read, dbrr, gen_bclrb_dd_ea), + bclr_dd_adr32(0x01b9, 0xf1ff, ea_adr32s8_read, dbrr, gen_bclrb_dx_dt), - bset_dd_ds(0x01c0, 0xf1f8, gen_bsetl_dd_ds, dbrr, dbrr), + bset_dd_ds(0x01c0, 0xf1f8, gen_bsetl_dx_dy, dbrr, dbrr), movep_l_dd_das(0x01c8, 0xf1f8, ea_das32, dbrr, op_movepl_dd_das), - bset_dd_ais(0x01d0, 0xf1f8, ea_ais8_read, dbrr, gen_bsetb_dd_ea), + bset_dd_ais(0x01d0, 0xf1f8, ea_ais8_read, dbrr, gen_bsetb_dx_dt), - bset_dd_aips(0x01d8, 0xf1f8, ea_aips8_read, dbrr, gen_bsetb_dd_ea), + bset_dd_aips(0x01d8, 0xf1f8, ea_aips8_read, dbrr, gen_bsetb_dx_dt), - bset_dd_pais(0x01e0, 0xf1f8, ea_pais8_read, dbrr, gen_bsetb_dd_ea), + bset_dd_pais(0x01e0, 0xf1f8, ea_pais8_read, dbrr, gen_bsetb_dx_dt), - bset_dd_das(0x01e8, 0xf1f8, ea_das8_read, dbrr, gen_bsetb_dd_ea), + bset_dd_das(0x01e8, 0xf1f8, ea_das8_read, dbrr, gen_bsetb_dx_dt), - bset_dd_dais(0x01f0, 0xf1f8, ea_dais8_read, dbrr, gen_bsetb_dd_ea), + bset_dd_dais(0x01f0, 0xf1f8, ea_dais8_read, dbrr, gen_bsetb_dx_dt), - bset_dd_adr16(0x01f8, 0xf1ff, ea_adr16s8_read, dbrr, gen_bsetb_dd_ea), + bset_dd_adr16(0x01f8, 0xf1ff, ea_adr16s8_read, dbrr, gen_bsetb_dx_dt), - bset_dd_adr32(0x01f9, 0xf1ff, ea_adr32s8_read, dbrr, gen_bsetb_dd_ea), + bset_dd_adr32(0x01f9, 0xf1ff, ea_adr32s8_read, dbrr, gen_bsetb_dx_dt), - andi_b_imm8_ds(0x0200, 0xfff8, op_imm16, gen_andb_dt_ds, dbrr), + andi_b_imm8_ds(0x0200, 0xfff8, op_imm16, gen_andb_dt_dy, dbrr), - andi_b_imm8_ais(0x0210, 0xfff8, op_imm16, ea_ais8_read, gen_andb_im_ea), + andi_b_imm8_ais(0x0210, 0xfff8, op_imm16, ea_ais8_read, gen_andb_alub_dt), - andi_b_imm8_aips(0x0218, 0xfff8, op_imm16, ea_aips8_read, gen_andb_im_ea), + andi_b_imm8_aips(0x0218, 0xfff8, op_imm16, ea_aips8_read, gen_andb_alub_dt), - andi_b_imm8_pais(0x0220, 0xfff8, op_imm16, ea_pais8_read, gen_andb_im_ea), + andi_b_imm8_pais(0x0220, 0xfff8, op_imm16, ea_pais8_read, gen_andb_alub_dt), - andi_b_imm8_das(0x0228, 0xfff8, op_imm16, ea_das8_read, gen_andb_im_ea), + andi_b_imm8_das(0x0228, 0xfff8, op_imm16, ea_das8_read, gen_andb_alub_dt), - andi_b_imm8_dais(0x0230, 0xfff8, op_imm16, ea_dais8_read, gen_andb_im_ea), + andi_b_imm8_dais(0x0230, 0xfff8, op_imm16, ea_dais8_read, gen_andb_alub_dt), - andi_b_imm8_adr16(0x0238, 0xffff, op_imm16, ea_adr16s8_read, gen_andb_im_ea), + andi_b_imm8_adr16(0x0238, 0xffff, op_imm16, ea_adr16s8_read, gen_andb_alub_dt), - andi_b_imm8_adr32(0x0239, 0xffff, op_imm16, ea_adr32s8_read, gen_andb_im_ea), + andi_b_imm8_adr32(0x0239, 0xffff, op_imm16, ea_adr32s8_read, gen_andb_alub_dt), andi_imm8_ccr(0x023c, 0xffff, op_imm16, gen_andb_dt_ccr, dbrr), - andi_w_imm16_ds(0x0240, 0xfff8, op_imm16, gen_andw_dt_ds, dbrr), + andi_w_imm16_ds(0x0240, 0xfff8, op_imm16, gen_andw_dt_dy, dbrr), - andi_w_imm16_ais(0x0250, 0xfff8, op_imm16, ea_ais16_read, gen_andw_im_ea), + andi_w_imm16_ais(0x0250, 0xfff8, op_imm16, ea_ais16_read, gen_andw_alub_dt), - andi_w_imm16_aips(0x0258, 0xfff8, op_imm16, ea_aips16_read, gen_andw_im_ea), + andi_w_imm16_aips(0x0258, 0xfff8, op_imm16, ea_aips16_read, gen_andw_alub_dt), - andi_w_imm16_pais(0x0260, 0xfff8, op_imm16, ea_pais16_read, gen_andw_im_ea), + andi_w_imm16_pais(0x0260, 0xfff8, op_imm16, ea_pais16_read, gen_andw_alub_dt), - andi_w_imm16_das(0x0268, 0xfff8, op_imm16, ea_das16_read, gen_andw_im_ea), + andi_w_imm16_das(0x0268, 0xfff8, op_imm16, ea_das16_read, gen_andw_alub_dt), - andi_w_imm16_dais(0x0270, 0xfff8, op_imm16, ea_dais16_read, gen_andw_im_ea), + andi_w_imm16_dais(0x0270, 0xfff8, op_imm16, ea_dais16_read, gen_andw_alub_dt), - andi_w_imm16_adr16(0x0278, 0xffff, op_imm16, ea_adr16s16_read, gen_andw_im_ea), + andi_w_imm16_adr16(0x0278, 0xffff, op_imm16, ea_adr16s16_read, gen_andw_alub_dt), - andi_w_imm16_adr32(0x0279, 0xffff, op_imm16, ea_adr32s16_read, gen_andw_im_ea), + andi_w_imm16_adr32(0x0279, 0xffff, op_imm16, ea_adr32s16_read, gen_andw_alub_dt), andi_i16u_sr(0x027c, 0xffff, op_imm16, gen_andw_dt_sr, dbrr), - andi_l_imm32_ds(0x0280, 0xfff8, op_imm32, gen_andl_dt_ds, dbrr), + andi_l_imm32_ds(0x0280, 0xfff8, op_imm32, gen_andl_dt_dy, dbrr), - andi_l_imm32_ais(0x0290, 0xfff8, op_imm32, ea_ais32_read, gen_andl_im_ea), + andi_l_imm32_ais(0x0290, 0xfff8, op_imm32, ea_ais32_read, gen_andl_alub_dt), - andi_l_imm32_aips(0x0298, 0xfff8, op_imm32, ea_aips32_read, gen_andl_im_ea), + andi_l_imm32_aips(0x0298, 0xfff8, op_imm32, ea_aips32_read, gen_andl_alub_dt), - andi_l_imm32_pais(0x02a0, 0xfff8, op_imm32, ea_pais32_read, gen_andl_im_ea), + andi_l_imm32_pais(0x02a0, 0xfff8, op_imm32, ea_pais32_read, gen_andl_alub_dt), - andi_l_imm32_das(0x02a8, 0xfff8, op_imm32, ea_das32_read, gen_andl_im_ea), + andi_l_imm32_das(0x02a8, 0xfff8, op_imm32, ea_das32_read, gen_andl_alub_dt), - andi_l_imm32_dais(0x02b0, 0xfff8, op_imm32, ea_dais32_read, gen_andl_im_ea), + andi_l_imm32_dais(0x02b0, 0xfff8, op_imm32, ea_dais32_read, gen_andl_alub_dt), - andi_l_imm32_adr16(0x02b8, 0xffff, op_imm32, ea_adr16s32_read, gen_andl_im_ea), + andi_l_imm32_adr16(0x02b8, 0xffff, op_imm32, ea_adr16s32_read, gen_andl_alub_dt), - andi_l_imm32_adr32(0x02b9, 0xffff, op_imm32, ea_adr32s32_read, gen_andl_im_ea), + andi_l_imm32_adr32(0x02b9, 0xffff, op_imm32, ea_adr32s32_read, gen_andl_alub_dt), - subi_b_imm8_ds(0x0400, 0xfff8, op_imm16, gen_subb_dt_ds, dbrr), + subi_b_imm8_ds(0x0400, 0xfff8, op_imm16, gen_subb_dt_dy, dbrr), - subi_b_imm8_ais(0x0410, 0xfff8, op_imm16, ea_ais8_read, gen_subb_im_ea), + subi_b_imm8_ais(0x0410, 0xfff8, op_imm16, ea_ais8_read, gen_subb_alub_dt), - subi_b_imm8_aips(0x0418, 0xfff8, op_imm16, ea_aips8_read, gen_subb_im_ea), + subi_b_imm8_aips(0x0418, 0xfff8, op_imm16, ea_aips8_read, gen_subb_alub_dt), - subi_b_imm8_pais(0x0420, 0xfff8, op_imm16, ea_pais8_read, gen_subb_im_ea), + subi_b_imm8_pais(0x0420, 0xfff8, op_imm16, ea_pais8_read, gen_subb_alub_dt), - subi_b_imm8_das(0x0428, 0xfff8, op_imm16, ea_das8_read, gen_subb_im_ea), + subi_b_imm8_das(0x0428, 0xfff8, op_imm16, ea_das8_read, gen_subb_alub_dt), - subi_b_imm8_dais(0x0430, 0xfff8, op_imm16, ea_dais8_read, gen_subb_im_ea), + subi_b_imm8_dais(0x0430, 0xfff8, op_imm16, ea_dais8_read, gen_subb_alub_dt), - subi_b_imm8_adr16(0x0438, 0xffff, op_imm16, ea_adr16s8_read, gen_subb_im_ea), + subi_b_imm8_adr16(0x0438, 0xffff, op_imm16, ea_adr16s8_read, gen_subb_alub_dt), - subi_b_imm8_adr32(0x0439, 0xffff, op_imm16, ea_adr32s8_read, gen_subb_im_ea), + subi_b_imm8_adr32(0x0439, 0xffff, op_imm16, ea_adr32s8_read, gen_subb_alub_dt), - subi_w_imm16_ds(0x0440, 0xfff8, op_imm16, gen_subw_dt_ds, dbrr), + subi_w_imm16_ds(0x0440, 0xfff8, op_imm16, gen_subw_dt_dy, dbrr), - subi_w_imm16_ais(0x0450, 0xfff8, op_imm16, ea_ais16_read, gen_subw_im_ea), + subi_w_imm16_ais(0x0450, 0xfff8, op_imm16, ea_ais16_read, gen_subw_alub_dt), - subi_w_imm16_aips(0x0458, 0xfff8, op_imm16, ea_aips16_read, gen_subw_im_ea), + subi_w_imm16_aips(0x0458, 0xfff8, op_imm16, ea_aips16_read, gen_subw_alub_dt), - subi_w_imm16_pais(0x0460, 0xfff8, op_imm16, ea_pais16_read, gen_subw_im_ea), + subi_w_imm16_pais(0x0460, 0xfff8, op_imm16, ea_pais16_read, gen_subw_alub_dt), - subi_w_imm16_das(0x0468, 0xfff8, op_imm16, ea_das16_read, gen_subw_im_ea), + subi_w_imm16_das(0x0468, 0xfff8, op_imm16, ea_das16_read, gen_subw_alub_dt), - subi_w_imm16_dais(0x0470, 0xfff8, op_imm16, ea_dais16_read, gen_subw_im_ea), + subi_w_imm16_dais(0x0470, 0xfff8, op_imm16, ea_dais16_read, gen_subw_alub_dt), - subi_w_imm16_adr16(0x0478, 0xffff, op_imm16, ea_adr16s16_read, gen_subw_im_ea), + subi_w_imm16_adr16(0x0478, 0xffff, op_imm16, ea_adr16s16_read, gen_subw_alub_dt), - subi_w_imm16_adr32(0x0479, 0xffff, op_imm16, ea_adr32s16_read, gen_subw_im_ea), + subi_w_imm16_adr32(0x0479, 0xffff, op_imm16, ea_adr32s16_read, gen_subw_alub_dt), - subi_l_imm32_ds(0x0480, 0xfff8, op_imm32, gen_subl_dt_ds, dbrr), + subi_l_imm32_ds(0x0480, 0xfff8, op_imm32, gen_subl_dt_dy, dbrr), - subi_l_imm32_ais(0x0490, 0xfff8, op_imm32, ea_ais32_read, gen_subl_im_ea), + subi_l_imm32_ais(0x0490, 0xfff8, op_imm32, ea_ais32_read, gen_subl_alub_dt), - subi_l_imm32_aips(0x0498, 0xfff8, op_imm32, ea_aips32_read, gen_subl_im_ea), + subi_l_imm32_aips(0x0498, 0xfff8, op_imm32, ea_aips32_read, gen_subl_alub_dt), - subi_l_imm32_pais(0x04a0, 0xfff8, op_imm32, ea_pais32_read, gen_subl_im_ea), + subi_l_imm32_pais(0x04a0, 0xfff8, op_imm32, ea_pais32_read, gen_subl_alub_dt), - subi_l_imm32_das(0x04a8, 0xfff8, op_imm32, ea_das32_read, gen_subl_im_ea), + subi_l_imm32_das(0x04a8, 0xfff8, op_imm32, ea_das32_read, gen_subl_alub_dt), - subi_l_imm32_dais(0x04b0, 0xfff8, op_imm32, ea_dais32_read, gen_subl_im_ea), + subi_l_imm32_dais(0x04b0, 0xfff8, op_imm32, ea_dais32_read, gen_subl_alub_dt), - subi_l_imm32_adr16(0x04b8, 0xffff, op_imm32, ea_adr16s32_read, gen_subl_im_ea), + subi_l_imm32_adr16(0x04b8, 0xffff, op_imm32, ea_adr16s32_read, gen_subl_alub_dt), - subi_l_imm32_adr32(0x04b9, 0xffff, op_imm32, ea_adr32s32_read, gen_subl_im_ea), + subi_l_imm32_adr32(0x04b9, 0xffff, op_imm32, ea_adr32s32_read, gen_subl_alub_dt), - addi_b_imm8_ds(0x0600, 0xfff8, op_imm16, gen_addb_dt_ds, dbrr), + addi_b_imm8_ds(0x0600, 0xfff8, op_imm16, gen_addb_dt_dy, dbrr), - addi_b_imm8_ais(0x0610, 0xfff8, op_imm16, ea_ais8_read, gen_addb_im_ea), + addi_b_imm8_ais(0x0610, 0xfff8, op_imm16, ea_ais8_read, gen_addb_alub_dt), - addi_b_imm8_aips(0x0618, 0xfff8, op_imm16, ea_aips8_read, gen_addb_im_ea), + addi_b_imm8_aips(0x0618, 0xfff8, op_imm16, ea_aips8_read, gen_addb_alub_dt), - addi_b_imm8_pais(0x0620, 0xfff8, op_imm16, ea_pais8_read, gen_addb_im_ea), + addi_b_imm8_pais(0x0620, 0xfff8, op_imm16, ea_pais8_read, gen_addb_alub_dt), - addi_b_imm8_das(0x0628, 0xfff8, op_imm16, ea_das8_read, gen_addb_im_ea), + addi_b_imm8_das(0x0628, 0xfff8, op_imm16, ea_das8_read, gen_addb_alub_dt), - addi_b_imm8_dais(0x0630, 0xfff8, op_imm16, ea_dais8_read, gen_addb_im_ea), + addi_b_imm8_dais(0x0630, 0xfff8, op_imm16, ea_dais8_read, gen_addb_alub_dt), - addi_b_imm8_adr16(0x0638, 0xffff, op_imm16, ea_adr16s8_read, gen_addb_im_ea), + addi_b_imm8_adr16(0x0638, 0xffff, op_imm16, ea_adr16s8_read, gen_addb_alub_dt), - addi_b_imm8_adr32(0x0639, 0xffff, op_imm16, ea_adr32s8_read, gen_addb_im_ea), + addi_b_imm8_adr32(0x0639, 0xffff, op_imm16, ea_adr32s8_read, gen_addb_alub_dt), - addi_w_imm16_ds(0x0640, 0xfff8, op_imm16, gen_addw_dt_ds, dbrr), + addi_w_imm16_ds(0x0640, 0xfff8, op_imm16, gen_addw_dt_dy, dbrr), - addi_w_imm16_ais(0x0650, 0xfff8, op_imm16, ea_ais16_read, gen_addw_im_ea), + addi_w_imm16_ais(0x0650, 0xfff8, op_imm16, ea_ais16_read, gen_addw_alub_dt), - addi_w_imm16_aips(0x0658, 0xfff8, op_imm16, ea_aips16_read, gen_addw_im_ea), + addi_w_imm16_aips(0x0658, 0xfff8, op_imm16, ea_aips16_read, gen_addw_alub_dt), - addi_w_imm16_pais(0x0660, 0xfff8, op_imm16, ea_pais16_read, gen_addw_im_ea), + addi_w_imm16_pais(0x0660, 0xfff8, op_imm16, ea_pais16_read, gen_addw_alub_dt), - addi_w_imm16_das(0x0668, 0xfff8, op_imm16, ea_das16_read, gen_addw_im_ea), + addi_w_imm16_das(0x0668, 0xfff8, op_imm16, ea_das16_read, gen_addw_alub_dt), - addi_w_imm16_dais(0x0670, 0xfff8, op_imm16, ea_dais16_read, gen_addw_im_ea), + addi_w_imm16_dais(0x0670, 0xfff8, op_imm16, ea_dais16_read, gen_addw_alub_dt), - addi_w_imm16_adr16(0x0678, 0xffff, op_imm16, ea_adr16s16_read, gen_addw_im_ea), + addi_w_imm16_adr16(0x0678, 0xffff, op_imm16, ea_adr16s16_read, gen_addw_alub_dt), - addi_w_imm16_adr32(0x0679, 0xffff, op_imm16, ea_adr32s16_read, gen_addw_im_ea), + addi_w_imm16_adr32(0x0679, 0xffff, op_imm16, ea_adr32s16_read, gen_addw_alub_dt), - addi_l_imm32_ds(0x0680, 0xfff8, op_imm32, gen_addl_dt_ds, dbrr), + addi_l_imm32_ds(0x0680, 0xfff8, op_imm32, gen_addl_dt_dy, dbrr), - addi_l_imm32_ais(0x0690, 0xfff8, op_imm32, ea_ais32_read, gen_addl_im_ea), + addi_l_imm32_ais(0x0690, 0xfff8, op_imm32, ea_ais32_read, gen_addl_alub_dt), - addi_l_imm32_aips(0x0698, 0xfff8, op_imm32, ea_aips32_read, gen_addl_im_ea), + addi_l_imm32_aips(0x0698, 0xfff8, op_imm32, ea_aips32_read, gen_addl_alub_dt), - addi_l_imm32_pais(0x06a0, 0xfff8, op_imm32, ea_pais32_read, gen_addl_im_ea), + addi_l_imm32_pais(0x06a0, 0xfff8, op_imm32, ea_pais32_read, gen_addl_alub_dt), - addi_l_imm32_das(0x06a8, 0xfff8, op_imm32, ea_das32_read, gen_addl_im_ea), + addi_l_imm32_das(0x06a8, 0xfff8, op_imm32, ea_das32_read, gen_addl_alub_dt), - addi_l_imm32_dais(0x06b0, 0xfff8, op_imm32, ea_dais32_read, gen_addl_im_ea), + addi_l_imm32_dais(0x06b0, 0xfff8, op_imm32, ea_dais32_read, gen_addl_alub_dt), - addi_l_imm32_adr16(0x06b8, 0xffff, op_imm32, ea_adr16s32_read, gen_addl_im_ea), + addi_l_imm32_adr16(0x06b8, 0xffff, op_imm32, ea_adr16s32_read, gen_addl_alub_dt), - addi_l_imm32_adr32(0x06b9, 0xffff, op_imm32, ea_adr32s32_read, gen_addl_im_ea), + addi_l_imm32_adr32(0x06b9, 0xffff, op_imm32, ea_adr32s32_read, gen_addl_alub_dt), - btst_imm8_ds(0x0800, 0xfff8, op_imm16, gen_btstl_dt_ds, dbrr), + btst_imm8_ds(0x0800, 0xfff8, op_imm16, gen_btstl_dt_dy, dbrr), - btst_imm8_ais(0x0810, 0xfff8, op_imm16, ea_ais8_read, gen_btstb_im_ea), + btst_imm8_ais(0x0810, 0xfff8, op_imm16, ea_ais8_read, gen_btstb_alub_dt), - btst_imm8_aips(0x0818, 0xfff8, op_imm16, ea_aips8_read, gen_btstb_im_ea), + btst_imm8_aips(0x0818, 0xfff8, op_imm16, ea_aips8_read, gen_btstb_alub_dt), - btst_imm8_pais(0x0820, 0xfff8, op_imm16, ea_pais8_read, gen_btstb_im_ea), + btst_imm8_pais(0x0820, 0xfff8, op_imm16, ea_pais8_read, gen_btstb_alub_dt), - btst_imm8_das(0x0828, 0xfff8, op_imm16, ea_das8_read, gen_btstb_im_ea), + btst_imm8_das(0x0828, 0xfff8, op_imm16, ea_das8_read, gen_btstb_alub_dt), - btst_imm8_dais(0x0830, 0xfff8, op_imm16, ea_dais8_read, gen_btstb_im_ea), + btst_imm8_dais(0x0830, 0xfff8, op_imm16, ea_dais8_read, gen_btstb_alub_dt), - btst_imm8_adr16(0x0838, 0xffff, op_imm16, ea_adr16s8_read, gen_btstb_im_ea), + btst_imm8_adr16(0x0838, 0xffff, op_imm16, ea_adr16s8_read, gen_btstb_alub_dt), - btst_imm8_adr32(0x0839, 0xffff, op_imm16, ea_adr32s8_read, gen_btstb_im_ea), + btst_imm8_adr32(0x0839, 0xffff, op_imm16, ea_adr32s8_read, gen_btstb_alub_dt), - btst_imm8_dpc(0x083a, 0xffff, op_imm16, ea_dpc8_read, gen_btstb_im_ea), + btst_imm8_dpc(0x083a, 0xffff, op_imm16, ea_dpc8_read, gen_btstb_alub_dt), - btst_imm8_dpci(0x083b, 0xffff, op_imm16, ea_dpci8_read, gen_btstb_im_ea), + btst_imm8_dpci(0x083b, 0xffff, op_imm16, ea_dpci8_read, gen_btstb_alub_dt), - bchg_imm8_ds(0x0840, 0xfff8, op_imm16, gen_bchgl_dt_ds, dbrr), + bchg_imm8_ds(0x0840, 0xfff8, op_imm16, gen_bchgl_dt_dy, dbrr), - bchg_imm8_ais(0x0850, 0xfff8, op_imm16, ea_ais8_read, gen_bchgb_im_ea), + bchg_imm8_ais(0x0850, 0xfff8, op_imm16, ea_ais8_read, gen_bchgb_alub_dt), - bchg_imm8_aips(0x0858, 0xfff8, op_imm16, ea_aips8_read, gen_bchgb_im_ea), + bchg_imm8_aips(0x0858, 0xfff8, op_imm16, ea_aips8_read, gen_bchgb_alub_dt), - bchg_imm8_pais(0x0860, 0xfff8, op_imm16, ea_pais8_read, gen_bchgb_im_ea), + bchg_imm8_pais(0x0860, 0xfff8, op_imm16, ea_pais8_read, gen_bchgb_alub_dt), - bchg_imm8_das(0x0868, 0xfff8, op_imm16, ea_das8_read, gen_bchgb_im_ea), + bchg_imm8_das(0x0868, 0xfff8, op_imm16, ea_das8_read, gen_bchgb_alub_dt), - bchg_imm8_dais(0x0870, 0xfff8, op_imm16, ea_dais8_read, gen_bchgb_im_ea), + bchg_imm8_dais(0x0870, 0xfff8, op_imm16, ea_dais8_read, gen_bchgb_alub_dt), - bchg_imm8_adr16(0x0878, 0xffff, op_imm16, ea_adr16s8_read, gen_bchgb_im_ea), + bchg_imm8_adr16(0x0878, 0xffff, op_imm16, ea_adr16s8_read, gen_bchgb_alub_dt), - bchg_imm8_adr32(0x0879, 0xffff, op_imm16, ea_adr32s8_read, gen_bchgb_im_ea), + bchg_imm8_adr32(0x0879, 0xffff, op_imm16, ea_adr32s8_read, gen_bchgb_alub_dt), - bclr_imm8_ds(0x0880, 0xfff8, op_imm16, gen_bclrl_dt_ds, dbrr), + bclr_imm8_ds(0x0880, 0xfff8, op_imm16, gen_bclrl_dt_dy, dbrr), - bclr_imm8_ais(0x0890, 0xfff8, op_imm16, ea_ais8_read, gen_bclrb_im_ea), + bclr_imm8_ais(0x0890, 0xfff8, op_imm16, ea_ais8_read, gen_bclrb_alub_dt), - bclr_imm8_aips(0x0898, 0xfff8, op_imm16, ea_aips8_read, gen_bclrb_im_ea), + bclr_imm8_aips(0x0898, 0xfff8, op_imm16, ea_aips8_read, gen_bclrb_alub_dt), - bclr_imm8_pais(0x08a0, 0xfff8, op_imm16, ea_pais8_read, gen_bclrb_im_ea), + bclr_imm8_pais(0x08a0, 0xfff8, op_imm16, ea_pais8_read, gen_bclrb_alub_dt), - bclr_imm8_das(0x08a8, 0xfff8, op_imm16, ea_das8_read, gen_bclrb_im_ea), + bclr_imm8_das(0x08a8, 0xfff8, op_imm16, ea_das8_read, gen_bclrb_alub_dt), - bclr_imm8_dais(0x08b0, 0xfff8, op_imm16, ea_dais8_read, gen_bclrb_im_ea), + bclr_imm8_dais(0x08b0, 0xfff8, op_imm16, ea_dais8_read, gen_bclrb_alub_dt), - bclr_imm8_adr16(0x08b8, 0xffff, op_imm16, ea_adr16s8_read, gen_bclrb_im_ea), + bclr_imm8_adr16(0x08b8, 0xffff, op_imm16, ea_adr16s8_read, gen_bclrb_alub_dt), - bclr_imm8_adr32(0x08b9, 0xffff, op_imm16, ea_adr32s8_read, gen_bclrb_im_ea), + bclr_imm8_adr32(0x08b9, 0xffff, op_imm16, ea_adr32s8_read, gen_bclrb_alub_dt), - bset_imm8_ds(0x08c0, 0xfff8, op_imm16, gen_bsetl_dt_ds, dbrr), + bset_imm8_ds(0x08c0, 0xfff8, op_imm16, gen_bsetl_dt_dy, dbrr), - bset_imm8_ais(0x08d0, 0xfff8, op_imm16, ea_ais8_read, gen_bsetb_im_ea), + bset_imm8_ais(0x08d0, 0xfff8, op_imm16, ea_ais8_read, gen_bsetb_alub_dt), - bset_imm8_aips(0x08d8, 0xfff8, op_imm16, ea_aips8_read, gen_bsetb_im_ea), + bset_imm8_aips(0x08d8, 0xfff8, op_imm16, ea_aips8_read, gen_bsetb_alub_dt), - bset_imm8_pais(0x08e0, 0xfff8, op_imm16, ea_pais8_read, gen_bsetb_im_ea), + bset_imm8_pais(0x08e0, 0xfff8, op_imm16, ea_pais8_read, gen_bsetb_alub_dt), - bset_imm8_das(0x08e8, 0xfff8, op_imm16, ea_das8_read, gen_bsetb_im_ea), + bset_imm8_das(0x08e8, 0xfff8, op_imm16, ea_das8_read, gen_bsetb_alub_dt), - bset_imm8_dais(0x08f0, 0xfff8, op_imm16, ea_dais8_read, gen_bsetb_im_ea), + bset_imm8_dais(0x08f0, 0xfff8, op_imm16, ea_dais8_read, gen_bsetb_alub_dt), - bset_imm8_adr16(0x08f8, 0xffff, op_imm16, ea_adr16s8_read, gen_bsetb_im_ea), + bset_imm8_adr16(0x08f8, 0xffff, op_imm16, ea_adr16s8_read, gen_bsetb_alub_dt), - bset_imm8_adr32(0x08f9, 0xffff, op_imm16, ea_adr32s8_read, gen_bsetb_im_ea), + bset_imm8_adr32(0x08f9, 0xffff, op_imm16, ea_adr32s8_read, gen_bsetb_alub_dt), - eori_b_imm8_ds(0x0a00, 0xfff8, op_imm16, gen_eorb_dt_ds, dbrr), + eori_b_imm8_ds(0x0a00, 0xfff8, op_imm16, gen_eorb_dt_dy, dbrr), - eori_b_imm8_ais(0x0a10, 0xfff8, op_imm16, ea_ais8_read, gen_eorb_im_ea), + eori_b_imm8_ais(0x0a10, 0xfff8, op_imm16, ea_ais8_read, gen_eorb_alub_dt), - eori_b_imm8_aips(0x0a18, 0xfff8, op_imm16, ea_aips8_read, gen_eorb_im_ea), + eori_b_imm8_aips(0x0a18, 0xfff8, op_imm16, ea_aips8_read, gen_eorb_alub_dt), - eori_b_imm8_pais(0x0a20, 0xfff8, op_imm16, ea_pais8_read, gen_eorb_im_ea), + eori_b_imm8_pais(0x0a20, 0xfff8, op_imm16, ea_pais8_read, gen_eorb_alub_dt), - eori_b_imm8_das(0x0a28, 0xfff8, op_imm16, ea_das8_read, gen_eorb_im_ea), + eori_b_imm8_das(0x0a28, 0xfff8, op_imm16, ea_das8_read, gen_eorb_alub_dt), - eori_b_imm8_dais(0x0a30, 0xfff8, op_imm16, ea_dais8_read, gen_eorb_im_ea), + eori_b_imm8_dais(0x0a30, 0xfff8, op_imm16, ea_dais8_read, gen_eorb_alub_dt), - eori_b_imm8_adr16(0x0a38, 0xffff, op_imm16, ea_adr16s8_read, gen_eorb_im_ea), + eori_b_imm8_adr16(0x0a38, 0xffff, op_imm16, ea_adr16s8_read, gen_eorb_alub_dt), - eori_b_imm8_adr32(0x0a39, 0xffff, op_imm16, ea_adr32s8_read, gen_eorb_im_ea), + eori_b_imm8_adr32(0x0a39, 0xffff, op_imm16, ea_adr32s8_read, gen_eorb_alub_dt), eori_imm8_ccr(0x0a3c, 0xffff, op_imm16, gen_eorb_dt_ccr, dbrr), - eori_w_imm16_ds(0x0a40, 0xfff8, op_imm16, gen_eorw_dt_ds, dbrr), + eori_w_imm16_ds(0x0a40, 0xfff8, op_imm16, gen_eorw_dt_dy, dbrr), - eori_w_imm16_ais(0x0a50, 0xfff8, op_imm16, ea_ais16_read, gen_eorw_im_ea), + eori_w_imm16_ais(0x0a50, 0xfff8, op_imm16, ea_ais16_read, gen_eorw_alub_dt), - eori_w_imm16_aips(0x0a58, 0xfff8, op_imm16, ea_aips16_read, gen_eorw_im_ea), + eori_w_imm16_aips(0x0a58, 0xfff8, op_imm16, ea_aips16_read, gen_eorw_alub_dt), - eori_w_imm16_pais(0x0a60, 0xfff8, op_imm16, ea_pais16_read, gen_eorw_im_ea), + eori_w_imm16_pais(0x0a60, 0xfff8, op_imm16, ea_pais16_read, gen_eorw_alub_dt), - eori_w_imm16_das(0x0a68, 0xfff8, op_imm16, ea_das16_read, gen_eorw_im_ea), + eori_w_imm16_das(0x0a68, 0xfff8, op_imm16, ea_das16_read, gen_eorw_alub_dt), - eori_w_imm16_dais(0x0a70, 0xfff8, op_imm16, ea_dais16_read, gen_eorw_im_ea), + eori_w_imm16_dais(0x0a70, 0xfff8, op_imm16, ea_dais16_read, gen_eorw_alub_dt), - eori_w_imm16_adr16(0x0a78, 0xffff, op_imm16, ea_adr16s16_read, gen_eorw_im_ea), + eori_w_imm16_adr16(0x0a78, 0xffff, op_imm16, ea_adr16s16_read, gen_eorw_alub_dt), - eori_w_imm16_adr32(0x0a79, 0xffff, op_imm16, ea_adr32s16_read, gen_eorw_im_ea), + eori_w_imm16_adr32(0x0a79, 0xffff, op_imm16, ea_adr32s16_read, gen_eorw_alub_dt), eori_i16u_sr(0x0a7c, 0xffff, op_imm16, gen_eorw_dt_sr, dbrr), - eori_l_imm32_ds(0x0a80, 0xfff8, op_imm32, gen_eorl_dt_ds, dbrr), + eori_l_imm32_ds(0x0a80, 0xfff8, op_imm32, gen_eorl_dt_dy, dbrr), - eori_l_imm32_ais(0x0a90, 0xfff8, op_imm32, ea_ais32_read, gen_eorl_im_ea), + eori_l_imm32_ais(0x0a90, 0xfff8, op_imm32, ea_ais32_read, gen_eorl_alub_dt), - eori_l_imm32_aips(0x0a98, 0xfff8, op_imm32, ea_aips32_read, gen_eorl_im_ea), + eori_l_imm32_aips(0x0a98, 0xfff8, op_imm32, ea_aips32_read, gen_eorl_alub_dt), - eori_l_imm32_pais(0x0aa0, 0xfff8, op_imm32, ea_pais32_read, gen_eorl_im_ea), + eori_l_imm32_pais(0x0aa0, 0xfff8, op_imm32, ea_pais32_read, gen_eorl_alub_dt), - eori_l_imm32_das(0x0aa8, 0xfff8, op_imm32, ea_das32_read, gen_eorl_im_ea), + eori_l_imm32_das(0x0aa8, 0xfff8, op_imm32, ea_das32_read, gen_eorl_alub_dt), - eori_l_imm32_dais(0x0ab0, 0xfff8, op_imm32, ea_dais32_read, gen_eorl_im_ea), + eori_l_imm32_dais(0x0ab0, 0xfff8, op_imm32, ea_dais32_read, gen_eorl_alub_dt), - eori_l_imm32_adr16(0x0ab8, 0xffff, op_imm32, ea_adr16s32_read, gen_eorl_im_ea), + eori_l_imm32_adr16(0x0ab8, 0xffff, op_imm32, ea_adr16s32_read, gen_eorl_alub_dt), - eori_l_imm32_adr32(0x0ab9, 0xffff, op_imm32, ea_adr32s32_read, gen_eorl_im_ea), + eori_l_imm32_adr32(0x0ab9, 0xffff, op_imm32, ea_adr32s32_read, gen_eorl_alub_dt), - cmpi_b_imm8_ds(0x0c00, 0xfff8, op_imm16, gen_cmpb_dt_ds, dbrr), + cmpi_b_imm8_ds(0x0c00, 0xfff8, op_imm16, gen_cmpb_dt_dy, dbrr), - cmpi_b_imm8_ais(0x0c10, 0xfff8, op_imm16, ea_ais8_read, gen_cmpb_im_ea), + cmpi_b_imm8_ais(0x0c10, 0xfff8, op_imm16, ea_ais8_read, gen_cmpb_alub_dt), - cmpi_b_imm8_aips(0x0c18, 0xfff8, op_imm16, ea_aips8_read, gen_cmpb_im_ea), + cmpi_b_imm8_aips(0x0c18, 0xfff8, op_imm16, ea_aips8_read, gen_cmpb_alub_dt), - cmpi_b_imm8_pais(0x0c20, 0xfff8, op_imm16, ea_pais8_read, gen_cmpb_im_ea), + cmpi_b_imm8_pais(0x0c20, 0xfff8, op_imm16, ea_pais8_read, gen_cmpb_alub_dt), - cmpi_b_imm8_das(0x0c28, 0xfff8, op_imm16, ea_das8_read, gen_cmpb_im_ea), + cmpi_b_imm8_das(0x0c28, 0xfff8, op_imm16, ea_das8_read, gen_cmpb_alub_dt), - cmpi_b_imm8_dais(0x0c30, 0xfff8, op_imm16, ea_dais8_read, gen_cmpb_im_ea), + cmpi_b_imm8_dais(0x0c30, 0xfff8, op_imm16, ea_dais8_read, gen_cmpb_alub_dt), - cmpi_b_imm8_adr16(0x0c38, 0xffff, op_imm16, ea_adr16s8_read, gen_cmpb_im_ea), + cmpi_b_imm8_adr16(0x0c38, 0xffff, op_imm16, ea_adr16s8_read, gen_cmpb_alub_dt), - cmpi_b_imm8_adr32(0x0c39, 0xffff, op_imm16, ea_adr32s8_read, gen_cmpb_im_ea), + cmpi_b_imm8_adr32(0x0c39, 0xffff, op_imm16, ea_adr32s8_read, gen_cmpb_alub_dt), - cmpi_w_imm16_ds(0x0c40, 0xfff8, op_imm16, gen_cmpw_dt_ds, dbrr), + cmpi_w_imm16_ds(0x0c40, 0xfff8, op_imm16, gen_cmpw_dt_dy, dbrr), - cmpi_w_imm16_ais(0x0c50, 0xfff8, op_imm16, ea_ais16_read, gen_cmpw_im_ea), + cmpi_w_imm16_ais(0x0c50, 0xfff8, op_imm16, ea_ais16_read, gen_cmpw_alub_dt), - cmpi_w_imm16_aips(0x0c58, 0xfff8, op_imm16, ea_aips16_read, gen_cmpw_im_ea), + cmpi_w_imm16_aips(0x0c58, 0xfff8, op_imm16, ea_aips16_read, gen_cmpw_alub_dt), - cmpi_w_imm16_pais(0x0c60, 0xfff8, op_imm16, ea_pais16_read, gen_cmpw_im_ea), + cmpi_w_imm16_pais(0x0c60, 0xfff8, op_imm16, ea_pais16_read, gen_cmpw_alub_dt), - cmpi_w_imm16_das(0x0c68, 0xfff8, op_imm16, ea_das16_read, gen_cmpw_im_ea), + cmpi_w_imm16_das(0x0c68, 0xfff8, op_imm16, ea_das16_read, gen_cmpw_alub_dt), - cmpi_w_imm16_dais(0x0c70, 0xfff8, op_imm16, ea_dais16_read, gen_cmpw_im_ea), + cmpi_w_imm16_dais(0x0c70, 0xfff8, op_imm16, ea_dais16_read, gen_cmpw_alub_dt), - cmpi_w_imm16_adr16(0x0c78, 0xffff, op_imm16, ea_adr16s16_read, gen_cmpw_im_ea), + cmpi_w_imm16_adr16(0x0c78, 0xffff, op_imm16, ea_adr16s16_read, gen_cmpw_alub_dt), - cmpi_w_imm16_adr32(0x0c79, 0xffff, op_imm16, ea_adr32s16_read, gen_cmpw_im_ea), + cmpi_w_imm16_adr32(0x0c79, 0xffff, op_imm16, ea_adr32s16_read, gen_cmpw_alub_dt), - cmpi_l_imm32_ds(0x0c80, 0xfff8, op_imm32, gen_cmpl_dt_ds, dbrr), + cmpi_l_imm32_ds(0x0c80, 0xfff8, op_imm32, gen_cmpl_dt_dy, dbrr), - cmpi_l_imm32_ais(0x0c90, 0xfff8, op_imm32, ea_ais32_read, gen_cmpl_im_ea), + cmpi_l_imm32_ais(0x0c90, 0xfff8, op_imm32, ea_ais32_read, gen_cmpl_alub_dt), - cmpi_l_imm32_aips(0x0c98, 0xfff8, op_imm32, ea_aips32_read, gen_cmpl_im_ea), + cmpi_l_imm32_aips(0x0c98, 0xfff8, op_imm32, ea_aips32_read, gen_cmpl_alub_dt), - cmpi_l_imm32_pais(0x0ca0, 0xfff8, op_imm32, ea_pais32_read, gen_cmpl_im_ea), + cmpi_l_imm32_pais(0x0ca0, 0xfff8, op_imm32, ea_pais32_read, gen_cmpl_alub_dt), - cmpi_l_imm32_das(0x0ca8, 0xfff8, op_imm32, ea_das32_read, gen_cmpl_im_ea), + cmpi_l_imm32_das(0x0ca8, 0xfff8, op_imm32, ea_das32_read, gen_cmpl_alub_dt), - cmpi_l_imm32_dais(0x0cb0, 0xfff8, op_imm32, ea_dais32_read, gen_cmpl_im_ea), + cmpi_l_imm32_dais(0x0cb0, 0xfff8, op_imm32, ea_dais32_read, gen_cmpl_alub_dt), - cmpi_l_imm32_adr16(0x0cb8, 0xffff, op_imm32, ea_adr16s32_read, gen_cmpl_im_ea), + cmpi_l_imm32_adr16(0x0cb8, 0xffff, op_imm32, ea_adr16s32_read, gen_cmpl_alub_dt), - cmpi_l_imm32_adr32(0x0cb9, 0xffff, op_imm32, ea_adr32s32_read, gen_cmpl_im_ea), + cmpi_l_imm32_adr32(0x0cb9, 0xffff, op_imm32, ea_adr32s32_read, gen_cmpl_alub_dt), - move_b_ds_dd(0x1000, 0xf1f8, gen_moveb_ds_dd, dbrr, dbrr), + move_b_ds_dd(0x1000, 0xf1f8, gen_moveb_dy_dx, dbrr, dbrr), - move_b_ais_dd(0x1010, 0xf1f8, ea_ais8_read, dbrr, gen_moveb_dt_dd), + move_b_ais_dd(0x1010, 0xf1f8, ea_ais8_read, dbrr, gen_moveb_dt_dx), - move_b_aips_dd(0x1018, 0xf1f8, ea_aips8_read, dbrr, gen_moveb_dt_dd), + move_b_aips_dd(0x1018, 0xf1f8, ea_aips8_read, dbrr, gen_moveb_dt_dx), - move_b_pais_dd(0x1020, 0xf1f8, ea_pais8_read, dbrr, gen_moveb_dt_dd), + move_b_pais_dd(0x1020, 0xf1f8, ea_pais8_read, dbrr, gen_moveb_dt_dx), - move_b_das_dd(0x1028, 0xf1f8, ea_das8_read, dbrr, gen_moveb_dt_dd), + move_b_das_dd(0x1028, 0xf1f8, ea_das8_read, dbrr, gen_moveb_dt_dx), - move_b_dais_dd(0x1030, 0xf1f8, ea_dais8_read, dbrr, gen_moveb_dt_dd), + move_b_dais_dd(0x1030, 0xf1f8, ea_dais8_read, dbrr, gen_moveb_dt_dx), - move_b_adr16_dd(0x1038, 0xf1ff, ea_adr16s8_read, dbrr, gen_moveb_dt_dd), + move_b_adr16_dd(0x1038, 0xf1ff, ea_adr16s8_read, dbrr, gen_moveb_dt_dx), - move_b_adr32_dd(0x1039, 0xf1ff, ea_adr32s8_read, dbrr, gen_moveb_dt_dd), + move_b_adr32_dd(0x1039, 0xf1ff, ea_adr32s8_read, dbrr, gen_moveb_dt_dx), - move_b_dpc_dd(0x103a, 0xf1ff, ea_dpc8_read, dbrr, gen_moveb_dt_dd), + move_b_dpc_dd(0x103a, 0xf1ff, ea_dpc8_read, dbrr, gen_moveb_dt_dx), - move_b_dpci_dd(0x103b, 0xf1ff, ea_dpci8_read, dbrr, gen_moveb_dt_dd), + move_b_dpci_dd(0x103b, 0xf1ff, ea_dpci8_read, dbrr, gen_moveb_dt_dx), - move_b_imm8_dd(0x103c, 0xf1ff, ea_imm8_read, dbrr, gen_moveb_dt_dd), + move_b_imm8_dd(0x103c, 0xf1ff, ea_imm8_read, dbrr, gen_moveb_dt_dx), - move_b_ds_aid(0x1080, 0xf1f8, ea_aid8, gen_moveb_ds_ea, dbrr), + move_b_ds_aid(0x1080, 0xf1f8, ea_aid8, gen_moveb_dy_dt, dbrr), - move_b_ais_aid(0x1090, 0xf1f8, ea_ais8_read, gen_moveb_dt_ea, ea_aid8), + move_b_ais_aid(0x1090, 0xf1f8, ea_ais8_read, gen_moveb_dt_dt, ea_aid8), - move_b_aips_aid(0x1098, 0xf1f8, ea_aips8_read, gen_moveb_dt_ea, ea_aid8), + move_b_aips_aid(0x1098, 0xf1f8, ea_aips8_read, gen_moveb_dt_dt, ea_aid8), - move_b_pais_aid(0x10a0, 0xf1f8, ea_pais8_read, gen_moveb_dt_ea, ea_aid8), + move_b_pais_aid(0x10a0, 0xf1f8, ea_pais8_read, gen_moveb_dt_dt, ea_aid8), - move_b_das_aid(0x10a8, 0xf1f8, ea_das8_read, gen_moveb_dt_ea, ea_aid8), + move_b_das_aid(0x10a8, 0xf1f8, ea_das8_read, gen_moveb_dt_dt, ea_aid8), - move_b_dais_aid(0x10b0, 0xf1f8, ea_dais8_read, gen_moveb_dt_ea, ea_aid8), + move_b_dais_aid(0x10b0, 0xf1f8, ea_dais8_read, gen_moveb_dt_dt, ea_aid8), - move_b_adr16_aid(0x10b8, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_ea, ea_aid8), + move_b_adr16_aid(0x10b8, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_dt, ea_aid8), - move_b_adr32_aid(0x10b9, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_ea, ea_aid8), + move_b_adr32_aid(0x10b9, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_dt, ea_aid8), - move_b_dpc_aid(0x10ba, 0xf1ff, ea_dpc8_read, gen_moveb_dt_ea, ea_aid8), + move_b_dpc_aid(0x10ba, 0xf1ff, ea_dpc8_read, gen_moveb_dt_dt, ea_aid8), - move_b_dpci_aid(0x10bb, 0xf1ff, ea_dpci8_read, gen_moveb_dt_ea, ea_aid8), + move_b_dpci_aid(0x10bb, 0xf1ff, ea_dpci8_read, gen_moveb_dt_dt, ea_aid8), - move_b_imm8_aid(0x10bc, 0xf1ff, ea_imm8_read, gen_moveb_dt_ea, ea_aid8), + move_b_imm8_aid(0x10bc, 0xf1ff, ea_imm8_read, gen_moveb_dt_dt, ea_aid8), - move_b_ds_aipd(0x10c0, 0xf1f8, ea_aipd8, gen_moveb_ds_ea, dbrr), + move_b_ds_aipd(0x10c0, 0xf1f8, ea_aipd8, gen_moveb_dy_dt, dbrr), - move_b_ais_aipd(0x10d0, 0xf1f8, ea_ais8_read, gen_moveb_dt_ea, ea_aipd8), + move_b_ais_aipd(0x10d0, 0xf1f8, ea_ais8_read, gen_moveb_dt_dt, ea_aipd8), - move_b_aips_aipd(0x10d8, 0xf1f8, ea_aips8_read, gen_moveb_dt_ea, ea_aipd8), + move_b_aips_aipd(0x10d8, 0xf1f8, ea_aips8_read, gen_moveb_dt_dt, ea_aipd8), - move_b_pais_aipd(0x10e0, 0xf1f8, ea_pais8_read, gen_moveb_dt_ea, ea_aipd8), + move_b_pais_aipd(0x10e0, 0xf1f8, ea_pais8_read, gen_moveb_dt_dt, ea_aipd8), - move_b_das_aipd(0x10e8, 0xf1f8, ea_das8_read, gen_moveb_dt_ea, ea_aipd8), + move_b_das_aipd(0x10e8, 0xf1f8, ea_das8_read, gen_moveb_dt_dt, ea_aipd8), - move_b_dais_aipd(0x10f0, 0xf1f8, ea_dais8_read, gen_moveb_dt_ea, ea_aipd8), + move_b_dais_aipd(0x10f0, 0xf1f8, ea_dais8_read, gen_moveb_dt_dt, ea_aipd8), - move_b_adr16_aipd(0x10f8, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_ea, ea_aipd8), + move_b_adr16_aipd(0x10f8, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_dt, ea_aipd8), - move_b_adr32_aipd(0x10f9, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_ea, ea_aipd8), + move_b_adr32_aipd(0x10f9, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_dt, ea_aipd8), - move_b_dpc_aipd(0x10fa, 0xf1ff, ea_dpc8_read, gen_moveb_dt_ea, ea_aipd8), + move_b_dpc_aipd(0x10fa, 0xf1ff, ea_dpc8_read, gen_moveb_dt_dt, ea_aipd8), - move_b_dpci_aipd(0x10fb, 0xf1ff, ea_dpci8_read, gen_moveb_dt_ea, ea_aipd8), + move_b_dpci_aipd(0x10fb, 0xf1ff, ea_dpci8_read, gen_moveb_dt_dt, ea_aipd8), - move_b_imm8_aipd(0x10fc, 0xf1ff, ea_imm8_read, gen_moveb_dt_ea, ea_aipd8), + move_b_imm8_aipd(0x10fc, 0xf1ff, ea_imm8_read, gen_moveb_dt_dt, ea_aipd8), - move_b_ds_paid(0x1100, 0xf1f8, ea_paid8, gen_moveb_ds_ea, dbrr), + move_b_ds_paid(0x1100, 0xf1f8, ea_paid8, gen_moveb_dy_dt, dbrr), - move_b_ais_paid(0x1110, 0xf1f8, ea_ais8_read, gen_moveb_dt_ea, ea_paid8), + move_b_ais_paid(0x1110, 0xf1f8, ea_ais8_read, gen_moveb_dt_dt, ea_paid8), - move_b_aips_paid(0x1118, 0xf1f8, ea_aips8_read, gen_moveb_dt_ea, ea_paid8), + move_b_aips_paid(0x1118, 0xf1f8, ea_aips8_read, gen_moveb_dt_dt, ea_paid8), - move_b_pais_paid(0x1120, 0xf1f8, ea_pais8_read, gen_moveb_dt_ea, ea_paid8), + move_b_pais_paid(0x1120, 0xf1f8, ea_pais8_read, gen_moveb_dt_dt, ea_paid8), - move_b_das_paid(0x1128, 0xf1f8, ea_das8_read, gen_moveb_dt_ea, ea_paid8), + move_b_das_paid(0x1128, 0xf1f8, ea_das8_read, gen_moveb_dt_dt, ea_paid8), - move_b_dais_paid(0x1130, 0xf1f8, ea_dais8_read, gen_moveb_dt_ea, ea_paid8), + move_b_dais_paid(0x1130, 0xf1f8, ea_dais8_read, gen_moveb_dt_dt, ea_paid8), - move_b_adr16_paid(0x1138, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_ea, ea_paid8), + move_b_adr16_paid(0x1138, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_dt, ea_paid8), - move_b_adr32_paid(0x1139, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_ea, ea_paid8), + move_b_adr32_paid(0x1139, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_dt, ea_paid8), - move_b_dpc_paid(0x113a, 0xf1ff, ea_dpc8_read, gen_moveb_dt_ea, ea_paid8), + move_b_dpc_paid(0x113a, 0xf1ff, ea_dpc8_read, gen_moveb_dt_dt, ea_paid8), - move_b_dpci_paid(0x113b, 0xf1ff, ea_dpci8_read, gen_moveb_dt_ea, ea_paid8), + move_b_dpci_paid(0x113b, 0xf1ff, ea_dpci8_read, gen_moveb_dt_dt, ea_paid8), - move_b_imm8_paid(0x113c, 0xf1ff, ea_imm8_read, gen_moveb_dt_ea, ea_paid8), + move_b_imm8_paid(0x113c, 0xf1ff, ea_imm8_read, gen_moveb_dt_dt, ea_paid8), - move_b_ds_dad(0x1140, 0xf1f8, ea_dad8, gen_moveb_ds_ea, dbrr), + move_b_ds_dad(0x1140, 0xf1f8, ea_dad8, gen_moveb_dy_dt, dbrr), - move_b_ais_dad(0x1150, 0xf1f8, ea_ais8_read, gen_moveb_dt_ea, ea_dad8), + move_b_ais_dad(0x1150, 0xf1f8, ea_ais8_read, gen_moveb_dt_dt, ea_dad8), - move_b_aips_dad(0x1158, 0xf1f8, ea_aips8_read, gen_moveb_dt_ea, ea_dad8), + move_b_aips_dad(0x1158, 0xf1f8, ea_aips8_read, gen_moveb_dt_dt, ea_dad8), - move_b_pais_dad(0x1160, 0xf1f8, ea_pais8_read, gen_moveb_dt_ea, ea_dad8), + move_b_pais_dad(0x1160, 0xf1f8, ea_pais8_read, gen_moveb_dt_dt, ea_dad8), - move_b_das_dad(0x1168, 0xf1f8, ea_das8_read, gen_moveb_dt_ea, ea_dad8), + move_b_das_dad(0x1168, 0xf1f8, ea_das8_read, gen_moveb_dt_dt, ea_dad8), - move_b_dais_dad(0x1170, 0xf1f8, ea_dais8_read, gen_moveb_dt_ea, ea_dad8), + move_b_dais_dad(0x1170, 0xf1f8, ea_dais8_read, gen_moveb_dt_dt, ea_dad8), - move_b_adr16_dad(0x1178, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_ea, ea_dad8), + move_b_adr16_dad(0x1178, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_dt, ea_dad8), - move_b_adr32_dad(0x1179, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_ea, ea_dad8), + move_b_adr32_dad(0x1179, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_dt, ea_dad8), - move_b_dpc_dad(0x117a, 0xf1ff, ea_dpc8_read, gen_moveb_dt_ea, ea_dad8), + move_b_dpc_dad(0x117a, 0xf1ff, ea_dpc8_read, gen_moveb_dt_dt, ea_dad8), - move_b_dpci_dad(0x117b, 0xf1ff, ea_dpci8_read, gen_moveb_dt_ea, ea_dad8), + move_b_dpci_dad(0x117b, 0xf1ff, ea_dpci8_read, gen_moveb_dt_dt, ea_dad8), - move_b_imm8_dad(0x117c, 0xf1ff, ea_imm8_read, gen_moveb_dt_ea, ea_dad8), + move_b_imm8_dad(0x117c, 0xf1ff, ea_imm8_read, gen_moveb_dt_dt, ea_dad8), - move_b_ds_daid(0x1180, 0xf1f8, ea_daid8, gen_moveb_ds_ea, dbrr), + move_b_ds_daid(0x1180, 0xf1f8, ea_daid8, gen_moveb_dy_dt, dbrr), - move_b_ais_daid(0x1190, 0xf1f8, ea_ais8_read, gen_moveb_dt_ea, ea_daid8), + move_b_ais_daid(0x1190, 0xf1f8, ea_ais8_read, gen_moveb_dt_dt, ea_daid8), - move_b_aips_daid(0x1198, 0xf1f8, ea_aips8_read, gen_moveb_dt_ea, ea_daid8), + move_b_aips_daid(0x1198, 0xf1f8, ea_aips8_read, gen_moveb_dt_dt, ea_daid8), - move_b_pais_daid(0x11a0, 0xf1f8, ea_pais8_read, gen_moveb_dt_ea, ea_daid8), + move_b_pais_daid(0x11a0, 0xf1f8, ea_pais8_read, gen_moveb_dt_dt, ea_daid8), - move_b_das_daid(0x11a8, 0xf1f8, ea_das8_read, gen_moveb_dt_ea, ea_daid8), + move_b_das_daid(0x11a8, 0xf1f8, ea_das8_read, gen_moveb_dt_dt, ea_daid8), - move_b_dais_daid(0x11b0, 0xf1f8, ea_dais8_read, gen_moveb_dt_ea, ea_daid8), + move_b_dais_daid(0x11b0, 0xf1f8, ea_dais8_read, gen_moveb_dt_dt, ea_daid8), - move_b_adr16_daid(0x11b8, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_ea, ea_daid8), + move_b_adr16_daid(0x11b8, 0xf1ff, ea_adr16s8_read, gen_moveb_dt_dt, ea_daid8), - move_b_adr32_daid(0x11b9, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_ea, ea_daid8), + move_b_adr32_daid(0x11b9, 0xf1ff, ea_adr32s8_read, gen_moveb_dt_dt, ea_daid8), - move_b_dpc_daid(0x11ba, 0xf1ff, ea_dpc8_read, gen_moveb_dt_ea, ea_daid8), + move_b_dpc_daid(0x11ba, 0xf1ff, ea_dpc8_read, gen_moveb_dt_dt, ea_daid8), - move_b_dpci_daid(0x11bb, 0xf1ff, ea_dpci8_read, gen_moveb_dt_ea, ea_daid8), + move_b_dpci_daid(0x11bb, 0xf1ff, ea_dpci8_read, gen_moveb_dt_dt, ea_daid8), - move_b_imm8_daid(0x11bc, 0xf1ff, ea_imm8_read, gen_moveb_dt_ea, ea_daid8), + move_b_imm8_daid(0x11bc, 0xf1ff, ea_imm8_read, gen_moveb_dt_dt, ea_daid8), - move_b_ds_adr16(0x11c0, 0xfff8, ea_adr16d8, gen_moveb_ds_ea, dbrr), + move_b_ds_adr16(0x11c0, 0xfff8, ea_adr16d8, gen_moveb_dy_dt, dbrr), - move_b_ais_adr16(0x11d0, 0xfff8, ea_ais8_read, gen_moveb_dt_ea, ea_adr16d8), + move_b_ais_adr16(0x11d0, 0xfff8, ea_ais8_read, gen_moveb_dt_dt, ea_adr16d8), - move_b_aips_adr16(0x11d8, 0xfff8, ea_aips8_read, gen_moveb_dt_ea, ea_adr16d8), + move_b_aips_adr16(0x11d8, 0xfff8, ea_aips8_read, gen_moveb_dt_dt, ea_adr16d8), - move_b_pais_adr16(0x11e0, 0xfff8, ea_pais8_read, gen_moveb_dt_ea, ea_adr16d8), + move_b_pais_adr16(0x11e0, 0xfff8, ea_pais8_read, gen_moveb_dt_dt, ea_adr16d8), - move_b_das_adr16(0x11e8, 0xfff8, ea_das8_read, gen_moveb_dt_ea, ea_adr16d8), + move_b_das_adr16(0x11e8, 0xfff8, ea_das8_read, gen_moveb_dt_dt, ea_adr16d8), - move_b_dais_adr16(0x11f0, 0xfff8, ea_dais8_read, gen_moveb_dt_ea, ea_adr16d8), + move_b_dais_adr16(0x11f0, 0xfff8, ea_dais8_read, gen_moveb_dt_dt, ea_adr16d8), - move_b_adr16_adr16(0x11f8, 0xffff, ea_adr16s8_read, gen_moveb_dt_ea, ea_adr16d8), + move_b_adr16_adr16(0x11f8, 0xffff, ea_adr16s8_read, gen_moveb_dt_dt, ea_adr16d8), - move_b_adr32_adr16(0x11f9, 0xffff, ea_adr32s8_read, gen_moveb_dt_ea, ea_adr16d8), + move_b_adr32_adr16(0x11f9, 0xffff, ea_adr32s8_read, gen_moveb_dt_dt, ea_adr16d8), - move_b_dpc_adr16(0x11fa, 0xffff, ea_dpc8_read, gen_moveb_dt_ea, ea_adr16d8), + move_b_dpc_adr16(0x11fa, 0xffff, ea_dpc8_read, gen_moveb_dt_dt, ea_adr16d8), - move_b_dpci_adr16(0x11fb, 0xffff, ea_dpci8_read, gen_moveb_dt_ea, ea_adr16d8), + move_b_dpci_adr16(0x11fb, 0xffff, ea_dpci8_read, gen_moveb_dt_dt, ea_adr16d8), - move_b_imm8_adr16(0x11fc, 0xffff, ea_imm8_read, gen_moveb_dt_ea, ea_adr16d8), + move_b_imm8_adr16(0x11fc, 0xffff, ea_imm8_read, gen_moveb_dt_dt, ea_adr16d8), - move_b_ds_adr32(0x13c0, 0xfff8, ea_adr32d8, gen_moveb_ds_ea, dbrr), + move_b_ds_adr32(0x13c0, 0xfff8, ea_adr32d8, gen_moveb_dy_dt, dbrr), - move_b_ais_adr32(0x13d0, 0xfff8, ea_ais8_read, gen_moveb_dt_ea, ea_adr32d8), + move_b_ais_adr32(0x13d0, 0xfff8, ea_ais8_read, gen_moveb_dt_dt, ea_adr32d8), - move_b_aips_adr32(0x13d8, 0xfff8, ea_aips8_read, gen_moveb_dt_ea, ea_adr32d8), + move_b_aips_adr32(0x13d8, 0xfff8, ea_aips8_read, gen_moveb_dt_dt, ea_adr32d8), - move_b_pais_adr32(0x13e0, 0xfff8, ea_pais8_read, gen_moveb_dt_ea, ea_adr32d8), + move_b_pais_adr32(0x13e0, 0xfff8, ea_pais8_read, gen_moveb_dt_dt, ea_adr32d8), - move_b_das_adr32(0x13e8, 0xfff8, ea_das8_read, gen_moveb_dt_ea, ea_adr32d8), + move_b_das_adr32(0x13e8, 0xfff8, ea_das8_read, gen_moveb_dt_dt, ea_adr32d8), - move_b_dais_adr32(0x13f0, 0xfff8, ea_dais8_read, gen_moveb_dt_ea, ea_adr32d8), + move_b_dais_adr32(0x13f0, 0xfff8, ea_dais8_read, gen_moveb_dt_dt, ea_adr32d8), - move_b_adr16_adr32(0x13f8, 0xffff, ea_adr16s8_read, gen_moveb_dt_ea, ea_adr32d8), + move_b_adr16_adr32(0x13f8, 0xffff, ea_adr16s8_read, gen_moveb_dt_dt, ea_adr32d8), - move_b_adr32_adr32(0x13f9, 0xffff, ea_adr32s8_read, gen_moveb_dt_ea, ea_adr32d8), + move_b_adr32_adr32(0x13f9, 0xffff, ea_adr32s8_read, gen_moveb_dt_dt, ea_adr32d8), - move_b_dpc_adr32(0x13fa, 0xffff, ea_dpc8_read, gen_moveb_dt_ea, ea_adr32d8), + move_b_dpc_adr32(0x13fa, 0xffff, ea_dpc8_read, gen_moveb_dt_dt, ea_adr32d8), - move_b_dpci_adr32(0x13fb, 0xffff, ea_dpci8_read, gen_moveb_dt_ea, ea_adr32d8), + move_b_dpci_adr32(0x13fb, 0xffff, ea_dpci8_read, gen_moveb_dt_dt, ea_adr32d8), - move_b_imm8_adr32(0x13fc, 0xffff, ea_imm8_read, gen_moveb_dt_ea, ea_adr32d8), + move_b_imm8_adr32(0x13fc, 0xffff, ea_imm8_read, gen_moveb_dt_dt, ea_adr32d8), - move_l_ds_dd(0x2000, 0xf1f8, gen_movel_ds_dd, dbrr, dbrr), + move_l_ds_dd(0x2000, 0xf1f8, gen_movel_dy_dx, dbrr, dbrr), - move_l_as_dd(0x2008, 0xf1f8, gen_movel_as_dd, dbrr, dbrr), + move_l_as_dd(0x2008, 0xf1f8, gen_movel_ay_dx, dbrr, dbrr), - move_l_ais_dd(0x2010, 0xf1f8, ea_ais32_read, dbrr, gen_movel_dt_dd), + move_l_ais_dd(0x2010, 0xf1f8, ea_ais32_read, dbrr, gen_movel_dt_dx), - move_l_aips_dd(0x2018, 0xf1f8, ea_aips32_read, dbrr, gen_movel_dt_dd), + move_l_aips_dd(0x2018, 0xf1f8, ea_aips32_read, dbrr, gen_movel_dt_dx), - move_l_pais_dd(0x2020, 0xf1f8, ea_pais32_read, dbrr, gen_movel_dt_dd), + move_l_pais_dd(0x2020, 0xf1f8, ea_pais32_read, dbrr, gen_movel_dt_dx), - move_l_das_dd(0x2028, 0xf1f8, ea_das32_read, dbrr, gen_movel_dt_dd), + move_l_das_dd(0x2028, 0xf1f8, ea_das32_read, dbrr, gen_movel_dt_dx), - move_l_dais_dd(0x2030, 0xf1f8, ea_dais32_read, dbrr, gen_movel_dt_dd), + move_l_dais_dd(0x2030, 0xf1f8, ea_dais32_read, dbrr, gen_movel_dt_dx), - move_l_adr16_dd(0x2038, 0xf1ff, ea_adr16s32_read, dbrr, gen_movel_dt_dd), + move_l_adr16_dd(0x2038, 0xf1ff, ea_adr16s32_read, dbrr, gen_movel_dt_dx), - move_l_adr32_dd(0x2039, 0xf1ff, ea_adr32s32_read, dbrr, gen_movel_dt_dd), + move_l_adr32_dd(0x2039, 0xf1ff, ea_adr32s32_read, dbrr, gen_movel_dt_dx), - move_l_dpc_dd(0x203a, 0xf1ff, ea_dpc32_read, dbrr, gen_movel_dt_dd), + move_l_dpc_dd(0x203a, 0xf1ff, ea_dpc32_read, dbrr, gen_movel_dt_dx), - move_l_dpci_dd(0x203b, 0xf1ff, ea_dpci32_read, dbrr, gen_movel_dt_dd), + move_l_dpci_dd(0x203b, 0xf1ff, ea_dpci32_read, dbrr, gen_movel_dt_dx), - move_l_imm32_dd(0x203c, 0xf1ff, ea_imm32_read, dbrr, gen_movel_dt_dd), + move_l_imm32_dd(0x203c, 0xf1ff, ea_imm32_read, dbrr, gen_movel_dt_dx), - movea_l_ds_ad(0x2040, 0xf1f8, gen_movel_ds_ad, dbrr, dbrr), + movea_l_ds_ad(0x2040, 0xf1f8, gen_movel_dy_ax, dbrr, dbrr), - movea_l_as_ad(0x2048, 0xf1f8, gen_movel_as_ad, dbrr, dbrr), + movea_l_as_ad(0x2048, 0xf1f8, gen_movel_ay_ax, dbrr, dbrr), - movea_l_ais_ad(0x2050, 0xf1f8, ea_ais32_read, dbrr, gen_movel_dt_ad), + movea_l_ais_ad(0x2050, 0xf1f8, ea_ais32_read, dbrr, gen_movel_dt_ax), - movea_l_aips_ad(0x2058, 0xf1f8, ea_aips32_read, dbrr, gen_movel_dt_ad), + movea_l_aips_ad(0x2058, 0xf1f8, ea_aips32_read, dbrr, gen_movel_dt_ax), - movea_l_pais_ad(0x2060, 0xf1f8, ea_pais32_read, dbrr, gen_movel_dt_ad), + movea_l_pais_ad(0x2060, 0xf1f8, ea_pais32_read, dbrr, gen_movel_dt_ax), - movea_l_das_ad(0x2068, 0xf1f8, ea_das32_read, dbrr, gen_movel_dt_ad), + movea_l_das_ad(0x2068, 0xf1f8, ea_das32_read, dbrr, gen_movel_dt_ax), - movea_l_dais_ad(0x2070, 0xf1f8, ea_dais32_read, dbrr, gen_movel_dt_ad), + movea_l_dais_ad(0x2070, 0xf1f8, ea_dais32_read, dbrr, gen_movel_dt_ax), - movea_l_adr16_ad(0x2078, 0xf1ff, ea_adr16s32_read, dbrr, gen_movel_dt_ad), + movea_l_adr16_ad(0x2078, 0xf1ff, ea_adr16s32_read, dbrr, gen_movel_dt_ax), - movea_l_adr32_ad(0x2079, 0xf1ff, ea_adr32s32_read, dbrr, gen_movel_dt_ad), + movea_l_adr32_ad(0x2079, 0xf1ff, ea_adr32s32_read, dbrr, gen_movel_dt_ax), - movea_l_dpc_ad(0x207a, 0xf1ff, ea_dpc32_read, dbrr, gen_movel_dt_ad), + movea_l_dpc_ad(0x207a, 0xf1ff, ea_dpc32_read, dbrr, gen_movel_dt_ax), - movea_l_dpci_ad(0x207b, 0xf1ff, ea_dpci32_read, dbrr, gen_movel_dt_ad), + movea_l_dpci_ad(0x207b, 0xf1ff, ea_dpci32_read, dbrr, gen_movel_dt_ax), - movea_l_imm32_ad(0x207c, 0xf1ff, ea_imm32_read, dbrr, gen_movel_dt_ad), + movea_l_imm32_ad(0x207c, 0xf1ff, ea_imm32_read, dbrr, gen_movel_dt_ax), - move_l_ds_aid(0x2080, 0xf1f8, ea_aid32, gen_movel_ds_ea, dbrr), + move_l_ds_aid(0x2080, 0xf1f8, ea_aid32, gen_movel_dy_dt, dbrr), - move_l_as_aid(0x2088, 0xf1f8, ea_as_dt, gen_movel_dt_ea, ea_aid32), + move_l_as_aid(0x2088, 0xf1f8, ea_as_dt, gen_movel_dt_dt, ea_aid32), - move_l_ais_aid(0x2090, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_aid32), + move_l_ais_aid(0x2090, 0xf1f8, ea_ais32_read, gen_movel_dt_dt, ea_aid32), - move_l_aips_aid(0x2098, 0xf1f8, ea_aips32_read, gen_movel_dt_ea, ea_aid32), + move_l_aips_aid(0x2098, 0xf1f8, ea_aips32_read, gen_movel_dt_dt, ea_aid32), - move_l_pais_aid(0x20a0, 0xf1f8, ea_pais32_read, gen_movel_dt_ea, ea_aid32), + move_l_pais_aid(0x20a0, 0xf1f8, ea_pais32_read, gen_movel_dt_dt, ea_aid32), - move_l_das_aid(0x20a8, 0xf1f8, ea_das32_read, gen_movel_dt_ea, ea_aid32), + move_l_das_aid(0x20a8, 0xf1f8, ea_das32_read, gen_movel_dt_dt, ea_aid32), - move_l_dais_aid(0x20b0, 0xf1f8, ea_dais32_read, gen_movel_dt_ea, ea_aid32), + move_l_dais_aid(0x20b0, 0xf1f8, ea_dais32_read, gen_movel_dt_dt, ea_aid32), - move_l_adr16_aid(0x20b8, 0xf1ff, ea_adr16s32_read, gen_movel_dt_ea, ea_aid32), + move_l_adr16_aid(0x20b8, 0xf1ff, ea_adr16s32_read, gen_movel_dt_dt, ea_aid32), - move_l_adr32_aid(0x20b9, 0xf1ff, ea_adr32s32_read, gen_movel_dt_ea, ea_aid32), + move_l_adr32_aid(0x20b9, 0xf1ff, ea_adr32s32_read, gen_movel_dt_dt, ea_aid32), - move_l_dpc_aid(0x20ba, 0xf1ff, ea_dpc32_read, gen_movel_dt_ea, ea_aid32), + move_l_dpc_aid(0x20ba, 0xf1ff, ea_dpc32_read, gen_movel_dt_dt, ea_aid32), - move_l_dpci_aid(0x20bb, 0xf1ff, ea_dpci32_read, gen_movel_dt_ea, ea_aid32), + move_l_dpci_aid(0x20bb, 0xf1ff, ea_dpci32_read, gen_movel_dt_dt, ea_aid32), - move_l_imm32_aid(0x20bc, 0xf1ff, ea_imm32_read, gen_movel_dt_ea, ea_aid32), + move_l_imm32_aid(0x20bc, 0xf1ff, ea_imm32_read, gen_movel_dt_dt, ea_aid32), - move_l_ds_aipd(0x20c0, 0xf1f8, ea_aipd32, gen_movel_ds_ea, dbrr), + move_l_ds_aipd(0x20c0, 0xf1f8, ea_aipd32, gen_movel_dy_dt, dbrr), - move_l_as_aipd(0x20c8, 0xf1f8, ea_as_dt, gen_movel_dt_ea, ea_aipd32), + move_l_as_aipd(0x20c8, 0xf1f8, ea_as_dt, gen_movel_dt_dt, ea_aipd32), - move_l_ais_aipd(0x20d0, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_aipd32), + move_l_ais_aipd(0x20d0, 0xf1f8, ea_ais32_read, gen_movel_dt_dt, ea_aipd32), - move_l_aips_aipd(0x20d8, 0xf1f8, ea_aips32_read, gen_movel_dt_ea, ea_aipd32), + move_l_aips_aipd(0x20d8, 0xf1f8, ea_aips32_read, gen_movel_dt_dt, ea_aipd32), - move_l_pais_aipd(0x20e0, 0xf1f8, ea_pais32_read, gen_movel_dt_ea, ea_aipd32), + move_l_pais_aipd(0x20e0, 0xf1f8, ea_pais32_read, gen_movel_dt_dt, ea_aipd32), - move_l_das_aipd(0x20e8, 0xf1f8, ea_das32_read, gen_movel_dt_ea, ea_aipd32), + move_l_das_aipd(0x20e8, 0xf1f8, ea_das32_read, gen_movel_dt_dt, ea_aipd32), - move_l_dais_aipd(0x20f0, 0xf1f8, ea_dais32_read, gen_movel_dt_ea, ea_aipd32), + move_l_dais_aipd(0x20f0, 0xf1f8, ea_dais32_read, gen_movel_dt_dt, ea_aipd32), - move_l_adr16_aipd(0x20f8, 0xf1ff, ea_adr16s32_read, gen_movel_dt_ea, ea_aipd32), + move_l_adr16_aipd(0x20f8, 0xf1ff, ea_adr16s32_read, gen_movel_dt_dt, ea_aipd32), - move_l_adr32_aipd(0x20f9, 0xf1ff, ea_adr32s32_read, gen_movel_dt_ea, ea_aipd32), + move_l_adr32_aipd(0x20f9, 0xf1ff, ea_adr32s32_read, gen_movel_dt_dt, ea_aipd32), - move_l_dpc_aipd(0x20fa, 0xf1ff, ea_dpc32_read, gen_movel_dt_ea, ea_aipd32), + move_l_dpc_aipd(0x20fa, 0xf1ff, ea_dpc32_read, gen_movel_dt_dt, ea_aipd32), - move_l_dpci_aipd(0x20fb, 0xf1ff, ea_dpci32_read, gen_movel_dt_ea, ea_aipd32), + move_l_dpci_aipd(0x20fb, 0xf1ff, ea_dpci32_read, gen_movel_dt_dt, ea_aipd32), - move_l_imm32_aipd(0x20fc, 0xf1ff, ea_imm32_read, gen_movel_dt_ea, ea_aipd32), + move_l_imm32_aipd(0x20fc, 0xf1ff, ea_imm32_read, gen_movel_dt_dt, ea_aipd32), - move_l_ds_paid(0x2100, 0xf1f8, ea_paid32, gen_movel_ds_ea, dbrr), + move_l_ds_paid(0x2100, 0xf1f8, ea_paid32, gen_movel_dy_dt, dbrr), - move_l_as_paid(0x2108, 0xf1f8, ea_as_dt, gen_movel_dt_ea, ea_paid32), + move_l_as_paid(0x2108, 0xf1f8, ea_as_dt, gen_movel_dt_dt, ea_paid32), - move_l_ais_paid(0x2110, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_paid32), + move_l_ais_paid(0x2110, 0xf1f8, ea_ais32_read, gen_movel_dt_dt, ea_paid32), - move_l_aips_paid(0x2118, 0xf1f8, ea_aips32_read, gen_movel_dt_ea, ea_paid32), + move_l_aips_paid(0x2118, 0xf1f8, ea_aips32_read, gen_movel_dt_dt, ea_paid32), - move_l_pais_paid(0x2120, 0xf1f8, ea_pais32_read, gen_movel_dt_ea, ea_paid32), + move_l_pais_paid(0x2120, 0xf1f8, ea_pais32_read, gen_movel_dt_dt, ea_paid32), - move_l_das_paid(0x2128, 0xf1f8, ea_das32_read, gen_movel_dt_ea, ea_paid32), + move_l_das_paid(0x2128, 0xf1f8, ea_das32_read, gen_movel_dt_dt, ea_paid32), - move_l_dais_paid(0x2130, 0xf1f8, ea_dais32_read, gen_movel_dt_ea, ea_paid32), + move_l_dais_paid(0x2130, 0xf1f8, ea_dais32_read, gen_movel_dt_dt, ea_paid32), - move_l_adr16_paid(0x2138, 0xf1ff, ea_adr16s32_read, gen_movel_dt_ea, ea_paid32), + move_l_adr16_paid(0x2138, 0xf1ff, ea_adr16s32_read, gen_movel_dt_dt, ea_paid32), - move_l_adr32_paid(0x2139, 0xf1ff, ea_adr32s32_read, gen_movel_dt_ea, ea_paid32), + move_l_adr32_paid(0x2139, 0xf1ff, ea_adr32s32_read, gen_movel_dt_dt, ea_paid32), - move_l_dpc_paid(0x213a, 0xf1ff, ea_dpc32_read, gen_movel_dt_ea, ea_paid32), + move_l_dpc_paid(0x213a, 0xf1ff, ea_dpc32_read, gen_movel_dt_dt, ea_paid32), - move_l_dpci_paid(0x213b, 0xf1ff, ea_dpci32_read, gen_movel_dt_ea, ea_paid32), + move_l_dpci_paid(0x213b, 0xf1ff, ea_dpci32_read, gen_movel_dt_dt, ea_paid32), - move_l_imm32_paid(0x213c, 0xf1ff, ea_imm32_read, gen_movel_dt_ea, ea_paid32), + move_l_imm32_paid(0x213c, 0xf1ff, ea_imm32_read, gen_movel_dt_dt, ea_paid32), - move_l_ds_dad(0x2140, 0xf1f8, ea_dad32, gen_movel_ds_ea, dbrr), + move_l_ds_dad(0x2140, 0xf1f8, ea_dad32, gen_movel_dy_dt, dbrr), - move_l_as_dad(0x2148, 0xf1f8, ea_as_dt, gen_movel_dt_ea, ea_dad32), + move_l_as_dad(0x2148, 0xf1f8, ea_as_dt, gen_movel_dt_dt, ea_dad32), - move_l_ais_dad(0x2150, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_dad32), + move_l_ais_dad(0x2150, 0xf1f8, ea_ais32_read, gen_movel_dt_dt, ea_dad32), - move_l_aips_dad(0x2158, 0xf1f8, ea_aips32_read, gen_movel_dt_ea, ea_dad32), + move_l_aips_dad(0x2158, 0xf1f8, ea_aips32_read, gen_movel_dt_dt, ea_dad32), - move_l_pais_dad(0x2160, 0xf1f8, ea_pais32_read, gen_movel_dt_ea, ea_dad32), + move_l_pais_dad(0x2160, 0xf1f8, ea_pais32_read, gen_movel_dt_dt, ea_dad32), - move_l_das_dad(0x2168, 0xf1f8, ea_das32_read, gen_movel_dt_ea, ea_dad32), + move_l_das_dad(0x2168, 0xf1f8, ea_das32_read, gen_movel_dt_dt, ea_dad32), - move_l_dais_dad(0x2170, 0xf1f8, ea_dais32_read, gen_movel_dt_ea, ea_dad32), + move_l_dais_dad(0x2170, 0xf1f8, ea_dais32_read, gen_movel_dt_dt, ea_dad32), - move_l_adr16_dad(0x2178, 0xf1ff, ea_adr16s32_read, gen_movel_dt_ea, ea_dad32), + move_l_adr16_dad(0x2178, 0xf1ff, ea_adr16s32_read, gen_movel_dt_dt, ea_dad32), - move_l_adr32_dad(0x2179, 0xf1ff, ea_adr32s32_read, gen_movel_dt_ea, ea_dad32), + move_l_adr32_dad(0x2179, 0xf1ff, ea_adr32s32_read, gen_movel_dt_dt, ea_dad32), - move_l_dpc_dad(0x217a, 0xf1ff, ea_dpc32_read, gen_movel_dt_ea, ea_dad32), + move_l_dpc_dad(0x217a, 0xf1ff, ea_dpc32_read, gen_movel_dt_dt, ea_dad32), - move_l_dpci_dad(0x217b, 0xf1ff, ea_dpci32_read, gen_movel_dt_ea, ea_dad32), + move_l_dpci_dad(0x217b, 0xf1ff, ea_dpci32_read, gen_movel_dt_dt, ea_dad32), - move_l_imm32_dad(0x217c, 0xf1ff, ea_imm32_read, gen_movel_dt_ea, ea_dad32), + move_l_imm32_dad(0x217c, 0xf1ff, ea_imm32_read, gen_movel_dt_dt, ea_dad32), - move_l_ds_daid(0x2180, 0xf1f8, ea_daid32, gen_movel_ds_ea, dbrr), + move_l_ds_daid(0x2180, 0xf1f8, ea_daid32, gen_movel_dy_dt, dbrr), - move_l_as_daid(0x2188, 0xf1f8, ea_as_dt, gen_movel_dt_ea, ea_daid32), + move_l_as_daid(0x2188, 0xf1f8, ea_as_dt, gen_movel_dt_dt, ea_daid32), - move_l_ais_daid(0x2190, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_daid32), + move_l_ais_daid(0x2190, 0xf1f8, ea_ais32_read, gen_movel_dt_dt, ea_daid32), - move_l_aips_daid(0x2198, 0xf1f8, ea_aips32_read, gen_movel_dt_ea, ea_daid32), + move_l_aips_daid(0x2198, 0xf1f8, ea_aips32_read, gen_movel_dt_dt, ea_daid32), - move_l_pais_daid(0x21a0, 0xf1f8, ea_pais32_read, gen_movel_dt_ea, ea_daid32), + move_l_pais_daid(0x21a0, 0xf1f8, ea_pais32_read, gen_movel_dt_dt, ea_daid32), - move_l_das_daid(0x21a8, 0xf1f8, ea_das32_read, gen_movel_dt_ea, ea_daid32), + move_l_das_daid(0x21a8, 0xf1f8, ea_das32_read, gen_movel_dt_dt, ea_daid32), - move_l_dais_daid(0x21b0, 0xf1f8, ea_dais32_read, gen_movel_dt_ea, ea_daid32), + move_l_dais_daid(0x21b0, 0xf1f8, ea_dais32_read, gen_movel_dt_dt, ea_daid32), - move_l_adr16_daid(0x21b8, 0xf1ff, ea_adr16s32_read, gen_movel_dt_ea, ea_daid32), + move_l_adr16_daid(0x21b8, 0xf1ff, ea_adr16s32_read, gen_movel_dt_dt, ea_daid32), - move_l_adr32_daid(0x21b9, 0xf1ff, ea_adr32s32_read, gen_movel_dt_ea, ea_daid32), + move_l_adr32_daid(0x21b9, 0xf1ff, ea_adr32s32_read, gen_movel_dt_dt, ea_daid32), - move_l_dpc_daid(0x21ba, 0xf1ff, ea_dpc32_read, gen_movel_dt_ea, ea_daid32), + move_l_dpc_daid(0x21ba, 0xf1ff, ea_dpc32_read, gen_movel_dt_dt, ea_daid32), - move_l_dpci_daid(0x21bb, 0xf1ff, ea_dpci32_read, gen_movel_dt_ea, ea_daid32), + move_l_dpci_daid(0x21bb, 0xf1ff, ea_dpci32_read, gen_movel_dt_dt, ea_daid32), - move_l_imm32_daid(0x21bc, 0xf1ff, ea_imm32_read, gen_movel_dt_ea, ea_daid32), + move_l_imm32_daid(0x21bc, 0xf1ff, ea_imm32_read, gen_movel_dt_dt, ea_daid32), - move_l_ds_adr16(0x21c0, 0xfff8, ea_adr16d32, gen_movel_ds_ea, dbrr), + move_l_ds_adr16(0x21c0, 0xfff8, ea_adr16d32, gen_movel_dy_dt, dbrr), - move_l_as_adr16(0x21c8, 0xfff8, ea_as_dt, gen_movel_dt_ea, ea_adr16d32), + move_l_as_adr16(0x21c8, 0xfff8, ea_as_dt, gen_movel_dt_dt, ea_adr16d32), - move_l_ais_adr16(0x21d0, 0xfff8, ea_ais32_read, gen_movel_dt_ea, ea_adr16d32), + move_l_ais_adr16(0x21d0, 0xfff8, ea_ais32_read, gen_movel_dt_dt, ea_adr16d32), - move_l_aips_adr16(0x21d8, 0xfff8, ea_aips32_read, gen_movel_dt_ea, ea_adr16d32), + move_l_aips_adr16(0x21d8, 0xfff8, ea_aips32_read, gen_movel_dt_dt, ea_adr16d32), - move_l_pais_adr16(0x21e0, 0xfff8, ea_pais32_read, gen_movel_dt_ea, ea_adr16d32), + move_l_pais_adr16(0x21e0, 0xfff8, ea_pais32_read, gen_movel_dt_dt, ea_adr16d32), - move_l_das_adr16(0x21e8, 0xfff8, ea_das32_read, gen_movel_dt_ea, ea_adr16d32), + move_l_das_adr16(0x21e8, 0xfff8, ea_das32_read, gen_movel_dt_dt, ea_adr16d32), - move_l_dais_adr16(0x21f0, 0xfff8, ea_dais32_read, gen_movel_dt_ea, ea_adr16d32), + move_l_dais_adr16(0x21f0, 0xfff8, ea_dais32_read, gen_movel_dt_dt, ea_adr16d32), - move_l_adr16_adr16(0x21f8, 0xffff, ea_adr16s32_read, gen_movel_dt_ea, ea_adr16d32), + move_l_adr16_adr16(0x21f8, 0xffff, ea_adr16s32_read, gen_movel_dt_dt, ea_adr16d32), - move_l_adr32_adr16(0x21f9, 0xffff, ea_adr32s32_read, gen_movel_dt_ea, ea_adr16d32), + move_l_adr32_adr16(0x21f9, 0xffff, ea_adr32s32_read, gen_movel_dt_dt, ea_adr16d32), - move_l_dpc_adr16(0x21fa, 0xffff, ea_dpc32_read, gen_movel_dt_ea, ea_adr16d32), + move_l_dpc_adr16(0x21fa, 0xffff, ea_dpc32_read, gen_movel_dt_dt, ea_adr16d32), - move_l_dpci_adr16(0x21fb, 0xffff, ea_dpci32_read, gen_movel_dt_ea, ea_adr16d32), + move_l_dpci_adr16(0x21fb, 0xffff, ea_dpci32_read, gen_movel_dt_dt, ea_adr16d32), - move_l_imm32_adr16(0x21fc, 0xffff, ea_imm32_read, gen_movel_dt_ea, ea_adr16d32), + move_l_imm32_adr16(0x21fc, 0xffff, ea_imm32_read, gen_movel_dt_dt, ea_adr16d32), - move_l_ds_adr32(0x23c0, 0xfff8, ea_adr32d32, gen_movel_ds_ea, dbrr), + move_l_ds_adr32(0x23c0, 0xfff8, ea_adr32d32, gen_movel_dy_dt, dbrr), - move_l_as_adr32(0x23c8, 0xfff8, ea_as_dt, gen_movel_dt_ea, ea_adr32d32), + move_l_as_adr32(0x23c8, 0xfff8, ea_as_dt, gen_movel_dt_dt, ea_adr32d32), - move_l_ais_adr32(0x23d0, 0xfff8, ea_ais32_read, gen_movel_dt_ea, ea_adr32d32), + move_l_ais_adr32(0x23d0, 0xfff8, ea_ais32_read, gen_movel_dt_dt, ea_adr32d32), - move_l_aips_adr32(0x23d8, 0xfff8, ea_aips32_read, gen_movel_dt_ea, ea_adr32d32), + move_l_aips_adr32(0x23d8, 0xfff8, ea_aips32_read, gen_movel_dt_dt, ea_adr32d32), - move_l_pais_adr32(0x23e0, 0xfff8, ea_pais32_read, gen_movel_dt_ea, ea_adr32d32), + move_l_pais_adr32(0x23e0, 0xfff8, ea_pais32_read, gen_movel_dt_dt, ea_adr32d32), - move_l_das_adr32(0x23e8, 0xfff8, ea_das32_read, gen_movel_dt_ea, ea_adr32d32), + move_l_das_adr32(0x23e8, 0xfff8, ea_das32_read, gen_movel_dt_dt, ea_adr32d32), - move_l_dais_adr32(0x23f0, 0xfff8, ea_dais32_read, gen_movel_dt_ea, ea_adr32d32), + move_l_dais_adr32(0x23f0, 0xfff8, ea_dais32_read, gen_movel_dt_dt, ea_adr32d32), - move_l_adr16_adr32(0x23f8, 0xffff, ea_adr16s32_read, gen_movel_dt_ea, ea_adr32d32), + move_l_adr16_adr32(0x23f8, 0xffff, ea_adr16s32_read, gen_movel_dt_dt, ea_adr32d32), - move_l_adr32_adr32(0x23f9, 0xffff, ea_adr32s32_read, gen_movel_dt_ea, ea_adr32d32), + move_l_adr32_adr32(0x23f9, 0xffff, ea_adr32s32_read, gen_movel_dt_dt, ea_adr32d32), - move_l_dpc_adr32(0x23fa, 0xffff, ea_dpc32_read, gen_movel_dt_ea, ea_adr32d32), + move_l_dpc_adr32(0x23fa, 0xffff, ea_dpc32_read, gen_movel_dt_dt, ea_adr32d32), - move_l_dpci_adr32(0x23fb, 0xffff, ea_dpci32_read, gen_movel_dt_ea, ea_adr32d32), + move_l_dpci_adr32(0x23fb, 0xffff, ea_dpci32_read, gen_movel_dt_dt, ea_adr32d32), - move_l_imm32_adr32(0x23fc, 0xffff, ea_imm32_read, gen_movel_dt_ea, ea_adr32d32), + move_l_imm32_adr32(0x23fc, 0xffff, ea_imm32_read, gen_movel_dt_dt, ea_adr32d32), - move_w_ds_dd(0x3000, 0xf1f8, gen_movew_ds_dd, dbrr, dbrr), + move_w_ds_dd(0x3000, 0xf1f8, gen_movew_dy_dx, dbrr, dbrr), - move_w_as_dd(0x3008, 0xf1f8, gen_movew_as_dd, dbrr, dbrr), + move_w_as_dd(0x3008, 0xf1f8, gen_movew_ay_dx, dbrr, dbrr), - move_w_ais_dd(0x3010, 0xf1f8, ea_ais16_read, dbrr, gen_movew_dt_dd), + move_w_ais_dd(0x3010, 0xf1f8, ea_ais16_read, dbrr, gen_movew_dt_dx), - move_w_aips_dd(0x3018, 0xf1f8, ea_aips16_read, dbrr, gen_movew_dt_dd), + move_w_aips_dd(0x3018, 0xf1f8, ea_aips16_read, dbrr, gen_movew_dt_dx), - move_w_pais_dd(0x3020, 0xf1f8, ea_pais16_read, dbrr, gen_movew_dt_dd), + move_w_pais_dd(0x3020, 0xf1f8, ea_pais16_read, dbrr, gen_movew_dt_dx), - move_w_das_dd(0x3028, 0xf1f8, ea_das16_read, dbrr, gen_movew_dt_dd), + move_w_das_dd(0x3028, 0xf1f8, ea_das16_read, dbrr, gen_movew_dt_dx), - move_w_dais_dd(0x3030, 0xf1f8, ea_dais16_read, dbrr, gen_movew_dt_dd), + move_w_dais_dd(0x3030, 0xf1f8, ea_dais16_read, dbrr, gen_movew_dt_dx), - move_w_adr16_dd(0x3038, 0xf1ff, ea_adr16s16_read, dbrr, gen_movew_dt_dd), + move_w_adr16_dd(0x3038, 0xf1ff, ea_adr16s16_read, dbrr, gen_movew_dt_dx), - move_w_adr32_dd(0x3039, 0xf1ff, ea_adr32s16_read, dbrr, gen_movew_dt_dd), + move_w_adr32_dd(0x3039, 0xf1ff, ea_adr32s16_read, dbrr, gen_movew_dt_dx), - move_w_dpc_dd(0x303a, 0xf1ff, ea_dpc16_read, dbrr, gen_movew_dt_dd), + move_w_dpc_dd(0x303a, 0xf1ff, ea_dpc16_read, dbrr, gen_movew_dt_dx), - move_w_dpci_dd(0x303b, 0xf1ff, ea_dpci16_read, dbrr, gen_movew_dt_dd), + move_w_dpci_dd(0x303b, 0xf1ff, ea_dpci16_read, dbrr, gen_movew_dt_dx), - move_w_imm16_dd(0x303c, 0xf1ff, ea_imm16_read, dbrr, gen_movew_dt_dd), + move_w_imm16_dd(0x303c, 0xf1ff, ea_imm16_read, dbrr, gen_movew_dt_dx), - movea_w_ds_ad(0x3040, 0xf1f8, gen_movew_ds_ad, dbrr, dbrr), + movea_w_ds_ad(0x3040, 0xf1f8, gen_movew_dy_ax, dbrr, dbrr), - movea_w_as_ad(0x3048, 0xf1f8, gen_movew_as_ad, dbrr, dbrr), + movea_w_as_ad(0x3048, 0xf1f8, gen_movew_ay_ax, dbrr, dbrr), - movea_w_ais_ad(0x3050, 0xf1f8, ea_ais16_read, dbrr, gen_movew_dt_ad), + movea_w_ais_ad(0x3050, 0xf1f8, ea_ais16_read, dbrr, gen_movew_dt_ax), - movea_w_aips_ad(0x3058, 0xf1f8, ea_aips16_read, dbrr, gen_movew_dt_ad), + movea_w_aips_ad(0x3058, 0xf1f8, ea_aips16_read, dbrr, gen_movew_dt_ax), - movea_w_pais_ad(0x3060, 0xf1f8, ea_pais16_read, dbrr, gen_movew_dt_ad), + movea_w_pais_ad(0x3060, 0xf1f8, ea_pais16_read, dbrr, gen_movew_dt_ax), - movea_w_das_ad(0x3068, 0xf1f8, ea_das16_read, dbrr, gen_movew_dt_ad), + movea_w_das_ad(0x3068, 0xf1f8, ea_das16_read, dbrr, gen_movew_dt_ax), - movea_w_dais_ad(0x3070, 0xf1f8, ea_dais16_read, dbrr, gen_movew_dt_ad), + movea_w_dais_ad(0x3070, 0xf1f8, ea_dais16_read, dbrr, gen_movew_dt_ax), - movea_w_adr16_ad(0x3078, 0xf1ff, ea_adr16s16_read, dbrr, gen_movew_dt_ad), + movea_w_adr16_ad(0x3078, 0xf1ff, ea_adr16s16_read, dbrr, gen_movew_dt_ax), - movea_w_adr32_ad(0x3079, 0xf1ff, ea_adr32s16_read, dbrr, gen_movew_dt_ad), + movea_w_adr32_ad(0x3079, 0xf1ff, ea_adr32s16_read, dbrr, gen_movew_dt_ax), - movea_w_dpc_ad(0x307a, 0xf1ff, ea_dpc16_read, dbrr, gen_movew_dt_ad), + movea_w_dpc_ad(0x307a, 0xf1ff, ea_dpc16_read, dbrr, gen_movew_dt_ax), - movea_w_dpci_ad(0x307b, 0xf1ff, ea_dpci16_read, dbrr, gen_movew_dt_ad), + movea_w_dpci_ad(0x307b, 0xf1ff, ea_dpci16_read, dbrr, gen_movew_dt_ax), - movea_w_imm16_ad(0x307c, 0xf1ff, ea_imm16_read, dbrr, gen_movew_dt_ad), + movea_w_imm16_ad(0x307c, 0xf1ff, ea_imm16_read, dbrr, gen_movew_dt_ax), - move_w_ds_aid(0x3080, 0xf1f8, ea_aid16, gen_movew_ds_ea, dbrr), + move_w_ds_aid(0x3080, 0xf1f8, ea_aid16, gen_movew_dy_dt, dbrr), - move_w_as_aid(0x3088, 0xf1f8, ea_as_dt, gen_movew_dt_ea, ea_aid16), + move_w_as_aid(0x3088, 0xf1f8, ea_as_dt, gen_movew_dt_dt, ea_aid16), - move_w_ais_aid(0x3090, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_aid16), + move_w_ais_aid(0x3090, 0xf1f8, ea_ais16_read, gen_movew_dt_dt, ea_aid16), - move_w_aips_aid(0x3098, 0xf1f8, ea_aips16_read, gen_movew_dt_ea, ea_aid16), + move_w_aips_aid(0x3098, 0xf1f8, ea_aips16_read, gen_movew_dt_dt, ea_aid16), - move_w_pais_aid(0x30a0, 0xf1f8, ea_pais16_read, gen_movew_dt_ea, ea_aid16), + move_w_pais_aid(0x30a0, 0xf1f8, ea_pais16_read, gen_movew_dt_dt, ea_aid16), - move_w_das_aid(0x30a8, 0xf1f8, ea_das16_read, gen_movew_dt_ea, ea_aid16), + move_w_das_aid(0x30a8, 0xf1f8, ea_das16_read, gen_movew_dt_dt, ea_aid16), - move_w_dais_aid(0x30b0, 0xf1f8, ea_dais16_read, gen_movew_dt_ea, ea_aid16), + move_w_dais_aid(0x30b0, 0xf1f8, ea_dais16_read, gen_movew_dt_dt, ea_aid16), - move_w_adr16_aid(0x30b8, 0xf1ff, ea_adr16s16_read, gen_movew_dt_ea, ea_aid16), + move_w_adr16_aid(0x30b8, 0xf1ff, ea_adr16s16_read, gen_movew_dt_dt, ea_aid16), - move_w_adr32_aid(0x30b9, 0xf1ff, ea_adr32s16_read, gen_movew_dt_ea, ea_aid16), + move_w_adr32_aid(0x30b9, 0xf1ff, ea_adr32s16_read, gen_movew_dt_dt, ea_aid16), - move_w_dpc_aid(0x30ba, 0xf1ff, ea_dpc16_read, gen_movew_dt_ea, ea_aid16), + move_w_dpc_aid(0x30ba, 0xf1ff, ea_dpc16_read, gen_movew_dt_dt, ea_aid16), - move_w_dpci_aid(0x30bb, 0xf1ff, ea_dpci16_read, gen_movew_dt_ea, ea_aid16), + move_w_dpci_aid(0x30bb, 0xf1ff, ea_dpci16_read, gen_movew_dt_dt, ea_aid16), - move_w_imm16_aid(0x30bc, 0xf1ff, ea_imm16_read, gen_movew_dt_ea, ea_aid16), + move_w_imm16_aid(0x30bc, 0xf1ff, ea_imm16_read, gen_movew_dt_dt, ea_aid16), - move_w_ds_aipd(0x30c0, 0xf1f8, ea_aipd16, gen_movew_ds_ea, dbrr), + move_w_ds_aipd(0x30c0, 0xf1f8, ea_aipd16, gen_movew_dy_dt, dbrr), - move_w_as_aipd(0x30c8, 0xf1f8, ea_as_dt, gen_movew_dt_ea, ea_aipd16), + move_w_as_aipd(0x30c8, 0xf1f8, ea_as_dt, gen_movew_dt_dt, ea_aipd16), - move_w_ais_aipd(0x30d0, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_aipd16), + move_w_ais_aipd(0x30d0, 0xf1f8, ea_ais16_read, gen_movew_dt_dt, ea_aipd16), - move_w_aips_aipd(0x30d8, 0xf1f8, ea_aips16_read, gen_movew_dt_ea, ea_aipd16), + move_w_aips_aipd(0x30d8, 0xf1f8, ea_aips16_read, gen_movew_dt_dt, ea_aipd16), - move_w_pais_aipd(0x30e0, 0xf1f8, ea_pais16_read, gen_movew_dt_ea, ea_aipd16), + move_w_pais_aipd(0x30e0, 0xf1f8, ea_pais16_read, gen_movew_dt_dt, ea_aipd16), - move_w_das_aipd(0x30e8, 0xf1f8, ea_das16_read, gen_movew_dt_ea, ea_aipd16), + move_w_das_aipd(0x30e8, 0xf1f8, ea_das16_read, gen_movew_dt_dt, ea_aipd16), - move_w_dais_aipd(0x30f0, 0xf1f8, ea_dais16_read, gen_movew_dt_ea, ea_aipd16), + move_w_dais_aipd(0x30f0, 0xf1f8, ea_dais16_read, gen_movew_dt_dt, ea_aipd16), - move_w_adr16_aipd(0x30f8, 0xf1ff, ea_adr16s16_read, gen_movew_dt_ea, ea_aipd16), + move_w_adr16_aipd(0x30f8, 0xf1ff, ea_adr16s16_read, gen_movew_dt_dt, ea_aipd16), - move_w_adr32_aipd(0x30f9, 0xf1ff, ea_adr32s16_read, gen_movew_dt_ea, ea_aipd16), + move_w_adr32_aipd(0x30f9, 0xf1ff, ea_adr32s16_read, gen_movew_dt_dt, ea_aipd16), - move_w_dpc_aipd(0x30fa, 0xf1ff, ea_dpc16_read, gen_movew_dt_ea, ea_aipd16), + move_w_dpc_aipd(0x30fa, 0xf1ff, ea_dpc16_read, gen_movew_dt_dt, ea_aipd16), - move_w_dpci_aipd(0x30fb, 0xf1ff, ea_dpci16_read, gen_movew_dt_ea, ea_aipd16), + move_w_dpci_aipd(0x30fb, 0xf1ff, ea_dpci16_read, gen_movew_dt_dt, ea_aipd16), - move_w_imm16_aipd(0x30fc, 0xf1ff, ea_imm16_read, gen_movew_dt_ea, ea_aipd16), + move_w_imm16_aipd(0x30fc, 0xf1ff, ea_imm16_read, gen_movew_dt_dt, ea_aipd16), - move_w_ds_paid(0x3100, 0xf1f8, ea_paid16, gen_movew_ds_ea, dbrr), + move_w_ds_paid(0x3100, 0xf1f8, ea_paid16, gen_movew_dy_dt, dbrr), - move_w_as_paid(0x3108, 0xf1f8, ea_as_dt, gen_movew_dt_ea, ea_paid16), + move_w_as_paid(0x3108, 0xf1f8, ea_as_dt, gen_movew_dt_dt, ea_paid16), - move_w_ais_paid(0x3110, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_paid16), + move_w_ais_paid(0x3110, 0xf1f8, ea_ais16_read, gen_movew_dt_dt, ea_paid16), - move_w_aips_paid(0x3118, 0xf1f8, ea_aips16_read, gen_movew_dt_ea, ea_paid16), + move_w_aips_paid(0x3118, 0xf1f8, ea_aips16_read, gen_movew_dt_dt, ea_paid16), - move_w_pais_paid(0x3120, 0xf1f8, ea_pais16_read, gen_movew_dt_ea, ea_paid16), + move_w_pais_paid(0x3120, 0xf1f8, ea_pais16_read, gen_movew_dt_dt, ea_paid16), - move_w_das_paid(0x3128, 0xf1f8, ea_das16_read, gen_movew_dt_ea, ea_paid16), + move_w_das_paid(0x3128, 0xf1f8, ea_das16_read, gen_movew_dt_dt, ea_paid16), - move_w_dais_paid(0x3130, 0xf1f8, ea_dais16_read, gen_movew_dt_ea, ea_paid16), + move_w_dais_paid(0x3130, 0xf1f8, ea_dais16_read, gen_movew_dt_dt, ea_paid16), - move_w_adr16_paid(0x3138, 0xf1ff, ea_adr16s16_read, gen_movew_dt_ea, ea_paid16), + move_w_adr16_paid(0x3138, 0xf1ff, ea_adr16s16_read, gen_movew_dt_dt, ea_paid16), - move_w_adr32_paid(0x3139, 0xf1ff, ea_adr32s16_read, gen_movew_dt_ea, ea_paid16), + move_w_adr32_paid(0x3139, 0xf1ff, ea_adr32s16_read, gen_movew_dt_dt, ea_paid16), - move_w_dpc_paid(0x313a, 0xf1ff, ea_dpc16_read, gen_movew_dt_ea, ea_paid16), + move_w_dpc_paid(0x313a, 0xf1ff, ea_dpc16_read, gen_movew_dt_dt, ea_paid16), - move_w_dpci_paid(0x313b, 0xf1ff, ea_dpci16_read, gen_movew_dt_ea, ea_paid16), + move_w_dpci_paid(0x313b, 0xf1ff, ea_dpci16_read, gen_movew_dt_dt, ea_paid16), - move_w_imm16_paid(0x313c, 0xf1ff, ea_imm16_read, gen_movew_dt_ea, ea_paid16), + move_w_imm16_paid(0x313c, 0xf1ff, ea_imm16_read, gen_movew_dt_dt, ea_paid16), - move_w_ds_dad(0x3140, 0xf1f8, ea_dad16, gen_movew_ds_ea, dbrr), + move_w_ds_dad(0x3140, 0xf1f8, ea_dad16, gen_movew_dy_dt, dbrr), - move_w_as_dad(0x3148, 0xf1f8, ea_as_dt, gen_movew_dt_ea, ea_dad16), + move_w_as_dad(0x3148, 0xf1f8, ea_as_dt, gen_movew_dt_dt, ea_dad16), - move_w_ais_dad(0x3150, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_dad16), + move_w_ais_dad(0x3150, 0xf1f8, ea_ais16_read, gen_movew_dt_dt, ea_dad16), - move_w_aips_dad(0x3158, 0xf1f8, ea_aips16_read, gen_movew_dt_ea, ea_dad16), + move_w_aips_dad(0x3158, 0xf1f8, ea_aips16_read, gen_movew_dt_dt, ea_dad16), - move_w_pais_dad(0x3160, 0xf1f8, ea_pais16_read, gen_movew_dt_ea, ea_dad16), + move_w_pais_dad(0x3160, 0xf1f8, ea_pais16_read, gen_movew_dt_dt, ea_dad16), - move_w_das_dad(0x3168, 0xf1f8, ea_das16_read, gen_movew_dt_ea, ea_dad16), + move_w_das_dad(0x3168, 0xf1f8, ea_das16_read, gen_movew_dt_dt, ea_dad16), - move_w_dais_dad(0x3170, 0xf1f8, ea_dais16_read, gen_movew_dt_ea, ea_dad16), + move_w_dais_dad(0x3170, 0xf1f8, ea_dais16_read, gen_movew_dt_dt, ea_dad16), - move_w_adr16_dad(0x3178, 0xf1ff, ea_adr16s16_read, gen_movew_dt_ea, ea_dad16), + move_w_adr16_dad(0x3178, 0xf1ff, ea_adr16s16_read, gen_movew_dt_dt, ea_dad16), - move_w_adr32_dad(0x3179, 0xf1ff, ea_adr32s16_read, gen_movew_dt_ea, ea_dad16), + move_w_adr32_dad(0x3179, 0xf1ff, ea_adr32s16_read, gen_movew_dt_dt, ea_dad16), - move_w_dpc_dad(0x317a, 0xf1ff, ea_dpc16_read, gen_movew_dt_ea, ea_dad16), + move_w_dpc_dad(0x317a, 0xf1ff, ea_dpc16_read, gen_movew_dt_dt, ea_dad16), - move_w_dpci_dad(0x317b, 0xf1ff, ea_dpci16_read, gen_movew_dt_ea, ea_dad16), + move_w_dpci_dad(0x317b, 0xf1ff, ea_dpci16_read, gen_movew_dt_dt, ea_dad16), - move_w_imm16_dad(0x317c, 0xf1ff, ea_imm16_read, gen_movew_dt_ea, ea_dad16), + move_w_imm16_dad(0x317c, 0xf1ff, ea_imm16_read, gen_movew_dt_dt, ea_dad16), - move_w_ds_daid(0x3180, 0xf1f8, ea_daid16, gen_movew_ds_ea, dbrr), + move_w_ds_daid(0x3180, 0xf1f8, ea_daid16, gen_movew_dy_dt, dbrr), - move_w_as_daid(0x3188, 0xf1f8, ea_as_dt, gen_movew_dt_ea, ea_daid16), + move_w_as_daid(0x3188, 0xf1f8, ea_as_dt, gen_movew_dt_dt, ea_daid16), - move_w_ais_daid(0x3190, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_daid16), + move_w_ais_daid(0x3190, 0xf1f8, ea_ais16_read, gen_movew_dt_dt, ea_daid16), - move_w_aips_daid(0x3198, 0xf1f8, ea_aips16_read, gen_movew_dt_ea, ea_daid16), + move_w_aips_daid(0x3198, 0xf1f8, ea_aips16_read, gen_movew_dt_dt, ea_daid16), - move_w_pais_daid(0x31a0, 0xf1f8, ea_pais16_read, gen_movew_dt_ea, ea_daid16), + move_w_pais_daid(0x31a0, 0xf1f8, ea_pais16_read, gen_movew_dt_dt, ea_daid16), - move_w_das_daid(0x31a8, 0xf1f8, ea_das16_read, gen_movew_dt_ea, ea_daid16), + move_w_das_daid(0x31a8, 0xf1f8, ea_das16_read, gen_movew_dt_dt, ea_daid16), - move_w_dais_daid(0x31b0, 0xf1f8, ea_dais16_read, gen_movew_dt_ea, ea_daid16), + move_w_dais_daid(0x31b0, 0xf1f8, ea_dais16_read, gen_movew_dt_dt, ea_daid16), - move_w_adr16_daid(0x31b8, 0xf1ff, ea_adr16s16_read, gen_movew_dt_ea, ea_daid16), + move_w_adr16_daid(0x31b8, 0xf1ff, ea_adr16s16_read, gen_movew_dt_dt, ea_daid16), - move_w_adr32_daid(0x31b9, 0xf1ff, ea_adr32s16_read, gen_movew_dt_ea, ea_daid16), + move_w_adr32_daid(0x31b9, 0xf1ff, ea_adr32s16_read, gen_movew_dt_dt, ea_daid16), - move_w_dpc_daid(0x31ba, 0xf1ff, ea_dpc16_read, gen_movew_dt_ea, ea_daid16), + move_w_dpc_daid(0x31ba, 0xf1ff, ea_dpc16_read, gen_movew_dt_dt, ea_daid16), - move_w_dpci_daid(0x31bb, 0xf1ff, ea_dpci16_read, gen_movew_dt_ea, ea_daid16), + move_w_dpci_daid(0x31bb, 0xf1ff, ea_dpci16_read, gen_movew_dt_dt, ea_daid16), - move_w_imm16_daid(0x31bc, 0xf1ff, ea_imm16_read, gen_movew_dt_ea, ea_daid16), + move_w_imm16_daid(0x31bc, 0xf1ff, ea_imm16_read, gen_movew_dt_dt, ea_daid16), - move_w_ds_adr16(0x31c0, 0xfff8, ea_adr16d16, gen_movew_ds_ea, dbrr), + move_w_ds_adr16(0x31c0, 0xfff8, ea_adr16d16, gen_movew_dy_dt, dbrr), - move_w_as_adr16(0x31c8, 0xfff8, ea_as_dt, gen_movew_dt_ea, ea_adr16d16), + move_w_as_adr16(0x31c8, 0xfff8, ea_as_dt, gen_movew_dt_dt, ea_adr16d16), - move_w_ais_adr16(0x31d0, 0xfff8, ea_ais16_read, gen_movew_dt_ea, ea_adr16d16), + move_w_ais_adr16(0x31d0, 0xfff8, ea_ais16_read, gen_movew_dt_dt, ea_adr16d16), - move_w_aips_adr16(0x31d8, 0xfff8, ea_aips16_read, gen_movew_dt_ea, ea_adr16d16), + move_w_aips_adr16(0x31d8, 0xfff8, ea_aips16_read, gen_movew_dt_dt, ea_adr16d16), - move_w_pais_adr16(0x31e0, 0xfff8, ea_pais16_read, gen_movew_dt_ea, ea_adr16d16), + move_w_pais_adr16(0x31e0, 0xfff8, ea_pais16_read, gen_movew_dt_dt, ea_adr16d16), - move_w_das_adr16(0x31e8, 0xfff8, ea_das16_read, gen_movew_dt_ea, ea_adr16d16), + move_w_das_adr16(0x31e8, 0xfff8, ea_das16_read, gen_movew_dt_dt, ea_adr16d16), - move_w_dais_adr16(0x31f0, 0xfff8, ea_dais16_read, gen_movew_dt_ea, ea_adr16d16), + move_w_dais_adr16(0x31f0, 0xfff8, ea_dais16_read, gen_movew_dt_dt, ea_adr16d16), - move_w_adr16_adr16(0x31f8, 0xffff, ea_adr16s16_read, gen_movew_dt_ea, ea_adr16d16), + move_w_adr16_adr16(0x31f8, 0xffff, ea_adr16s16_read, gen_movew_dt_dt, ea_adr16d16), - move_w_adr32_adr16(0x31f9, 0xffff, ea_adr32s16_read, gen_movew_dt_ea, ea_adr16d16), + move_w_adr32_adr16(0x31f9, 0xffff, ea_adr32s16_read, gen_movew_dt_dt, ea_adr16d16), - move_w_dpc_adr16(0x31fa, 0xffff, ea_dpc16_read, gen_movew_dt_ea, ea_adr16d16), + move_w_dpc_adr16(0x31fa, 0xffff, ea_dpc16_read, gen_movew_dt_dt, ea_adr16d16), - move_w_dpci_adr16(0x31fb, 0xffff, ea_dpci16_read, gen_movew_dt_ea, ea_adr16d16), + move_w_dpci_adr16(0x31fb, 0xffff, ea_dpci16_read, gen_movew_dt_dt, ea_adr16d16), - move_w_imm16_adr16(0x31fc, 0xffff, ea_imm16_read, gen_movew_dt_ea, ea_adr16d16), + move_w_imm16_adr16(0x31fc, 0xffff, ea_imm16_read, gen_movew_dt_dt, ea_adr16d16), - move_w_ds_adr32(0x33c0, 0xfff8, ea_adr32d16, gen_movew_ds_ea, dbrr), + move_w_ds_adr32(0x33c0, 0xfff8, ea_adr32d16, gen_movew_dy_dt, dbrr), - move_w_as_adr32(0x33c8, 0xfff8, ea_as_dt, gen_movew_dt_ea, ea_adr32d16), + move_w_as_adr32(0x33c8, 0xfff8, ea_as_dt, gen_movew_dt_dt, ea_adr32d16), - move_w_ais_adr32(0x33d0, 0xfff8, ea_ais16_read, gen_movew_dt_ea, ea_adr32d16), + move_w_ais_adr32(0x33d0, 0xfff8, ea_ais16_read, gen_movew_dt_dt, ea_adr32d16), - move_w_aips_adr32(0x33d8, 0xfff8, ea_aips16_read, gen_movew_dt_ea, ea_adr32d16), + move_w_aips_adr32(0x33d8, 0xfff8, ea_aips16_read, gen_movew_dt_dt, ea_adr32d16), - move_w_pais_adr32(0x33e0, 0xfff8, ea_pais16_read, gen_movew_dt_ea, ea_adr32d16), + move_w_pais_adr32(0x33e0, 0xfff8, ea_pais16_read, gen_movew_dt_dt, ea_adr32d16), - move_w_das_adr32(0x33e8, 0xfff8, ea_das16_read, gen_movew_dt_ea, ea_adr32d16), + move_w_das_adr32(0x33e8, 0xfff8, ea_das16_read, gen_movew_dt_dt, ea_adr32d16), - move_w_dais_adr32(0x33f0, 0xfff8, ea_dais16_read, gen_movew_dt_ea, ea_adr32d16), + move_w_dais_adr32(0x33f0, 0xfff8, ea_dais16_read, gen_movew_dt_dt, ea_adr32d16), - move_w_adr16_adr32(0x33f8, 0xffff, ea_adr16s16_read, gen_movew_dt_ea, ea_adr32d16), + move_w_adr16_adr32(0x33f8, 0xffff, ea_adr16s16_read, gen_movew_dt_dt, ea_adr32d16), - move_w_adr32_adr32(0x33f9, 0xffff, ea_adr32s16_read, gen_movew_dt_ea, ea_adr32d16), + move_w_adr32_adr32(0x33f9, 0xffff, ea_adr32s16_read, gen_movew_dt_dt, ea_adr32d16), - move_w_dpc_adr32(0x33fa, 0xffff, ea_dpc16_read, gen_movew_dt_ea, ea_adr32d16), + move_w_dpc_adr32(0x33fa, 0xffff, ea_dpc16_read, gen_movew_dt_dt, ea_adr32d16), - move_w_dpci_adr32(0x33fb, 0xffff, ea_dpci16_read, gen_movew_dt_ea, ea_adr32d16), + move_w_dpci_adr32(0x33fb, 0xffff, ea_dpci16_read, gen_movew_dt_dt, ea_adr32d16), - move_w_imm16_adr32(0x33fc, 0xffff, ea_imm16_read, gen_movew_dt_ea, ea_adr32d16), + move_w_imm16_adr32(0x33fc, 0xffff, ea_imm16_read, gen_movew_dt_dt, ea_adr32d16), - negx_b_ds(0x4000, 0xfff8, gen_negxb_ds, dbrr, dbrr), + negx_b_ds(0x4000, 0xfff8, gen_negxb_dy, dbrr, dbrr), - negx_b_ais(0x4010, 0xfff8, ea_ais8_read, dbrr, gen_negxb_ea), + negx_b_ais(0x4010, 0xfff8, ea_ais8_read, dbrr, gen_negxb_dt), - negx_b_aips(0x4018, 0xfff8, ea_aips8_read, dbrr, gen_negxb_ea), + negx_b_aips(0x4018, 0xfff8, ea_aips8_read, dbrr, gen_negxb_dt), - negx_b_pais(0x4020, 0xfff8, ea_pais8_read, dbrr, gen_negxb_ea), + negx_b_pais(0x4020, 0xfff8, ea_pais8_read, dbrr, gen_negxb_dt), - negx_b_das(0x4028, 0xfff8, ea_das8_read, dbrr, gen_negxb_ea), + negx_b_das(0x4028, 0xfff8, ea_das8_read, dbrr, gen_negxb_dt), - negx_b_dais(0x4030, 0xfff8, ea_dais8_read, dbrr, gen_negxb_ea), + negx_b_dais(0x4030, 0xfff8, ea_dais8_read, dbrr, gen_negxb_dt), - negx_b_adr16(0x4038, 0xffff, ea_adr16s8_read, dbrr, gen_negxb_ea), + negx_b_adr16(0x4038, 0xffff, ea_adr16s8_read, dbrr, gen_negxb_dt), - negx_b_adr32(0x4039, 0xffff, ea_adr32s8_read, dbrr, gen_negxb_ea), + negx_b_adr32(0x4039, 0xffff, ea_adr32s8_read, dbrr, gen_negxb_dt), - negx_w_ds(0x4040, 0xfff8, gen_negxw_ds, dbrr, dbrr), + negx_w_ds(0x4040, 0xfff8, gen_negxw_dy, dbrr, dbrr), - negx_w_ais(0x4050, 0xfff8, ea_ais16_read, dbrr, gen_negxw_ea), + negx_w_ais(0x4050, 0xfff8, ea_ais16_read, dbrr, gen_negxw_dt), - negx_w_aips(0x4058, 0xfff8, ea_aips16_read, dbrr, gen_negxw_ea), + negx_w_aips(0x4058, 0xfff8, ea_aips16_read, dbrr, gen_negxw_dt), - negx_w_pais(0x4060, 0xfff8, ea_pais16_read, dbrr, gen_negxw_ea), + negx_w_pais(0x4060, 0xfff8, ea_pais16_read, dbrr, gen_negxw_dt), - negx_w_das(0x4068, 0xfff8, ea_das16_read, dbrr, gen_negxw_ea), + negx_w_das(0x4068, 0xfff8, ea_das16_read, dbrr, gen_negxw_dt), - negx_w_dais(0x4070, 0xfff8, ea_dais16_read, dbrr, gen_negxw_ea), + negx_w_dais(0x4070, 0xfff8, ea_dais16_read, dbrr, gen_negxw_dt), - negx_w_adr16(0x4078, 0xffff, ea_adr16s16_read, dbrr, gen_negxw_ea), + negx_w_adr16(0x4078, 0xffff, ea_adr16s16_read, dbrr, gen_negxw_dt), - negx_w_adr32(0x4079, 0xffff, ea_adr32s16_read, dbrr, gen_negxw_ea), + negx_w_adr32(0x4079, 0xffff, ea_adr32s16_read, dbrr, gen_negxw_dt), - negx_l_ds(0x4080, 0xfff8, gen_negxl_ds, dbrr, dbrr), + negx_l_ds(0x4080, 0xfff8, gen_negxl_dy, dbrr, dbrr), - negx_l_ais(0x4090, 0xfff8, ea_ais32_read, dbrr, gen_negxl_ea), + negx_l_ais(0x4090, 0xfff8, ea_ais32_read, dbrr, gen_negxl_dt), - negx_l_aips(0x4098, 0xfff8, ea_aips32_read, dbrr, gen_negxl_ea), + negx_l_aips(0x4098, 0xfff8, ea_aips32_read, dbrr, gen_negxl_dt), - negx_l_pais(0x40a0, 0xfff8, ea_pais32_read, dbrr, gen_negxl_ea), + negx_l_pais(0x40a0, 0xfff8, ea_pais32_read, dbrr, gen_negxl_dt), - negx_l_das(0x40a8, 0xfff8, ea_das32_read, dbrr, gen_negxl_ea), + negx_l_das(0x40a8, 0xfff8, ea_das32_read, dbrr, gen_negxl_dt), - negx_l_dais(0x40b0, 0xfff8, ea_dais32_read, dbrr, gen_negxl_ea), + negx_l_dais(0x40b0, 0xfff8, ea_dais32_read, dbrr, gen_negxl_dt), - negx_l_adr16(0x40b8, 0xffff, ea_adr16s32_read, dbrr, gen_negxl_ea), + negx_l_adr16(0x40b8, 0xffff, ea_adr16s32_read, dbrr, gen_negxl_dt), - negx_l_adr32(0x40b9, 0xffff, ea_adr32s32_read, dbrr, gen_negxl_ea), + negx_l_adr32(0x40b9, 0xffff, ea_adr32s32_read, dbrr, gen_negxl_dt), - move_sr_ds(0x40c0, 0xfff8, gen_movew_sr_ds, dbrr, dbrr), + move_sr_ds(0x40c0, 0xfff8, gen_movew_sr_dy, dbrr, dbrr), - move_sr_ais(0x40d0, 0xfff8, ea_ais16, dbrr, gen_movew_sr_ea), + move_sr_ais(0x40d0, 0xfff8, ea_ais16, dbrr, gen_movew_sr_dt), - move_sr_aips(0x40d8, 0xfff8, ea_aips16, dbrr, gen_movew_sr_ea), + move_sr_aips(0x40d8, 0xfff8, ea_aips16, dbrr, gen_movew_sr_dt), - move_sr_pais(0x40e0, 0xfff8, ea_pais16, dbrr, gen_movew_sr_ea), + move_sr_pais(0x40e0, 0xfff8, ea_pais16, dbrr, gen_movew_sr_dt), - move_sr_das(0x40e8, 0xfff8, ea_das16, dbrr, gen_movew_sr_ea), + move_sr_das(0x40e8, 0xfff8, ea_das16, dbrr, gen_movew_sr_dt), - move_sr_dais(0x40f0, 0xfff8, ea_dais16, dbrr, gen_movew_sr_ea), + move_sr_dais(0x40f0, 0xfff8, ea_dais16, dbrr, gen_movew_sr_dt), - move_sr_adr16(0x40f8, 0xffff, ea_adr16s16, dbrr, gen_movew_sr_ea), + move_sr_adr16(0x40f8, 0xffff, ea_adr16s16, dbrr, gen_movew_sr_dt), - move_sr_adr32(0x40f9, 0xffff, ea_adr32s16, dbrr, gen_movew_sr_ea), + move_sr_adr32(0x40f9, 0xffff, ea_adr32s16, dbrr, gen_movew_sr_dt), chk_w_ds_dd(0x4180, 0xf1f8, op_chk_w_ds, dbrr, dbrr), @@ -1625,71 +1625,71 @@ public enum MacroPLA { clr_l_adr32(0x42b9, 0xffff, ea_adr32s32, dbrr, op_clrl_ea), - move_ccr_ds(0x42c0, 0xfff8, gen_movew_ccr_ds, dbrr, dbrr), + move_ccr_ds(0x42c0, 0xfff8, gen_movew_ccr_dy, dbrr, dbrr), - move_ccr_ais(0x42d0, 0xfff8, ea_ais16, dbrr, gen_movew_ccr_ea), + move_ccr_ais(0x42d0, 0xfff8, ea_ais16, dbrr, gen_movew_ccr_dt), - move_ccr_aips(0x42d8, 0xfff8, ea_aips16, dbrr, gen_movew_ccr_ea), + move_ccr_aips(0x42d8, 0xfff8, ea_aips16, dbrr, gen_movew_ccr_dt), - move_ccr_pais(0x42e0, 0xfff8, ea_pais16, dbrr, gen_movew_ccr_ea), + move_ccr_pais(0x42e0, 0xfff8, ea_pais16, dbrr, gen_movew_ccr_dt), - move_ccr_das(0x42e8, 0xfff8, ea_das16, dbrr, gen_movew_ccr_ea), + move_ccr_das(0x42e8, 0xfff8, ea_das16, dbrr, gen_movew_ccr_dt), - move_ccr_dais(0x42f0, 0xfff8, ea_dais16, dbrr, gen_movew_ccr_ea), + move_ccr_dais(0x42f0, 0xfff8, ea_dais16, dbrr, gen_movew_ccr_dt), - move_ccr_adr16(0x42f8, 0xffff, ea_adr16s16, dbrr, gen_movew_ccr_ea), + move_ccr_adr16(0x42f8, 0xffff, ea_adr16s16, dbrr, gen_movew_ccr_dt), - move_ccr_adr32(0x42f9, 0xffff, ea_adr32s16, dbrr, gen_movew_ccr_ea), + move_ccr_adr32(0x42f9, 0xffff, ea_adr32s16, dbrr, gen_movew_ccr_dt), - neg_b_ds(0x4400, 0xfff8, gen_negb_ds, dbrr, dbrr), + neg_b_ds(0x4400, 0xfff8, gen_negb_dy, dbrr, dbrr), - neg_b_ais(0x4410, 0xfff8, ea_ais8_read, dbrr, gen_negb_ea), + neg_b_ais(0x4410, 0xfff8, ea_ais8_read, dbrr, gen_negb_dt), - neg_b_aips(0x4418, 0xfff8, ea_aips8_read, dbrr, gen_negb_ea), + neg_b_aips(0x4418, 0xfff8, ea_aips8_read, dbrr, gen_negb_dt), - neg_b_pais(0x4420, 0xfff8, ea_pais8_read, dbrr, gen_negb_ea), + neg_b_pais(0x4420, 0xfff8, ea_pais8_read, dbrr, gen_negb_dt), - neg_b_das(0x4428, 0xfff8, ea_das8_read, dbrr, gen_negb_ea), + neg_b_das(0x4428, 0xfff8, ea_das8_read, dbrr, gen_negb_dt), - neg_b_dais(0x4430, 0xfff8, ea_dais8_read, dbrr, gen_negb_ea), + neg_b_dais(0x4430, 0xfff8, ea_dais8_read, dbrr, gen_negb_dt), - neg_b_adr16(0x4438, 0xffff, ea_adr16s8_read, dbrr, gen_negb_ea), + neg_b_adr16(0x4438, 0xffff, ea_adr16s8_read, dbrr, gen_negb_dt), - neg_b_adr32(0x4439, 0xffff, ea_adr32s8_read, dbrr, gen_negb_ea), + neg_b_adr32(0x4439, 0xffff, ea_adr32s8_read, dbrr, gen_negb_dt), - neg_w_ds(0x4440, 0xfff8, gen_negw_ds, dbrr, dbrr), + neg_w_ds(0x4440, 0xfff8, gen_negw_dy, dbrr, dbrr), - neg_w_ais(0x4450, 0xfff8, ea_ais16_read, dbrr, gen_negw_ea), + neg_w_ais(0x4450, 0xfff8, ea_ais16_read, dbrr, gen_negw_dt), - neg_w_aips(0x4458, 0xfff8, ea_aips16_read, dbrr, gen_negw_ea), + neg_w_aips(0x4458, 0xfff8, ea_aips16_read, dbrr, gen_negw_dt), - neg_w_pais(0x4460, 0xfff8, ea_pais16_read, dbrr, gen_negw_ea), + neg_w_pais(0x4460, 0xfff8, ea_pais16_read, dbrr, gen_negw_dt), - neg_w_das(0x4468, 0xfff8, ea_das16_read, dbrr, gen_negw_ea), + neg_w_das(0x4468, 0xfff8, ea_das16_read, dbrr, gen_negw_dt), - neg_w_dais(0x4470, 0xfff8, ea_dais16_read, dbrr, gen_negw_ea), + neg_w_dais(0x4470, 0xfff8, ea_dais16_read, dbrr, gen_negw_dt), - neg_w_adr16(0x4478, 0xffff, ea_adr16s16_read, dbrr, gen_negw_ea), + neg_w_adr16(0x4478, 0xffff, ea_adr16s16_read, dbrr, gen_negw_dt), - neg_w_adr32(0x4479, 0xffff, ea_adr32s16_read, dbrr, gen_negw_ea), + neg_w_adr32(0x4479, 0xffff, ea_adr32s16_read, dbrr, gen_negw_dt), - neg_l_ds(0x4480, 0xfff8, gen_negl_ds, dbrr, dbrr), + neg_l_ds(0x4480, 0xfff8, gen_negl_dy, dbrr, dbrr), - neg_l_ais(0x4490, 0xfff8, ea_ais32_read, dbrr, gen_negl_ea), + neg_l_ais(0x4490, 0xfff8, ea_ais32_read, dbrr, gen_negl_dt), - neg_l_aips(0x4498, 0xfff8, ea_aips32_read, dbrr, gen_negl_ea), + neg_l_aips(0x4498, 0xfff8, ea_aips32_read, dbrr, gen_negl_dt), - neg_l_pais(0x44a0, 0xfff8, ea_pais32_read, dbrr, gen_negl_ea), + neg_l_pais(0x44a0, 0xfff8, ea_pais32_read, dbrr, gen_negl_dt), - neg_l_das(0x44a8, 0xfff8, ea_das32_read, dbrr, gen_negl_ea), + neg_l_das(0x44a8, 0xfff8, ea_das32_read, dbrr, gen_negl_dt), - neg_l_dais(0x44b0, 0xfff8, ea_dais32_read, dbrr, gen_negl_ea), + neg_l_dais(0x44b0, 0xfff8, ea_dais32_read, dbrr, gen_negl_dt), - neg_l_adr16(0x44b8, 0xffff, ea_adr16s32_read, dbrr, gen_negl_ea), + neg_l_adr16(0x44b8, 0xffff, ea_adr16s32_read, dbrr, gen_negl_dt), - neg_l_adr32(0x44b9, 0xffff, ea_adr32s32_read, dbrr, gen_negl_ea), + neg_l_adr32(0x44b9, 0xffff, ea_adr32s32_read, dbrr, gen_negl_dt), - move_ds_ccr(0x44c0, 0xfff8, gen_movew_ds_ccr, dbrr, dbrr), + move_ds_ccr(0x44c0, 0xfff8, gen_movew_dy_ccr, dbrr, dbrr), move_ais_ccr(0x44d0, 0xfff8, ea_ais16_read, dbrr, gen_movew_dt_ccr), @@ -1711,55 +1711,55 @@ public enum MacroPLA { move_imm16_ccr(0x44fc, 0xffff, ea_imm16_read, dbrr, gen_movew_dt_ccr), - not_b_ds(0x4600, 0xfff8, gen_notb_ds, dbrr, dbrr), + not_b_ds(0x4600, 0xfff8, gen_notb_dy, dbrr, dbrr), - not_b_ais(0x4610, 0xfff8, ea_ais8_read, dbrr, gen_notb_ea), + not_b_ais(0x4610, 0xfff8, ea_ais8_read, dbrr, gen_notb_dt), - not_b_aips(0x4618, 0xfff8, ea_aips8_read, dbrr, gen_notb_ea), + not_b_aips(0x4618, 0xfff8, ea_aips8_read, dbrr, gen_notb_dt), - not_b_pais(0x4620, 0xfff8, ea_pais8_read, dbrr, gen_notb_ea), + not_b_pais(0x4620, 0xfff8, ea_pais8_read, dbrr, gen_notb_dt), - not_b_das(0x4628, 0xfff8, ea_das8_read, dbrr, gen_notb_ea), + not_b_das(0x4628, 0xfff8, ea_das8_read, dbrr, gen_notb_dt), - not_b_dais(0x4630, 0xfff8, ea_dais8_read, dbrr, gen_notb_ea), + not_b_dais(0x4630, 0xfff8, ea_dais8_read, dbrr, gen_notb_dt), - not_b_adr16(0x4638, 0xffff, ea_adr16s8_read, dbrr, gen_notb_ea), + not_b_adr16(0x4638, 0xffff, ea_adr16s8_read, dbrr, gen_notb_dt), - not_b_adr32(0x4639, 0xffff, ea_adr32s8_read, dbrr, gen_notb_ea), + not_b_adr32(0x4639, 0xffff, ea_adr32s8_read, dbrr, gen_notb_dt), - not_w_ds(0x4640, 0xfff8, gen_notw_ds, dbrr, dbrr), + not_w_ds(0x4640, 0xfff8, gen_notw_dy, dbrr, dbrr), - not_w_ais(0x4650, 0xfff8, ea_ais16_read, dbrr, gen_notw_ea), + not_w_ais(0x4650, 0xfff8, ea_ais16_read, dbrr, gen_notw_dt), - not_w_aips(0x4658, 0xfff8, ea_aips16_read, dbrr, gen_notw_ea), + not_w_aips(0x4658, 0xfff8, ea_aips16_read, dbrr, gen_notw_dt), - not_w_pais(0x4660, 0xfff8, ea_pais16_read, dbrr, gen_notw_ea), + not_w_pais(0x4660, 0xfff8, ea_pais16_read, dbrr, gen_notw_dt), - not_w_das(0x4668, 0xfff8, ea_das16_read, dbrr, gen_notw_ea), + not_w_das(0x4668, 0xfff8, ea_das16_read, dbrr, gen_notw_dt), - not_w_dais(0x4670, 0xfff8, ea_dais16_read, dbrr, gen_notw_ea), + not_w_dais(0x4670, 0xfff8, ea_dais16_read, dbrr, gen_notw_dt), - not_w_adr16(0x4678, 0xffff, ea_adr16s16_read, dbrr, gen_notw_ea), + not_w_adr16(0x4678, 0xffff, ea_adr16s16_read, dbrr, gen_notw_dt), - not_w_adr32(0x4679, 0xffff, ea_adr32s16_read, dbrr, gen_notw_ea), + not_w_adr32(0x4679, 0xffff, ea_adr32s16_read, dbrr, gen_notw_dt), - not_l_ds(0x4680, 0xfff8, gen_notl_ds, dbrr, dbrr), + not_l_ds(0x4680, 0xfff8, gen_notl_dy, dbrr, dbrr), - not_l_ais(0x4690, 0xfff8, ea_ais32_read, dbrr, gen_notl_ea), + not_l_ais(0x4690, 0xfff8, ea_ais32_read, dbrr, gen_notl_dt), - not_l_aips(0x4698, 0xfff8, ea_aips32_read, dbrr, gen_notl_ea), + not_l_aips(0x4698, 0xfff8, ea_aips32_read, dbrr, gen_notl_dt), - not_l_pais(0x46a0, 0xfff8, ea_pais32_read, dbrr, gen_notl_ea), + not_l_pais(0x46a0, 0xfff8, ea_pais32_read, dbrr, gen_notl_dt), - not_l_das(0x46a8, 0xfff8, ea_das32_read, dbrr, gen_notl_ea), + not_l_das(0x46a8, 0xfff8, ea_das32_read, dbrr, gen_notl_dt), - not_l_dais(0x46b0, 0xfff8, ea_dais32_read, dbrr, gen_notl_ea), + not_l_dais(0x46b0, 0xfff8, ea_dais32_read, dbrr, gen_notl_dt), - not_l_adr16(0x46b8, 0xffff, ea_adr16s32_read, dbrr, gen_notl_ea), + not_l_adr16(0x46b8, 0xffff, ea_adr16s32_read, dbrr, gen_notl_dt), - not_l_adr32(0x46b9, 0xffff, ea_adr32s32_read, dbrr, gen_notl_ea), + not_l_adr32(0x46b9, 0xffff, ea_adr32s32_read, dbrr, gen_notl_dt), - move_ds_sr(0x46c0, 0xfff8, gen_movew_ds_sr, dbrr, dbrr), + move_ds_sr(0x46c0, 0xfff8, gen_movew_dy_sr, dbrr, dbrr), move_ais_sr(0x46d0, 0xfff8, ea_ais16_read, dbrr, gen_movew_dt_sr), @@ -1781,23 +1781,23 @@ public enum MacroPLA { move_imm16_sr(0x46fc, 0xffff, ea_imm16_read, dbrr, gen_movew_dt_sr), - nbcd_b_ds(0x4800, 0xfff8, gen_nbcdb_ds, dbrr, dbrr), + nbcd_b_ds(0x4800, 0xfff8, gen_nbcdb_dy, dbrr, dbrr), link_as_imm32(0x4808, 0xfff8, op_imm32, op_link_as_imm32, dbrr), - nbcd_b_ais(0x4810, 0xfff8, ea_ais8_read, dbrr, gen_nbcdb_ea), + nbcd_b_ais(0x4810, 0xfff8, ea_ais8_read, dbrr, gen_nbcdb_dt), - nbcd_b_aips(0x4818, 0xfff8, ea_aips8_read, dbrr, gen_nbcdb_ea), + nbcd_b_aips(0x4818, 0xfff8, ea_aips8_read, dbrr, gen_nbcdb_dt), - nbcd_b_pais(0x4820, 0xfff8, ea_pais8_read, dbrr, gen_nbcdb_ea), + nbcd_b_pais(0x4820, 0xfff8, ea_pais8_read, dbrr, gen_nbcdb_dt), - nbcd_b_das(0x4828, 0xfff8, ea_das8_read, dbrr, gen_nbcdb_ea), + nbcd_b_das(0x4828, 0xfff8, ea_das8_read, dbrr, gen_nbcdb_dt), - nbcd_b_dais(0x4830, 0xfff8, ea_dais8_read, dbrr, gen_nbcdb_ea), + nbcd_b_dais(0x4830, 0xfff8, ea_dais8_read, dbrr, gen_nbcdb_dt), - nbcd_b_adr16(0x4838, 0xffff, ea_adr16s8_read, dbrr, gen_nbcdb_ea), + nbcd_b_adr16(0x4838, 0xffff, ea_adr16s8_read, dbrr, gen_nbcdb_dt), - nbcd_b_adr32(0x4839, 0xffff, ea_adr32s8_read, dbrr, gen_nbcdb_ea), + nbcd_b_adr32(0x4839, 0xffff, ea_adr32s8_read, dbrr, gen_nbcdb_dt), swap_ds(0x4840, 0xfff8, op_swap_ds, dbrr, dbrr), @@ -1855,53 +1855,53 @@ public enum MacroPLA { extb_l_ds(0x49c0, 0xfff8, op_extbl_ds, dbrr, dbrr), - tst_b_ds(0x4a00, 0xfff8, gen_tstb_ds, dbrr, dbrr), + tst_b_ds(0x4a00, 0xfff8, gen_tstb_dy, dbrr, dbrr), - tst_b_ais(0x4a10, 0xfff8, ea_ais8_read, dbrr, gen_tstb_ea), + tst_b_ais(0x4a10, 0xfff8, ea_ais8_read, dbrr, gen_tstb_dt), - tst_b_aips(0x4a18, 0xfff8, ea_aips8_read, dbrr, gen_tstb_ea), + tst_b_aips(0x4a18, 0xfff8, ea_aips8_read, dbrr, gen_tstb_dt), - tst_b_pais(0x4a20, 0xfff8, ea_pais8_read, dbrr, gen_tstb_ea), + tst_b_pais(0x4a20, 0xfff8, ea_pais8_read, dbrr, gen_tstb_dt), - tst_b_das(0x4a28, 0xfff8, ea_das8_read, dbrr, gen_tstb_ea), + tst_b_das(0x4a28, 0xfff8, ea_das8_read, dbrr, gen_tstb_dt), - tst_b_dais(0x4a30, 0xfff8, ea_dais8_read, dbrr, gen_tstb_ea), + tst_b_dais(0x4a30, 0xfff8, ea_dais8_read, dbrr, gen_tstb_dt), - tst_b_adr16(0x4a38, 0xffff, ea_adr16s8_read, dbrr, gen_tstb_ea), + tst_b_adr16(0x4a38, 0xffff, ea_adr16s8_read, dbrr, gen_tstb_dt), - tst_b_adr32(0x4a39, 0xffff, ea_adr32s8_read, dbrr, gen_tstb_ea), + tst_b_adr32(0x4a39, 0xffff, ea_adr32s8_read, dbrr, gen_tstb_dt), - tst_w_ds(0x4a40, 0xfff8, gen_tstw_ds, dbrr, dbrr), + tst_w_ds(0x4a40, 0xfff8, gen_tstw_dy, dbrr, dbrr), - tst_w_ais(0x4a50, 0xfff8, ea_ais16_read, dbrr, gen_tstw_ea), + tst_w_ais(0x4a50, 0xfff8, ea_ais16_read, dbrr, gen_tstw_dt), - tst_w_aips(0x4a58, 0xfff8, ea_aips16_read, dbrr, gen_tstw_ea), + tst_w_aips(0x4a58, 0xfff8, ea_aips16_read, dbrr, gen_tstw_dt), - tst_w_pais(0x4a60, 0xfff8, ea_pais16_read, dbrr, gen_tstw_ea), + tst_w_pais(0x4a60, 0xfff8, ea_pais16_read, dbrr, gen_tstw_dt), - tst_w_das(0x4a68, 0xfff8, ea_das16_read, dbrr, gen_tstw_ea), + tst_w_das(0x4a68, 0xfff8, ea_das16_read, dbrr, gen_tstw_dt), - tst_w_dais(0x4a70, 0xfff8, ea_dais16_read, dbrr, gen_tstw_ea), + tst_w_dais(0x4a70, 0xfff8, ea_dais16_read, dbrr, gen_tstw_dt), - tst_w_adr16(0x4a78, 0xffff, ea_adr16s16_read, dbrr, gen_tstw_ea), + tst_w_adr16(0x4a78, 0xffff, ea_adr16s16_read, dbrr, gen_tstw_dt), - tst_w_adr32(0x4a79, 0xffff, ea_adr32s16_read, dbrr, gen_tstw_ea), + tst_w_adr32(0x4a79, 0xffff, ea_adr32s16_read, dbrr, gen_tstw_dt), - tst_l_ds(0x4a80, 0xfff8, gen_tstl_ds, dbrr, dbrr), + tst_l_ds(0x4a80, 0xfff8, gen_tstl_dy, dbrr, dbrr), - tst_l_ais(0x4a90, 0xfff8, ea_ais32_read, dbrr, gen_tstl_ea), + tst_l_ais(0x4a90, 0xfff8, ea_ais32_read, dbrr, gen_tstl_dt), - tst_l_aips(0x4a98, 0xfff8, ea_aips32_read, dbrr, gen_tstl_ea), + tst_l_aips(0x4a98, 0xfff8, ea_aips32_read, dbrr, gen_tstl_dt), - tst_l_pais(0x4aa0, 0xfff8, ea_pais32_read, dbrr, gen_tstl_ea), + tst_l_pais(0x4aa0, 0xfff8, ea_pais32_read, dbrr, gen_tstl_dt), - tst_l_das(0x4aa8, 0xfff8, ea_das32_read, dbrr, gen_tstl_ea), + tst_l_das(0x4aa8, 0xfff8, ea_das32_read, dbrr, gen_tstl_dt), - tst_l_dais(0x4ab0, 0xfff8, ea_dais32_read, dbrr, gen_tstl_ea), + tst_l_dais(0x4ab0, 0xfff8, ea_dais32_read, dbrr, gen_tstl_dt), - tst_l_adr16(0x4ab8, 0xffff, ea_adr16s32_read, dbrr, gen_tstl_ea), + tst_l_adr16(0x4ab8, 0xffff, ea_adr16s32_read, dbrr, gen_tstl_dt), - tst_l_adr32(0x4ab9, 0xffff, ea_adr32s32_read, dbrr, gen_tstl_ea), + tst_l_adr32(0x4ab9, 0xffff, ea_adr32s32_read, dbrr, gen_tstl_dt), illegal(0x4afc, 0xffff, op_illegal, dbrr, dbrr), @@ -1993,57 +1993,57 @@ public enum MacroPLA { jmp_dpci(0x4efb, 0xffff, ea_dpci16, dbrr, op_jmp), - addq_b_imm3_ds(0x5000, 0xf1f8, gen_addb_ir_ds, dbrr, dbrr), + addq_b_imm3_ds(0x5000, 0xf1f8, gen_addb_ir_dy, dbrr, dbrr), - addq_b_imm3_ais(0x5010, 0xf1f8, ea_ais8_read, dbrr, gen_addb_ir_ea), + addq_b_imm3_ais(0x5010, 0xf1f8, ea_ais8_read, dbrr, gen_addb_ir_dt), - addq_b_imm3_aips(0x5018, 0xf1f8, ea_aips8_read, dbrr, gen_addb_ir_ea), + addq_b_imm3_aips(0x5018, 0xf1f8, ea_aips8_read, dbrr, gen_addb_ir_dt), - addq_b_imm3_pais(0x5020, 0xf1f8, ea_pais8_read, dbrr, gen_addb_ir_ea), + addq_b_imm3_pais(0x5020, 0xf1f8, ea_pais8_read, dbrr, gen_addb_ir_dt), - addq_b_imm3_das(0x5028, 0xf1f8, ea_das8_read, dbrr, gen_addb_ir_ea), + addq_b_imm3_das(0x5028, 0xf1f8, ea_das8_read, dbrr, gen_addb_ir_dt), - addq_b_imm3_dais(0x5030, 0xf1f8, ea_dais8_read, dbrr, gen_addb_ir_ea), + addq_b_imm3_dais(0x5030, 0xf1f8, ea_dais8_read, dbrr, gen_addb_ir_dt), - addq_b_imm3_adr16(0x5038, 0xf1ff, ea_adr16s8_read, dbrr, gen_addb_ir_ea), + addq_b_imm3_adr16(0x5038, 0xf1ff, ea_adr16s8_read, dbrr, gen_addb_ir_dt), - addq_b_imm3_adr32(0x5039, 0xf1ff, ea_adr32s8_read, dbrr, gen_addb_ir_ea), + addq_b_imm3_adr32(0x5039, 0xf1ff, ea_adr32s8_read, dbrr, gen_addb_ir_dt), - addq_w_imm3_ds(0x5040, 0xf1f8, gen_addw_ir_ds, dbrr, dbrr), + addq_w_imm3_ds(0x5040, 0xf1f8, gen_addw_ir_dy, dbrr, dbrr), - addq_w_imm3_as(0x5048, 0xf1f8, gen_addw_ir_as, dbrr, dbrr), + addq_w_imm3_as(0x5048, 0xf1f8, gen_addw_ir_ay, dbrr, dbrr), - addq_w_imm3_ais(0x5050, 0xf1f8, ea_ais16_read, dbrr, gen_addw_ir_ea), + addq_w_imm3_ais(0x5050, 0xf1f8, ea_ais16_read, dbrr, gen_addw_ir_dt), - addq_w_imm3_aips(0x5058, 0xf1f8, ea_aips16_read, dbrr, gen_addw_ir_ea), + addq_w_imm3_aips(0x5058, 0xf1f8, ea_aips16_read, dbrr, gen_addw_ir_dt), - addq_w_imm3_pais(0x5060, 0xf1f8, ea_pais16_read, dbrr, gen_addw_ir_ea), + addq_w_imm3_pais(0x5060, 0xf1f8, ea_pais16_read, dbrr, gen_addw_ir_dt), - addq_w_imm3_das(0x5068, 0xf1f8, ea_das16_read, dbrr, gen_addw_ir_ea), + addq_w_imm3_das(0x5068, 0xf1f8, ea_das16_read, dbrr, gen_addw_ir_dt), - addq_w_imm3_dais(0x5070, 0xf1f8, ea_dais16_read, dbrr, gen_addw_ir_ea), + addq_w_imm3_dais(0x5070, 0xf1f8, ea_dais16_read, dbrr, gen_addw_ir_dt), - addq_w_imm3_adr16(0x5078, 0xf1ff, ea_adr16s16_read, dbrr, gen_addw_ir_ea), + addq_w_imm3_adr16(0x5078, 0xf1ff, ea_adr16s16_read, dbrr, gen_addw_ir_dt), - addq_w_imm3_adr32(0x5079, 0xf1ff, ea_adr32s16_read, dbrr, gen_addw_ir_ea), + addq_w_imm3_adr32(0x5079, 0xf1ff, ea_adr32s16_read, dbrr, gen_addw_ir_dt), - addq_l_imm3_ds(0x5080, 0xf1f8, gen_addl_ir_ds, dbrr, dbrr), + addq_l_imm3_ds(0x5080, 0xf1f8, gen_addl_ir_dy, dbrr, dbrr), - addq_l_imm3_as(0x5088, 0xf1f8, gen_addl_ir_as, dbrr, dbrr), + addq_l_imm3_as(0x5088, 0xf1f8, gen_addl_ir_ay, dbrr, dbrr), - addq_l_imm3_ais(0x5090, 0xf1f8, ea_ais32_read, dbrr, gen_addl_ir_ea), + addq_l_imm3_ais(0x5090, 0xf1f8, ea_ais32_read, dbrr, gen_addl_ir_dt), - addq_l_imm3_aips(0x5098, 0xf1f8, ea_aips32_read, dbrr, gen_addl_ir_ea), + addq_l_imm3_aips(0x5098, 0xf1f8, ea_aips32_read, dbrr, gen_addl_ir_dt), - addq_l_imm3_pais(0x50a0, 0xf1f8, ea_pais32_read, dbrr, gen_addl_ir_ea), + addq_l_imm3_pais(0x50a0, 0xf1f8, ea_pais32_read, dbrr, gen_addl_ir_dt), - addq_l_imm3_das(0x50a8, 0xf1f8, ea_das32_read, dbrr, gen_addl_ir_ea), + addq_l_imm3_das(0x50a8, 0xf1f8, ea_das32_read, dbrr, gen_addl_ir_dt), - addq_l_imm3_dais(0x50b0, 0xf1f8, ea_dais32_read, dbrr, gen_addl_ir_ea), + addq_l_imm3_dais(0x50b0, 0xf1f8, ea_dais32_read, dbrr, gen_addl_ir_dt), - addq_l_imm3_adr16(0x50b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_addl_ir_ea), + addq_l_imm3_adr16(0x50b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_addl_ir_dt), - addq_l_imm3_adr32(0x50b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_addl_ir_ea), + addq_l_imm3_adr32(0x50b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_addl_ir_dt), scc_b_ds(0x50c0, 0xf0f8, op_scc_b_ds, dbrr, dbrr), @@ -2069,57 +2069,57 @@ public enum MacroPLA { trapcc(0x50fc, 0xf0ff, op_trapcc, dbrr, dbrr), - subq_b_imm3_ds(0x5100, 0xf1f8, gen_subb_ir_ds, dbrr, dbrr), + subq_b_imm3_ds(0x5100, 0xf1f8, gen_subb_ir_dy, dbrr, dbrr), - subq_b_imm3_ais(0x5110, 0xf1f8, ea_ais8_read, dbrr, gen_subb_ir_ea), + subq_b_imm3_ais(0x5110, 0xf1f8, ea_ais8_read, dbrr, gen_subb_ir_dt), - subq_b_imm3_aips(0x5118, 0xf1f8, ea_aips8_read, dbrr, gen_subb_ir_ea), + subq_b_imm3_aips(0x5118, 0xf1f8, ea_aips8_read, dbrr, gen_subb_ir_dt), - subq_b_imm3_pais(0x5120, 0xf1f8, ea_pais8_read, dbrr, gen_subb_ir_ea), + subq_b_imm3_pais(0x5120, 0xf1f8, ea_pais8_read, dbrr, gen_subb_ir_dt), - subq_b_imm3_das(0x5128, 0xf1f8, ea_das8_read, dbrr, gen_subb_ir_ea), + subq_b_imm3_das(0x5128, 0xf1f8, ea_das8_read, dbrr, gen_subb_ir_dt), - subq_b_imm3_dais(0x5130, 0xf1f8, ea_dais8_read, dbrr, gen_subb_ir_ea), + subq_b_imm3_dais(0x5130, 0xf1f8, ea_dais8_read, dbrr, gen_subb_ir_dt), - subq_b_imm3_adr16(0x5138, 0xf1ff, ea_adr16s8_read, dbrr, gen_subb_ir_ea), + subq_b_imm3_adr16(0x5138, 0xf1ff, ea_adr16s8_read, dbrr, gen_subb_ir_dt), - subq_b_imm3_adr32(0x5139, 0xf1ff, ea_adr32s8_read, dbrr, gen_subb_ir_ea), + subq_b_imm3_adr32(0x5139, 0xf1ff, ea_adr32s8_read, dbrr, gen_subb_ir_dt), - subq_w_imm3_ds(0x5140, 0xf1f8, gen_subw_ir_ds, dbrr, dbrr), + subq_w_imm3_ds(0x5140, 0xf1f8, gen_subw_ir_dy, dbrr, dbrr), - subq_w_imm3_as(0x5148, 0xf1f8, gen_subw_ir_as, dbrr, dbrr), + subq_w_imm3_as(0x5148, 0xf1f8, gen_subw_ir_ay, dbrr, dbrr), - subq_w_imm3_ais(0x5150, 0xf1f8, ea_ais16_read, dbrr, gen_subw_ir_ea), + subq_w_imm3_ais(0x5150, 0xf1f8, ea_ais16_read, dbrr, gen_subw_ir_dt), - subq_w_imm3_aips(0x5158, 0xf1f8, ea_aips16_read, dbrr, gen_subw_ir_ea), + subq_w_imm3_aips(0x5158, 0xf1f8, ea_aips16_read, dbrr, gen_subw_ir_dt), - subq_w_imm3_pais(0x5160, 0xf1f8, ea_pais16_read, dbrr, gen_subw_ir_ea), + subq_w_imm3_pais(0x5160, 0xf1f8, ea_pais16_read, dbrr, gen_subw_ir_dt), - subq_w_imm3_das(0x5168, 0xf1f8, ea_das16_read, dbrr, gen_subw_ir_ea), + subq_w_imm3_das(0x5168, 0xf1f8, ea_das16_read, dbrr, gen_subw_ir_dt), - subq_w_imm3_dais(0x5170, 0xf1f8, ea_dais16_read, dbrr, gen_subw_ir_ea), + subq_w_imm3_dais(0x5170, 0xf1f8, ea_dais16_read, dbrr, gen_subw_ir_dt), - subq_w_imm3_adr16(0x5178, 0xf1ff, ea_adr16s16_read, dbrr, gen_subw_ir_ea), + subq_w_imm3_adr16(0x5178, 0xf1ff, ea_adr16s16_read, dbrr, gen_subw_ir_dt), - subq_w_imm3_adr32(0x5179, 0xf1ff, ea_adr32s16_read, dbrr, gen_subw_ir_ea), + subq_w_imm3_adr32(0x5179, 0xf1ff, ea_adr32s16_read, dbrr, gen_subw_ir_dt), - subq_l_imm3_ds(0x5180, 0xf1f8, gen_subl_ir_ds, dbrr, dbrr), + subq_l_imm3_ds(0x5180, 0xf1f8, gen_subl_ir_dy, dbrr, dbrr), - subq_l_imm3_as(0x5188, 0xf1f8, gen_subl_ir_as, dbrr, dbrr), + subq_l_imm3_as(0x5188, 0xf1f8, gen_subl_ir_ay, dbrr, dbrr), - subq_l_imm3_ais(0x5190, 0xf1f8, ea_ais32_read, dbrr, gen_subl_ir_ea), + subq_l_imm3_ais(0x5190, 0xf1f8, ea_ais32_read, dbrr, gen_subl_ir_dt), - subq_l_imm3_aips(0x5198, 0xf1f8, ea_aips32_read, dbrr, gen_subl_ir_ea), + subq_l_imm3_aips(0x5198, 0xf1f8, ea_aips32_read, dbrr, gen_subl_ir_dt), - subq_l_imm3_pais(0x51a0, 0xf1f8, ea_pais32_read, dbrr, gen_subl_ir_ea), + subq_l_imm3_pais(0x51a0, 0xf1f8, ea_pais32_read, dbrr, gen_subl_ir_dt), - subq_l_imm3_das(0x51a8, 0xf1f8, ea_das32_read, dbrr, gen_subl_ir_ea), + subq_l_imm3_das(0x51a8, 0xf1f8, ea_das32_read, dbrr, gen_subl_ir_dt), - subq_l_imm3_dais(0x51b0, 0xf1f8, ea_dais32_read, dbrr, gen_subl_ir_ea), + subq_l_imm3_dais(0x51b0, 0xf1f8, ea_dais32_read, dbrr, gen_subl_ir_dt), - subq_l_imm3_adr16(0x51b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_subl_ir_ea), + subq_l_imm3_adr16(0x51b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_subl_ir_dt), - subq_l_imm3_adr32(0x51b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_subl_ir_ea), + subq_l_imm3_adr32(0x51b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_subl_ir_dt), bra_rel16(0x6000, 0xffff, op_bra16, dbrr, dbrr), @@ -2139,999 +2139,999 @@ public enum MacroPLA { bsr_rel32(0x61ff, 0xffff, op_bsr32, dbrr, dbrr), - moveq_imm8o_dd(0x7000, 0xf100, gen_movel_im_dd, dbrr, dbrr), + moveq_imm8o_dd(0x7000, 0xf100, gen_movel_ir_dx, dbrr, dbrr), - or_b_ds_dd(0x8000, 0xf1f8, gen_orb_ds_dd, dbrr, dbrr), + or_b_ds_dd(0x8000, 0xf1f8, gen_orb_dy_dx, dbrr, dbrr), - or_b_ais_dd(0x8010, 0xf1f8, ea_ais8_read, dbrr, gen_orb_dt_dd), + or_b_ais_dd(0x8010, 0xf1f8, ea_ais8_read, dbrr, gen_orb_dt_dx), - or_b_aips_dd(0x8018, 0xf1f8, ea_aips8_read, dbrr, gen_orb_dt_dd), + or_b_aips_dd(0x8018, 0xf1f8, ea_aips8_read, dbrr, gen_orb_dt_dx), - or_b_pais_dd(0x8020, 0xf1f8, ea_pais8_read, dbrr, gen_orb_dt_dd), + or_b_pais_dd(0x8020, 0xf1f8, ea_pais8_read, dbrr, gen_orb_dt_dx), - or_b_das_dd(0x8028, 0xf1f8, ea_das8_read, dbrr, gen_orb_dt_dd), + or_b_das_dd(0x8028, 0xf1f8, ea_das8_read, dbrr, gen_orb_dt_dx), - or_b_dais_dd(0x8030, 0xf1f8, ea_dais8_read, dbrr, gen_orb_dt_dd), + or_b_dais_dd(0x8030, 0xf1f8, ea_dais8_read, dbrr, gen_orb_dt_dx), - or_b_adr16_dd(0x8038, 0xf1ff, ea_adr16s8_read, dbrr, gen_orb_dt_dd), + or_b_adr16_dd(0x8038, 0xf1ff, ea_adr16s8_read, dbrr, gen_orb_dt_dx), - or_b_adr32_dd(0x8039, 0xf1ff, ea_adr32s8_read, dbrr, gen_orb_dt_dd), + or_b_adr32_dd(0x8039, 0xf1ff, ea_adr32s8_read, dbrr, gen_orb_dt_dx), - or_b_dpc_dd(0x803a, 0xf1ff, ea_dpc8_read, dbrr, gen_orb_dt_dd), + or_b_dpc_dd(0x803a, 0xf1ff, ea_dpc8_read, dbrr, gen_orb_dt_dx), - or_b_dpci_dd(0x803b, 0xf1ff, ea_dpci8_read, dbrr, gen_orb_dt_dd), + or_b_dpci_dd(0x803b, 0xf1ff, ea_dpci8_read, dbrr, gen_orb_dt_dx), - or_b_imm8_dd(0x803c, 0xf1ff, ea_imm8_read, dbrr, gen_orb_dt_dd), + or_b_imm8_dd(0x803c, 0xf1ff, ea_imm8_read, dbrr, gen_orb_dt_dx), - or_w_ds_dd(0x8040, 0xf1f8, gen_orw_ds_dd, dbrr, dbrr), + or_w_ds_dd(0x8040, 0xf1f8, gen_orw_dy_dx, dbrr, dbrr), - or_w_ais_dd(0x8050, 0xf1f8, ea_ais16_read, dbrr, gen_orw_dt_dd), + or_w_ais_dd(0x8050, 0xf1f8, ea_ais16_read, dbrr, gen_orw_dt_dx), - or_w_aips_dd(0x8058, 0xf1f8, ea_aips16_read, dbrr, gen_orw_dt_dd), + or_w_aips_dd(0x8058, 0xf1f8, ea_aips16_read, dbrr, gen_orw_dt_dx), - or_w_pais_dd(0x8060, 0xf1f8, ea_pais16_read, dbrr, gen_orw_dt_dd), + or_w_pais_dd(0x8060, 0xf1f8, ea_pais16_read, dbrr, gen_orw_dt_dx), - or_w_das_dd(0x8068, 0xf1f8, ea_das16_read, dbrr, gen_orw_dt_dd), + or_w_das_dd(0x8068, 0xf1f8, ea_das16_read, dbrr, gen_orw_dt_dx), - or_w_dais_dd(0x8070, 0xf1f8, ea_dais16_read, dbrr, gen_orw_dt_dd), + or_w_dais_dd(0x8070, 0xf1f8, ea_dais16_read, dbrr, gen_orw_dt_dx), - or_w_adr16_dd(0x8078, 0xf1ff, ea_adr16s16_read, dbrr, gen_orw_dt_dd), + or_w_adr16_dd(0x8078, 0xf1ff, ea_adr16s16_read, dbrr, gen_orw_dt_dx), - or_w_adr32_dd(0x8079, 0xf1ff, ea_adr32s16_read, dbrr, gen_orw_dt_dd), + or_w_adr32_dd(0x8079, 0xf1ff, ea_adr32s16_read, dbrr, gen_orw_dt_dx), - or_w_dpc_dd(0x807a, 0xf1ff, ea_dpc16_read, dbrr, gen_orw_dt_dd), + or_w_dpc_dd(0x807a, 0xf1ff, ea_dpc16_read, dbrr, gen_orw_dt_dx), - or_w_dpci_dd(0x807b, 0xf1ff, ea_dpci16_read, dbrr, gen_orw_dt_dd), + or_w_dpci_dd(0x807b, 0xf1ff, ea_dpci16_read, dbrr, gen_orw_dt_dx), - or_w_imm16_dd(0x807c, 0xf1ff, ea_imm16_read, dbrr, gen_orw_dt_dd), + or_w_imm16_dd(0x807c, 0xf1ff, ea_imm16_read, dbrr, gen_orw_dt_dx), - or_l_ds_dd(0x8080, 0xf1f8, gen_orl_ds_dd, dbrr, dbrr), + or_l_ds_dd(0x8080, 0xf1f8, gen_orl_dy_dx, dbrr, dbrr), - or_l_ais_dd(0x8090, 0xf1f8, ea_ais32_read, dbrr, gen_orl_dt_dd), + or_l_ais_dd(0x8090, 0xf1f8, ea_ais32_read, dbrr, gen_orl_dt_dx), - or_l_aips_dd(0x8098, 0xf1f8, ea_aips32_read, dbrr, gen_orl_dt_dd), + or_l_aips_dd(0x8098, 0xf1f8, ea_aips32_read, dbrr, gen_orl_dt_dx), - or_l_pais_dd(0x80a0, 0xf1f8, ea_pais32_read, dbrr, gen_orl_dt_dd), + or_l_pais_dd(0x80a0, 0xf1f8, ea_pais32_read, dbrr, gen_orl_dt_dx), - or_l_das_dd(0x80a8, 0xf1f8, ea_das32_read, dbrr, gen_orl_dt_dd), + or_l_das_dd(0x80a8, 0xf1f8, ea_das32_read, dbrr, gen_orl_dt_dx), - or_l_dais_dd(0x80b0, 0xf1f8, ea_dais32_read, dbrr, gen_orl_dt_dd), + or_l_dais_dd(0x80b0, 0xf1f8, ea_dais32_read, dbrr, gen_orl_dt_dx), - or_l_adr16_dd(0x80b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_orl_dt_dd), + or_l_adr16_dd(0x80b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_orl_dt_dx), - or_l_adr32_dd(0x80b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_orl_dt_dd), + or_l_adr32_dd(0x80b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_orl_dt_dx), - or_l_dpc_dd(0x80ba, 0xf1ff, ea_dpc32_read, dbrr, gen_orl_dt_dd), + or_l_dpc_dd(0x80ba, 0xf1ff, ea_dpc32_read, dbrr, gen_orl_dt_dx), - or_l_dpci_dd(0x80bb, 0xf1ff, ea_dpci32_read, dbrr, gen_orl_dt_dd), + or_l_dpci_dd(0x80bb, 0xf1ff, ea_dpci32_read, dbrr, gen_orl_dt_dx), - or_l_imm32_dd(0x80bc, 0xf1ff, ea_imm32_read, dbrr, gen_orl_dt_dd), + or_l_imm32_dd(0x80bc, 0xf1ff, ea_imm32_read, dbrr, gen_orl_dt_dx), - divu_w_ds(0x80c0, 0xf1f8, gen_divuw_ds_dd, dbrr, dbrr), + divu_w_ds(0x80c0, 0xf1f8, gen_divuw_dy_dx, dbrr, dbrr), - divu_w_ais(0x80d0, 0xf1f8, ea_ais16_read, dbrr, gen_divuw_dt_dd), + divu_w_ais(0x80d0, 0xf1f8, ea_ais16_read, dbrr, gen_divuw_dt_dx), - divu_w_aips(0x80d8, 0xf1f8, ea_aips16_read, dbrr, gen_divuw_dt_dd), + divu_w_aips(0x80d8, 0xf1f8, ea_aips16_read, dbrr, gen_divuw_dt_dx), - divu_w_pais(0x80e0, 0xf1f8, ea_pais16_read, dbrr, gen_divuw_dt_dd), + divu_w_pais(0x80e0, 0xf1f8, ea_pais16_read, dbrr, gen_divuw_dt_dx), - divu_w_das(0x80e8, 0xf1f8, ea_das16_read, dbrr, gen_divuw_dt_dd), + divu_w_das(0x80e8, 0xf1f8, ea_das16_read, dbrr, gen_divuw_dt_dx), - divu_w_dais(0x80f0, 0xf1f8, ea_dais16_read, dbrr, gen_divuw_dt_dd), + divu_w_dais(0x80f0, 0xf1f8, ea_dais16_read, dbrr, gen_divuw_dt_dx), - divu_w_adr16(0x80f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_divuw_dt_dd), + divu_w_adr16(0x80f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_divuw_dt_dx), - divu_w_adr32(0x80f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_divuw_dt_dd), + divu_w_adr32(0x80f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_divuw_dt_dx), - divu_w_dpc(0x80fa, 0xf1ff, ea_dpc16_read, dbrr, gen_divuw_dt_dd), + divu_w_dpc(0x80fa, 0xf1ff, ea_dpc16_read, dbrr, gen_divuw_dt_dx), - divu_w_dpci(0x80fb, 0xf1ff, ea_dpci16_read, dbrr, gen_divuw_dt_dd), + divu_w_dpci(0x80fb, 0xf1ff, ea_dpci16_read, dbrr, gen_divuw_dt_dx), - divu_w_imm16(0x80fc, 0xf1ff, ea_imm16_read, dbrr, gen_divuw_dt_dd), + divu_w_imm16(0x80fc, 0xf1ff, ea_imm16_read, dbrr, gen_divuw_dt_dx), - sbcd_ds_dd(0x8100, 0xf1f8, gen_sbcdb_ds_dd, dbrr, dbrr), + sbcd_ds_dd(0x8100, 0xf1f8, gen_sbcdb_dy_dx, dbrr, dbrr), - sbcd_pais_paid(0x8108, 0xf1f8, ea_pais8_read, gen_sbcdb_im_ea, ea_paid8_read), + sbcd_pais_paid(0x8108, 0xf1f8, ea_pais8_read, gen_sbcdb_alub_dt, ea_paid8_read), - or_b_dd_ais(0x8110, 0xf1f8, ea_ais8_read, dbrr, gen_orb_dd_ea), + or_b_dd_ais(0x8110, 0xf1f8, ea_ais8_read, dbrr, gen_orb_dx_dt), - or_b_dd_aips(0x8118, 0xf1f8, ea_aips8_read, dbrr, gen_orb_dd_ea), + or_b_dd_aips(0x8118, 0xf1f8, ea_aips8_read, dbrr, gen_orb_dx_dt), - or_b_dd_pais(0x8120, 0xf1f8, ea_pais8_read, dbrr, gen_orb_dd_ea), + or_b_dd_pais(0x8120, 0xf1f8, ea_pais8_read, dbrr, gen_orb_dx_dt), - or_b_dd_das(0x8128, 0xf1f8, ea_das8_read, dbrr, gen_orb_dd_ea), + or_b_dd_das(0x8128, 0xf1f8, ea_das8_read, dbrr, gen_orb_dx_dt), - or_b_dd_dais(0x8130, 0xf1f8, ea_dais8_read, dbrr, gen_orb_dd_ea), + or_b_dd_dais(0x8130, 0xf1f8, ea_dais8_read, dbrr, gen_orb_dx_dt), - or_b_dd_adr16(0x8138, 0xf1ff, ea_adr16s8_read, dbrr, gen_orb_dd_ea), + or_b_dd_adr16(0x8138, 0xf1ff, ea_adr16s8_read, dbrr, gen_orb_dx_dt), - or_b_dd_adr32(0x8139, 0xf1ff, ea_adr32s8_read, dbrr, gen_orb_dd_ea), + or_b_dd_adr32(0x8139, 0xf1ff, ea_adr32s8_read, dbrr, gen_orb_dx_dt), - or_w_dd_ais(0x8150, 0xf1f8, ea_ais16_read, dbrr, gen_orw_dd_ea), + or_w_dd_ais(0x8150, 0xf1f8, ea_ais16_read, dbrr, gen_orw_dx_dt), - or_w_dd_aips(0x8158, 0xf1f8, ea_aips16_read, dbrr, gen_orw_dd_ea), + or_w_dd_aips(0x8158, 0xf1f8, ea_aips16_read, dbrr, gen_orw_dx_dt), - or_w_dd_pais(0x8160, 0xf1f8, ea_pais16_read, dbrr, gen_orw_dd_ea), + or_w_dd_pais(0x8160, 0xf1f8, ea_pais16_read, dbrr, gen_orw_dx_dt), - or_w_dd_das(0x8168, 0xf1f8, ea_das16_read, dbrr, gen_orw_dd_ea), + or_w_dd_das(0x8168, 0xf1f8, ea_das16_read, dbrr, gen_orw_dx_dt), - or_w_dd_dais(0x8170, 0xf1f8, ea_dais16_read, dbrr, gen_orw_dd_ea), + or_w_dd_dais(0x8170, 0xf1f8, ea_dais16_read, dbrr, gen_orw_dx_dt), - or_w_dd_adr16(0x8178, 0xf1ff, ea_adr16s16_read, dbrr, gen_orw_dd_ea), + or_w_dd_adr16(0x8178, 0xf1ff, ea_adr16s16_read, dbrr, gen_orw_dx_dt), - or_w_dd_adr32(0x8179, 0xf1ff, ea_adr32s16_read, dbrr, gen_orw_dd_ea), + or_w_dd_adr32(0x8179, 0xf1ff, ea_adr32s16_read, dbrr, gen_orw_dx_dt), - or_l_dd_ais(0x8190, 0xf1f8, ea_ais32_read, dbrr, gen_orl_dd_ea), + or_l_dd_ais(0x8190, 0xf1f8, ea_ais32_read, dbrr, gen_orl_dx_dt), - or_l_dd_aips(0x8198, 0xf1f8, ea_aips32_read, dbrr, gen_orl_dd_ea), + or_l_dd_aips(0x8198, 0xf1f8, ea_aips32_read, dbrr, gen_orl_dx_dt), - or_l_dd_pais(0x81a0, 0xf1f8, ea_pais32_read, dbrr, gen_orl_dd_ea), + or_l_dd_pais(0x81a0, 0xf1f8, ea_pais32_read, dbrr, gen_orl_dx_dt), - or_l_dd_das(0x81a8, 0xf1f8, ea_das32_read, dbrr, gen_orl_dd_ea), + or_l_dd_das(0x81a8, 0xf1f8, ea_das32_read, dbrr, gen_orl_dx_dt), - or_l_dd_dais(0x81b0, 0xf1f8, ea_dais32_read, dbrr, gen_orl_dd_ea), + or_l_dd_dais(0x81b0, 0xf1f8, ea_dais32_read, dbrr, gen_orl_dx_dt), - or_l_dd_adr16(0x81b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_orl_dd_ea), + or_l_dd_adr16(0x81b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_orl_dx_dt), - or_l_dd_adr32(0x81b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_orl_dd_ea), + or_l_dd_adr32(0x81b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_orl_dx_dt), - divs_w_ds(0x81c0, 0xf1f8, gen_divsw_ds_dd, dbrr, dbrr), + divs_w_ds(0x81c0, 0xf1f8, gen_divsw_dy_dx, dbrr, dbrr), - divs_w_ais(0x81d0, 0xf1f8, ea_ais16_read, dbrr, gen_divsw_dt_dd), + divs_w_ais(0x81d0, 0xf1f8, ea_ais16_read, dbrr, gen_divsw_dt_dx), - divs_w_aips(0x81d8, 0xf1f8, ea_aips16_read, dbrr, gen_divsw_dt_dd), + divs_w_aips(0x81d8, 0xf1f8, ea_aips16_read, dbrr, gen_divsw_dt_dx), - divs_w_pais(0x81e0, 0xf1f8, ea_pais16_read, dbrr, gen_divsw_dt_dd), + divs_w_pais(0x81e0, 0xf1f8, ea_pais16_read, dbrr, gen_divsw_dt_dx), - divs_w_das(0x81e8, 0xf1f8, ea_das16_read, dbrr, gen_divsw_dt_dd), + divs_w_das(0x81e8, 0xf1f8, ea_das16_read, dbrr, gen_divsw_dt_dx), - divs_w_dais(0x81f0, 0xf1f8, ea_dais16_read, dbrr, gen_divsw_dt_dd), + divs_w_dais(0x81f0, 0xf1f8, ea_dais16_read, dbrr, gen_divsw_dt_dx), - divs_w_adr16(0x81f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_divsw_dt_dd), + divs_w_adr16(0x81f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_divsw_dt_dx), - divs_w_adr32(0x81f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_divsw_dt_dd), + divs_w_adr32(0x81f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_divsw_dt_dx), - divs_w_dpc(0x81fa, 0xf1ff, ea_dpc16_read, dbrr, gen_divsw_dt_dd), + divs_w_dpc(0x81fa, 0xf1ff, ea_dpc16_read, dbrr, gen_divsw_dt_dx), - divs_w_dpci(0x81fb, 0xf1ff, ea_dpci16_read, dbrr, gen_divsw_dt_dd), + divs_w_dpci(0x81fb, 0xf1ff, ea_dpci16_read, dbrr, gen_divsw_dt_dx), - divs_w_imm16(0x81fc, 0xf1ff, ea_imm16_read, dbrr, gen_divsw_dt_dd), + divs_w_imm16(0x81fc, 0xf1ff, ea_imm16_read, dbrr, gen_divsw_dt_dx), - sub_b_ds_dd(0x9000, 0xf1f8, gen_subb_ds_dd, dbrr, dbrr), + sub_b_ds_dd(0x9000, 0xf1f8, gen_subb_dy_dx, dbrr, dbrr), - sub_b_ais_dd(0x9010, 0xf1f8, ea_ais8_read, dbrr, gen_subb_dt_dd), + sub_b_ais_dd(0x9010, 0xf1f8, ea_ais8_read, dbrr, gen_subb_dt_dx), - sub_b_aips_dd(0x9018, 0xf1f8, ea_aips8_read, dbrr, gen_subb_dt_dd), + sub_b_aips_dd(0x9018, 0xf1f8, ea_aips8_read, dbrr, gen_subb_dt_dx), - sub_b_pais_dd(0x9020, 0xf1f8, ea_pais8_read, dbrr, gen_subb_dt_dd), + sub_b_pais_dd(0x9020, 0xf1f8, ea_pais8_read, dbrr, gen_subb_dt_dx), - sub_b_das_dd(0x9028, 0xf1f8, ea_das8_read, dbrr, gen_subb_dt_dd), + sub_b_das_dd(0x9028, 0xf1f8, ea_das8_read, dbrr, gen_subb_dt_dx), - sub_b_dais_dd(0x9030, 0xf1f8, ea_dais8_read, dbrr, gen_subb_dt_dd), + sub_b_dais_dd(0x9030, 0xf1f8, ea_dais8_read, dbrr, gen_subb_dt_dx), - sub_b_adr16_dd(0x9038, 0xf1ff, ea_adr16s8_read, dbrr, gen_subb_dt_dd), + sub_b_adr16_dd(0x9038, 0xf1ff, ea_adr16s8_read, dbrr, gen_subb_dt_dx), - sub_b_adr32_dd(0x9039, 0xf1ff, ea_adr32s8_read, dbrr, gen_subb_dt_dd), + sub_b_adr32_dd(0x9039, 0xf1ff, ea_adr32s8_read, dbrr, gen_subb_dt_dx), - sub_b_dpc_dd(0x903a, 0xf1ff, ea_dpc8_read, dbrr, gen_subb_dt_dd), + sub_b_dpc_dd(0x903a, 0xf1ff, ea_dpc8_read, dbrr, gen_subb_dt_dx), - sub_b_dpci_dd(0x903b, 0xf1ff, ea_dpci8_read, dbrr, gen_subb_dt_dd), + sub_b_dpci_dd(0x903b, 0xf1ff, ea_dpci8_read, dbrr, gen_subb_dt_dx), - sub_b_imm8_dd(0x903c, 0xf1ff, ea_imm8_read, dbrr, gen_subb_dt_dd), + sub_b_imm8_dd(0x903c, 0xf1ff, ea_imm8_read, dbrr, gen_subb_dt_dx), - sub_w_ds_dd(0x9040, 0xf1f8, gen_subw_ds_dd, dbrr, dbrr), + sub_w_ds_dd(0x9040, 0xf1f8, gen_subw_dy_dx, dbrr, dbrr), - sub_w_as_dd(0x9048, 0xf1f8, gen_subw_as_dd, dbrr, dbrr), + sub_w_as_dd(0x9048, 0xf1f8, gen_subw_ay_dx, dbrr, dbrr), - sub_w_ais_dd(0x9050, 0xf1f8, ea_ais16_read, dbrr, gen_subw_dt_dd), + sub_w_ais_dd(0x9050, 0xf1f8, ea_ais16_read, dbrr, gen_subw_dt_dx), - sub_w_aips_dd(0x9058, 0xf1f8, ea_aips16_read, dbrr, gen_subw_dt_dd), + sub_w_aips_dd(0x9058, 0xf1f8, ea_aips16_read, dbrr, gen_subw_dt_dx), - sub_w_pais_dd(0x9060, 0xf1f8, ea_pais16_read, dbrr, gen_subw_dt_dd), + sub_w_pais_dd(0x9060, 0xf1f8, ea_pais16_read, dbrr, gen_subw_dt_dx), - sub_w_das_dd(0x9068, 0xf1f8, ea_das16_read, dbrr, gen_subw_dt_dd), + sub_w_das_dd(0x9068, 0xf1f8, ea_das16_read, dbrr, gen_subw_dt_dx), - sub_w_dais_dd(0x9070, 0xf1f8, ea_dais16_read, dbrr, gen_subw_dt_dd), + sub_w_dais_dd(0x9070, 0xf1f8, ea_dais16_read, dbrr, gen_subw_dt_dx), - sub_w_adr16_dd(0x9078, 0xf1ff, ea_adr16s16_read, dbrr, gen_subw_dt_dd), + sub_w_adr16_dd(0x9078, 0xf1ff, ea_adr16s16_read, dbrr, gen_subw_dt_dx), - sub_w_adr32_dd(0x9079, 0xf1ff, ea_adr32s16_read, dbrr, gen_subw_dt_dd), + sub_w_adr32_dd(0x9079, 0xf1ff, ea_adr32s16_read, dbrr, gen_subw_dt_dx), - sub_w_dpc_dd(0x907a, 0xf1ff, ea_dpc16_read, dbrr, gen_subw_dt_dd), + sub_w_dpc_dd(0x907a, 0xf1ff, ea_dpc16_read, dbrr, gen_subw_dt_dx), - sub_w_dpci_dd(0x907b, 0xf1ff, ea_dpci16_read, dbrr, gen_subw_dt_dd), + sub_w_dpci_dd(0x907b, 0xf1ff, ea_dpci16_read, dbrr, gen_subw_dt_dx), - sub_w_imm16_dd(0x907c, 0xf1ff, ea_imm16_read, dbrr, gen_subw_dt_dd), + sub_w_imm16_dd(0x907c, 0xf1ff, ea_imm16_read, dbrr, gen_subw_dt_dx), - sub_l_ds_dd(0x9080, 0xf1f8, gen_subl_ds_dd, dbrr, dbrr), + sub_l_ds_dd(0x9080, 0xf1f8, gen_subl_dy_dx, dbrr, dbrr), - sub_l_as_dd(0x9088, 0xf1f8, gen_subl_as_dd, dbrr, dbrr), + sub_l_as_dd(0x9088, 0xf1f8, gen_subl_ay_dx, dbrr, dbrr), - sub_l_ais_dd(0x9090, 0xf1f8, ea_ais32_read, dbrr, gen_subl_dt_dd), + sub_l_ais_dd(0x9090, 0xf1f8, ea_ais32_read, dbrr, gen_subl_dt_dx), - sub_l_aips_dd(0x9098, 0xf1f8, ea_aips32_read, dbrr, gen_subl_dt_dd), + sub_l_aips_dd(0x9098, 0xf1f8, ea_aips32_read, dbrr, gen_subl_dt_dx), - sub_l_pais_dd(0x90a0, 0xf1f8, ea_pais32_read, dbrr, gen_subl_dt_dd), + sub_l_pais_dd(0x90a0, 0xf1f8, ea_pais32_read, dbrr, gen_subl_dt_dx), - sub_l_das_dd(0x90a8, 0xf1f8, ea_das32_read, dbrr, gen_subl_dt_dd), + sub_l_das_dd(0x90a8, 0xf1f8, ea_das32_read, dbrr, gen_subl_dt_dx), - sub_l_dais_dd(0x90b0, 0xf1f8, ea_dais32_read, dbrr, gen_subl_dt_dd), + sub_l_dais_dd(0x90b0, 0xf1f8, ea_dais32_read, dbrr, gen_subl_dt_dx), - sub_l_adr16_dd(0x90b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_subl_dt_dd), + sub_l_adr16_dd(0x90b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_subl_dt_dx), - sub_l_adr32_dd(0x90b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_subl_dt_dd), + sub_l_adr32_dd(0x90b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_subl_dt_dx), - sub_l_dpc_dd(0x90ba, 0xf1ff, ea_dpc32_read, dbrr, gen_subl_dt_dd), + sub_l_dpc_dd(0x90ba, 0xf1ff, ea_dpc32_read, dbrr, gen_subl_dt_dx), - sub_l_dpci_dd(0x90bb, 0xf1ff, ea_dpci32_read, dbrr, gen_subl_dt_dd), + sub_l_dpci_dd(0x90bb, 0xf1ff, ea_dpci32_read, dbrr, gen_subl_dt_dx), - sub_l_imm32_dd(0x90bc, 0xf1ff, ea_imm32_read, dbrr, gen_subl_dt_dd), + sub_l_imm32_dd(0x90bc, 0xf1ff, ea_imm32_read, dbrr, gen_subl_dt_dx), - suba_w_ds_ad(0x90c0, 0xf1f8, gen_subw_ds_ad, dbrr, dbrr), + suba_w_ds_ad(0x90c0, 0xf1f8, gen_subw_dy_ax, dbrr, dbrr), - suba_w_as_ad(0x90c8, 0xf1f8, gen_subw_as_ad, dbrr, dbrr), + suba_w_as_ad(0x90c8, 0xf1f8, gen_subw_ay_ax, dbrr, dbrr), - suba_w_ais_ad(0x90d0, 0xf1f8, ea_ais16_read, dbrr, gen_subw_dt_ad), + suba_w_ais_ad(0x90d0, 0xf1f8, ea_ais16_read, dbrr, gen_subw_dt_ax), - suba_w_aips_ad(0x90d8, 0xf1f8, ea_aips16_read, dbrr, gen_subw_dt_ad), + suba_w_aips_ad(0x90d8, 0xf1f8, ea_aips16_read, dbrr, gen_subw_dt_ax), - suba_w_pais_ad(0x90e0, 0xf1f8, ea_pais16_read, dbrr, gen_subw_dt_ad), + suba_w_pais_ad(0x90e0, 0xf1f8, ea_pais16_read, dbrr, gen_subw_dt_ax), - suba_w_das_ad(0x90e8, 0xf1f8, ea_das16_read, dbrr, gen_subw_dt_ad), + suba_w_das_ad(0x90e8, 0xf1f8, ea_das16_read, dbrr, gen_subw_dt_ax), - suba_w_dais_ad(0x90f0, 0xf1f8, ea_dais16_read, dbrr, gen_subw_dt_ad), + suba_w_dais_ad(0x90f0, 0xf1f8, ea_dais16_read, dbrr, gen_subw_dt_ax), - suba_w_adr16_ad(0x90f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_subw_dt_ad), + suba_w_adr16_ad(0x90f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_subw_dt_ax), - suba_w_adr32_ad(0x90f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_subw_dt_ad), + suba_w_adr32_ad(0x90f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_subw_dt_ax), - suba_w_dpc_ad(0x90fa, 0xf1ff, ea_dpc16_read, dbrr, gen_subw_dt_ad), + suba_w_dpc_ad(0x90fa, 0xf1ff, ea_dpc16_read, dbrr, gen_subw_dt_ax), - suba_w_dpci_ad(0x90fb, 0xf1ff, ea_dpci16_read, dbrr, gen_subw_dt_ad), + suba_w_dpci_ad(0x90fb, 0xf1ff, ea_dpci16_read, dbrr, gen_subw_dt_ax), - suba_w_imm16_ad(0x90fc, 0xf1ff, ea_imm16_read, dbrr, gen_subw_dt_ad), + suba_w_imm16_ad(0x90fc, 0xf1ff, ea_imm16_read, dbrr, gen_subw_dt_ax), - subx_b_ds_dd(0x9100, 0xf1f8, gen_subxb_ds_dd, dbrr, dbrr), + subx_b_ds_dd(0x9100, 0xf1f8, gen_subxb_dy_dx, dbrr, dbrr), - subx_b_pais_paid(0x9108, 0xf1f8, ea_pais8_read, gen_subxb_im_ea, ea_paid8_read), + subx_b_pais_paid(0x9108, 0xf1f8, ea_pais8_read, gen_subxb_alub_dt, ea_paid8_read), - sub_b_dd_ais(0x9110, 0xf1f8, ea_ais8_read, dbrr, gen_subb_dd_ea), + sub_b_dd_ais(0x9110, 0xf1f8, ea_ais8_read, dbrr, gen_subb_dx_dt), - sub_b_dd_aips(0x9118, 0xf1f8, ea_aips8_read, dbrr, gen_subb_dd_ea), + sub_b_dd_aips(0x9118, 0xf1f8, ea_aips8_read, dbrr, gen_subb_dx_dt), - sub_b_dd_pais(0x9120, 0xf1f8, ea_pais8_read, dbrr, gen_subb_dd_ea), + sub_b_dd_pais(0x9120, 0xf1f8, ea_pais8_read, dbrr, gen_subb_dx_dt), - sub_b_dd_das(0x9128, 0xf1f8, ea_das8_read, dbrr, gen_subb_dd_ea), + sub_b_dd_das(0x9128, 0xf1f8, ea_das8_read, dbrr, gen_subb_dx_dt), - sub_b_dd_dais(0x9130, 0xf1f8, ea_dais8_read, dbrr, gen_subb_dd_ea), + sub_b_dd_dais(0x9130, 0xf1f8, ea_dais8_read, dbrr, gen_subb_dx_dt), - sub_b_dd_adr16(0x9138, 0xf1ff, ea_adr16s8_read, dbrr, gen_subb_dd_ea), + sub_b_dd_adr16(0x9138, 0xf1ff, ea_adr16s8_read, dbrr, gen_subb_dx_dt), - sub_b_dd_adr32(0x9139, 0xf1ff, ea_adr32s8_read, dbrr, gen_subb_dd_ea), + sub_b_dd_adr32(0x9139, 0xf1ff, ea_adr32s8_read, dbrr, gen_subb_dx_dt), - subx_w_ds_dd(0x9140, 0xf1f8, gen_subxw_ds_dd, dbrr, dbrr), + subx_w_ds_dd(0x9140, 0xf1f8, gen_subxw_dy_dx, dbrr, dbrr), - subx_w_pais_paid(0x9148, 0xf1f8, ea_pais16_read, gen_subxw_im_ea, ea_paid16_read), + subx_w_pais_paid(0x9148, 0xf1f8, ea_pais16_read, gen_subxw_alub_dt, ea_paid16_read), - sub_w_dd_ais(0x9150, 0xf1f8, ea_ais16_read, dbrr, gen_subw_dd_ea), + sub_w_dd_ais(0x9150, 0xf1f8, ea_ais16_read, dbrr, gen_subw_dx_dt), - sub_w_dd_aips(0x9158, 0xf1f8, ea_aips16_read, dbrr, gen_subw_dd_ea), + sub_w_dd_aips(0x9158, 0xf1f8, ea_aips16_read, dbrr, gen_subw_dx_dt), - sub_w_dd_pais(0x9160, 0xf1f8, ea_pais16_read, dbrr, gen_subw_dd_ea), + sub_w_dd_pais(0x9160, 0xf1f8, ea_pais16_read, dbrr, gen_subw_dx_dt), - sub_w_dd_das(0x9168, 0xf1f8, ea_das16_read, dbrr, gen_subw_dd_ea), + sub_w_dd_das(0x9168, 0xf1f8, ea_das16_read, dbrr, gen_subw_dx_dt), - sub_w_dd_dais(0x9170, 0xf1f8, ea_dais16_read, dbrr, gen_subw_dd_ea), + sub_w_dd_dais(0x9170, 0xf1f8, ea_dais16_read, dbrr, gen_subw_dx_dt), - sub_w_dd_adr16(0x9178, 0xf1ff, ea_adr16s16_read, dbrr, gen_subw_dd_ea), + sub_w_dd_adr16(0x9178, 0xf1ff, ea_adr16s16_read, dbrr, gen_subw_dx_dt), - sub_w_dd_adr32(0x9179, 0xf1ff, ea_adr32s16_read, dbrr, gen_subw_dd_ea), + sub_w_dd_adr32(0x9179, 0xf1ff, ea_adr32s16_read, dbrr, gen_subw_dx_dt), - subx_l_ds_dd(0x9180, 0xf1f8, gen_subxl_ds_dd, dbrr, dbrr), + subx_l_ds_dd(0x9180, 0xf1f8, gen_subxl_dy_dx, dbrr, dbrr), - subx_l_pais_paid(0x9188, 0xf1f8, ea_pais32_read, gen_subxl_im_ea, ea_paid32_read), + subx_l_pais_paid(0x9188, 0xf1f8, ea_pais32_read, gen_subxl_alub_dt, ea_paid32_read), - sub_l_dd_ais(0x9190, 0xf1f8, ea_ais32_read, dbrr, gen_subl_dd_ea), + sub_l_dd_ais(0x9190, 0xf1f8, ea_ais32_read, dbrr, gen_subl_dx_dt), - sub_l_dd_aips(0x9198, 0xf1f8, ea_aips32_read, dbrr, gen_subl_dd_ea), + sub_l_dd_aips(0x9198, 0xf1f8, ea_aips32_read, dbrr, gen_subl_dx_dt), - sub_l_dd_pais(0x91a0, 0xf1f8, ea_pais32_read, dbrr, gen_subl_dd_ea), + sub_l_dd_pais(0x91a0, 0xf1f8, ea_pais32_read, dbrr, gen_subl_dx_dt), - sub_l_dd_das(0x91a8, 0xf1f8, ea_das32_read, dbrr, gen_subl_dd_ea), + sub_l_dd_das(0x91a8, 0xf1f8, ea_das32_read, dbrr, gen_subl_dx_dt), - sub_l_dd_dais(0x91b0, 0xf1f8, ea_dais32_read, dbrr, gen_subl_dd_ea), + sub_l_dd_dais(0x91b0, 0xf1f8, ea_dais32_read, dbrr, gen_subl_dx_dt), - sub_l_dd_adr16(0x91b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_subl_dd_ea), + sub_l_dd_adr16(0x91b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_subl_dx_dt), - sub_l_dd_adr32(0x91b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_subl_dd_ea), + sub_l_dd_adr32(0x91b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_subl_dx_dt), - suba_l_ds_ad(0x91c0, 0xf1f8, gen_subl_ds_ad, dbrr, dbrr), + suba_l_ds_ad(0x91c0, 0xf1f8, gen_subl_dy_ax, dbrr, dbrr), - suba_l_as_ad(0x91c8, 0xf1f8, gen_subl_as_ad, dbrr, dbrr), + suba_l_as_ad(0x91c8, 0xf1f8, gen_subl_ay_ax, dbrr, dbrr), - suba_l_ais_ad(0x91d0, 0xf1f8, ea_ais32_read, dbrr, gen_subl_dt_ad), + suba_l_ais_ad(0x91d0, 0xf1f8, ea_ais32_read, dbrr, gen_subl_dt_ax), - suba_l_aips_ad(0x91d8, 0xf1f8, ea_aips32_read, dbrr, gen_subl_dt_ad), + suba_l_aips_ad(0x91d8, 0xf1f8, ea_aips32_read, dbrr, gen_subl_dt_ax), - suba_l_pais_ad(0x91e0, 0xf1f8, ea_pais32_read, dbrr, gen_subl_dt_ad), + suba_l_pais_ad(0x91e0, 0xf1f8, ea_pais32_read, dbrr, gen_subl_dt_ax), - suba_l_das_ad(0x91e8, 0xf1f8, ea_das32_read, dbrr, gen_subl_dt_ad), + suba_l_das_ad(0x91e8, 0xf1f8, ea_das32_read, dbrr, gen_subl_dt_ax), - suba_l_dais_ad(0x91f0, 0xf1f8, ea_dais32_read, dbrr, gen_subl_dt_ad), + suba_l_dais_ad(0x91f0, 0xf1f8, ea_dais32_read, dbrr, gen_subl_dt_ax), - suba_l_adr16_ad(0x91f8, 0xf1ff, ea_adr16s32_read, dbrr, gen_subl_dt_ad), + suba_l_adr16_ad(0x91f8, 0xf1ff, ea_adr16s32_read, dbrr, gen_subl_dt_ax), - suba_l_adr32_ad(0x91f9, 0xf1ff, ea_adr32s32_read, dbrr, gen_subl_dt_ad), + suba_l_adr32_ad(0x91f9, 0xf1ff, ea_adr32s32_read, dbrr, gen_subl_dt_ax), - suba_l_dpc_ad(0x91fa, 0xf1ff, ea_dpc32_read, dbrr, gen_subl_dt_ad), + suba_l_dpc_ad(0x91fa, 0xf1ff, ea_dpc32_read, dbrr, gen_subl_dt_ax), - suba_l_dpci_ad(0x91fb, 0xf1ff, ea_dpci32_read, dbrr, gen_subl_dt_ad), + suba_l_dpci_ad(0x91fb, 0xf1ff, ea_dpci32_read, dbrr, gen_subl_dt_ax), - suba_l_imm32_ad(0x91fc, 0xf1ff, ea_imm32_read, dbrr, gen_subl_dt_ad), + suba_l_imm32_ad(0x91fc, 0xf1ff, ea_imm32_read, dbrr, gen_subl_dt_ax), linea_imm12(0xa000, 0xf000, op_linea, dbrr, dbrr), - cmp_b_ds_dd(0xb000, 0xf1f8, gen_cmpb_ds_dd, dbrr, dbrr), + cmp_b_ds_dd(0xb000, 0xf1f8, gen_cmpb_dy_dx, dbrr, dbrr), - cmp_b_ais_dd(0xb010, 0xf1f8, ea_ais8_read, dbrr, gen_cmpb_dt_dd), + cmp_b_ais_dd(0xb010, 0xf1f8, ea_ais8_read, dbrr, gen_cmpb_dt_dx), - cmp_b_aips_dd(0xb018, 0xf1f8, ea_aips8_read, dbrr, gen_cmpb_dt_dd), + cmp_b_aips_dd(0xb018, 0xf1f8, ea_aips8_read, dbrr, gen_cmpb_dt_dx), - cmp_b_pais_dd(0xb020, 0xf1f8, ea_pais8_read, dbrr, gen_cmpb_dt_dd), + cmp_b_pais_dd(0xb020, 0xf1f8, ea_pais8_read, dbrr, gen_cmpb_dt_dx), - cmp_b_das_dd(0xb028, 0xf1f8, ea_das8_read, dbrr, gen_cmpb_dt_dd), + cmp_b_das_dd(0xb028, 0xf1f8, ea_das8_read, dbrr, gen_cmpb_dt_dx), - cmp_b_dais_dd(0xb030, 0xf1f8, ea_dais8_read, dbrr, gen_cmpb_dt_dd), + cmp_b_dais_dd(0xb030, 0xf1f8, ea_dais8_read, dbrr, gen_cmpb_dt_dx), - cmp_b_adr16_dd(0xb038, 0xf1ff, ea_adr16s8_read, dbrr, gen_cmpb_dt_dd), + cmp_b_adr16_dd(0xb038, 0xf1ff, ea_adr16s8_read, dbrr, gen_cmpb_dt_dx), - cmp_b_adr32_dd(0xb039, 0xf1ff, ea_adr32s8_read, dbrr, gen_cmpb_dt_dd), + cmp_b_adr32_dd(0xb039, 0xf1ff, ea_adr32s8_read, dbrr, gen_cmpb_dt_dx), - cmp_b_dpc_dd(0xb03a, 0xf1ff, ea_dpc8_read, dbrr, gen_cmpb_dt_dd), + cmp_b_dpc_dd(0xb03a, 0xf1ff, ea_dpc8_read, dbrr, gen_cmpb_dt_dx), - cmp_b_dpci_dd(0xb03b, 0xf1ff, ea_dpci8_read, dbrr, gen_cmpb_dt_dd), + cmp_b_dpci_dd(0xb03b, 0xf1ff, ea_dpci8_read, dbrr, gen_cmpb_dt_dx), - cmp_b_imm8_dd(0xb03c, 0xf1ff, ea_imm8_read, dbrr, gen_cmpb_dt_dd), + cmp_b_imm8_dd(0xb03c, 0xf1ff, ea_imm8_read, dbrr, gen_cmpb_dt_dx), - cmp_w_ds_dd(0xb040, 0xf1f8, gen_cmpw_ds_dd, dbrr, dbrr), + cmp_w_ds_dd(0xb040, 0xf1f8, gen_cmpw_dy_dx, dbrr, dbrr), - cmp_w_as_dd(0xb048, 0xf1f8, gen_cmpw_as_dd, dbrr, dbrr), + cmp_w_as_dd(0xb048, 0xf1f8, gen_cmpw_ay_dx, dbrr, dbrr), - cmp_w_ais_dd(0xb050, 0xf1f8, ea_ais16_read, dbrr, gen_cmpw_dt_dd), + cmp_w_ais_dd(0xb050, 0xf1f8, ea_ais16_read, dbrr, gen_cmpw_dt_dx), - cmp_w_aips_dd(0xb058, 0xf1f8, ea_aips16_read, dbrr, gen_cmpw_dt_dd), + cmp_w_aips_dd(0xb058, 0xf1f8, ea_aips16_read, dbrr, gen_cmpw_dt_dx), - cmp_w_pais_dd(0xb060, 0xf1f8, ea_pais16_read, dbrr, gen_cmpw_dt_dd), + cmp_w_pais_dd(0xb060, 0xf1f8, ea_pais16_read, dbrr, gen_cmpw_dt_dx), - cmp_w_das_dd(0xb068, 0xf1f8, ea_das16_read, dbrr, gen_cmpw_dt_dd), + cmp_w_das_dd(0xb068, 0xf1f8, ea_das16_read, dbrr, gen_cmpw_dt_dx), - cmp_w_dais_dd(0xb070, 0xf1f8, ea_dais16_read, dbrr, gen_cmpw_dt_dd), + cmp_w_dais_dd(0xb070, 0xf1f8, ea_dais16_read, dbrr, gen_cmpw_dt_dx), - cmp_w_adr16_dd(0xb078, 0xf1ff, ea_adr16s16_read, dbrr, gen_cmpw_dt_dd), + cmp_w_adr16_dd(0xb078, 0xf1ff, ea_adr16s16_read, dbrr, gen_cmpw_dt_dx), - cmp_w_adr32_dd(0xb079, 0xf1ff, ea_adr32s16_read, dbrr, gen_cmpw_dt_dd), + cmp_w_adr32_dd(0xb079, 0xf1ff, ea_adr32s16_read, dbrr, gen_cmpw_dt_dx), - cmp_w_dpc_dd(0xb07a, 0xf1ff, ea_dpc16_read, dbrr, gen_cmpw_dt_dd), + cmp_w_dpc_dd(0xb07a, 0xf1ff, ea_dpc16_read, dbrr, gen_cmpw_dt_dx), - cmp_w_dpci_dd(0xb07b, 0xf1ff, ea_dpci16_read, dbrr, gen_cmpw_dt_dd), + cmp_w_dpci_dd(0xb07b, 0xf1ff, ea_dpci16_read, dbrr, gen_cmpw_dt_dx), - cmp_w_imm16_dd(0xb07c, 0xf1ff, ea_imm16_read, dbrr, gen_cmpw_dt_dd), + cmp_w_imm16_dd(0xb07c, 0xf1ff, ea_imm16_read, dbrr, gen_cmpw_dt_dx), - cmp_l_ds_dd(0xb080, 0xf1f8, gen_cmpl_ds_dd, dbrr, dbrr), + cmp_l_ds_dd(0xb080, 0xf1f8, gen_cmpl_dy_dx, dbrr, dbrr), - cmp_l_as_dd(0xb088, 0xf1f8, gen_cmpl_as_dd, dbrr, dbrr), + cmp_l_as_dd(0xb088, 0xf1f8, gen_cmpl_ay_dx, dbrr, dbrr), - cmp_l_ais_dd(0xb090, 0xf1f8, ea_ais32_read, dbrr, gen_cmpl_dt_dd), + cmp_l_ais_dd(0xb090, 0xf1f8, ea_ais32_read, dbrr, gen_cmpl_dt_dx), - cmp_l_aips_dd(0xb098, 0xf1f8, ea_aips32_read, dbrr, gen_cmpl_dt_dd), + cmp_l_aips_dd(0xb098, 0xf1f8, ea_aips32_read, dbrr, gen_cmpl_dt_dx), - cmp_l_pais_dd(0xb0a0, 0xf1f8, ea_pais32_read, dbrr, gen_cmpl_dt_dd), + cmp_l_pais_dd(0xb0a0, 0xf1f8, ea_pais32_read, dbrr, gen_cmpl_dt_dx), - cmp_l_das_dd(0xb0a8, 0xf1f8, ea_das32_read, dbrr, gen_cmpl_dt_dd), + cmp_l_das_dd(0xb0a8, 0xf1f8, ea_das32_read, dbrr, gen_cmpl_dt_dx), - cmp_l_dais_dd(0xb0b0, 0xf1f8, ea_dais32_read, dbrr, gen_cmpl_dt_dd), + cmp_l_dais_dd(0xb0b0, 0xf1f8, ea_dais32_read, dbrr, gen_cmpl_dt_dx), - cmp_l_adr16_dd(0xb0b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_cmpl_dt_dd), + cmp_l_adr16_dd(0xb0b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_cmpl_dt_dx), - cmp_l_adr32_dd(0xb0b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_cmpl_dt_dd), + cmp_l_adr32_dd(0xb0b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_cmpl_dt_dx), - cmp_l_dpc_dd(0xb0ba, 0xf1ff, ea_dpc32_read, dbrr, gen_cmpl_dt_dd), + cmp_l_dpc_dd(0xb0ba, 0xf1ff, ea_dpc32_read, dbrr, gen_cmpl_dt_dx), - cmp_l_dpci_dd(0xb0bb, 0xf1ff, ea_dpci32_read, dbrr, gen_cmpl_dt_dd), + cmp_l_dpci_dd(0xb0bb, 0xf1ff, ea_dpci32_read, dbrr, gen_cmpl_dt_dx), - cmp_l_imm32_dd(0xb0bc, 0xf1ff, ea_imm32_read, dbrr, gen_cmpl_dt_dd), + cmp_l_imm32_dd(0xb0bc, 0xf1ff, ea_imm32_read, dbrr, gen_cmpl_dt_dx), - cmpa_w_ds_ad(0xb0c0, 0xf1f8, gen_cmpw_ds_ad, dbrr, dbrr), + cmpa_w_ds_ad(0xb0c0, 0xf1f8, gen_cmpw_dy_ax, dbrr, dbrr), - cmpa_w_as_ad(0xb0c8, 0xf1f8, gen_cmpw_as_ad, dbrr, dbrr), + cmpa_w_as_ad(0xb0c8, 0xf1f8, gen_cmpw_ay_ax, dbrr, dbrr), - cmpa_w_ais_ad(0xb0d0, 0xf1f8, ea_ais16_read, dbrr, gen_cmpw_dt_ad), + cmpa_w_ais_ad(0xb0d0, 0xf1f8, ea_ais16_read, dbrr, gen_cmpw_dt_ax), - cmpa_w_aips_ad(0xb0d8, 0xf1f8, ea_aips16_read, dbrr, gen_cmpw_dt_ad), + cmpa_w_aips_ad(0xb0d8, 0xf1f8, ea_aips16_read, dbrr, gen_cmpw_dt_ax), - cmpa_w_pais_ad(0xb0e0, 0xf1f8, ea_pais16_read, dbrr, gen_cmpw_dt_ad), + cmpa_w_pais_ad(0xb0e0, 0xf1f8, ea_pais16_read, dbrr, gen_cmpw_dt_ax), - cmpa_w_das_ad(0xb0e8, 0xf1f8, ea_das16_read, dbrr, gen_cmpw_dt_ad), + cmpa_w_das_ad(0xb0e8, 0xf1f8, ea_das16_read, dbrr, gen_cmpw_dt_ax), - cmpa_w_dais_ad(0xb0f0, 0xf1f8, ea_dais16_read, dbrr, gen_cmpw_dt_ad), + cmpa_w_dais_ad(0xb0f0, 0xf1f8, ea_dais16_read, dbrr, gen_cmpw_dt_ax), - cmpa_w_adr16_ad(0xb0f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_cmpw_dt_ad), + cmpa_w_adr16_ad(0xb0f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_cmpw_dt_ax), - cmpa_w_adr32_ad(0xb0f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_cmpw_dt_ad), + cmpa_w_adr32_ad(0xb0f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_cmpw_dt_ax), - cmpa_w_dpc_ad(0xb0fa, 0xf1ff, ea_dpc16_read, dbrr, gen_cmpw_dt_ad), + cmpa_w_dpc_ad(0xb0fa, 0xf1ff, ea_dpc16_read, dbrr, gen_cmpw_dt_ax), - cmpa_w_dpci_ad(0xb0fb, 0xf1ff, ea_dpci16_read, dbrr, gen_cmpw_dt_ad), + cmpa_w_dpci_ad(0xb0fb, 0xf1ff, ea_dpci16_read, dbrr, gen_cmpw_dt_ax), - cmpa_w_imm16_ad(0xb0fc, 0xf1ff, ea_imm16_read, dbrr, gen_cmpw_dt_ad), + cmpa_w_imm16_ad(0xb0fc, 0xf1ff, ea_imm16_read, dbrr, gen_cmpw_dt_ax), - eor_b_dd_ds(0xb100, 0xf1f8, gen_eorb_dd_ds, dbrr, dbrr), + eor_b_dd_ds(0xb100, 0xf1f8, gen_eorb_dx_dy, dbrr, dbrr), - cmpm_b_aips_aipd(0xb108, 0xf1f8, ea_aips8_read, gen_cmpmb_im_ea, ea_aipd8_read), + cmpm_b_aips_aipd(0xb108, 0xf1f8, ea_aips8_read, gen_cmpmb_alub_dt, ea_aipd8_read), - eor_b_dd_ais(0xb110, 0xf1f8, ea_ais8_read, dbrr, gen_eorb_dd_ea), + eor_b_dd_ais(0xb110, 0xf1f8, ea_ais8_read, dbrr, gen_eorb_dx_dt), - eor_b_dd_aips(0xb118, 0xf1f8, ea_aips8_read, dbrr, gen_eorb_dd_ea), + eor_b_dd_aips(0xb118, 0xf1f8, ea_aips8_read, dbrr, gen_eorb_dx_dt), - eor_b_dd_pais(0xb120, 0xf1f8, ea_pais8_read, dbrr, gen_eorb_dd_ea), + eor_b_dd_pais(0xb120, 0xf1f8, ea_pais8_read, dbrr, gen_eorb_dx_dt), - eor_b_dd_das(0xb128, 0xf1f8, ea_das8_read, dbrr, gen_eorb_dd_ea), + eor_b_dd_das(0xb128, 0xf1f8, ea_das8_read, dbrr, gen_eorb_dx_dt), - eor_b_dd_dais(0xb130, 0xf1f8, ea_dais8_read, dbrr, gen_eorb_dd_ea), + eor_b_dd_dais(0xb130, 0xf1f8, ea_dais8_read, dbrr, gen_eorb_dx_dt), - eor_b_dd_adr16(0xb138, 0xf1ff, ea_adr16s8_read, dbrr, gen_eorb_dd_ea), + eor_b_dd_adr16(0xb138, 0xf1ff, ea_adr16s8_read, dbrr, gen_eorb_dx_dt), - eor_b_dd_adr32(0xb139, 0xf1ff, ea_adr32s8_read, dbrr, gen_eorb_dd_ea), + eor_b_dd_adr32(0xb139, 0xf1ff, ea_adr32s8_read, dbrr, gen_eorb_dx_dt), - eor_w_dd_ds(0xb140, 0xf1f8, gen_eorw_dd_ds, dbrr, dbrr), + eor_w_dd_ds(0xb140, 0xf1f8, gen_eorw_dx_dy, dbrr, dbrr), - cmpm_w_aips_aipd(0xb148, 0xf1f8, ea_aips16_read, gen_cmpmw_im_ea, ea_aipd16_read), + cmpm_w_aips_aipd(0xb148, 0xf1f8, ea_aips16_read, gen_cmpmw_alub_dt, ea_aipd16_read), - eor_w_dd_ais(0xb150, 0xf1f8, ea_ais16_read, dbrr, gen_eorw_dd_ea), + eor_w_dd_ais(0xb150, 0xf1f8, ea_ais16_read, dbrr, gen_eorw_dx_dt), - eor_w_dd_aips(0xb158, 0xf1f8, ea_aips16_read, dbrr, gen_eorw_dd_ea), + eor_w_dd_aips(0xb158, 0xf1f8, ea_aips16_read, dbrr, gen_eorw_dx_dt), - eor_w_dd_pais(0xb160, 0xf1f8, ea_pais16_read, dbrr, gen_eorw_dd_ea), + eor_w_dd_pais(0xb160, 0xf1f8, ea_pais16_read, dbrr, gen_eorw_dx_dt), - eor_w_dd_das(0xb168, 0xf1f8, ea_das16_read, dbrr, gen_eorw_dd_ea), + eor_w_dd_das(0xb168, 0xf1f8, ea_das16_read, dbrr, gen_eorw_dx_dt), - eor_w_dd_dais(0xb170, 0xf1f8, ea_dais16_read, dbrr, gen_eorw_dd_ea), + eor_w_dd_dais(0xb170, 0xf1f8, ea_dais16_read, dbrr, gen_eorw_dx_dt), - eor_w_dd_adr16(0xb178, 0xf1ff, ea_adr16s16_read, dbrr, gen_eorw_dd_ea), + eor_w_dd_adr16(0xb178, 0xf1ff, ea_adr16s16_read, dbrr, gen_eorw_dx_dt), - eor_w_dd_adr32(0xb179, 0xf1ff, ea_adr32s16_read, dbrr, gen_eorw_dd_ea), + eor_w_dd_adr32(0xb179, 0xf1ff, ea_adr32s16_read, dbrr, gen_eorw_dx_dt), - eor_l_dd_ds(0xb180, 0xf1f8, gen_eorl_dd_ds, dbrr, dbrr), + eor_l_dd_ds(0xb180, 0xf1f8, gen_eorl_dx_dy, dbrr, dbrr), - cmpm_l_aips_aipd(0xb188, 0xf1f8, ea_aips32_read, gen_cmpml_im_ea, ea_aipd32_read), + cmpm_l_aips_aipd(0xb188, 0xf1f8, ea_aips32_read, gen_cmpml_alub_dt, ea_aipd32_read), - eor_l_dd_ais(0xb190, 0xf1f8, ea_ais32_read, dbrr, gen_eorl_dd_ea), + eor_l_dd_ais(0xb190, 0xf1f8, ea_ais32_read, dbrr, gen_eorl_dx_dt), - eor_l_dd_aips(0xb198, 0xf1f8, ea_aips32_read, dbrr, gen_eorl_dd_ea), + eor_l_dd_aips(0xb198, 0xf1f8, ea_aips32_read, dbrr, gen_eorl_dx_dt), - eor_l_dd_pais(0xb1a0, 0xf1f8, ea_pais32_read, dbrr, gen_eorl_dd_ea), + eor_l_dd_pais(0xb1a0, 0xf1f8, ea_pais32_read, dbrr, gen_eorl_dx_dt), - eor_l_dd_das(0xb1a8, 0xf1f8, ea_das32_read, dbrr, gen_eorl_dd_ea), + eor_l_dd_das(0xb1a8, 0xf1f8, ea_das32_read, dbrr, gen_eorl_dx_dt), - eor_l_dd_dais(0xb1b0, 0xf1f8, ea_dais32_read, dbrr, gen_eorl_dd_ea), + eor_l_dd_dais(0xb1b0, 0xf1f8, ea_dais32_read, dbrr, gen_eorl_dx_dt), - eor_l_dd_adr16(0xb1b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_eorl_dd_ea), + eor_l_dd_adr16(0xb1b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_eorl_dx_dt), - eor_l_dd_adr32(0xb1b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_eorl_dd_ea), + eor_l_dd_adr32(0xb1b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_eorl_dx_dt), - cmpa_l_ds_ad(0xb1c0, 0xf1f8, gen_cmpl_ds_ad, dbrr, dbrr), + cmpa_l_ds_ad(0xb1c0, 0xf1f8, gen_cmpl_dy_ax, dbrr, dbrr), - cmpa_l_as_ad(0xb1c8, 0xf1f8, gen_cmpl_as_ad, dbrr, dbrr), + cmpa_l_as_ad(0xb1c8, 0xf1f8, gen_cmpl_ay_ax, dbrr, dbrr), - cmpa_l_ais_ad(0xb1d0, 0xf1f8, ea_ais32_read, dbrr, gen_cmpl_dt_ad), + cmpa_l_ais_ad(0xb1d0, 0xf1f8, ea_ais32_read, dbrr, gen_cmpl_dt_ax), - cmpa_l_aips_ad(0xb1d8, 0xf1f8, ea_aips32_read, dbrr, gen_cmpl_dt_ad), + cmpa_l_aips_ad(0xb1d8, 0xf1f8, ea_aips32_read, dbrr, gen_cmpl_dt_ax), - cmpa_l_pais_ad(0xb1e0, 0xf1f8, ea_pais32_read, dbrr, gen_cmpl_dt_ad), + cmpa_l_pais_ad(0xb1e0, 0xf1f8, ea_pais32_read, dbrr, gen_cmpl_dt_ax), - cmpa_l_das_ad(0xb1e8, 0xf1f8, ea_das32_read, dbrr, gen_cmpl_dt_ad), + cmpa_l_das_ad(0xb1e8, 0xf1f8, ea_das32_read, dbrr, gen_cmpl_dt_ax), - cmpa_l_dais_ad(0xb1f0, 0xf1f8, ea_dais32_read, dbrr, gen_cmpl_dt_ad), + cmpa_l_dais_ad(0xb1f0, 0xf1f8, ea_dais32_read, dbrr, gen_cmpl_dt_ax), - cmpa_l_adr16_ad(0xb1f8, 0xf1ff, ea_adr16s32_read, dbrr, gen_cmpl_dt_ad), + cmpa_l_adr16_ad(0xb1f8, 0xf1ff, ea_adr16s32_read, dbrr, gen_cmpl_dt_ax), - cmpa_l_adr32_ad(0xb1f9, 0xf1ff, ea_adr32s32_read, dbrr, gen_cmpl_dt_ad), + cmpa_l_adr32_ad(0xb1f9, 0xf1ff, ea_adr32s32_read, dbrr, gen_cmpl_dt_ax), - cmpa_l_dpc_ad(0xb1fa, 0xf1ff, ea_dpc32_read, dbrr, gen_cmpl_dt_ad), + cmpa_l_dpc_ad(0xb1fa, 0xf1ff, ea_dpc32_read, dbrr, gen_cmpl_dt_ax), - cmpa_l_dpci_ad(0xb1fb, 0xf1ff, ea_dpci32_read, dbrr, gen_cmpl_dt_ad), + cmpa_l_dpci_ad(0xb1fb, 0xf1ff, ea_dpci32_read, dbrr, gen_cmpl_dt_ax), - cmpa_l_imm32_ad(0xb1fc, 0xf1ff, ea_imm32_read, dbrr, gen_cmpl_dt_ad), + cmpa_l_imm32_ad(0xb1fc, 0xf1ff, ea_imm32_read, dbrr, gen_cmpl_dt_ax), - and_b_ds_dd(0xc000, 0xf1f8, gen_andb_ds_dd, dbrr, dbrr), + and_b_ds_dd(0xc000, 0xf1f8, gen_andb_dy_dx, dbrr, dbrr), - and_b_ais_dd(0xc010, 0xf1f8, ea_ais8_read, dbrr, gen_andb_dt_dd), + and_b_ais_dd(0xc010, 0xf1f8, ea_ais8_read, dbrr, gen_andb_dt_dx), - and_b_aips_dd(0xc018, 0xf1f8, ea_aips8_read, dbrr, gen_andb_dt_dd), + and_b_aips_dd(0xc018, 0xf1f8, ea_aips8_read, dbrr, gen_andb_dt_dx), - and_b_pais_dd(0xc020, 0xf1f8, ea_pais8_read, dbrr, gen_andb_dt_dd), + and_b_pais_dd(0xc020, 0xf1f8, ea_pais8_read, dbrr, gen_andb_dt_dx), - and_b_das_dd(0xc028, 0xf1f8, ea_das8_read, dbrr, gen_andb_dt_dd), + and_b_das_dd(0xc028, 0xf1f8, ea_das8_read, dbrr, gen_andb_dt_dx), - and_b_dais_dd(0xc030, 0xf1f8, ea_dais8_read, dbrr, gen_andb_dt_dd), + and_b_dais_dd(0xc030, 0xf1f8, ea_dais8_read, dbrr, gen_andb_dt_dx), - and_b_adr16_dd(0xc038, 0xf1ff, ea_adr16s8_read, dbrr, gen_andb_dt_dd), + and_b_adr16_dd(0xc038, 0xf1ff, ea_adr16s8_read, dbrr, gen_andb_dt_dx), - and_b_adr32_dd(0xc039, 0xf1ff, ea_adr32s8_read, dbrr, gen_andb_dt_dd), + and_b_adr32_dd(0xc039, 0xf1ff, ea_adr32s8_read, dbrr, gen_andb_dt_dx), - and_b_dpc_dd(0xc03a, 0xf1ff, ea_dpc8_read, dbrr, gen_andb_dt_dd), + and_b_dpc_dd(0xc03a, 0xf1ff, ea_dpc8_read, dbrr, gen_andb_dt_dx), - and_b_dpci_dd(0xc03b, 0xf1ff, ea_dpci8_read, dbrr, gen_andb_dt_dd), + and_b_dpci_dd(0xc03b, 0xf1ff, ea_dpci8_read, dbrr, gen_andb_dt_dx), - and_b_imm8_dd(0xc03c, 0xf1ff, ea_imm8_read, dbrr, gen_andb_dt_dd), + and_b_imm8_dd(0xc03c, 0xf1ff, ea_imm8_read, dbrr, gen_andb_dt_dx), - and_w_ds_dd(0xc040, 0xf1f8, gen_andw_ds_dd, dbrr, dbrr), + and_w_ds_dd(0xc040, 0xf1f8, gen_andw_dy_dx, dbrr, dbrr), - and_w_ais_dd(0xc050, 0xf1f8, ea_ais16_read, dbrr, gen_andw_dt_dd), + and_w_ais_dd(0xc050, 0xf1f8, ea_ais16_read, dbrr, gen_andw_dt_dx), - and_w_aips_dd(0xc058, 0xf1f8, ea_aips16_read, dbrr, gen_andw_dt_dd), + and_w_aips_dd(0xc058, 0xf1f8, ea_aips16_read, dbrr, gen_andw_dt_dx), - and_w_pais_dd(0xc060, 0xf1f8, ea_pais16_read, dbrr, gen_andw_dt_dd), + and_w_pais_dd(0xc060, 0xf1f8, ea_pais16_read, dbrr, gen_andw_dt_dx), - and_w_das_dd(0xc068, 0xf1f8, ea_das16_read, dbrr, gen_andw_dt_dd), + and_w_das_dd(0xc068, 0xf1f8, ea_das16_read, dbrr, gen_andw_dt_dx), - and_w_dais_dd(0xc070, 0xf1f8, ea_dais16_read, dbrr, gen_andw_dt_dd), + and_w_dais_dd(0xc070, 0xf1f8, ea_dais16_read, dbrr, gen_andw_dt_dx), - and_w_adr16_dd(0xc078, 0xf1ff, ea_adr16s16_read, dbrr, gen_andw_dt_dd), + and_w_adr16_dd(0xc078, 0xf1ff, ea_adr16s16_read, dbrr, gen_andw_dt_dx), - and_w_adr32_dd(0xc079, 0xf1ff, ea_adr32s16_read, dbrr, gen_andw_dt_dd), + and_w_adr32_dd(0xc079, 0xf1ff, ea_adr32s16_read, dbrr, gen_andw_dt_dx), - and_w_dpc_dd(0xc07a, 0xf1ff, ea_dpc16_read, dbrr, gen_andw_dt_dd), + and_w_dpc_dd(0xc07a, 0xf1ff, ea_dpc16_read, dbrr, gen_andw_dt_dx), - and_w_dpci_dd(0xc07b, 0xf1ff, ea_dpci16_read, dbrr, gen_andw_dt_dd), + and_w_dpci_dd(0xc07b, 0xf1ff, ea_dpci16_read, dbrr, gen_andw_dt_dx), - and_w_imm16_dd(0xc07c, 0xf1ff, ea_imm16_read, dbrr, gen_andw_dt_dd), + and_w_imm16_dd(0xc07c, 0xf1ff, ea_imm16_read, dbrr, gen_andw_dt_dx), - and_l_ds_dd(0xc080, 0xf1f8, gen_andl_ds_dd, dbrr, dbrr), + and_l_ds_dd(0xc080, 0xf1f8, gen_andl_dy_dx, dbrr, dbrr), - and_l_ais_dd(0xc090, 0xf1f8, ea_ais32_read, dbrr, gen_andl_dt_dd), + and_l_ais_dd(0xc090, 0xf1f8, ea_ais32_read, dbrr, gen_andl_dt_dx), - and_l_aips_dd(0xc098, 0xf1f8, ea_aips32_read, dbrr, gen_andl_dt_dd), + and_l_aips_dd(0xc098, 0xf1f8, ea_aips32_read, dbrr, gen_andl_dt_dx), - and_l_pais_dd(0xc0a0, 0xf1f8, ea_pais32_read, dbrr, gen_andl_dt_dd), + and_l_pais_dd(0xc0a0, 0xf1f8, ea_pais32_read, dbrr, gen_andl_dt_dx), - and_l_das_dd(0xc0a8, 0xf1f8, ea_das32_read, dbrr, gen_andl_dt_dd), + and_l_das_dd(0xc0a8, 0xf1f8, ea_das32_read, dbrr, gen_andl_dt_dx), - and_l_dais_dd(0xc0b0, 0xf1f8, ea_dais32_read, dbrr, gen_andl_dt_dd), + and_l_dais_dd(0xc0b0, 0xf1f8, ea_dais32_read, dbrr, gen_andl_dt_dx), - and_l_adr16_dd(0xc0b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_andl_dt_dd), + and_l_adr16_dd(0xc0b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_andl_dt_dx), - and_l_adr32_dd(0xc0b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_andl_dt_dd), + and_l_adr32_dd(0xc0b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_andl_dt_dx), - and_l_dpc_dd(0xc0ba, 0xf1ff, ea_dpc32_read, dbrr, gen_andl_dt_dd), + and_l_dpc_dd(0xc0ba, 0xf1ff, ea_dpc32_read, dbrr, gen_andl_dt_dx), - and_l_dpci_dd(0xc0bb, 0xf1ff, ea_dpci32_read, dbrr, gen_andl_dt_dd), + and_l_dpci_dd(0xc0bb, 0xf1ff, ea_dpci32_read, dbrr, gen_andl_dt_dx), - and_l_imm32_dd(0xc0bc, 0xf1ff, ea_imm32_read, dbrr, gen_andl_dt_dd), + and_l_imm32_dd(0xc0bc, 0xf1ff, ea_imm32_read, dbrr, gen_andl_dt_dx), - mulu_w_ds(0xc0c0, 0xf1f8, gen_muluw_ds_dd, dbrr, dbrr), + mulu_w_ds(0xc0c0, 0xf1f8, gen_muluw_dy_dx, dbrr, dbrr), - mulu_w_ais(0xc0d0, 0xf1f8, ea_ais16_read, dbrr, gen_muluw_dt_dd), + mulu_w_ais(0xc0d0, 0xf1f8, ea_ais16_read, dbrr, gen_muluw_dt_dx), - mulu_w_aips(0xc0d8, 0xf1f8, ea_aips16_read, dbrr, gen_muluw_dt_dd), + mulu_w_aips(0xc0d8, 0xf1f8, ea_aips16_read, dbrr, gen_muluw_dt_dx), - mulu_w_pais(0xc0e0, 0xf1f8, ea_pais16_read, dbrr, gen_muluw_dt_dd), + mulu_w_pais(0xc0e0, 0xf1f8, ea_pais16_read, dbrr, gen_muluw_dt_dx), - mulu_w_das(0xc0e8, 0xf1f8, ea_das16_read, dbrr, gen_muluw_dt_dd), + mulu_w_das(0xc0e8, 0xf1f8, ea_das16_read, dbrr, gen_muluw_dt_dx), - mulu_w_dais(0xc0f0, 0xf1f8, ea_dais16_read, dbrr, gen_muluw_dt_dd), + mulu_w_dais(0xc0f0, 0xf1f8, ea_dais16_read, dbrr, gen_muluw_dt_dx), - mulu_w_adr16(0xc0f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_muluw_dt_dd), + mulu_w_adr16(0xc0f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_muluw_dt_dx), - mulu_w_adr32(0xc0f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_muluw_dt_dd), + mulu_w_adr32(0xc0f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_muluw_dt_dx), - mulu_w_dpc(0xc0fa, 0xf1ff, ea_dpc16_read, dbrr, gen_muluw_dt_dd), + mulu_w_dpc(0xc0fa, 0xf1ff, ea_dpc16_read, dbrr, gen_muluw_dt_dx), - mulu_w_dpci(0xc0fb, 0xf1ff, ea_dpci16_read, dbrr, gen_muluw_dt_dd), + mulu_w_dpci(0xc0fb, 0xf1ff, ea_dpci16_read, dbrr, gen_muluw_dt_dx), - mulu_w_imm16(0xc0fc, 0xf1ff, ea_imm16_read, dbrr, gen_muluw_dt_dd), + mulu_w_imm16(0xc0fc, 0xf1ff, ea_imm16_read, dbrr, gen_muluw_dt_dx), - abcd_ds_dd(0xc100, 0xf1f8, gen_abcdb_ds_dd, dbrr, dbrr), + abcd_ds_dd(0xc100, 0xf1f8, gen_abcdb_dy_dx, dbrr, dbrr), - abcd_pais_paid(0xc108, 0xf1f8, ea_pais8_read, gen_abcdb_im_ea, ea_paid8_read), + abcd_pais_paid(0xc108, 0xf1f8, ea_pais8_read, gen_abcdb_alub_dt, ea_paid8_read), - and_b_dd_ais(0xc110, 0xf1f8, ea_ais8_read, dbrr, gen_andb_dd_ea), + and_b_dd_ais(0xc110, 0xf1f8, ea_ais8_read, dbrr, gen_andb_dx_dt), - and_b_dd_aips(0xc118, 0xf1f8, ea_aips8_read, dbrr, gen_andb_dd_ea), + and_b_dd_aips(0xc118, 0xf1f8, ea_aips8_read, dbrr, gen_andb_dx_dt), - and_b_dd_pais(0xc120, 0xf1f8, ea_pais8_read, dbrr, gen_andb_dd_ea), + and_b_dd_pais(0xc120, 0xf1f8, ea_pais8_read, dbrr, gen_andb_dx_dt), - and_b_dd_das(0xc128, 0xf1f8, ea_das8_read, dbrr, gen_andb_dd_ea), + and_b_dd_das(0xc128, 0xf1f8, ea_das8_read, dbrr, gen_andb_dx_dt), - and_b_dd_dais(0xc130, 0xf1f8, ea_dais8_read, dbrr, gen_andb_dd_ea), + and_b_dd_dais(0xc130, 0xf1f8, ea_dais8_read, dbrr, gen_andb_dx_dt), - and_b_dd_adr16(0xc138, 0xf1ff, ea_adr16s8_read, dbrr, gen_andb_dd_ea), + and_b_dd_adr16(0xc138, 0xf1ff, ea_adr16s8_read, dbrr, gen_andb_dx_dt), - and_b_dd_adr32(0xc139, 0xf1ff, ea_adr32s8_read, dbrr, gen_andb_dd_ea), + and_b_dd_adr32(0xc139, 0xf1ff, ea_adr32s8_read, dbrr, gen_andb_dx_dt), exg_dd_ds(0xc140, 0xf1f8, op_exg_dd_ds, dbrr, dbrr), exg_ad_as(0xc148, 0xf1f8, op_exg_ad_as, dbrr, dbrr), - and_w_dd_ais(0xc150, 0xf1f8, ea_ais16_read, dbrr, gen_andw_dd_ea), + and_w_dd_ais(0xc150, 0xf1f8, ea_ais16_read, dbrr, gen_andw_dx_dt), - and_w_dd_aips(0xc158, 0xf1f8, ea_aips16_read, dbrr, gen_andw_dd_ea), + and_w_dd_aips(0xc158, 0xf1f8, ea_aips16_read, dbrr, gen_andw_dx_dt), - and_w_dd_pais(0xc160, 0xf1f8, ea_pais16_read, dbrr, gen_andw_dd_ea), + and_w_dd_pais(0xc160, 0xf1f8, ea_pais16_read, dbrr, gen_andw_dx_dt), - and_w_dd_das(0xc168, 0xf1f8, ea_das16_read, dbrr, gen_andw_dd_ea), + and_w_dd_das(0xc168, 0xf1f8, ea_das16_read, dbrr, gen_andw_dx_dt), - and_w_dd_dais(0xc170, 0xf1f8, ea_dais16_read, dbrr, gen_andw_dd_ea), + and_w_dd_dais(0xc170, 0xf1f8, ea_dais16_read, dbrr, gen_andw_dx_dt), - and_w_dd_adr16(0xc178, 0xf1ff, ea_adr16s16_read, dbrr, gen_andw_dd_ea), + and_w_dd_adr16(0xc178, 0xf1ff, ea_adr16s16_read, dbrr, gen_andw_dx_dt), - and_w_dd_adr32(0xc179, 0xf1ff, ea_adr32s16_read, dbrr, gen_andw_dd_ea), + and_w_dd_adr32(0xc179, 0xf1ff, ea_adr32s16_read, dbrr, gen_andw_dx_dt), exg_dd_as(0xc188, 0xf1f8, op_exg_dd_as, dbrr, dbrr), - and_l_dd_ais(0xc190, 0xf1f8, ea_ais32_read, dbrr, gen_andl_dd_ea), + and_l_dd_ais(0xc190, 0xf1f8, ea_ais32_read, dbrr, gen_andl_dx_dt), - and_l_dd_aips(0xc198, 0xf1f8, ea_aips32_read, dbrr, gen_andl_dd_ea), + and_l_dd_aips(0xc198, 0xf1f8, ea_aips32_read, dbrr, gen_andl_dx_dt), - and_l_dd_pais(0xc1a0, 0xf1f8, ea_pais32_read, dbrr, gen_andl_dd_ea), + and_l_dd_pais(0xc1a0, 0xf1f8, ea_pais32_read, dbrr, gen_andl_dx_dt), - and_l_dd_das(0xc1a8, 0xf1f8, ea_das32_read, dbrr, gen_andl_dd_ea), + and_l_dd_das(0xc1a8, 0xf1f8, ea_das32_read, dbrr, gen_andl_dx_dt), - and_l_dd_dais(0xc1b0, 0xf1f8, ea_dais32_read, dbrr, gen_andl_dd_ea), + and_l_dd_dais(0xc1b0, 0xf1f8, ea_dais32_read, dbrr, gen_andl_dx_dt), - and_l_dd_adr16(0xc1b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_andl_dd_ea), + and_l_dd_adr16(0xc1b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_andl_dx_dt), - and_l_dd_adr32(0xc1b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_andl_dd_ea), + and_l_dd_adr32(0xc1b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_andl_dx_dt), - muls_w_ds(0xc1c0, 0xf1f8, gen_mulsw_ds_dd, dbrr, dbrr), + muls_w_ds(0xc1c0, 0xf1f8, gen_mulsw_dy_dx, dbrr, dbrr), - muls_w_ais(0xc1d0, 0xf1f8, ea_ais16_read, dbrr, gen_mulsw_dt_dd), + muls_w_ais(0xc1d0, 0xf1f8, ea_ais16_read, dbrr, gen_mulsw_dt_dx), - muls_w_aips(0xc1d8, 0xf1f8, ea_aips16_read, dbrr, gen_mulsw_dt_dd), + muls_w_aips(0xc1d8, 0xf1f8, ea_aips16_read, dbrr, gen_mulsw_dt_dx), - muls_w_pais(0xc1e0, 0xf1f8, ea_pais16_read, dbrr, gen_mulsw_dt_dd), + muls_w_pais(0xc1e0, 0xf1f8, ea_pais16_read, dbrr, gen_mulsw_dt_dx), - muls_w_das(0xc1e8, 0xf1f8, ea_das16_read, dbrr, gen_mulsw_dt_dd), + muls_w_das(0xc1e8, 0xf1f8, ea_das16_read, dbrr, gen_mulsw_dt_dx), - muls_w_dais(0xc1f0, 0xf1f8, ea_dais16_read, dbrr, gen_mulsw_dt_dd), + muls_w_dais(0xc1f0, 0xf1f8, ea_dais16_read, dbrr, gen_mulsw_dt_dx), - muls_w_adr16(0xc1f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_mulsw_dt_dd), + muls_w_adr16(0xc1f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_mulsw_dt_dx), - muls_w_adr32(0xc1f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_mulsw_dt_dd), + muls_w_adr32(0xc1f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_mulsw_dt_dx), - muls_w_dpc(0xc1fa, 0xf1ff, ea_dpc16_read, dbrr, gen_mulsw_dt_dd), + muls_w_dpc(0xc1fa, 0xf1ff, ea_dpc16_read, dbrr, gen_mulsw_dt_dx), - muls_w_dpci(0xc1fb, 0xf1ff, ea_dpci16_read, dbrr, gen_mulsw_dt_dd), + muls_w_dpci(0xc1fb, 0xf1ff, ea_dpci16_read, dbrr, gen_mulsw_dt_dx), - muls_w_imm16(0xc1fc, 0xf1ff, ea_imm16_read, dbrr, gen_mulsw_dt_dd), + muls_w_imm16(0xc1fc, 0xf1ff, ea_imm16_read, dbrr, gen_mulsw_dt_dx), - add_b_ds_dd(0xd000, 0xf1f8, gen_addb_ds_dd, dbrr, dbrr), + add_b_ds_dd(0xd000, 0xf1f8, gen_addb_dy_dx, dbrr, dbrr), - add_b_ais_dd(0xd010, 0xf1f8, ea_ais8_read, dbrr, gen_addb_dt_dd), + add_b_ais_dd(0xd010, 0xf1f8, ea_ais8_read, dbrr, gen_addb_dt_dx), - add_b_aips_dd(0xd018, 0xf1f8, ea_aips8_read, dbrr, gen_addb_dt_dd), + add_b_aips_dd(0xd018, 0xf1f8, ea_aips8_read, dbrr, gen_addb_dt_dx), - add_b_pais_dd(0xd020, 0xf1f8, ea_pais8_read, dbrr, gen_addb_dt_dd), + add_b_pais_dd(0xd020, 0xf1f8, ea_pais8_read, dbrr, gen_addb_dt_dx), - add_b_das_dd(0xd028, 0xf1f8, ea_das8_read, dbrr, gen_addb_dt_dd), + add_b_das_dd(0xd028, 0xf1f8, ea_das8_read, dbrr, gen_addb_dt_dx), - add_b_dais_dd(0xd030, 0xf1f8, ea_dais8_read, dbrr, gen_addb_dt_dd), + add_b_dais_dd(0xd030, 0xf1f8, ea_dais8_read, dbrr, gen_addb_dt_dx), - add_b_adr16_dd(0xd038, 0xf1ff, ea_adr16s8_read, dbrr, gen_addb_dt_dd), + add_b_adr16_dd(0xd038, 0xf1ff, ea_adr16s8_read, dbrr, gen_addb_dt_dx), - add_b_adr32_dd(0xd039, 0xf1ff, ea_adr32s8_read, dbrr, gen_addb_dt_dd), + add_b_adr32_dd(0xd039, 0xf1ff, ea_adr32s8_read, dbrr, gen_addb_dt_dx), - add_b_dpc_dd(0xd03a, 0xf1ff, ea_dpc8_read, dbrr, gen_addb_dt_dd), + add_b_dpc_dd(0xd03a, 0xf1ff, ea_dpc8_read, dbrr, gen_addb_dt_dx), - add_b_dpci_dd(0xd03b, 0xf1ff, ea_dpci8_read, dbrr, gen_addb_dt_dd), + add_b_dpci_dd(0xd03b, 0xf1ff, ea_dpci8_read, dbrr, gen_addb_dt_dx), - add_b_imm8_dd(0xd03c, 0xf1ff, ea_imm8_read, dbrr, gen_addb_dt_dd), + add_b_imm8_dd(0xd03c, 0xf1ff, ea_imm8_read, dbrr, gen_addb_dt_dx), - add_w_ds_dd(0xd040, 0xf1f8, gen_addw_ds_dd, dbrr, dbrr), + add_w_ds_dd(0xd040, 0xf1f8, gen_addw_dy_dx, dbrr, dbrr), - add_w_as_dd(0xd048, 0xf1f8, gen_addw_as_dd, dbrr, dbrr), + add_w_as_dd(0xd048, 0xf1f8, gen_addw_ay_dx, dbrr, dbrr), - add_w_ais_dd(0xd050, 0xf1f8, ea_ais16_read, dbrr, gen_addw_dt_dd), + add_w_ais_dd(0xd050, 0xf1f8, ea_ais16_read, dbrr, gen_addw_dt_dx), - add_w_aips_dd(0xd058, 0xf1f8, ea_aips16_read, dbrr, gen_addw_dt_dd), + add_w_aips_dd(0xd058, 0xf1f8, ea_aips16_read, dbrr, gen_addw_dt_dx), - add_w_pais_dd(0xd060, 0xf1f8, ea_pais16_read, dbrr, gen_addw_dt_dd), + add_w_pais_dd(0xd060, 0xf1f8, ea_pais16_read, dbrr, gen_addw_dt_dx), - add_w_das_dd(0xd068, 0xf1f8, ea_das16_read, dbrr, gen_addw_dt_dd), + add_w_das_dd(0xd068, 0xf1f8, ea_das16_read, dbrr, gen_addw_dt_dx), - add_w_dais_dd(0xd070, 0xf1f8, ea_dais16_read, dbrr, gen_addw_dt_dd), + add_w_dais_dd(0xd070, 0xf1f8, ea_dais16_read, dbrr, gen_addw_dt_dx), - add_w_adr16_dd(0xd078, 0xf1ff, ea_adr16s16_read, dbrr, gen_addw_dt_dd), + add_w_adr16_dd(0xd078, 0xf1ff, ea_adr16s16_read, dbrr, gen_addw_dt_dx), - add_w_adr32_dd(0xd079, 0xf1ff, ea_adr32s16_read, dbrr, gen_addw_dt_dd), + add_w_adr32_dd(0xd079, 0xf1ff, ea_adr32s16_read, dbrr, gen_addw_dt_dx), - add_w_dpc_dd(0xd07a, 0xf1ff, ea_dpc16_read, dbrr, gen_addw_dt_dd), + add_w_dpc_dd(0xd07a, 0xf1ff, ea_dpc16_read, dbrr, gen_addw_dt_dx), - add_w_dpci_dd(0xd07b, 0xf1ff, ea_dpci16_read, dbrr, gen_addw_dt_dd), + add_w_dpci_dd(0xd07b, 0xf1ff, ea_dpci16_read, dbrr, gen_addw_dt_dx), - add_w_imm16_dd(0xd07c, 0xf1ff, ea_imm16_read, dbrr, gen_addw_dt_dd), + add_w_imm16_dd(0xd07c, 0xf1ff, ea_imm16_read, dbrr, gen_addw_dt_dx), - add_l_ds_dd(0xd080, 0xf1f8, gen_addl_ds_dd, dbrr, dbrr), + add_l_ds_dd(0xd080, 0xf1f8, gen_addl_dy_dx, dbrr, dbrr), - add_l_as_dd(0xd088, 0xf1f8, gen_addl_as_dd, dbrr, dbrr), + add_l_as_dd(0xd088, 0xf1f8, gen_addl_ay_dx, dbrr, dbrr), - add_l_ais_dd(0xd090, 0xf1f8, ea_ais32_read, dbrr, gen_addl_dt_dd), + add_l_ais_dd(0xd090, 0xf1f8, ea_ais32_read, dbrr, gen_addl_dt_dx), - add_l_aips_dd(0xd098, 0xf1f8, ea_aips32_read, dbrr, gen_addl_dt_dd), + add_l_aips_dd(0xd098, 0xf1f8, ea_aips32_read, dbrr, gen_addl_dt_dx), - add_l_pais_dd(0xd0a0, 0xf1f8, ea_pais32_read, dbrr, gen_addl_dt_dd), + add_l_pais_dd(0xd0a0, 0xf1f8, ea_pais32_read, dbrr, gen_addl_dt_dx), - add_l_das_dd(0xd0a8, 0xf1f8, ea_das32_read, dbrr, gen_addl_dt_dd), + add_l_das_dd(0xd0a8, 0xf1f8, ea_das32_read, dbrr, gen_addl_dt_dx), - add_l_dais_dd(0xd0b0, 0xf1f8, ea_dais32_read, dbrr, gen_addl_dt_dd), + add_l_dais_dd(0xd0b0, 0xf1f8, ea_dais32_read, dbrr, gen_addl_dt_dx), - add_l_adr16_dd(0xd0b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_addl_dt_dd), + add_l_adr16_dd(0xd0b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_addl_dt_dx), - add_l_adr32_dd(0xd0b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_addl_dt_dd), + add_l_adr32_dd(0xd0b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_addl_dt_dx), - add_l_dpc_dd(0xd0ba, 0xf1ff, ea_dpc32_read, dbrr, gen_addl_dt_dd), + add_l_dpc_dd(0xd0ba, 0xf1ff, ea_dpc32_read, dbrr, gen_addl_dt_dx), - add_l_dpci_dd(0xd0bb, 0xf1ff, ea_dpci32_read, dbrr, gen_addl_dt_dd), + add_l_dpci_dd(0xd0bb, 0xf1ff, ea_dpci32_read, dbrr, gen_addl_dt_dx), - add_l_imm32_dd(0xd0bc, 0xf1ff, ea_imm32_read, dbrr, gen_addl_dt_dd), + add_l_imm32_dd(0xd0bc, 0xf1ff, ea_imm32_read, dbrr, gen_addl_dt_dx), - adda_w_ds_ad(0xd0c0, 0xf1f8, gen_addw_ds_ad, dbrr, dbrr), + adda_w_ds_ad(0xd0c0, 0xf1f8, gen_addw_dy_ax, dbrr, dbrr), - adda_w_as_ad(0xd0c8, 0xf1f8, gen_addw_as_ad, dbrr, dbrr), + adda_w_as_ad(0xd0c8, 0xf1f8, gen_addw_ay_ax, dbrr, dbrr), - adda_w_ais_ad(0xd0d0, 0xf1f8, ea_ais16_read, dbrr, gen_addw_dt_ad), + adda_w_ais_ad(0xd0d0, 0xf1f8, ea_ais16_read, dbrr, gen_addw_dt_ax), - adda_w_aips_ad(0xd0d8, 0xf1f8, ea_aips16_read, dbrr, gen_addw_dt_ad), + adda_w_aips_ad(0xd0d8, 0xf1f8, ea_aips16_read, dbrr, gen_addw_dt_ax), - adda_w_pais_ad(0xd0e0, 0xf1f8, ea_pais16_read, dbrr, gen_addw_dt_ad), + adda_w_pais_ad(0xd0e0, 0xf1f8, ea_pais16_read, dbrr, gen_addw_dt_ax), - adda_w_das_ad(0xd0e8, 0xf1f8, ea_das16_read, dbrr, gen_addw_dt_ad), + adda_w_das_ad(0xd0e8, 0xf1f8, ea_das16_read, dbrr, gen_addw_dt_ax), - adda_w_dais_ad(0xd0f0, 0xf1f8, ea_dais16_read, dbrr, gen_addw_dt_ad), + adda_w_dais_ad(0xd0f0, 0xf1f8, ea_dais16_read, dbrr, gen_addw_dt_ax), - adda_w_adr16_ad(0xd0f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_addw_dt_ad), + adda_w_adr16_ad(0xd0f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_addw_dt_ax), - adda_w_adr32_ad(0xd0f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_addw_dt_ad), + adda_w_adr32_ad(0xd0f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_addw_dt_ax), - adda_w_dpc_ad(0xd0fa, 0xf1ff, ea_dpc16_read, dbrr, gen_addw_dt_ad), + adda_w_dpc_ad(0xd0fa, 0xf1ff, ea_dpc16_read, dbrr, gen_addw_dt_ax), - adda_w_dpci_ad(0xd0fb, 0xf1ff, ea_dpci16_read, dbrr, gen_addw_dt_ad), + adda_w_dpci_ad(0xd0fb, 0xf1ff, ea_dpci16_read, dbrr, gen_addw_dt_ax), - adda_w_imm16_ad(0xd0fc, 0xf1ff, ea_imm16_read, dbrr, gen_addw_dt_ad), + adda_w_imm16_ad(0xd0fc, 0xf1ff, ea_imm16_read, dbrr, gen_addw_dt_ax), - addx_b_ds_dd(0xd100, 0xf1f8, gen_addxb_ds_dd, dbrr, dbrr), + addx_b_ds_dd(0xd100, 0xf1f8, gen_addxb_dy_dx, dbrr, dbrr), - addx_b_pais_paid(0xd108, 0xf1f8, ea_pais8_read, gen_addxb_im_ea, ea_paid8_read), + addx_b_pais_paid(0xd108, 0xf1f8, ea_pais8_read, gen_addxb_alub_dt, ea_paid8_read), - add_b_dd_ais(0xd110, 0xf1f8, ea_ais8_read, dbrr, gen_addb_dd_ea), + add_b_dd_ais(0xd110, 0xf1f8, ea_ais8_read, dbrr, gen_addb_dx_dt), - add_b_dd_aips(0xd118, 0xf1f8, ea_aips8_read, dbrr, gen_addb_dd_ea), + add_b_dd_aips(0xd118, 0xf1f8, ea_aips8_read, dbrr, gen_addb_dx_dt), - add_b_dd_pais(0xd120, 0xf1f8, ea_pais8_read, dbrr, gen_addb_dd_ea), + add_b_dd_pais(0xd120, 0xf1f8, ea_pais8_read, dbrr, gen_addb_dx_dt), - add_b_dd_das(0xd128, 0xf1f8, ea_das8_read, dbrr, gen_addb_dd_ea), + add_b_dd_das(0xd128, 0xf1f8, ea_das8_read, dbrr, gen_addb_dx_dt), - add_b_dd_dais(0xd130, 0xf1f8, ea_dais8_read, dbrr, gen_addb_dd_ea), + add_b_dd_dais(0xd130, 0xf1f8, ea_dais8_read, dbrr, gen_addb_dx_dt), - add_b_dd_adr16(0xd138, 0xf1ff, ea_adr16s8_read, dbrr, gen_addb_dd_ea), + add_b_dd_adr16(0xd138, 0xf1ff, ea_adr16s8_read, dbrr, gen_addb_dx_dt), - add_b_dd_adr32(0xd139, 0xf1ff, ea_adr32s8_read, dbrr, gen_addb_dd_ea), + add_b_dd_adr32(0xd139, 0xf1ff, ea_adr32s8_read, dbrr, gen_addb_dx_dt), - addx_w_ds_dd(0xd140, 0xf1f8, gen_addxw_ds_dd, dbrr, dbrr), + addx_w_ds_dd(0xd140, 0xf1f8, gen_addxw_dy_dx, dbrr, dbrr), - addx_w_pais_paid(0xd148, 0xf1f8, ea_pais16_read, gen_addxw_im_ea, ea_paid16_read), + addx_w_pais_paid(0xd148, 0xf1f8, ea_pais16_read, gen_addxw_alub_dt, ea_paid16_read), - add_w_dd_ais(0xd150, 0xf1f8, ea_ais16_read, dbrr, gen_addw_dd_ea), + add_w_dd_ais(0xd150, 0xf1f8, ea_ais16_read, dbrr, gen_addw_dx_dt), - add_w_dd_aips(0xd158, 0xf1f8, ea_aips16_read, dbrr, gen_addw_dd_ea), + add_w_dd_aips(0xd158, 0xf1f8, ea_aips16_read, dbrr, gen_addw_dx_dt), - add_w_dd_pais(0xd160, 0xf1f8, ea_pais16_read, dbrr, gen_addw_dd_ea), + add_w_dd_pais(0xd160, 0xf1f8, ea_pais16_read, dbrr, gen_addw_dx_dt), - add_w_dd_das(0xd168, 0xf1f8, ea_das16_read, dbrr, gen_addw_dd_ea), + add_w_dd_das(0xd168, 0xf1f8, ea_das16_read, dbrr, gen_addw_dx_dt), - add_w_dd_dais(0xd170, 0xf1f8, ea_dais16_read, dbrr, gen_addw_dd_ea), + add_w_dd_dais(0xd170, 0xf1f8, ea_dais16_read, dbrr, gen_addw_dx_dt), - add_w_dd_adr16(0xd178, 0xf1ff, ea_adr16s16_read, dbrr, gen_addw_dd_ea), + add_w_dd_adr16(0xd178, 0xf1ff, ea_adr16s16_read, dbrr, gen_addw_dx_dt), - add_w_dd_adr32(0xd179, 0xf1ff, ea_adr32s16_read, dbrr, gen_addw_dd_ea), + add_w_dd_adr32(0xd179, 0xf1ff, ea_adr32s16_read, dbrr, gen_addw_dx_dt), - addx_l_ds_dd(0xd180, 0xf1f8, gen_addxl_ds_dd, dbrr, dbrr), + addx_l_ds_dd(0xd180, 0xf1f8, gen_addxl_dy_dx, dbrr, dbrr), - addx_l_pais_paid(0xd188, 0xf1f8, ea_pais32_read, gen_addxl_im_ea, ea_paid32_read), + addx_l_pais_paid(0xd188, 0xf1f8, ea_pais32_read, gen_addxl_alub_dt, ea_paid32_read), - add_l_dd_ais(0xd190, 0xf1f8, ea_ais32_read, dbrr, gen_addl_dd_ea), + add_l_dd_ais(0xd190, 0xf1f8, ea_ais32_read, dbrr, gen_addl_dx_dt), - add_l_dd_aips(0xd198, 0xf1f8, ea_aips32_read, dbrr, gen_addl_dd_ea), + add_l_dd_aips(0xd198, 0xf1f8, ea_aips32_read, dbrr, gen_addl_dx_dt), - add_l_dd_pais(0xd1a0, 0xf1f8, ea_pais32_read, dbrr, gen_addl_dd_ea), + add_l_dd_pais(0xd1a0, 0xf1f8, ea_pais32_read, dbrr, gen_addl_dx_dt), - add_l_dd_das(0xd1a8, 0xf1f8, ea_das32_read, dbrr, gen_addl_dd_ea), + add_l_dd_das(0xd1a8, 0xf1f8, ea_das32_read, dbrr, gen_addl_dx_dt), - add_l_dd_dais(0xd1b0, 0xf1f8, ea_dais32_read, dbrr, gen_addl_dd_ea), + add_l_dd_dais(0xd1b0, 0xf1f8, ea_dais32_read, dbrr, gen_addl_dx_dt), - add_l_dd_adr16(0xd1b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_addl_dd_ea), + add_l_dd_adr16(0xd1b8, 0xf1ff, ea_adr16s32_read, dbrr, gen_addl_dx_dt), - add_l_dd_adr32(0xd1b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_addl_dd_ea), + add_l_dd_adr32(0xd1b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_addl_dx_dt), - adda_l_ds_ad(0xd1c0, 0xf1f8, gen_addl_ds_ad, dbrr, dbrr), + adda_l_ds_ad(0xd1c0, 0xf1f8, gen_addl_dy_ax, dbrr, dbrr), - adda_l_as_ad(0xd1c8, 0xf1f8, gen_addl_as_ad, dbrr, dbrr), + adda_l_as_ad(0xd1c8, 0xf1f8, gen_addl_ay_ax, dbrr, dbrr), - adda_l_ais_ad(0xd1d0, 0xf1f8, ea_ais32_read, dbrr, gen_addl_dt_ad), + adda_l_ais_ad(0xd1d0, 0xf1f8, ea_ais32_read, dbrr, gen_addl_dt_ax), - adda_l_aips_ad(0xd1d8, 0xf1f8, ea_aips32_read, dbrr, gen_addl_dt_ad), + adda_l_aips_ad(0xd1d8, 0xf1f8, ea_aips32_read, dbrr, gen_addl_dt_ax), - adda_l_pais_ad(0xd1e0, 0xf1f8, ea_pais32_read, dbrr, gen_addl_dt_ad), + adda_l_pais_ad(0xd1e0, 0xf1f8, ea_pais32_read, dbrr, gen_addl_dt_ax), - adda_l_das_ad(0xd1e8, 0xf1f8, ea_das32_read, dbrr, gen_addl_dt_ad), + adda_l_das_ad(0xd1e8, 0xf1f8, ea_das32_read, dbrr, gen_addl_dt_ax), - adda_l_dais_ad(0xd1f0, 0xf1f8, ea_dais32_read, dbrr, gen_addl_dt_ad), + adda_l_dais_ad(0xd1f0, 0xf1f8, ea_dais32_read, dbrr, gen_addl_dt_ax), - adda_l_adr16_ad(0xd1f8, 0xf1ff, ea_adr16s32_read, dbrr, gen_addl_dt_ad), + adda_l_adr16_ad(0xd1f8, 0xf1ff, ea_adr16s32_read, dbrr, gen_addl_dt_ax), - adda_l_adr32_ad(0xd1f9, 0xf1ff, ea_adr32s32_read, dbrr, gen_addl_dt_ad), + adda_l_adr32_ad(0xd1f9, 0xf1ff, ea_adr32s32_read, dbrr, gen_addl_dt_ax), - adda_l_dpc_ad(0xd1fa, 0xf1ff, ea_dpc32_read, dbrr, gen_addl_dt_ad), + adda_l_dpc_ad(0xd1fa, 0xf1ff, ea_dpc32_read, dbrr, gen_addl_dt_ax), - adda_l_dpci_ad(0xd1fb, 0xf1ff, ea_dpci32_read, dbrr, gen_addl_dt_ad), + adda_l_dpci_ad(0xd1fb, 0xf1ff, ea_dpci32_read, dbrr, gen_addl_dt_ax), - adda_l_imm32_ad(0xd1fc, 0xf1ff, ea_imm32_read, dbrr, gen_addl_dt_ad), + adda_l_imm32_ad(0xd1fc, 0xf1ff, ea_imm32_read, dbrr, gen_addl_dt_ax), - asr_b_imm3_ds(0xe000, 0xf1f8, gen_asrb_ir_ds, dbrr, dbrr), + asr_b_imm3_ds(0xe000, 0xf1f8, gen_asrb_ir_dy, dbrr, dbrr), - lsr_b_imm3_ds(0xe008, 0xf1f8, gen_lsrb_ir_ds, dbrr, dbrr), + lsr_b_imm3_ds(0xe008, 0xf1f8, gen_lsrb_ir_dy, dbrr, dbrr), - ror_b_imm3_ds(0xe018, 0xf1f8, gen_rorb_ir_ds, dbrr, dbrr), + ror_b_imm3_ds(0xe018, 0xf1f8, gen_rorb_ir_dy, dbrr, dbrr), - asr_b_dd_ds(0xe020, 0xf1f8, gen_asrb_dd_ds, dbrr, dbrr), + asr_b_dd_ds(0xe020, 0xf1f8, gen_asrb_dx_dy, dbrr, dbrr), - lsr_b_dd_ds(0xe028, 0xf1f8, gen_lsrb_dd_ds, dbrr, dbrr), + lsr_b_dd_ds(0xe028, 0xf1f8, gen_lsrb_dx_dy, dbrr, dbrr), - ror_b_dd_ds(0xe038, 0xf1f8, gen_rorb_dd_ds, dbrr, dbrr), + ror_b_dd_ds(0xe038, 0xf1f8, gen_rorb_dx_dy, dbrr, dbrr), - asr_w_imm3_ds(0xe040, 0xf1f8, gen_asrw_ir_ds, dbrr, dbrr), + asr_w_imm3_ds(0xe040, 0xf1f8, gen_asrw_ir_dy, dbrr, dbrr), - lsr_w_imm3_ds(0xe048, 0xf1f8, gen_lsrw_ir_ds, dbrr, dbrr), + lsr_w_imm3_ds(0xe048, 0xf1f8, gen_lsrw_ir_dy, dbrr, dbrr), - ror_w_imm3_ds(0xe058, 0xf1f8, gen_rorw_ir_ds, dbrr, dbrr), + ror_w_imm3_ds(0xe058, 0xf1f8, gen_rorw_ir_dy, dbrr, dbrr), - asr_w_dd_ds(0xe060, 0xf1f8, gen_asrw_dd_ds, dbrr, dbrr), + asr_w_dd_ds(0xe060, 0xf1f8, gen_asrw_dx_dy, dbrr, dbrr), - lsr_w_dd_ds(0xe068, 0xf1f8, gen_lsrw_dd_ds, dbrr, dbrr), + lsr_w_dd_ds(0xe068, 0xf1f8, gen_lsrw_dx_dy, dbrr, dbrr), - ror_w_dd_ds(0xe078, 0xf1f8, gen_rorw_dd_ds, dbrr, dbrr), + ror_w_dd_ds(0xe078, 0xf1f8, gen_rorw_dx_dy, dbrr, dbrr), - asr_l_imm3_ds(0xe080, 0xf1f8, gen_asrl_ir_ds, dbrr, dbrr), + asr_l_imm3_ds(0xe080, 0xf1f8, gen_asrl_ir_dy, dbrr, dbrr), - lsr_l_imm3_ds(0xe088, 0xf1f8, gen_lsrl_ir_ds, dbrr, dbrr), + lsr_l_imm3_ds(0xe088, 0xf1f8, gen_lsrl_ir_dy, dbrr, dbrr), - ror_l_imm3_ds(0xe098, 0xf1f8, gen_rorl_ir_ds, dbrr, dbrr), + ror_l_imm3_ds(0xe098, 0xf1f8, gen_rorl_ir_dy, dbrr, dbrr), - asr_l_dd_ds(0xe0a0, 0xf1f8, gen_asrl_dd_ds, dbrr, dbrr), + asr_l_dd_ds(0xe0a0, 0xf1f8, gen_asrl_dx_dy, dbrr, dbrr), - lsr_l_dd_ds(0xe0a8, 0xf1f8, gen_lsrl_dd_ds, dbrr, dbrr), + lsr_l_dd_ds(0xe0a8, 0xf1f8, gen_lsrl_dx_dy, dbrr, dbrr), - ror_l_dd_ds(0xe0b8, 0xf1f8, gen_rorl_dd_ds, dbrr, dbrr), + ror_l_dd_ds(0xe0b8, 0xf1f8, gen_rorl_dx_dy, dbrr, dbrr), - asr_ais(0xe0d0, 0xfff8, ea_ais16_read, dbrr, gen_asrw_ea), + asr_ais(0xe0d0, 0xfff8, ea_ais16_read, dbrr, gen_asrw_dt), - asr_aips(0xe0d8, 0xfff8, ea_aips16_read, dbrr, gen_asrw_ea), + asr_aips(0xe0d8, 0xfff8, ea_aips16_read, dbrr, gen_asrw_dt), - asr_pais(0xe0e0, 0xfff8, ea_pais16_read, dbrr, gen_asrw_ea), + asr_pais(0xe0e0, 0xfff8, ea_pais16_read, dbrr, gen_asrw_dt), - asr_das(0xe0e8, 0xfff8, ea_das16_read, dbrr, gen_asrw_ea), + asr_das(0xe0e8, 0xfff8, ea_das16_read, dbrr, gen_asrw_dt), - asr_dais(0xe0f0, 0xfff8, ea_dais16_read, dbrr, gen_asrw_ea), + asr_dais(0xe0f0, 0xfff8, ea_dais16_read, dbrr, gen_asrw_dt), - asr_adr16(0xe0f8, 0xffff, ea_adr16s16_read, dbrr, gen_asrw_ea), + asr_adr16(0xe0f8, 0xffff, ea_adr16s16_read, dbrr, gen_asrw_dt), - asr_adr32(0xe0f9, 0xffff, ea_adr32s16_read, dbrr, gen_asrw_ea), + asr_adr32(0xe0f9, 0xffff, ea_adr32s16_read, dbrr, gen_asrw_dt), - asl_b_imm3_ds(0xe100, 0xf1f8, gen_aslb_ir_ds, dbrr, dbrr), + asl_b_imm3_ds(0xe100, 0xf1f8, gen_aslb_ir_dy, dbrr, dbrr), - lsl_b_imm3_ds(0xe108, 0xf1f8, gen_lslb_ir_ds, dbrr, dbrr), + lsl_b_imm3_ds(0xe108, 0xf1f8, gen_lslb_ir_dy, dbrr, dbrr), - rol_b_imm3_ds(0xe118, 0xf1f8, gen_rolb_ir_ds, dbrr, dbrr), + rol_b_imm3_ds(0xe118, 0xf1f8, gen_rolb_ir_dy, dbrr, dbrr), - asl_b_dd_ds(0xe120, 0xf1f8, gen_aslb_dd_ds, dbrr, dbrr), + asl_b_dd_ds(0xe120, 0xf1f8, gen_aslb_dx_dy, dbrr, dbrr), - lsl_b_dd_ds(0xe128, 0xf1f8, gen_lslb_dd_ds, dbrr, dbrr), + lsl_b_dd_ds(0xe128, 0xf1f8, gen_lslb_dx_dy, dbrr, dbrr), - rol_b_dd_ds(0xe138, 0xf1f8, gen_rolb_dd_ds, dbrr, dbrr), + rol_b_dd_ds(0xe138, 0xf1f8, gen_rolb_dx_dy, dbrr, dbrr), - asl_w_imm3_ds(0xe140, 0xf1f8, gen_aslw_ir_ds, dbrr, dbrr), + asl_w_imm3_ds(0xe140, 0xf1f8, gen_aslw_ir_dy, dbrr, dbrr), - lsl_w_imm3_ds(0xe148, 0xf1f8, gen_lslw_ir_ds, dbrr, dbrr), + lsl_w_imm3_ds(0xe148, 0xf1f8, gen_lslw_ir_dy, dbrr, dbrr), - rol_w_imm3_ds(0xe158, 0xf1f8, gen_rolw_ir_ds, dbrr, dbrr), + rol_w_imm3_ds(0xe158, 0xf1f8, gen_rolw_ir_dy, dbrr, dbrr), - asl_w_dd_ds(0xe160, 0xf1f8, gen_aslw_dd_ds, dbrr, dbrr), + asl_w_dd_ds(0xe160, 0xf1f8, gen_aslw_dx_dy, dbrr, dbrr), - lsl_w_dd_ds(0xe168, 0xf1f8, gen_lslw_dd_ds, dbrr, dbrr), + lsl_w_dd_ds(0xe168, 0xf1f8, gen_lslw_dx_dy, dbrr, dbrr), - rol_w_dd_ds(0xe178, 0xf1f8, gen_rolw_dd_ds, dbrr, dbrr), + rol_w_dd_ds(0xe178, 0xf1f8, gen_rolw_dx_dy, dbrr, dbrr), - asl_l_imm3_ds(0xe180, 0xf1f8, gen_asll_ir_ds, dbrr, dbrr), + asl_l_imm3_ds(0xe180, 0xf1f8, gen_asll_ir_dy, dbrr, dbrr), - lsl_l_imm3_ds(0xe188, 0xf1f8, gen_lsll_ir_ds, dbrr, dbrr), + lsl_l_imm3_ds(0xe188, 0xf1f8, gen_lsll_ir_dy, dbrr, dbrr), - rol_l_imm3_ds(0xe198, 0xf1f8, gen_roll_ir_ds, dbrr, dbrr), + rol_l_imm3_ds(0xe198, 0xf1f8, gen_roll_ir_dy, dbrr, dbrr), - asl_l_dd_ds(0xe1a0, 0xf1f8, gen_asll_dd_ds, dbrr, dbrr), + asl_l_dd_ds(0xe1a0, 0xf1f8, gen_asll_dx_dy, dbrr, dbrr), - lsl_l_dd_ds(0xe1a8, 0xf1f8, gen_lsll_dd_ds, dbrr, dbrr), + lsl_l_dd_ds(0xe1a8, 0xf1f8, gen_lsll_dx_dy, dbrr, dbrr), - rol_l_dd_ds(0xe1b8, 0xf1f8, gen_roll_dd_ds, dbrr, dbrr), + rol_l_dd_ds(0xe1b8, 0xf1f8, gen_roll_dx_dy, dbrr, dbrr), - asl_ais(0xe1d0, 0xfff8, ea_ais16_read, dbrr, gen_aslw_ea), + asl_ais(0xe1d0, 0xfff8, ea_ais16_read, dbrr, gen_aslw_dt), - asl_aips(0xe1d8, 0xfff8, ea_aips16_read, dbrr, gen_aslw_ea), + asl_aips(0xe1d8, 0xfff8, ea_aips16_read, dbrr, gen_aslw_dt), - asl_pais(0xe1e0, 0xfff8, ea_pais16_read, dbrr, gen_aslw_ea), + asl_pais(0xe1e0, 0xfff8, ea_pais16_read, dbrr, gen_aslw_dt), - asl_das(0xe1e8, 0xfff8, ea_das16_read, dbrr, gen_aslw_ea), + asl_das(0xe1e8, 0xfff8, ea_das16_read, dbrr, gen_aslw_dt), - asl_dais(0xe1f0, 0xfff8, ea_dais16_read, dbrr, gen_aslw_ea), + asl_dais(0xe1f0, 0xfff8, ea_dais16_read, dbrr, gen_aslw_dt), - asl_adr16(0xe1f8, 0xffff, ea_adr16s16_read, dbrr, gen_aslw_ea), + asl_adr16(0xe1f8, 0xffff, ea_adr16s16_read, dbrr, gen_aslw_dt), - asl_adr32(0xe1f9, 0xffff, ea_adr32s16_read, dbrr, gen_aslw_ea), + asl_adr32(0xe1f9, 0xffff, ea_adr32s16_read, dbrr, gen_aslw_dt), - lsr_ais(0xe2d0, 0xfff8, ea_ais16_read, dbrr, gen_lsrw_ea), + lsr_ais(0xe2d0, 0xfff8, ea_ais16_read, dbrr, gen_lsrw_dt), - lsr_aips(0xe2d8, 0xfff8, ea_aips16_read, dbrr, gen_lsrw_ea), + lsr_aips(0xe2d8, 0xfff8, ea_aips16_read, dbrr, gen_lsrw_dt), - lsr_pais(0xe2e0, 0xfff8, ea_pais16_read, dbrr, gen_lsrw_ea), + lsr_pais(0xe2e0, 0xfff8, ea_pais16_read, dbrr, gen_lsrw_dt), - lsr_das(0xe2e8, 0xfff8, ea_das16_read, dbrr, gen_lsrw_ea), + lsr_das(0xe2e8, 0xfff8, ea_das16_read, dbrr, gen_lsrw_dt), - lsr_dais(0xe2f0, 0xfff8, ea_dais16_read, dbrr, gen_lsrw_ea), + lsr_dais(0xe2f0, 0xfff8, ea_dais16_read, dbrr, gen_lsrw_dt), - lsr_adr16(0xe2f8, 0xffff, ea_adr16s16_read, dbrr, gen_lsrw_ea), + lsr_adr16(0xe2f8, 0xffff, ea_adr16s16_read, dbrr, gen_lsrw_dt), - lsr_adr32(0xe2f9, 0xffff, ea_adr32s16_read, dbrr, gen_lsrw_ea), + lsr_adr32(0xe2f9, 0xffff, ea_adr32s16_read, dbrr, gen_lsrw_dt), - lsl_ais(0xe3d0, 0xfff8, ea_ais16_read, dbrr, gen_lslw_ea), + lsl_ais(0xe3d0, 0xfff8, ea_ais16_read, dbrr, gen_lslw_dt), - lsl_aips(0xe3d8, 0xfff8, ea_aips16_read, dbrr, gen_lslw_ea), + lsl_aips(0xe3d8, 0xfff8, ea_aips16_read, dbrr, gen_lslw_dt), - lsl_pais(0xe3e0, 0xfff8, ea_pais16_read, dbrr, gen_lslw_ea), + lsl_pais(0xe3e0, 0xfff8, ea_pais16_read, dbrr, gen_lslw_dt), - lsl_das(0xe3e8, 0xfff8, ea_das16_read, dbrr, gen_lslw_ea), + lsl_das(0xe3e8, 0xfff8, ea_das16_read, dbrr, gen_lslw_dt), - lsl_dais(0xe3f0, 0xfff8, ea_dais16_read, dbrr, gen_lslw_ea), + lsl_dais(0xe3f0, 0xfff8, ea_dais16_read, dbrr, gen_lslw_dt), - lsl_adr16(0xe3f8, 0xffff, ea_adr16s16_read, dbrr, gen_lslw_ea), + lsl_adr16(0xe3f8, 0xffff, ea_adr16s16_read, dbrr, gen_lslw_dt), - lsl_adr32(0xe3f9, 0xffff, ea_adr32s16_read, dbrr, gen_lslw_ea), + lsl_adr32(0xe3f9, 0xffff, ea_adr32s16_read, dbrr, gen_lslw_dt), - ror_ais(0xe6d0, 0xfff8, ea_ais16_read, dbrr, gen_rorw_ea), + ror_ais(0xe6d0, 0xfff8, ea_ais16_read, dbrr, gen_rorw_dt), - ror_aips(0xe6d8, 0xfff8, ea_aips16_read, dbrr, gen_rorw_ea), + ror_aips(0xe6d8, 0xfff8, ea_aips16_read, dbrr, gen_rorw_dt), - ror_pais(0xe6e0, 0xfff8, ea_pais16_read, dbrr, gen_rorw_ea), + ror_pais(0xe6e0, 0xfff8, ea_pais16_read, dbrr, gen_rorw_dt), - ror_das(0xe6e8, 0xfff8, ea_das16_read, dbrr, gen_rorw_ea), + ror_das(0xe6e8, 0xfff8, ea_das16_read, dbrr, gen_rorw_dt), - ror_dais(0xe6f0, 0xfff8, ea_dais16_read, dbrr, gen_rorw_ea), + ror_dais(0xe6f0, 0xfff8, ea_dais16_read, dbrr, gen_rorw_dt), - ror_adr16(0xe6f8, 0xffff, ea_adr16s16_read, dbrr, gen_rorw_ea), + ror_adr16(0xe6f8, 0xffff, ea_adr16s16_read, dbrr, gen_rorw_dt), - ror_adr32(0xe6f9, 0xffff, ea_adr32s16_read, dbrr, gen_rorw_ea), + ror_adr32(0xe6f9, 0xffff, ea_adr32s16_read, dbrr, gen_rorw_dt), - rol_ais(0xe7d0, 0xfff8, ea_ais16_read, dbrr, gen_rolw_ea), + rol_ais(0xe7d0, 0xfff8, ea_ais16_read, dbrr, gen_rolw_dt), - rol_aips(0xe7d8, 0xfff8, ea_aips16_read, dbrr, gen_rolw_ea), + rol_aips(0xe7d8, 0xfff8, ea_aips16_read, dbrr, gen_rolw_dt), - rol_pais(0xe7e0, 0xfff8, ea_pais16_read, dbrr, gen_rolw_ea), + rol_pais(0xe7e0, 0xfff8, ea_pais16_read, dbrr, gen_rolw_dt), - rol_das(0xe7e8, 0xfff8, ea_das16_read, dbrr, gen_rolw_ea), + rol_das(0xe7e8, 0xfff8, ea_das16_read, dbrr, gen_rolw_dt), - rol_dais(0xe7f0, 0xfff8, ea_dais16_read, dbrr, gen_rolw_ea), + rol_dais(0xe7f0, 0xfff8, ea_dais16_read, dbrr, gen_rolw_dt), - rol_adr16(0xe7f8, 0xffff, ea_adr16s16_read, dbrr, gen_rolw_ea), + rol_adr16(0xe7f8, 0xffff, ea_adr16s16_read, dbrr, gen_rolw_dt), - rol_adr32(0xe7f9, 0xffff, ea_adr32s16_read, dbrr, gen_rolw_ea), + rol_adr32(0xe7f9, 0xffff, ea_adr32s16_read, dbrr, gen_rolw_dt), linef_imm12(0xf000, 0xf000, op_linef, dbrr, dbrr); diff --git a/miggy-emu/src/test/java/miggy/cpupoet/CoreTest.java b/miggy-emu/src/test/java/miggy/cpupoet/CoreTest.java index 8c59db9..42bc3a0 100644 --- a/miggy-emu/src/test/java/miggy/cpupoet/CoreTest.java +++ b/miggy-emu/src/test/java/miggy/cpupoet/CoreTest.java @@ -44,7 +44,7 @@ public class CoreTest extends Core { for (int i = 0; i < numTests; i++) { boolean skip = checkSkip(i, skips); - if ((i == 40) && "MOVEM.w".equals(name)) { + if ((i == 295) && "MOVE.w".equals(name)) { toString(); } executeBinTest(buffer, skip);