diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java index bc9bb89..11db238 100644 --- a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java +++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java @@ -1592,6 +1592,7 @@ public class CoreGenerator { addBeginFormattedControlFlow("if (word_chk(dar[ry], dar[rx]))"); settvn(6); addFormattedMicroInsn("mpc = (sswi & 0x%04x) != 0 ? trap2000 : trap0000", SSWI_FMT2); + addFormattedMicroInsn("continue"); addEndControlFlow(); microprefetch(true, null); // prefetch ir from pc and resume execution @@ -1600,6 +1601,7 @@ public class CoreGenerator { addBeginFormattedControlFlow("if (word_chk(dt, dar[rx]))"); settvn(6); addFormattedMicroInsn("mpc = (sswi & 0x%04x) != 0 ? trap2000 : trap0000", SSWI_FMT2); + addFormattedMicroInsn("continue"); addEndControlFlow(); microprefetch(true, null); // prefetch ir from pc and resume execution @@ -2545,11 +2547,13 @@ public class CoreGenerator { addState("op_bcc16"); addBeginFormattedControlFlow("if (!testCC((ir & 0x0f00) >> 8))"); + addFormattedMicroInsn("scan += 2"); consume(10, 2, 0); microprefetch(true, null); // prefetch ir from pc and resume execution addEndControlFlow(); addState("op_bra16"); + anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, null); consume(10, 2, 0); addFormattedMicroInsn("scan = (short) dt"); addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow @@ -2557,11 +2561,19 @@ public class CoreGenerator { addState("op_bcc32"); addBeginFormattedControlFlow("if (!testCC((ir & 0x0f00) >> 8))"); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_DNGR); + addFormattedMicroInsn("scan += 4"); + addEndControlFlow(); consume(14, 3, 0); microprefetch(true, null); // prefetch ir from pc and resume execution addEndControlFlow(); addState("op_bra32"); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) != 0)", SSWI_DNGR); + addFormattedMicroInsn("mpc = op_bra8"); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + anyread32("dt", SSW_DF | SSW_P, "pc + scan", 0, false, null); consume(14, 3, 0); addFormattedMicroInsn("scan = dt"); addFormattedMicroInsn("sswi |= (sr & 0x%04x)", SR_T0); // trigger trace flow @@ -2577,6 +2589,9 @@ public class CoreGenerator { microprefetch(true, null); // prefetch ir from pc and resume execution addState("op_bsr16"); + anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 2"); + }); consume(18, 2, 2); addFormattedMicroInsn("au = dar[sp] - 4"); addFormattedMicroInsn("dar[sp] = au"); @@ -2586,6 +2601,13 @@ public class CoreGenerator { microprefetch(true, null); // prefetch ir from pc and resume execution addState("op_bsr32"); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) != 0)", SSWI_DNGR); + addFormattedMicroInsn("mpc = op_bsr8"); + addFormattedMicroInsn("continue"); + addEndControlFlow(); + anyread32("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + addFormattedMicroInsn("scan += 4"); + }); consume(22, 3, 2); addFormattedMicroInsn("au = dar[sp] - 4"); addFormattedMicroInsn("dar[sp] = au"); diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java index 37c5351..0222907 100644 --- a/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java +++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java @@ -544,14 +544,14 @@ public class CorePLAGenerator { appendOP(gen, entries, array, 0x50fc, 0xf0ff, "trapcc", "op_trapcc", "dbrr", "dbrr"); appendOP(gen, entries, array, 0x6000, 0xff00, "bra_rel8", "op_bra8", "dbrr", "dbrr"); - appendOP(gen, entries, array, 0x6000, 0xffff, "bra_rel16", "op_imm16", "op_bra16", "dbrr"); - appendOP(gen, entries, array, 0x60ff, 0xffff, "bra_rel32", "op_imm32", "op_bra32", "dbrr"); + appendOP(gen, entries, array, 0x6000, 0xffff, "bra_rel16", "op_bra16", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x60ff, 0xffff, "bra_rel32", "op_bra32", "dbrr", "dbrr"); appendOP(gen, entries, array, 0x6100, 0xff00, "bsr_rel8", "op_bsr8", "dbrr", "dbrr"); - appendOP(gen, entries, array, 0x6100, 0xffff, "bsr_rel16", "op_imm16", "op_bsr16", "dbrr"); - appendOP(gen, entries, array, 0x61ff, 0xffff, "bsr_rel32", "op_imm32", "op_bsr32", "dbrr"); + appendOP(gen, entries, array, 0x6100, 0xffff, "bsr_rel16", "op_bsr16", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x61ff, 0xffff, "bsr_rel32", "op_bsr32", "dbrr", "dbrr"); appendOP(gen, entries, array, 0x6000, 0xf000, "bcc_rel8", "op_bcc8", "dbrr", "dbrr"); - appendOP(gen, entries, array, 0x6000, 0xf0ff, "bcc_rel16", "op_imm16", "op_bcc16", "dbrr"); - appendOP(gen, entries, array, 0x60ff, 0xf0ff, "bcc_rel32", "op_imm32", "op_bcc32", "dbrr"); + appendOP(gen, entries, array, 0x6000, 0xf0ff, "bcc_rel16", "op_bcc16", "dbrr", "dbrr"); + appendOP(gen, entries, array, 0x60ff, 0xf0ff, "bcc_rel32", "op_bcc32", "dbrr", "dbrr"); appendOP(gen, entries, array, 0x7000, 0xf100, "moveq_imm8o_dd", move(gen, "l", "imm8o", "dd"), "dbrr", "dbrr"); diff --git a/miggy-emu/src/main/java/miggy/cpupoet/Core.java b/miggy-emu/src/main/java/miggy/cpupoet/Core.java index 826b485..1f68fbd 100644 --- a/miggy-emu/src/main/java/miggy/cpupoet/Core.java +++ b/miggy-emu/src/main/java/miggy/cpupoet/Core.java @@ -403,591 +403,591 @@ public abstract class Core extends CoreALU { protected static final int op_bra16 = 300; - protected static final int op_bcc32 = 301; + protected static final int op_bcc32 = 302; - protected static final int op_bra32 = 302; + protected static final int op_bra32 = 303; - protected static final int op_bsr8 = 303; + protected static final int op_bsr8 = 305; - protected static final int op_bsr16 = 305; + protected static final int op_bsr16 = 307; - protected static final int op_bsr32 = 307; + protected static final int op_bsr32 = 310; - protected static final int op_dbcc = 309; + protected static final int op_dbcc = 313; - protected static final int op_bkpt = 311; + protected static final int op_bkpt = 315; - protected static final int op_illegal = 312; + protected static final int op_illegal = 316; - protected static final int op_jmp = 313; + protected static final int op_jmp = 317; - protected static final int op_jsr = 314; + protected static final int op_jsr = 318; - protected static final int op_linea = 316; + protected static final int op_linea = 320; - protected static final int op_linef = 317; + protected static final int op_linef = 321; - protected static final int op_nop = 318; + protected static final int op_nop = 322; - protected static final int op_rte = 319; + protected static final int op_rte = 323; - private static final int check_vob = 320; + private static final int check_vob = 324; - private static final int rteill = 321; + private static final int rteill = 325; - private static final int exit_trap = 322; + private static final int exit_trap = 326; - private static final int rte0000 = 323; + private static final int rte0000 = 327; - private static final int rte1000 = 324; + private static final int rte1000 = 328; - private static final int rte2000 = 325; + private static final int rte2000 = 329; - private static final int rte8000 = 326; + private static final int rte8000 = 330; - protected static final int op_rtr = 327; + protected static final int op_rtr = 331; - protected static final int op_rts = 330; + protected static final int op_rts = 334; - protected static final int op_reset = 332; + protected static final int op_reset = 336; - protected static final int op_trap = 333; + protected static final int op_trap = 337; - protected static final int op_trapv = 334; + protected static final int op_trapv = 338; - protected static final int op_trapcc = 335; + protected static final int op_trapcc = 339; - protected static final int op_trapcc16 = 336; + protected static final int op_trapcc16 = 340; - protected static final int op_trapcc32 = 337; + protected static final int op_trapcc32 = 341; - protected static final int gen_orb_dt_ds = 338; + protected static final int gen_orb_dt_ds = 342; - protected static final int gen_orb_im_ea = 339; + protected static final int gen_orb_im_ea = 343; - protected static final int gen_orw_dt_ds = 340; + protected static final int gen_orw_dt_ds = 344; - protected static final int gen_orw_im_ea = 341; + protected static final int gen_orw_im_ea = 345; - protected static final int gen_orl_dt_ds = 342; + protected static final int gen_orl_dt_ds = 346; - protected static final int gen_orl_im_ea = 343; + protected static final int gen_orl_im_ea = 347; - protected static final int gen_orb_dt_ccr = 344; + protected static final int gen_orb_dt_ccr = 348; - protected static final int gen_orw_dt_sr = 345; + protected static final int gen_orw_dt_sr = 349; - protected static final int gen_btstl_dd_ds = 346; + protected static final int gen_btstl_dd_ds = 350; - protected static final int gen_btstb_dd_ea = 347; + protected static final int gen_btstb_dd_ea = 351; - protected static final int gen_bchgl_dd_ds = 348; + protected static final int gen_bchgl_dd_ds = 352; - protected static final int gen_bchgb_dd_ea = 349; + protected static final int gen_bchgb_dd_ea = 353; - protected static final int gen_bclrl_dd_ds = 350; + protected static final int gen_bclrl_dd_ds = 354; - protected static final int gen_bclrb_dd_ea = 351; + protected static final int gen_bclrb_dd_ea = 355; - protected static final int gen_bsetl_dd_ds = 352; + protected static final int gen_bsetl_dd_ds = 356; - protected static final int gen_bsetb_dd_ea = 353; + protected static final int gen_bsetb_dd_ea = 357; - protected static final int gen_andb_dt_ds = 354; + protected static final int gen_andb_dt_ds = 358; - protected static final int gen_andb_im_ea = 355; + protected static final int gen_andb_im_ea = 359; - protected static final int gen_andw_dt_ds = 356; + protected static final int gen_andw_dt_ds = 360; - protected static final int gen_andw_im_ea = 357; + protected static final int gen_andw_im_ea = 361; - protected static final int gen_andl_dt_ds = 358; + protected static final int gen_andl_dt_ds = 362; - protected static final int gen_andl_im_ea = 359; + protected static final int gen_andl_im_ea = 363; - protected static final int gen_andb_dt_ccr = 360; + protected static final int gen_andb_dt_ccr = 364; - protected static final int gen_andw_dt_sr = 361; + protected static final int gen_andw_dt_sr = 365; - protected static final int gen_subb_dt_ds = 362; + protected static final int gen_subb_dt_ds = 366; - protected static final int gen_subb_im_ea = 363; + protected static final int gen_subb_im_ea = 367; - protected static final int gen_subw_dt_ds = 364; + protected static final int gen_subw_dt_ds = 368; - protected static final int gen_subw_im_ea = 365; + protected static final int gen_subw_im_ea = 369; - protected static final int gen_subl_dt_ds = 366; + protected static final int gen_subl_dt_ds = 370; - protected static final int gen_subl_im_ea = 367; + protected static final int gen_subl_im_ea = 371; - protected static final int gen_addb_dt_ds = 368; + protected static final int gen_addb_dt_ds = 372; - protected static final int gen_addb_im_ea = 369; + protected static final int gen_addb_im_ea = 373; - protected static final int gen_addw_dt_ds = 370; + protected static final int gen_addw_dt_ds = 374; - protected static final int gen_addw_im_ea = 371; + protected static final int gen_addw_im_ea = 375; - protected static final int gen_addl_dt_ds = 372; + protected static final int gen_addl_dt_ds = 376; - protected static final int gen_addl_im_ea = 373; + protected static final int gen_addl_im_ea = 377; - protected static final int gen_btstl_dt_ds = 374; + protected static final int gen_btstl_dt_ds = 378; - protected static final int gen_btstb_im_ea = 375; + protected static final int gen_btstb_im_ea = 379; - protected static final int gen_bchgl_dt_ds = 376; + protected static final int gen_bchgl_dt_ds = 380; - protected static final int gen_bchgb_im_ea = 377; + protected static final int gen_bchgb_im_ea = 381; - protected static final int gen_bclrl_dt_ds = 378; + protected static final int gen_bclrl_dt_ds = 382; - protected static final int gen_bclrb_im_ea = 379; + protected static final int gen_bclrb_im_ea = 383; - protected static final int gen_bsetl_dt_ds = 380; + protected static final int gen_bsetl_dt_ds = 384; - protected static final int gen_bsetb_im_ea = 381; + protected static final int gen_bsetb_im_ea = 385; - protected static final int gen_eorb_dt_ds = 382; + protected static final int gen_eorb_dt_ds = 386; - protected static final int gen_eorb_im_ea = 383; + protected static final int gen_eorb_im_ea = 387; - protected static final int gen_eorw_dt_ds = 384; + protected static final int gen_eorw_dt_ds = 388; - protected static final int gen_eorw_im_ea = 385; + protected static final int gen_eorw_im_ea = 389; - protected static final int gen_eorl_dt_ds = 386; + protected static final int gen_eorl_dt_ds = 390; - protected static final int gen_eorl_im_ea = 387; + protected static final int gen_eorl_im_ea = 391; - protected static final int gen_eorb_dt_ccr = 388; + protected static final int gen_eorb_dt_ccr = 392; - protected static final int gen_eorw_dt_sr = 389; + protected static final int gen_eorw_dt_sr = 393; - protected static final int gen_cmpb_dt_ds = 390; + protected static final int gen_cmpb_dt_ds = 394; - protected static final int gen_cmpb_im_ea = 391; + protected static final int gen_cmpb_im_ea = 395; - protected static final int gen_cmpw_dt_ds = 392; + protected static final int gen_cmpw_dt_ds = 396; - protected static final int gen_cmpw_im_ea = 393; + protected static final int gen_cmpw_im_ea = 397; - protected static final int gen_cmpl_dt_ds = 394; + protected static final int gen_cmpl_dt_ds = 398; - protected static final int gen_cmpl_im_ea = 395; + protected static final int gen_cmpl_im_ea = 399; - protected static final int gen_moveb_ds_ea = 396; + protected static final int gen_moveb_ds_ea = 400; - protected static final int gen_moveb_dt_dd = 397; + protected static final int gen_moveb_dt_dd = 401; - protected static final int gen_moveb_ds_dd = 398; + protected static final int gen_moveb_ds_dd = 402; - protected static final int gen_moveb_dt_ea = 399; + protected static final int gen_moveb_dt_ea = 403; - protected static final int gen_movel_ds_ea = 400; + protected static final int gen_movel_ds_ea = 404; - protected static final int gen_movel_as_ea = 401; + protected static final int gen_movel_as_ea = 405; - protected static final int gen_movel_dt_dd = 402; + protected static final int gen_movel_dt_dd = 406; - protected static final int gen_movel_ds_dd = 403; + protected static final int gen_movel_ds_dd = 407; - protected static final int gen_movel_as_dd = 404; + protected static final int gen_movel_as_dd = 408; - protected static final int gen_movel_dt_ea = 405; + protected static final int gen_movel_dt_ea = 409; - protected static final int gen_movel_ds_ad = 406; + protected static final int gen_movel_ds_ad = 410; - protected static final int gen_movel_as_ad = 407; + protected static final int gen_movel_as_ad = 411; - protected static final int gen_movel_dt_ad = 408; + protected static final int gen_movel_dt_ad = 412; - protected static final int gen_movew_ds_ea = 409; + protected static final int gen_movew_ds_ea = 413; - protected static final int gen_movew_as_ea = 410; + protected static final int gen_movew_as_ea = 414; - protected static final int gen_movew_dt_dd = 411; + protected static final int gen_movew_dt_dd = 415; - protected static final int gen_movew_ds_dd = 412; + protected static final int gen_movew_ds_dd = 416; - protected static final int gen_movew_as_dd = 413; + protected static final int gen_movew_as_dd = 417; - protected static final int gen_movew_dt_ea = 414; + protected static final int gen_movew_dt_ea = 418; - protected static final int gen_movew_ds_ad = 415; + protected static final int gen_movew_ds_ad = 419; - protected static final int gen_movew_as_ad = 416; + protected static final int gen_movew_as_ad = 420; - protected static final int gen_movew_dt_ad = 417; + protected static final int gen_movew_dt_ad = 421; - protected static final int gen_negxb_ds = 418; + protected static final int gen_negxb_ds = 422; - protected static final int gen_negxb_ea = 419; + protected static final int gen_negxb_ea = 423; - protected static final int gen_negxw_ds = 420; + protected static final int gen_negxw_ds = 424; - protected static final int gen_negxw_ea = 421; + protected static final int gen_negxw_ea = 425; - protected static final int gen_negxl_ds = 422; + protected static final int gen_negxl_ds = 426; - protected static final int gen_negxl_ea = 423; + protected static final int gen_negxl_ea = 427; - protected static final int gen_movew_sr_ds = 424; + protected static final int gen_movew_sr_ds = 428; - protected static final int gen_movew_sr_ea = 425; + protected static final int gen_movew_sr_ea = 429; - protected static final int gen_movew_ccr_ds = 426; + protected static final int gen_movew_ccr_ds = 430; - protected static final int gen_movew_ccr_ea = 427; + protected static final int gen_movew_ccr_ea = 431; - protected static final int gen_movew_ds_ccr = 428; + protected static final int gen_movew_ds_ccr = 432; - protected static final int gen_movew_dt_ccr = 429; + protected static final int gen_movew_dt_ccr = 433; - protected static final int gen_movew_ds_sr = 430; + protected static final int gen_movew_ds_sr = 434; - protected static final int gen_movew_dt_sr = 431; + protected static final int gen_movew_dt_sr = 435; - protected static final int gen_negb_ds = 432; + protected static final int gen_negb_ds = 436; - protected static final int gen_negb_ea = 433; + protected static final int gen_negb_ea = 437; - protected static final int gen_negw_ds = 434; + protected static final int gen_negw_ds = 438; - protected static final int gen_negw_ea = 435; + protected static final int gen_negw_ea = 439; - protected static final int gen_negl_ds = 436; + protected static final int gen_negl_ds = 440; - protected static final int gen_negl_ea = 437; + protected static final int gen_negl_ea = 441; - protected static final int gen_notb_ds = 438; + protected static final int gen_notb_ds = 442; - protected static final int gen_notb_ea = 439; + protected static final int gen_notb_ea = 443; - protected static final int gen_notw_ds = 440; + protected static final int gen_notw_ds = 444; - protected static final int gen_notw_ea = 441; + protected static final int gen_notw_ea = 445; - protected static final int gen_notl_ds = 442; + protected static final int gen_notl_ds = 446; - protected static final int gen_notl_ea = 443; + protected static final int gen_notl_ea = 447; - protected static final int gen_nbcdb_ds = 444; + protected static final int gen_nbcdb_ds = 448; - protected static final int gen_nbcdb_ea = 445; + protected static final int gen_nbcdb_ea = 449; - protected static final int gen_tstb_ds = 446; + protected static final int gen_tstb_ds = 450; - protected static final int gen_tstb_ea = 447; + protected static final int gen_tstb_ea = 451; - protected static final int gen_tstw_ds = 448; + protected static final int gen_tstw_ds = 452; - protected static final int gen_tstw_ea = 449; + protected static final int gen_tstw_ea = 453; - protected static final int gen_tstl_ds = 450; + protected static final int gen_tstl_ds = 454; - protected static final int gen_tstl_ea = 451; + protected static final int gen_tstl_ea = 455; - protected static final int gen_addb_ir_ds = 452; + protected static final int gen_addb_ir_ds = 456; - protected static final int gen_addb_ir_ea = 453; + protected static final int gen_addb_ir_ea = 457; - protected static final int gen_addw_ir_ds = 454; + protected static final int gen_addw_ir_ds = 458; - protected static final int gen_addw_ir_as = 455; + protected static final int gen_addw_ir_as = 459; - protected static final int gen_addw_ir_ea = 456; + protected static final int gen_addw_ir_ea = 460; - protected static final int gen_addl_ir_ds = 457; + protected static final int gen_addl_ir_ds = 461; - protected static final int gen_addl_ir_as = 458; + protected static final int gen_addl_ir_as = 462; - protected static final int gen_addl_ir_ea = 459; + protected static final int gen_addl_ir_ea = 463; - protected static final int gen_subb_ir_ds = 460; + protected static final int gen_subb_ir_ds = 464; - protected static final int gen_subb_ir_ea = 461; + protected static final int gen_subb_ir_ea = 465; - protected static final int gen_subw_ir_ds = 462; + protected static final int gen_subw_ir_ds = 466; - protected static final int gen_subw_ir_as = 463; + protected static final int gen_subw_ir_as = 467; - protected static final int gen_subw_ir_ea = 464; + protected static final int gen_subw_ir_ea = 468; - protected static final int gen_subl_ir_ds = 465; + protected static final int gen_subl_ir_ds = 469; - protected static final int gen_subl_ir_as = 466; + protected static final int gen_subl_ir_as = 470; - protected static final int gen_subl_ir_ea = 467; + protected static final int gen_subl_ir_ea = 471; - protected static final int gen_movel_im_dd = 468; + protected static final int gen_movel_im_dd = 472; - protected static final int gen_orb_ds_dd = 469; + protected static final int gen_orb_ds_dd = 473; - protected static final int gen_orb_dt_dd = 470; + protected static final int gen_orb_dt_dd = 474; - protected static final int gen_orw_ds_dd = 471; + protected static final int gen_orw_ds_dd = 475; - protected static final int gen_orw_dt_dd = 472; + protected static final int gen_orw_dt_dd = 476; - protected static final int gen_orl_ds_dd = 473; + protected static final int gen_orl_ds_dd = 477; - protected static final int gen_orl_dt_dd = 474; + protected static final int gen_orl_dt_dd = 478; - protected static final int gen_sbcdb_ds_dd = 475; + protected static final int gen_sbcdb_ds_dd = 479; - protected static final int gen_sbcdb_im_ea = 476; + protected static final int gen_sbcdb_im_ea = 480; - protected static final int gen_orb_dd_ea = 477; + protected static final int gen_orb_dd_ea = 481; - protected static final int gen_orw_dd_ea = 478; + protected static final int gen_orw_dd_ea = 482; - protected static final int gen_orl_dd_ea = 479; + protected static final int gen_orl_dd_ea = 483; - protected static final int gen_subb_ds_dd = 480; + protected static final int gen_subb_ds_dd = 484; - protected static final int gen_subb_dt_dd = 481; + protected static final int gen_subb_dt_dd = 485; - protected static final int gen_subw_ds_dd = 482; + protected static final int gen_subw_ds_dd = 486; - protected static final int gen_subw_as_dd = 483; + protected static final int gen_subw_as_dd = 487; - protected static final int gen_subw_dt_dd = 484; + protected static final int gen_subw_dt_dd = 488; - protected static final int gen_subl_ds_dd = 485; + protected static final int gen_subl_ds_dd = 489; - protected static final int gen_subl_as_dd = 486; + protected static final int gen_subl_as_dd = 490; - protected static final int gen_subl_dt_dd = 487; + protected static final int gen_subl_dt_dd = 491; - protected static final int gen_subb_dd_ea = 488; + protected static final int gen_subb_dd_ea = 492; - protected static final int gen_subw_dd_ea = 489; + protected static final int gen_subw_dd_ea = 493; - protected static final int gen_subl_dd_ea = 490; + protected static final int gen_subl_dd_ea = 494; - protected static final int gen_subxb_ds_dd = 491; + protected static final int gen_subxb_ds_dd = 495; - protected static final int gen_subxb_im_ea = 492; + protected static final int gen_subxb_im_ea = 496; - protected static final int gen_subxw_ds_dd = 493; + protected static final int gen_subxw_ds_dd = 497; - protected static final int gen_subxw_im_ea = 494; + protected static final int gen_subxw_im_ea = 498; - protected static final int gen_subxl_ds_dd = 495; + protected static final int gen_subxl_ds_dd = 499; - protected static final int gen_subxl_im_ea = 496; + protected static final int gen_subxl_im_ea = 500; - protected static final int gen_subw_ds_ad = 497; + protected static final int gen_subw_ds_ad = 501; - protected static final int gen_subw_as_ad = 498; + protected static final int gen_subw_as_ad = 502; - protected static final int gen_subw_dt_ad = 499; + protected static final int gen_subw_dt_ad = 503; - protected static final int gen_subl_ds_ad = 500; + protected static final int gen_subl_ds_ad = 504; - protected static final int gen_subl_as_ad = 501; + protected static final int gen_subl_as_ad = 505; - protected static final int gen_subl_dt_ad = 502; + protected static final int gen_subl_dt_ad = 506; - protected static final int gen_cmpb_ds_dd = 503; + protected static final int gen_cmpb_ds_dd = 507; - protected static final int gen_cmpb_dt_dd = 504; + protected static final int gen_cmpb_dt_dd = 508; - protected static final int gen_cmpw_ds_dd = 505; + protected static final int gen_cmpw_ds_dd = 509; - protected static final int gen_cmpw_as_dd = 506; + protected static final int gen_cmpw_as_dd = 510; - protected static final int gen_cmpw_dt_dd = 507; + protected static final int gen_cmpw_dt_dd = 511; - protected static final int gen_cmpl_ds_dd = 508; + protected static final int gen_cmpl_ds_dd = 512; - protected static final int gen_cmpl_as_dd = 509; + protected static final int gen_cmpl_as_dd = 513; - protected static final int gen_cmpl_dt_dd = 510; + protected static final int gen_cmpl_dt_dd = 514; - protected static final int gen_cmpw_ds_ad = 511; + protected static final int gen_cmpw_ds_ad = 515; - protected static final int gen_cmpw_as_ad = 512; + protected static final int gen_cmpw_as_ad = 516; - protected static final int gen_cmpw_dt_ad = 513; + protected static final int gen_cmpw_dt_ad = 517; - protected static final int gen_cmpl_ds_ad = 514; + protected static final int gen_cmpl_ds_ad = 518; - protected static final int gen_cmpl_as_ad = 515; + protected static final int gen_cmpl_as_ad = 519; - protected static final int gen_cmpl_dt_ad = 516; + protected static final int gen_cmpl_dt_ad = 520; - protected static final int gen_cmpmb_im_ea = 517; + protected static final int gen_cmpmb_im_ea = 521; - protected static final int gen_cmpmw_im_ea = 518; + protected static final int gen_cmpmw_im_ea = 522; - protected static final int gen_cmpml_im_ea = 519; + protected static final int gen_cmpml_im_ea = 523; - protected static final int gen_eorb_dd_ds = 520; + protected static final int gen_eorb_dd_ds = 524; - protected static final int gen_eorb_dd_ea = 521; + protected static final int gen_eorb_dd_ea = 525; - protected static final int gen_eorw_dd_ds = 522; + protected static final int gen_eorw_dd_ds = 526; - protected static final int gen_eorw_dd_ea = 523; + protected static final int gen_eorw_dd_ea = 527; - protected static final int gen_eorl_dd_ds = 524; + protected static final int gen_eorl_dd_ds = 528; - protected static final int gen_eorl_dd_ea = 525; + protected static final int gen_eorl_dd_ea = 529; - protected static final int gen_andb_ds_dd = 526; + protected static final int gen_andb_ds_dd = 530; - protected static final int gen_andb_dt_dd = 527; + protected static final int gen_andb_dt_dd = 531; - protected static final int gen_andw_ds_dd = 528; + protected static final int gen_andw_ds_dd = 532; - protected static final int gen_andw_dt_dd = 529; + protected static final int gen_andw_dt_dd = 533; - protected static final int gen_andl_ds_dd = 530; + protected static final int gen_andl_ds_dd = 534; - protected static final int gen_andl_dt_dd = 531; + protected static final int gen_andl_dt_dd = 535; - protected static final int gen_andb_dd_ea = 532; + protected static final int gen_andb_dd_ea = 536; - protected static final int gen_andw_dd_ea = 533; + protected static final int gen_andw_dd_ea = 537; - protected static final int gen_andl_dd_ea = 534; + protected static final int gen_andl_dd_ea = 538; - protected static final int gen_abcdb_ds_dd = 535; + protected static final int gen_abcdb_ds_dd = 539; - protected static final int gen_abcdb_im_ea = 536; + protected static final int gen_abcdb_im_ea = 540; - protected static final int gen_addb_ds_dd = 537; + protected static final int gen_addb_ds_dd = 541; - protected static final int gen_addb_dt_dd = 538; + protected static final int gen_addb_dt_dd = 542; - protected static final int gen_addw_ds_dd = 539; + protected static final int gen_addw_ds_dd = 543; - protected static final int gen_addw_as_dd = 540; + protected static final int gen_addw_as_dd = 544; - protected static final int gen_addw_dt_dd = 541; + protected static final int gen_addw_dt_dd = 545; - protected static final int gen_addl_ds_dd = 542; + protected static final int gen_addl_ds_dd = 546; - protected static final int gen_addl_as_dd = 543; + protected static final int gen_addl_as_dd = 547; - protected static final int gen_addl_dt_dd = 544; + protected static final int gen_addl_dt_dd = 548; - protected static final int gen_addb_dd_ea = 545; + protected static final int gen_addb_dd_ea = 549; - protected static final int gen_addw_dd_ea = 546; + protected static final int gen_addw_dd_ea = 550; - protected static final int gen_addl_dd_ea = 547; + protected static final int gen_addl_dd_ea = 551; - protected static final int gen_addxb_ds_dd = 548; + protected static final int gen_addxb_ds_dd = 552; - protected static final int gen_addxb_im_ea = 549; + protected static final int gen_addxb_im_ea = 553; - protected static final int gen_addxw_ds_dd = 550; + protected static final int gen_addxw_ds_dd = 554; - protected static final int gen_addxw_im_ea = 551; + protected static final int gen_addxw_im_ea = 555; - protected static final int gen_addxl_ds_dd = 552; + protected static final int gen_addxl_ds_dd = 556; - protected static final int gen_addxl_im_ea = 553; + protected static final int gen_addxl_im_ea = 557; - protected static final int gen_addw_ds_ad = 554; + protected static final int gen_addw_ds_ad = 558; - protected static final int gen_addw_as_ad = 555; + protected static final int gen_addw_as_ad = 559; - protected static final int gen_addw_dt_ad = 556; + protected static final int gen_addw_dt_ad = 560; - protected static final int gen_addl_ds_ad = 557; + protected static final int gen_addl_ds_ad = 561; - protected static final int gen_addl_as_ad = 558; + protected static final int gen_addl_as_ad = 562; - protected static final int gen_addl_dt_ad = 559; + protected static final int gen_addl_dt_ad = 563; - protected static final int gen_asrb_ir_ds = 560; + protected static final int gen_asrb_ir_ds = 564; - protected static final int gen_asrb_dd_ds = 561; + protected static final int gen_asrb_dd_ds = 565; - protected static final int gen_asrw_ir_ds = 562; + protected static final int gen_asrw_ir_ds = 566; - protected static final int gen_asrw_dd_ds = 563; + protected static final int gen_asrw_dd_ds = 567; - protected static final int gen_asrl_ir_ds = 564; + protected static final int gen_asrl_ir_ds = 568; - protected static final int gen_asrl_dd_ds = 565; + protected static final int gen_asrl_dd_ds = 569; - protected static final int gen_asrw_ea = 566; + protected static final int gen_asrw_ea = 570; - protected static final int gen_aslb_ir_ds = 567; + protected static final int gen_aslb_ir_ds = 571; - protected static final int gen_aslb_dd_ds = 568; + protected static final int gen_aslb_dd_ds = 572; - protected static final int gen_aslw_ir_ds = 569; + protected static final int gen_aslw_ir_ds = 573; - protected static final int gen_aslw_dd_ds = 570; + protected static final int gen_aslw_dd_ds = 574; - protected static final int gen_asll_ir_ds = 571; + protected static final int gen_asll_ir_ds = 575; - protected static final int gen_asll_dd_ds = 572; + protected static final int gen_asll_dd_ds = 576; - protected static final int gen_aslw_ea = 573; + protected static final int gen_aslw_ea = 577; - protected static final int gen_lsrb_ir_ds = 574; + protected static final int gen_lsrb_ir_ds = 578; - protected static final int gen_lsrb_dd_ds = 575; + protected static final int gen_lsrb_dd_ds = 579; - protected static final int gen_lsrw_ir_ds = 576; + protected static final int gen_lsrw_ir_ds = 580; - protected static final int gen_lsrw_dd_ds = 577; + protected static final int gen_lsrw_dd_ds = 581; - protected static final int gen_lsrl_ir_ds = 578; + protected static final int gen_lsrl_ir_ds = 582; - protected static final int gen_lsrl_dd_ds = 579; + protected static final int gen_lsrl_dd_ds = 583; - protected static final int gen_lsrw_ea = 580; + protected static final int gen_lsrw_ea = 584; - protected static final int gen_lslb_ir_ds = 581; + protected static final int gen_lslb_ir_ds = 585; - protected static final int gen_lslb_dd_ds = 582; + protected static final int gen_lslb_dd_ds = 586; - protected static final int gen_lslw_ir_ds = 583; + protected static final int gen_lslw_ir_ds = 587; - protected static final int gen_lslw_dd_ds = 584; + protected static final int gen_lslw_dd_ds = 588; - protected static final int gen_lsll_ir_ds = 585; + protected static final int gen_lsll_ir_ds = 589; - protected static final int gen_lsll_dd_ds = 586; + protected static final int gen_lsll_dd_ds = 590; - protected static final int gen_lslw_ea = 587; + protected static final int gen_lslw_ea = 591; - protected static final int gen_rorb_ir_ds = 588; + protected static final int gen_rorb_ir_ds = 592; - protected static final int gen_rorb_dd_ds = 589; + protected static final int gen_rorb_dd_ds = 593; - protected static final int gen_rorw_ir_ds = 590; + protected static final int gen_rorw_ir_ds = 594; - protected static final int gen_rorw_dd_ds = 591; + protected static final int gen_rorw_dd_ds = 595; - protected static final int gen_rorl_ir_ds = 592; + protected static final int gen_rorl_ir_ds = 596; - protected static final int gen_rorl_dd_ds = 593; + protected static final int gen_rorl_dd_ds = 597; - protected static final int gen_rorw_ea = 594; + protected static final int gen_rorw_ea = 598; - protected static final int gen_rolb_ir_ds = 595; + protected static final int gen_rolb_ir_ds = 599; - protected static final int gen_rolb_dd_ds = 596; + protected static final int gen_rolb_dd_ds = 600; - protected static final int gen_rolw_ir_ds = 597; + protected static final int gen_rolw_ir_ds = 601; - protected static final int gen_rolw_dd_ds = 598; + protected static final int gen_rolw_dd_ds = 602; - protected static final int gen_roll_ir_ds = 599; + protected static final int gen_roll_ir_ds = 603; - protected static final int gen_roll_dd_ds = 600; + protected static final int gen_roll_dd_ds = 604; - protected static final int gen_rolw_ea = 601; + protected static final int gen_rolw_ea = 605; public static final int BKPT_EXIT = 0x00010000; @@ -4002,6 +4002,7 @@ public abstract class Core extends CoreALU { if (word_chk(dar[ry], dar[rx])) { tvn = 24; mpc = (sswi & 0x0008) != 0 ? trap2000 : trap0000; + continue; } mpc = resume_prefetch; continue; @@ -4010,6 +4011,7 @@ public abstract class Core extends CoreALU { if (word_chk(dt, dar[rx])) { tvn = 24; mpc = (sswi & 0x0008) != 0 ? trap2000 : trap0000; + continue; } mpc = resume_prefetch; continue; @@ -4566,50 +4568,65 @@ public abstract class Core extends CoreALU { continue; case 299: /* op_bcc16 */ if (!testCC((ir & 0x0f00) >> 8)) { + scan += 2; elapsed += 2; mpc = resume_prefetch; continue; } case 300: /* op_bra16 */ + nmpc = 301; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 301: + dt = dib; elapsed += 2; scan = (short) dt; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 301: /* op_bcc32 */ + case 302: /* op_bcc32 */ if (!testCC((ir & 0x0f00) >> 8)) { + if ((sswi & 0x0020) == 0) { + scan += 4; + } elapsed += 2; mpc = resume_prefetch; continue; } - case 302: /* op_bra32 */ + case 303: /* op_bra32 */ + if ((sswi & 0x0020) != 0) { + mpc = op_bra8; + continue; + } + nmpc = 304; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch32(aob); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtf32; + continue; + } + case 304: + dt = dib; elapsed += 2; scan = dt; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 303: /* op_bsr8 */ - elapsed += 2; - au = dar[sp] - 4; - dar[sp] = au; - nmpc = 304; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; - if (((aob = au) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - write32(aob, dob = pc + scan); - if ((ssw & 0x0070) != 0x0040) { - mpc = bevtw32; - continue; - } - case 304: - scan = (byte) ir; - sswi |= (sr & 0x4000); - mpc = resume_prefetch; - continue; - case 305: /* op_bsr16 */ + case 305: /* op_bsr8 */ elapsed += 2; au = dar[sp] - 4; dar[sp] = au; @@ -4626,15 +4643,30 @@ public abstract class Core extends CoreALU { continue; } case 306: - scan = (short) dt; + scan = (byte) ir; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 307: /* op_bsr32 */ + case 307: /* op_bsr16 */ + nmpc = 308; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 308: + dt = dib; elapsed += 2; au = dar[sp] - 4; dar[sp] = au; - nmpc = 308; + nmpc = 309; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -4646,12 +4678,52 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 308: + case 309: + scan = (short) dt; + sswi |= (sr & 0x4000); + mpc = resume_prefetch; + continue; + case 310: /* op_bsr32 */ + if ((sswi & 0x0020) != 0) { + mpc = op_bsr8; + continue; + } + nmpc = 311; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch32(aob); + scan += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtf32; + continue; + } + case 311: + dt = dib; + elapsed += 2; + au = dar[sp] - 4; + dar[sp] = au; + nmpc = 312; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; + if (((aob = au) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write32(aob, dob = pc + scan); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtw32; + continue; + } + case 312: scan = dt; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 309: /* op_dbcc */ + case 313: /* op_dbcc */ if (testCC((ir & 0x0f00) >> 8)) { elapsed += 2; scan += 2; @@ -4666,7 +4738,7 @@ public abstract class Core extends CoreALU { mpc = resume_prefetch; continue; } - nmpc = 310; + nmpc = 314; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4678,12 +4750,12 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 310: + case 314: scan += (short) dib; elapsed += 2; mpc = resume_prefetch; continue; - case 311: /* op_bkpt */ + case 315: /* op_bkpt */ elapsed += 6; hdlr = handle_bkpt(cip, ir & 0x0007); exit |= (hdlr & 0x00010000) != 0; @@ -4697,7 +4769,7 @@ public abstract class Core extends CoreALU { tvn = 16; mpc = trapill; continue; - case 312: /* op_illegal */ + case 316: /* op_illegal */ elapsed += 6; hdlr = handle_illegal(cip, ir); exit |= (hdlr & 0x00010000) != 0; @@ -4710,16 +4782,16 @@ public abstract class Core extends CoreALU { tvn = 16; mpc = trapill; continue; - case 313: /* op_jmp */ + case 317: /* op_jmp */ pc = at; scan = 0; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 314: /* op_jsr */ + case 318: /* op_jsr */ au = dar[sp] - 4; dar[sp] = au; - nmpc = 315; + nmpc = 319; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -4731,13 +4803,13 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 315: + case 319: pc = at; scan = 0; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 316: /* op_linea */ + case 320: /* op_linea */ elapsed += 6; hdlr = handle_linea(cip, ir & 0x0fff); exit |= (hdlr & 0x00010000) != 0; @@ -4750,15 +4822,15 @@ public abstract class Core extends CoreALU { tvn = 40; mpc = trapill; continue; - case 317: /* op_linef */ + case 321: /* op_linef */ elapsed += 6; tvn = 44; mpc = trapill; continue; - case 318: /* op_nop */ + case 322: /* op_nop */ mpc = resume_prefetch; continue; - case 319: /* op_rte */ + case 323: /* op_rte */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -4766,7 +4838,7 @@ public abstract class Core extends CoreALU { continue; } au = dar[sp]; - case 320: /* check_vob */ + case 324: /* check_vob */ elapsed += 4; ssw = (ssw & 0x0018) | 0x9105; if (((aob = au + 0x0006) & 0x000000001) != 0) { @@ -4780,12 +4852,12 @@ public abstract class Core extends CoreALU { } mpc = select_rte(dib); continue; - case 321: /* rteill */ + case 325: /* rteill */ elapsed += 6; tvn = 56; mpc = trapill; continue; - case 322: /* exit_trap */ + case 326: /* exit_trap */ elapsed += 8; ssw = (ssw & 0x0018) | 0x91c5; pc = read32(aob = au + 0x0002); @@ -4805,20 +4877,20 @@ public abstract class Core extends CoreALU { scan = 0; mpc = resume_prefetch; continue; - case 323: /* rte0000 */ + case 327: /* rte0000 */ dar[sp] = au + 8; mpc = exit_trap; continue; - case 324: /* rte1000 */ + case 328: /* rte1000 */ dar[sp] = au + 8; au = dar[sp = spi(sr | 0x1000)]; mpc = check_vob; continue; - case 325: /* rte2000 */ + case 329: /* rte2000 */ dar[sp] = au + 12; mpc = exit_trap; continue; - case 326: /* rte8000 */ + case 330: /* rte8000 */ elapsed += 6; elapsed += 8; ssw = (ssw & 0x0018) | 0x91c5; @@ -5053,9 +5125,9 @@ public abstract class Core extends CoreALU { continue; } break; - case 327: /* op_rtr */ + case 331: /* op_rtr */ au = dar[sp]; - nmpc = 328; + nmpc = 332; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; if (((aob = au + 0x0002) & 0x000000001) != 0) { @@ -5067,9 +5139,9 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 328: + case 332: pc = dib; - nmpc = 329; + nmpc = 333; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9101; dib = read16(aob = au); @@ -5077,7 +5149,7 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 329: + case 333: ssw &= ~0xbfe7; sr = (sr & ~0x001f) | (dib & 0x001f); scan = 0; @@ -5085,9 +5157,9 @@ public abstract class Core extends CoreALU { sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 330: /* op_rts */ + case 334: /* op_rts */ au = dar[sp]; - nmpc = 331; + nmpc = 335; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; if (((aob = au) & 0x000000001) != 0) { @@ -5099,7 +5171,7 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 331: + case 335: pc = dib; ssw &= ~0xbfe7; scan = 0; @@ -5107,16 +5179,16 @@ public abstract class Core extends CoreALU { sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 332: /* op_reset */ + case 336: /* op_reset */ elapsed += 126; mpc = resume_prefetch; continue; - case 333: /* op_trap */ + case 337: /* op_trap */ elapsed += 6; tvn = (32 + (ir & 0x000f)) << 2; mpc = trap0000; continue; - case 334: /* op_trapv */ + case 338: /* op_trapv */ if ((sr & 0x0002) != 0) { elapsed += 4; tvn = 28; @@ -5125,7 +5197,7 @@ public abstract class Core extends CoreALU { } mpc = resume_prefetch; continue; - case 335: /* op_trapcc */ + case 339: /* op_trapcc */ if (!testCC((ir & 0x0f00) >> 8)) { mpc = resume_prefetch; continue; @@ -5134,7 +5206,7 @@ public abstract class Core extends CoreALU { tvn = 28; mpc = trap2000; continue; - case 336: /* op_trapcc16 */ + case 340: /* op_trapcc16 */ scan += 2; if (!testCC((ir & 0x0f00) >> 8)) { mpc = resume_prefetch; @@ -5144,7 +5216,7 @@ public abstract class Core extends CoreALU { tvn = 28; mpc = trap2000; continue; - case 337: /* op_trapcc32 */ + case 341: /* op_trapcc32 */ scan += 4; if (!testCC((ir & 0x0f00) >> 8)) { mpc = resume_prefetch; @@ -5154,41 +5226,41 @@ public abstract class Core extends CoreALU { tvn = 28; mpc = trap2000; continue; - case 338: /* gen_orb_dt_ds */ + case 342: /* gen_orb_dt_ds */ ry = ir & 0x0007; dt = byte_or(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 339: /* gen_orb_im_ea */ + case 343: /* gen_orb_im_ea */ dt = byte_or(alub, dt); mpc = ea_resume_write8; continue; - case 340: /* gen_orw_dt_ds */ + case 344: /* gen_orw_dt_ds */ ry = ir & 0x0007; dt = word_or(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 341: /* gen_orw_im_ea */ + case 345: /* gen_orw_im_ea */ dt = word_or(alub, dt); mpc = ea_resume_write16; continue; - case 342: /* gen_orl_dt_ds */ + case 346: /* gen_orl_dt_ds */ ry = ir & 0x0007; dt = long_or(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 343: /* gen_orl_im_ea */ + case 347: /* gen_orl_im_ea */ dt = long_or(alub, dt); mpc = ea_resume_write32; continue; - case 344: /* gen_orb_dt_ccr */ + case 348: /* gen_orb_dt_ccr */ sr = (sr & ~0xff) | ((sr | dt) & 0x1f); mpc = resume_prefetch; continue; - case 345: /* gen_orw_dt_sr */ + case 349: /* gen_orw_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5198,88 +5270,88 @@ public abstract class Core extends CoreALU { sr = (sr | dt) & 0xf71f; mpc = resume_prefetch; continue; - case 346: /* gen_btstl_dd_ds */ + case 350: /* gen_btstl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; long_btst(dar[rx], dar[ry]); mpc = resume_prefetch; continue; - case 347: /* gen_btstb_dd_ea */ + case 351: /* gen_btstb_dd_ea */ rx = (ir >> 9) & 0x0007; byte_btst(dar[rx], dt); mpc = resume_prefetch; continue; - case 348: /* gen_bchgl_dd_ds */ + case 352: /* gen_bchgl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bchg(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 349: /* gen_bchgb_dd_ea */ + case 353: /* gen_bchgb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_bchg(dar[rx], dt); mpc = ea_resume_write8; continue; - case 350: /* gen_bclrl_dd_ds */ + case 354: /* gen_bclrl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bclr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 351: /* gen_bclrb_dd_ea */ + case 355: /* gen_bclrb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_bclr(dar[rx], dt); mpc = ea_resume_write8; continue; - case 352: /* gen_bsetl_dd_ds */ + case 356: /* gen_bsetl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bset(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 353: /* gen_bsetb_dd_ea */ + case 357: /* gen_bsetb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_bset(dar[rx], dt); mpc = ea_resume_write8; continue; - case 354: /* gen_andb_dt_ds */ + case 358: /* gen_andb_dt_ds */ ry = ir & 0x0007; dt = byte_and(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 355: /* gen_andb_im_ea */ + case 359: /* gen_andb_im_ea */ dt = byte_and(alub, dt); mpc = ea_resume_write8; continue; - case 356: /* gen_andw_dt_ds */ + case 360: /* gen_andw_dt_ds */ ry = ir & 0x0007; dt = word_and(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 357: /* gen_andw_im_ea */ + case 361: /* gen_andw_im_ea */ dt = word_and(alub, dt); mpc = ea_resume_write16; continue; - case 358: /* gen_andl_dt_ds */ + case 362: /* gen_andl_dt_ds */ ry = ir & 0x0007; dt = long_and(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 359: /* gen_andl_im_ea */ + case 363: /* gen_andl_im_ea */ dt = long_and(alub, dt); mpc = ea_resume_write32; continue; - case 360: /* gen_andb_dt_ccr */ + case 364: /* gen_andb_dt_ccr */ sr = (sr & ~0xff) | (sr & dt & 0x1f); mpc = resume_prefetch; continue; - case 361: /* gen_andw_dt_sr */ + case 365: /* gen_andw_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5289,140 +5361,140 @@ public abstract class Core extends CoreALU { sr = sr & dt; mpc = resume_prefetch; continue; - case 362: /* gen_subb_dt_ds */ + case 366: /* gen_subb_dt_ds */ ry = ir & 0x0007; dt = byte_sub(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 363: /* gen_subb_im_ea */ + case 367: /* gen_subb_im_ea */ dt = byte_sub(alub, dt); mpc = ea_resume_write8; continue; - case 364: /* gen_subw_dt_ds */ + case 368: /* gen_subw_dt_ds */ ry = ir & 0x0007; dt = word_sub(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 365: /* gen_subw_im_ea */ + case 369: /* gen_subw_im_ea */ dt = word_sub(alub, dt); mpc = ea_resume_write16; continue; - case 366: /* gen_subl_dt_ds */ + case 370: /* gen_subl_dt_ds */ ry = ir & 0x0007; dt = long_sub(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 367: /* gen_subl_im_ea */ + case 371: /* gen_subl_im_ea */ dt = long_sub(alub, dt); mpc = ea_resume_write32; continue; - case 368: /* gen_addb_dt_ds */ + case 372: /* gen_addb_dt_ds */ ry = ir & 0x0007; dt = byte_add(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 369: /* gen_addb_im_ea */ + case 373: /* gen_addb_im_ea */ dt = byte_add(alub, dt); mpc = ea_resume_write8; continue; - case 370: /* gen_addw_dt_ds */ + case 374: /* gen_addw_dt_ds */ ry = ir & 0x0007; dt = word_add(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 371: /* gen_addw_im_ea */ + case 375: /* gen_addw_im_ea */ dt = word_add(alub, dt); mpc = ea_resume_write16; continue; - case 372: /* gen_addl_dt_ds */ + case 376: /* gen_addl_dt_ds */ ry = ir & 0x0007; dt = long_add(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 373: /* gen_addl_im_ea */ + case 377: /* gen_addl_im_ea */ dt = long_add(alub, dt); mpc = ea_resume_write32; continue; - case 374: /* gen_btstl_dt_ds */ + case 378: /* gen_btstl_dt_ds */ ry = ir & 0x0007; long_btst(dt, dar[ry]); mpc = resume_prefetch; continue; - case 375: /* gen_btstb_im_ea */ + case 379: /* gen_btstb_im_ea */ byte_btst(alub, dt); mpc = resume_prefetch; continue; - case 376: /* gen_bchgl_dt_ds */ + case 380: /* gen_bchgl_dt_ds */ ry = ir & 0x0007; dt = long_bchg(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 377: /* gen_bchgb_im_ea */ + case 381: /* gen_bchgb_im_ea */ dt = byte_bchg(alub, dt); mpc = ea_resume_write8; continue; - case 378: /* gen_bclrl_dt_ds */ + case 382: /* gen_bclrl_dt_ds */ ry = ir & 0x0007; dt = long_bclr(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 379: /* gen_bclrb_im_ea */ + case 383: /* gen_bclrb_im_ea */ dt = byte_bclr(alub, dt); mpc = ea_resume_write8; continue; - case 380: /* gen_bsetl_dt_ds */ + case 384: /* gen_bsetl_dt_ds */ ry = ir & 0x0007; dt = long_bset(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 381: /* gen_bsetb_im_ea */ + case 385: /* gen_bsetb_im_ea */ dt = byte_bset(alub, dt); mpc = ea_resume_write8; continue; - case 382: /* gen_eorb_dt_ds */ + case 386: /* gen_eorb_dt_ds */ ry = ir & 0x0007; dt = byte_eor(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 383: /* gen_eorb_im_ea */ + case 387: /* gen_eorb_im_ea */ dt = byte_eor(alub, dt); mpc = ea_resume_write8; continue; - case 384: /* gen_eorw_dt_ds */ + case 388: /* gen_eorw_dt_ds */ ry = ir & 0x0007; dt = word_eor(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 385: /* gen_eorw_im_ea */ + case 389: /* gen_eorw_im_ea */ dt = word_eor(alub, dt); mpc = ea_resume_write16; continue; - case 386: /* gen_eorl_dt_ds */ + case 390: /* gen_eorl_dt_ds */ ry = ir & 0x0007; dt = long_eor(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 387: /* gen_eorl_im_ea */ + case 391: /* gen_eorl_im_ea */ dt = long_eor(alub, dt); mpc = ea_resume_write32; continue; - case 388: /* gen_eorb_dt_ccr */ + case 392: /* gen_eorb_dt_ccr */ sr = (sr & ~0xff) | ((sr ^ dt) & 0x1f); mpc = resume_prefetch; continue; - case 389: /* gen_eorw_dt_sr */ + case 393: /* gen_eorw_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5432,83 +5504,83 @@ public abstract class Core extends CoreALU { sr = (sr ^ dt) & 0xf71f; mpc = resume_prefetch; continue; - case 390: /* gen_cmpb_dt_ds */ + case 394: /* gen_cmpb_dt_ds */ ry = ir & 0x0007; byte_cmp(dt, dar[ry]); mpc = resume_prefetch; continue; - case 391: /* gen_cmpb_im_ea */ + case 395: /* gen_cmpb_im_ea */ byte_cmp(alub, dt); mpc = resume_prefetch; continue; - case 392: /* gen_cmpw_dt_ds */ + case 396: /* gen_cmpw_dt_ds */ ry = ir & 0x0007; word_cmp(dt, dar[ry]); mpc = resume_prefetch; continue; - case 393: /* gen_cmpw_im_ea */ + case 397: /* gen_cmpw_im_ea */ word_cmp(alub, dt); mpc = resume_prefetch; continue; - case 394: /* gen_cmpl_dt_ds */ + case 398: /* gen_cmpl_dt_ds */ ry = ir & 0x0007; long_cmp(dt, dar[ry]); mpc = resume_prefetch; continue; - case 395: /* gen_cmpl_im_ea */ + case 399: /* gen_cmpl_im_ea */ long_cmp(alub, dt); mpc = resume_prefetch; continue; - case 396: /* gen_moveb_ds_ea */ + case 400: /* gen_moveb_ds_ea */ ry = ir & 0x0007; byte_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write8; continue; - case 397: /* gen_moveb_dt_dd */ + case 401: /* gen_moveb_dt_dd */ rx = (ir >> 9) & 0x0007; byte_tst(dt); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 398: /* gen_moveb_ds_dd */ + case 402: /* gen_moveb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; byte_tst(dar[ry]); dar[rx] = (dar[rx] & ~0xff) | (dar[ry] & 0xff); mpc = resume_prefetch; continue; - case 399: /* gen_moveb_dt_ea */ + case 403: /* gen_moveb_dt_ea */ byte_tst(dt); mpc = ea_resume_write8; continue; - case 400: /* gen_movel_ds_ea */ + case 404: /* gen_movel_ds_ea */ ry = ir & 0x0007; long_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write32; continue; - case 401: /* gen_movel_as_ea */ + case 405: /* gen_movel_as_ea */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; long_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write32; continue; - case 402: /* gen_movel_dt_dd */ + case 406: /* gen_movel_dt_dd */ rx = (ir >> 9) & 0x0007; long_tst(dt); dar[rx] = dt; mpc = resume_prefetch; continue; - case 403: /* gen_movel_ds_dd */ + case 407: /* gen_movel_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; long_tst(dar[ry]); dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 404: /* gen_movel_as_dd */ + case 408: /* gen_movel_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5516,18 +5588,18 @@ public abstract class Core extends CoreALU { dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 405: /* gen_movel_dt_ea */ + case 409: /* gen_movel_dt_ea */ long_tst(dt); mpc = ea_resume_write32; continue; - case 406: /* gen_movel_ds_ad */ + case 410: /* gen_movel_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 407: /* gen_movel_as_ad */ + case 411: /* gen_movel_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5535,39 +5607,39 @@ public abstract class Core extends CoreALU { dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 408: /* gen_movel_dt_ad */ + case 412: /* gen_movel_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dt; mpc = resume_prefetch; continue; - case 409: /* gen_movew_ds_ea */ + case 413: /* gen_movew_ds_ea */ ry = ir & 0x0007; word_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write16; continue; - case 410: /* gen_movew_as_ea */ + case 414: /* gen_movew_as_ea */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; word_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write16; continue; - case 411: /* gen_movew_dt_dd */ + case 415: /* gen_movew_dt_dd */ rx = (ir >> 9) & 0x0007; word_tst(dt); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 412: /* gen_movew_ds_dd */ + case 416: /* gen_movew_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; word_tst(dar[ry]); dar[rx] = (dar[rx] & ~0xffff) | (dar[ry] & 0xffff); mpc = resume_prefetch; continue; - case 413: /* gen_movew_as_dd */ + case 417: /* gen_movew_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5575,18 +5647,18 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dar[ry] & 0xffff); mpc = resume_prefetch; continue; - case 414: /* gen_movew_dt_ea */ + case 418: /* gen_movew_dt_ea */ word_tst(dt); mpc = ea_resume_write16; continue; - case 415: /* gen_movew_ds_ad */ + case 419: /* gen_movew_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = (short) dar[ry]; mpc = resume_prefetch; continue; - case 416: /* gen_movew_as_ad */ + case 420: /* gen_movew_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5594,43 +5666,43 @@ public abstract class Core extends CoreALU { dar[rx] = (short) dar[ry]; mpc = resume_prefetch; continue; - case 417: /* gen_movew_dt_ad */ + case 421: /* gen_movew_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = (short) dt; mpc = resume_prefetch; continue; - case 418: /* gen_negxb_ds */ + case 422: /* gen_negxb_ds */ ry = ir & 0x0007; dt = byte_negx(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 419: /* gen_negxb_ea */ + case 423: /* gen_negxb_ea */ dt = byte_negx(dt); mpc = ea_resume_write8; continue; - case 420: /* gen_negxw_ds */ + case 424: /* gen_negxw_ds */ ry = ir & 0x0007; dt = word_negx(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 421: /* gen_negxw_ea */ + case 425: /* gen_negxw_ea */ dt = word_negx(dt); mpc = ea_resume_write16; continue; - case 422: /* gen_negxl_ds */ + case 426: /* gen_negxl_ds */ ry = ir & 0x0007; dt = long_negx(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 423: /* gen_negxl_ea */ + case 427: /* gen_negxl_ea */ dt = long_negx(dt); mpc = ea_resume_write32; continue; - case 424: /* gen_movew_sr_ds */ + case 428: /* gen_movew_sr_ds */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5641,7 +5713,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (sr & 0xffff); mpc = resume_prefetch; continue; - case 425: /* gen_movew_sr_ea */ + case 429: /* gen_movew_sr_ea */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5651,25 +5723,25 @@ public abstract class Core extends CoreALU { dt = (sr & 0xf71f); mpc = ea_resume_write16; continue; - case 426: /* gen_movew_ccr_ds */ + case 430: /* gen_movew_ccr_ds */ ry = ir & 0x0007; dar[ry] = (dar[ry] & ~0xffff) | (sr & 0x001f); mpc = resume_prefetch; continue; - case 427: /* gen_movew_ccr_ea */ + case 431: /* gen_movew_ccr_ea */ dt = (sr & 0x001f); mpc = ea_resume_write16; continue; - case 428: /* gen_movew_ds_ccr */ + case 432: /* gen_movew_ds_ccr */ ry = ir & 0x0007; sr = (sr & ~0xff) | (dar[ry] & 0x001f); mpc = resume_prefetch; continue; - case 429: /* gen_movew_dt_ccr */ + case 433: /* gen_movew_dt_ccr */ sr = (sr & ~0xff) | (dt & 0x001f); mpc = resume_prefetch; continue; - case 430: /* gen_movew_ds_sr */ + case 434: /* gen_movew_ds_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5680,7 +5752,7 @@ public abstract class Core extends CoreALU { sr = dar[ry] & 0xf71f; mpc = resume_prefetch; continue; - case 431: /* gen_movew_dt_sr */ + case 435: /* gen_movew_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5690,104 +5762,104 @@ public abstract class Core extends CoreALU { sr = dt & 0xf71f; mpc = resume_prefetch; continue; - case 432: /* gen_negb_ds */ + case 436: /* gen_negb_ds */ ry = ir & 0x0007; dt = byte_neg(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 433: /* gen_negb_ea */ + case 437: /* gen_negb_ea */ dt = byte_neg(dt); mpc = ea_resume_write8; continue; - case 434: /* gen_negw_ds */ + case 438: /* gen_negw_ds */ ry = ir & 0x0007; dt = word_neg(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 435: /* gen_negw_ea */ + case 439: /* gen_negw_ea */ dt = word_neg(dt); mpc = ea_resume_write16; continue; - case 436: /* gen_negl_ds */ + case 440: /* gen_negl_ds */ ry = ir & 0x0007; dt = long_neg(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 437: /* gen_negl_ea */ + case 441: /* gen_negl_ea */ dt = long_neg(dt); mpc = ea_resume_write32; continue; - case 438: /* gen_notb_ds */ + case 442: /* gen_notb_ds */ ry = ir & 0x0007; dt = byte_not(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 439: /* gen_notb_ea */ + case 443: /* gen_notb_ea */ dt = byte_not(dt); mpc = ea_resume_write8; continue; - case 440: /* gen_notw_ds */ + case 444: /* gen_notw_ds */ ry = ir & 0x0007; dt = word_not(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 441: /* gen_notw_ea */ + case 445: /* gen_notw_ea */ dt = word_not(dt); mpc = ea_resume_write16; continue; - case 442: /* gen_notl_ds */ + case 446: /* gen_notl_ds */ ry = ir & 0x0007; dt = long_not(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 443: /* gen_notl_ea */ + case 447: /* gen_notl_ea */ dt = long_not(dt); mpc = ea_resume_write32; continue; - case 444: /* gen_nbcdb_ds */ + case 448: /* gen_nbcdb_ds */ ry = ir & 0x0007; dt = byte_nbcd(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 445: /* gen_nbcdb_ea */ + case 449: /* gen_nbcdb_ea */ dt = byte_nbcd(dt); mpc = ea_resume_write8; continue; - case 446: /* gen_tstb_ds */ + case 450: /* gen_tstb_ds */ ry = ir & 0x0007; byte_tst(dar[ry]); mpc = resume_prefetch; continue; - case 447: /* gen_tstb_ea */ + case 451: /* gen_tstb_ea */ byte_tst(dt); mpc = resume_prefetch; continue; - case 448: /* gen_tstw_ds */ + case 452: /* gen_tstw_ds */ ry = ir & 0x0007; word_tst(dar[ry]); mpc = resume_prefetch; continue; - case 449: /* gen_tstw_ea */ + case 453: /* gen_tstw_ea */ word_tst(dt); mpc = resume_prefetch; continue; - case 450: /* gen_tstl_ds */ + case 454: /* gen_tstl_ds */ ry = ir & 0x0007; long_tst(dar[ry]); mpc = resume_prefetch; continue; - case 451: /* gen_tstl_ea */ + case 455: /* gen_tstl_ea */ long_tst(dt); mpc = resume_prefetch; continue; - case 452: /* gen_addb_ir_ds */ + case 456: /* gen_addb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5797,7 +5869,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 453: /* gen_addb_ir_ea */ + case 457: /* gen_addb_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5805,7 +5877,7 @@ public abstract class Core extends CoreALU { dt = byte_add(alub, dt); mpc = ea_resume_write8; continue; - case 454: /* gen_addw_ir_ds */ + case 458: /* gen_addw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5815,7 +5887,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 455: /* gen_addw_ir_as */ + case 459: /* gen_addw_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5825,7 +5897,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] + ((short) alub); mpc = resume_prefetch; continue; - case 456: /* gen_addw_ir_ea */ + case 460: /* gen_addw_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5833,7 +5905,7 @@ public abstract class Core extends CoreALU { dt = word_add(alub, dt); mpc = ea_resume_write16; continue; - case 457: /* gen_addl_ir_ds */ + case 461: /* gen_addl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5843,7 +5915,7 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 458: /* gen_addl_ir_as */ + case 462: /* gen_addl_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5853,7 +5925,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] + alub; mpc = resume_prefetch; continue; - case 459: /* gen_addl_ir_ea */ + case 463: /* gen_addl_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5861,7 +5933,7 @@ public abstract class Core extends CoreALU { dt = long_add(alub, dt); mpc = ea_resume_write32; continue; - case 460: /* gen_subb_ir_ds */ + case 464: /* gen_subb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5871,7 +5943,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 461: /* gen_subb_ir_ea */ + case 465: /* gen_subb_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5879,7 +5951,7 @@ public abstract class Core extends CoreALU { dt = byte_sub(alub, dt); mpc = ea_resume_write8; continue; - case 462: /* gen_subw_ir_ds */ + case 466: /* gen_subw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5889,7 +5961,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 463: /* gen_subw_ir_as */ + case 467: /* gen_subw_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5899,7 +5971,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] - ((short) alub); mpc = resume_prefetch; continue; - case 464: /* gen_subw_ir_ea */ + case 468: /* gen_subw_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5907,7 +5979,7 @@ public abstract class Core extends CoreALU { dt = word_sub(alub, dt); mpc = ea_resume_write16; continue; - case 465: /* gen_subl_ir_ds */ + case 469: /* gen_subl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5917,7 +5989,7 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 466: /* gen_subl_ir_as */ + case 470: /* gen_subl_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5927,7 +5999,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] - alub; mpc = resume_prefetch; continue; - case 467: /* gen_subl_ir_ea */ + case 471: /* gen_subl_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5935,99 +6007,99 @@ public abstract class Core extends CoreALU { dt = long_sub(alub, dt); mpc = ea_resume_write32; continue; - case 468: /* gen_movel_im_dd */ + case 472: /* gen_movel_im_dd */ dt = (byte) ir; rx = (ir >> 9) & 0x0007; long_tst(dt); dar[rx] = dt; mpc = resume_prefetch; continue; - case 469: /* gen_orb_ds_dd */ + case 473: /* gen_orb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_or(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 470: /* gen_orb_dt_dd */ + case 474: /* gen_orb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_or(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 471: /* gen_orw_ds_dd */ + case 475: /* gen_orw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_or(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 472: /* gen_orw_dt_dd */ + case 476: /* gen_orw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_or(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 473: /* gen_orl_ds_dd */ + case 477: /* gen_orl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_or(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 474: /* gen_orl_dt_dd */ + case 478: /* gen_orl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_or(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 475: /* gen_sbcdb_ds_dd */ + case 479: /* gen_sbcdb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_sbcd(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 476: /* gen_sbcdb_im_ea */ + case 480: /* gen_sbcdb_im_ea */ dt = byte_sbcd(alub, dt); mpc = ea_resume_write8; continue; - case 477: /* gen_orb_dd_ea */ + case 481: /* gen_orb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_or(dar[rx], dt); mpc = ea_resume_write8; continue; - case 478: /* gen_orw_dd_ea */ + case 482: /* gen_orw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_or(dar[rx], dt); mpc = ea_resume_write16; continue; - case 479: /* gen_orl_dd_ea */ + case 483: /* gen_orl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_or(dar[rx], dt); mpc = ea_resume_write32; continue; - case 480: /* gen_subb_ds_dd */ + case 484: /* gen_subb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_sub(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 481: /* gen_subb_dt_dd */ + case 485: /* gen_subb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_sub(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 482: /* gen_subw_ds_dd */ + case 486: /* gen_subw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_sub(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 483: /* gen_subw_as_dd */ + case 487: /* gen_subw_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6035,20 +6107,20 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 484: /* gen_subw_dt_dd */ + case 488: /* gen_subw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_sub(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 485: /* gen_subl_ds_dd */ + case 489: /* gen_subl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_sub(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 486: /* gen_subl_as_dd */ + case 490: /* gen_subl_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6056,68 +6128,68 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 487: /* gen_subl_dt_dd */ + case 491: /* gen_subl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_sub(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 488: /* gen_subb_dd_ea */ + case 492: /* gen_subb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_sub(dar[rx], dt); mpc = ea_resume_write8; continue; - case 489: /* gen_subw_dd_ea */ + case 493: /* gen_subw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_sub(dar[rx], dt); mpc = ea_resume_write16; continue; - case 490: /* gen_subl_dd_ea */ + case 494: /* gen_subl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_sub(dar[rx], dt); mpc = ea_resume_write32; continue; - case 491: /* gen_subxb_ds_dd */ + case 495: /* gen_subxb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_subx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 492: /* gen_subxb_im_ea */ + case 496: /* gen_subxb_im_ea */ dt = byte_subx(alub, dt); mpc = ea_resume_write8; continue; - case 493: /* gen_subxw_ds_dd */ + case 497: /* gen_subxw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_subx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 494: /* gen_subxw_im_ea */ + case 498: /* gen_subxw_im_ea */ dt = word_subx(alub, dt); mpc = ea_resume_write16; continue; - case 495: /* gen_subxl_ds_dd */ + case 499: /* gen_subxl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_subx(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 496: /* gen_subxl_im_ea */ + case 500: /* gen_subxl_im_ea */ dt = long_subx(alub, dt); mpc = ea_resume_write32; continue; - case 497: /* gen_subw_ds_ad */ + case 501: /* gen_subw_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - ((short) dar[ry]); mpc = resume_prefetch; continue; - case 498: /* gen_subw_as_ad */ + case 502: /* gen_subw_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6125,20 +6197,20 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] - ((short) dar[ry]); mpc = resume_prefetch; continue; - case 499: /* gen_subw_dt_ad */ + case 503: /* gen_subw_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - ((short) dt); mpc = resume_prefetch; continue; - case 500: /* gen_subl_ds_ad */ + case 504: /* gen_subl_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - dar[ry]; mpc = resume_prefetch; continue; - case 501: /* gen_subl_as_ad */ + case 505: /* gen_subl_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6146,67 +6218,67 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] - dar[ry]; mpc = resume_prefetch; continue; - case 502: /* gen_subl_dt_ad */ + case 506: /* gen_subl_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - dt; mpc = resume_prefetch; continue; - case 503: /* gen_cmpb_ds_dd */ + case 507: /* gen_cmpb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; byte_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 504: /* gen_cmpb_dt_dd */ + case 508: /* gen_cmpb_dt_dd */ rx = (ir >> 9) & 0x0007; byte_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 505: /* gen_cmpw_ds_dd */ + case 509: /* gen_cmpw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; word_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 506: /* gen_cmpw_as_dd */ + case 510: /* gen_cmpw_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; word_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 507: /* gen_cmpw_dt_dd */ + case 511: /* gen_cmpw_dt_dd */ rx = (ir >> 9) & 0x0007; word_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 508: /* gen_cmpl_ds_dd */ + case 512: /* gen_cmpl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 509: /* gen_cmpl_as_dd */ + case 513: /* gen_cmpl_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 510: /* gen_cmpl_dt_dd */ + case 514: /* gen_cmpl_dt_dd */ rx = (ir >> 9) & 0x0007; long_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 511: /* gen_cmpw_ds_ad */ + case 515: /* gen_cmpw_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp((short) dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 512: /* gen_cmpw_as_ad */ + case 516: /* gen_cmpw_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6214,20 +6286,20 @@ public abstract class Core extends CoreALU { long_cmp((short) dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 513: /* gen_cmpw_dt_ad */ + case 517: /* gen_cmpw_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp((short) dt, dar[rx]); mpc = resume_prefetch; continue; - case 514: /* gen_cmpl_ds_ad */ + case 518: /* gen_cmpl_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 515: /* gen_cmpl_as_ad */ + case 519: /* gen_cmpl_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6235,146 +6307,146 @@ public abstract class Core extends CoreALU { long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 516: /* gen_cmpl_dt_ad */ + case 520: /* gen_cmpl_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 517: /* gen_cmpmb_im_ea */ + case 521: /* gen_cmpmb_im_ea */ byte_cmp(alub, dt); mpc = resume_prefetch; continue; - case 518: /* gen_cmpmw_im_ea */ + case 522: /* gen_cmpmw_im_ea */ word_cmp(alub, dt); mpc = resume_prefetch; continue; - case 519: /* gen_cmpml_im_ea */ + case 523: /* gen_cmpml_im_ea */ long_cmp(alub, dt); mpc = resume_prefetch; continue; - case 520: /* gen_eorb_dd_ds */ + case 524: /* gen_eorb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_eor(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 521: /* gen_eorb_dd_ea */ + case 525: /* gen_eorb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_eor(dar[rx], dt); mpc = ea_resume_write8; continue; - case 522: /* gen_eorw_dd_ds */ + case 526: /* gen_eorw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_eor(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 523: /* gen_eorw_dd_ea */ + case 527: /* gen_eorw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_eor(dar[rx], dt); mpc = ea_resume_write16; continue; - case 524: /* gen_eorl_dd_ds */ + case 528: /* gen_eorl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_eor(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 525: /* gen_eorl_dd_ea */ + case 529: /* gen_eorl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_eor(dar[rx], dt); mpc = ea_resume_write32; continue; - case 526: /* gen_andb_ds_dd */ + case 530: /* gen_andb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_and(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 527: /* gen_andb_dt_dd */ + case 531: /* gen_andb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_and(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 528: /* gen_andw_ds_dd */ + case 532: /* gen_andw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_and(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 529: /* gen_andw_dt_dd */ + case 533: /* gen_andw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_and(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 530: /* gen_andl_ds_dd */ + case 534: /* gen_andl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_and(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 531: /* gen_andl_dt_dd */ + case 535: /* gen_andl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_and(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 532: /* gen_andb_dd_ea */ + case 536: /* gen_andb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_and(dar[rx], dt); mpc = ea_resume_write8; continue; - case 533: /* gen_andw_dd_ea */ + case 537: /* gen_andw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_and(dar[rx], dt); mpc = ea_resume_write16; continue; - case 534: /* gen_andl_dd_ea */ + case 538: /* gen_andl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_and(dar[rx], dt); mpc = ea_resume_write32; continue; - case 535: /* gen_abcdb_ds_dd */ + case 539: /* gen_abcdb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_abcd(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 536: /* gen_abcdb_im_ea */ + case 540: /* gen_abcdb_im_ea */ dt = byte_abcd(alub, dt); mpc = ea_resume_write8; continue; - case 537: /* gen_addb_ds_dd */ + case 541: /* gen_addb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_add(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 538: /* gen_addb_dt_dd */ + case 542: /* gen_addb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_add(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 539: /* gen_addw_ds_dd */ + case 543: /* gen_addw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_add(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 540: /* gen_addw_as_dd */ + case 544: /* gen_addw_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6382,20 +6454,20 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 541: /* gen_addw_dt_dd */ + case 545: /* gen_addw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_add(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 542: /* gen_addl_ds_dd */ + case 546: /* gen_addl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_add(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 543: /* gen_addl_as_dd */ + case 547: /* gen_addl_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6403,68 +6475,68 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 544: /* gen_addl_dt_dd */ + case 548: /* gen_addl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_add(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 545: /* gen_addb_dd_ea */ + case 549: /* gen_addb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_add(dar[rx], dt); mpc = ea_resume_write8; continue; - case 546: /* gen_addw_dd_ea */ + case 550: /* gen_addw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_add(dar[rx], dt); mpc = ea_resume_write16; continue; - case 547: /* gen_addl_dd_ea */ + case 551: /* gen_addl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_add(dar[rx], dt); mpc = ea_resume_write32; continue; - case 548: /* gen_addxb_ds_dd */ + case 552: /* gen_addxb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_addx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 549: /* gen_addxb_im_ea */ + case 553: /* gen_addxb_im_ea */ dt = byte_addx(alub, dt); mpc = ea_resume_write8; continue; - case 550: /* gen_addxw_ds_dd */ + case 554: /* gen_addxw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_addx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 551: /* gen_addxw_im_ea */ + case 555: /* gen_addxw_im_ea */ dt = word_addx(alub, dt); mpc = ea_resume_write16; continue; - case 552: /* gen_addxl_ds_dd */ + case 556: /* gen_addxl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_addx(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 553: /* gen_addxl_im_ea */ + case 557: /* gen_addxl_im_ea */ dt = long_addx(alub, dt); mpc = ea_resume_write32; continue; - case 554: /* gen_addw_ds_ad */ + case 558: /* gen_addw_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + ((short) dar[ry]); mpc = resume_prefetch; continue; - case 555: /* gen_addw_as_ad */ + case 559: /* gen_addw_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6472,20 +6544,20 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] + ((short) dar[ry]); mpc = resume_prefetch; continue; - case 556: /* gen_addw_dt_ad */ + case 560: /* gen_addw_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + ((short) dt); mpc = resume_prefetch; continue; - case 557: /* gen_addl_ds_ad */ + case 561: /* gen_addl_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + dar[ry]; mpc = resume_prefetch; continue; - case 558: /* gen_addl_as_ad */ + case 562: /* gen_addl_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6493,13 +6565,13 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] + dar[ry]; mpc = resume_prefetch; continue; - case 559: /* gen_addl_dt_ad */ + case 563: /* gen_addl_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + dt; mpc = resume_prefetch; continue; - case 560: /* gen_asrb_ir_ds */ + case 564: /* gen_asrb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6509,14 +6581,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 561: /* gen_asrb_dd_ds */ + case 565: /* gen_asrb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_asr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 562: /* gen_asrw_ir_ds */ + case 566: /* gen_asrw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6526,14 +6598,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 563: /* gen_asrw_dd_ds */ + case 567: /* gen_asrw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_asr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 564: /* gen_asrl_ir_ds */ + case 568: /* gen_asrl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6543,18 +6615,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 565: /* gen_asrl_dd_ds */ + case 569: /* gen_asrl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_asr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 566: /* gen_asrw_ea */ + case 570: /* gen_asrw_ea */ dt = word_asr(1, dt); mpc = ea_resume_write16; continue; - case 567: /* gen_aslb_ir_ds */ + case 571: /* gen_aslb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6564,14 +6636,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 568: /* gen_aslb_dd_ds */ + case 572: /* gen_aslb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_asl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 569: /* gen_aslw_ir_ds */ + case 573: /* gen_aslw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6581,14 +6653,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 570: /* gen_aslw_dd_ds */ + case 574: /* gen_aslw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_asl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 571: /* gen_asll_ir_ds */ + case 575: /* gen_asll_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6598,18 +6670,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 572: /* gen_asll_dd_ds */ + case 576: /* gen_asll_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_asl(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 573: /* gen_aslw_ea */ + case 577: /* gen_aslw_ea */ dt = word_asl(1, dt); mpc = ea_resume_write16; continue; - case 574: /* gen_lsrb_ir_ds */ + case 578: /* gen_lsrb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6619,14 +6691,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 575: /* gen_lsrb_dd_ds */ + case 579: /* gen_lsrb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_lsr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 576: /* gen_lsrw_ir_ds */ + case 580: /* gen_lsrw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6636,14 +6708,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 577: /* gen_lsrw_dd_ds */ + case 581: /* gen_lsrw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_lsr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 578: /* gen_lsrl_ir_ds */ + case 582: /* gen_lsrl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6653,18 +6725,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 579: /* gen_lsrl_dd_ds */ + case 583: /* gen_lsrl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_lsr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 580: /* gen_lsrw_ea */ + case 584: /* gen_lsrw_ea */ dt = word_lsr(1, dt); mpc = ea_resume_write16; continue; - case 581: /* gen_lslb_ir_ds */ + case 585: /* gen_lslb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6674,14 +6746,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 582: /* gen_lslb_dd_ds */ + case 586: /* gen_lslb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_lsl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 583: /* gen_lslw_ir_ds */ + case 587: /* gen_lslw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6691,14 +6763,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 584: /* gen_lslw_dd_ds */ + case 588: /* gen_lslw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_lsl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 585: /* gen_lsll_ir_ds */ + case 589: /* gen_lsll_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6708,18 +6780,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 586: /* gen_lsll_dd_ds */ + case 590: /* gen_lsll_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_lsl(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 587: /* gen_lslw_ea */ + case 591: /* gen_lslw_ea */ dt = word_lsl(1, dt); mpc = ea_resume_write16; continue; - case 588: /* gen_rorb_ir_ds */ + case 592: /* gen_rorb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6729,14 +6801,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 589: /* gen_rorb_dd_ds */ + case 593: /* gen_rorb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_ror(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 590: /* gen_rorw_ir_ds */ + case 594: /* gen_rorw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6746,14 +6818,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 591: /* gen_rorw_dd_ds */ + case 595: /* gen_rorw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_ror(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 592: /* gen_rorl_ir_ds */ + case 596: /* gen_rorl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6763,18 +6835,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 593: /* gen_rorl_dd_ds */ + case 597: /* gen_rorl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_ror(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 594: /* gen_rorw_ea */ + case 598: /* gen_rorw_ea */ dt = word_ror(1, dt); mpc = ea_resume_write16; continue; - case 595: /* gen_rolb_ir_ds */ + case 599: /* gen_rolb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6784,14 +6856,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 596: /* gen_rolb_dd_ds */ + case 600: /* gen_rolb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_rol(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 597: /* gen_rolw_ir_ds */ + case 601: /* gen_rolw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6801,14 +6873,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 598: /* gen_rolw_dd_ds */ + case 602: /* gen_rolw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_rol(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 599: /* gen_roll_ir_ds */ + case 603: /* gen_roll_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6818,14 +6890,14 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 600: /* gen_roll_dd_ds */ + case 604: /* gen_roll_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_rol(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 601: /* gen_rolw_ea */ + case 605: /* gen_rolw_ea */ dt = word_rol(1, dt); mpc = ea_resume_write16; continue; diff --git a/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java b/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java index 37c167c..46ae2ce 100644 --- a/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java +++ b/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java @@ -107,7 +107,7 @@ public class CoreALU { */ public static final int SSWI_XRMW = 1 << 6; /** - * Downgrade to 68000 for Bcc/dais + * Downgrade to 68000 for Bcc/CHK/dais */ public static final int SSWI_DNGR = 1 << 5; /** @@ -1141,8 +1141,14 @@ public class CoreALU { return true; } - /* leave N flag and continue execution */ - sr ^= (sr ^ z) & (FL_C | FL_V | FL_Z); + if ((sswi & SSWI_DNGR) != 0) { + int n = (dst >> 28) & FL_N; + + sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N); + } else { + /* leave N flag and continue execution */ + sr ^= (sr ^ z) & (FL_C | FL_V | FL_Z); + } return false; } diff --git a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java index 2930fa2..16767a2 100644 --- a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java +++ b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java @@ -2114,23 +2114,23 @@ public enum MacroPLA { subq_l_imm3_adr32(0x51b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_subl_ir_ea), - bra_rel16(0x6000, 0xffff, op_imm16, op_bra16, dbrr), + bra_rel16(0x6000, 0xffff, op_bra16, dbrr, dbrr), - bcc_rel16(0x6000, 0xf0ff, op_imm16, op_bcc16, dbrr), + bcc_rel16(0x6000, 0xf0ff, op_bcc16, dbrr, dbrr), bra_rel8(0x6000, 0xff00, op_bra8, dbrr, dbrr), bcc_rel8(0x6000, 0xf000, op_bcc8, dbrr, dbrr), - bra_rel32(0x60ff, 0xffff, op_imm32, op_bra32, dbrr), + bra_rel32(0x60ff, 0xffff, op_bra32, dbrr, dbrr), - bcc_rel32(0x60ff, 0xf0ff, op_imm32, op_bcc32, dbrr), + bcc_rel32(0x60ff, 0xf0ff, op_bcc32, dbrr, dbrr), - bsr_rel16(0x6100, 0xffff, op_imm16, op_bsr16, dbrr), + bsr_rel16(0x6100, 0xffff, op_bsr16, dbrr, dbrr), bsr_rel8(0x6100, 0xff00, op_bsr8, dbrr, dbrr), - bsr_rel32(0x61ff, 0xffff, op_imm32, op_bsr32, dbrr), + bsr_rel32(0x61ff, 0xffff, op_bsr32, dbrr, dbrr), moveq_imm8o_dd(0x7000, 0xf100, gen_movel_im_dd, dbrr, dbrr), diff --git a/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java b/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java index 3984022..7c29402 100644 --- a/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java +++ b/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java @@ -91,8 +91,8 @@ public class InstructionTests extends TestCase { public void testBcc() { CoreTest test = new CoreTest(0xffffff + 1, true); - test.executeBinTest("Bcc", 373, 466, 570, 1547, 1695, 1782, 2166, 2224, 2441); - test.executeBinTest("BSR", 25, 573, 814, 1357, 1443, 1509, 1734, 1934, 2232, 2338); + test.executeBinTest("Bcc"); + test.executeBinTest("BSR"); } public void testDBcc() { @@ -104,6 +104,7 @@ public class InstructionTests extends TestCase { public void testMisc() { CoreTest test = new CoreTest(0xffffff + 1, true); + test.executeBinTest("CHK"); test.executeBinTest("NOP"); test.executeBinTest("EXG"); test.executeBinTest("SWAP"); diff --git a/miggy-emu/src/test/resources/miggy/cpupoet/CHK.json.bin b/miggy-emu/src/test/resources/miggy/cpupoet/CHK.json.bin new file mode 100644 index 0000000..992f608 Binary files /dev/null and b/miggy-emu/src/test/resources/miggy/cpupoet/CHK.json.bin differ