From 0a4e1a5764bb7bbab9973e58d6db2795913cae8c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rodolphe=20de=20Saint=20L=C3=A9ger?= Date: Tue, 13 May 2025 11:10:19 +0200 Subject: [PATCH] add movem declaration --- .../java/miggy/cpu/genpoet/CoreGenerator.java | 32 +- .../miggy/cpu/genpoet/CorePLAGenerator.java | 48 + .../src/main/java/miggy/cpupoet/Core.java | 2306 +++++++++-------- .../src/main/java/miggy/cpupoet/MacroPLA.java | 74 + 4 files changed, 1300 insertions(+), 1160 deletions(-) diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java index b4f4d66..278de40 100644 --- a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java +++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java @@ -1254,18 +1254,18 @@ public class CoreGenerator { addFormattedMicroInsn("break"); addState("ea_dpc32_read"); - //setclr16("sswi", SSWI_EAFH, 0); - //addState("ea_dpc32"); + setclr16("sswi", SSWI_EAFH, 0); + addState("ea_dpc32"); fetchimm16("at", 0); addFormattedMicroInsn("at = ((short) at) + pc"); // add pc to temporary register - //addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); - //consume(4, 1, 0); - //addFormattedMicroInsn("nmpc = decoded.a3"); - //addFormattedMicroInsn("break"); - //addEndControlFlow(); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(4, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); consume(12, 3, 0); addState("eapc_read32"); - //setclr16("sswi", 0, SSWI_EAFH); + setclr16("sswi", 0, SSWI_EAFH); addFormattedMicroInsn("alub = dt"); // save dt to alub anyread32("dt", SSW_DF | SSW_P, "at", 0, false, null); addClearSSW(); @@ -1291,13 +1291,13 @@ public class CoreGenerator { addFormattedMicroInsn("mpc = eapc_read16"); addFormattedMicroInsn("continue"); - ea_dais_calculate_microcode("dpci", "32", true, true); + ea_dais_calculate_microcode("dpci", "32", true, false); addState("ea_dpci32_fetch"); - //addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); - //consume(8, 1, 0); - //addFormattedMicroInsn("nmpc = decoded.a3"); - //addFormattedMicroInsn("break"); - //addEndControlFlow(); + addBeginFormattedControlFlow("if ((sswi & 0x%04x) == 0)", SSWI_EAFH); + consume(8, 1, 0); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addEndControlFlow(); consume(14, 3, 0); addFormattedMicroInsn("mpc = eapc_read32"); addFormattedMicroInsn("continue"); @@ -1820,7 +1820,7 @@ public class CoreGenerator { addFormattedMicroInsn("mpc = %d", loop); addFormattedMicroInsn("continue"); - addState("op_movemw_aisp_rr"); + addState("op_movemw_aips_rr"); // read extension word anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { addFormattedMicroInsn("scan += 2"); @@ -1881,7 +1881,7 @@ public class CoreGenerator { addFormattedMicroInsn("mpc = %d", loop); addFormattedMicroInsn("continue"); - addState("op_moveml_aisp_rr"); + addState("op_moveml_aips_rr"); // read extension word anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { addFormattedMicroInsn("scan += 2"); diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java index 6ecab69..b8eceb4 100644 --- a/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java +++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java @@ -425,6 +425,54 @@ public class CorePLAGenerator { appendOP(gen, entries, array, 0x4e7a, 0xffff, "movec_cr_rz", "op_movec_cr_rz", "dbrr", "dbrr"); appendOP(gen, entries, array, 0x4e7b, 0xffff, "movec_rz_cr", "op_movec_rz_cr", "dbrr", "dbrr"); + appendOP_eas(0x4890, 0xffc0, "movem_w_list", EA_CTRL, "16", (opcode, opmask, opname, n1, mode) -> { + //opname = String.format("%s", opname); + + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_movemw_rr_ea"); + }); + + appendOP_eas(0x4890, 0xffc0, "movem_w_listp", EA_PAIS, "16", (opcode, opmask, opname, n1, mode) -> { + //opname = String.format("%s", opname); + + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_movemw_rr_pais"); + }); + + appendOP_eas(0x48d0, 0xffc0, "movem_l_list", EA_CTRL, "32", (opcode, opmask, opname, n1, mode) -> { + //opname = String.format("%s", opname); + + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_moveml_rr_ea"); + }); + + appendOP_eas(0x48d0, 0xffc0, "movem_l_listp", EA_PAIS, "32", (opcode, opmask, opname, n1, mode) -> { + //opname = String.format("%s", opname); + + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_moveml_rr_pais"); + }); + + appendOP_eas(0x4c90, 0xffc0, "movem_w", EA_CTRL, "16", (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_list", opname); + + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_movemw_ea_rr"); + }); + + appendOP_eas(0x4c90, 0xffc0, "movem_w", EA_AIPS, "16", (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_list", opname); + + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_movemw_aips_rr"); + }); + + appendOP_eas(0x4cd0, 0xffc0, "movem_l", EA_CTRL, "32", (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_list", opname); + + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_moveml_ea_rr"); + }); + + appendOP_eas(0x4cd0, 0xffc0, "movem_l", EA_AIPS, "32", (opcode, opmask, opname, n1, mode) -> { + opname = String.format("%s_list", opname); + + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_moveml_aips_rr"); + }); + appendOP_eas(0x4e90, 0xffc0, "jsr", EA_CTRL, "16", (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s", opname); diff --git a/miggy-emu/src/main/java/miggy/cpupoet/Core.java b/miggy-emu/src/main/java/miggy/cpupoet/Core.java index 9d58c12..cb0f73d 100644 --- a/miggy-emu/src/main/java/miggy/cpupoet/Core.java +++ b/miggy-emu/src/main/java/miggy/cpupoet/Core.java @@ -239,749 +239,753 @@ public abstract class Core extends CoreALU { protected static final int ea_dpc32_read = 157; - private static final int eapc_read32 = 159; + protected static final int ea_dpc32 = 158; - protected static final int ea_dpci8_read = 161; + private static final int eapc_read32 = 160; - private static final int ea_dpci8_base = 163; + protected static final int ea_dpci8_read = 162; - private static final int ea_dpci8_no_base = 164; + private static final int ea_dpci8_base = 164; - private static final int ea_dpci8_outer = 166; + private static final int ea_dpci8_no_base = 165; - private static final int ea_dpci8_fetch = 167; + private static final int ea_dpci8_outer = 167; - protected static final int ea_dpci16_read = 168; + private static final int ea_dpci8_fetch = 168; - protected static final int ea_dpci16 = 169; + protected static final int ea_dpci16_read = 169; - private static final int ea_dpci16_base = 171; + protected static final int ea_dpci16 = 170; - private static final int ea_dpci16_no_base = 172; + private static final int ea_dpci16_base = 172; - private static final int ea_dpci16_outer = 174; + private static final int ea_dpci16_no_base = 173; - private static final int ea_dpci16_fetch = 175; + private static final int ea_dpci16_outer = 175; - protected static final int ea_dpci32_read = 176; + private static final int ea_dpci16_fetch = 176; - private static final int ea_dpci32_base = 178; + protected static final int ea_dpci32_read = 177; - private static final int ea_dpci32_no_base = 179; + protected static final int ea_dpci32 = 178; - private static final int ea_dpci32_outer = 181; + private static final int ea_dpci32_base = 180; - private static final int ea_dpci32_fetch = 182; + private static final int ea_dpci32_no_base = 181; - protected static final int ea_adr16d8 = 183; + private static final int ea_dpci32_outer = 183; - protected static final int ea_adr16d16 = 185; + private static final int ea_dpci32_fetch = 184; - protected static final int ea_adr16d32 = 187; + protected static final int ea_adr16d8 = 185; - protected static final int ea_adr16s8_read = 189; + protected static final int ea_adr16d16 = 187; - protected static final int ea_adr16s8 = 190; + protected static final int ea_adr16d32 = 189; - protected static final int ea_adr16s16_read = 192; + protected static final int ea_adr16s8_read = 191; - protected static final int ea_adr16s16 = 193; + protected static final int ea_adr16s8 = 192; - protected static final int ea_adr16s32_read = 195; + protected static final int ea_adr16s16_read = 194; - protected static final int ea_adr16s32 = 196; + protected static final int ea_adr16s16 = 195; - protected static final int ea_adr32d8 = 198; + protected static final int ea_adr16s32_read = 197; - protected static final int ea_adr32d16 = 199; + protected static final int ea_adr16s32 = 198; - protected static final int ea_adr32d32 = 200; + protected static final int ea_adr32d8 = 200; - protected static final int ea_adr32s8_read = 202; + protected static final int ea_adr32d16 = 201; - protected static final int ea_adr32s8 = 203; + protected static final int ea_adr32d32 = 202; - protected static final int ea_adr32s16_read = 205; + protected static final int ea_adr32s8_read = 204; - protected static final int ea_adr32s16 = 206; + protected static final int ea_adr32s8 = 205; - protected static final int ea_adr32s32_read = 208; + protected static final int ea_adr32s16_read = 207; - protected static final int ea_adr32s32 = 209; + protected static final int ea_adr32s16 = 208; - protected static final int ea_imm8_read = 211; + protected static final int ea_adr32s32_read = 210; - protected static final int ea_imm16_read = 213; + protected static final int ea_adr32s32 = 211; - protected static final int ea_imm32_read = 215; + protected static final int ea_imm8_read = 213; - protected static final int op_movepw_dd_das = 217; + protected static final int ea_imm16_read = 215; - protected static final int op_movepw_das_dd = 221; + protected static final int ea_imm32_read = 217; - protected static final int op_movepl_dd_das = 224; + protected static final int op_movepw_dd_das = 219; - protected static final int op_movepl_das_dd = 230; + protected static final int op_movepw_das_dd = 223; - protected static final int op_clrb_ds = 235; + protected static final int op_movepl_dd_das = 226; - protected static final int op_clrw_ds = 236; + protected static final int op_movepl_das_dd = 232; - protected static final int op_clrl_ds = 237; + protected static final int op_clrb_ds = 237; - protected static final int op_clrb_ea = 238; + protected static final int op_clrw_ds = 238; - protected static final int op_clrw_ea = 239; + protected static final int op_clrl_ds = 239; - protected static final int op_clrl_ea = 240; + protected static final int op_clrb_ea = 240; - protected static final int op_lea_ea_ad = 241; + protected static final int op_clrw_ea = 241; - protected static final int op_pea = 242; + protected static final int op_clrl_ea = 242; - protected static final int op_swap_ds = 244; + protected static final int op_lea_ea_ad = 243; - protected static final int op_extw_ds = 245; + protected static final int op_pea = 244; - protected static final int op_extl_ds = 246; + protected static final int op_swap_ds = 246; - protected static final int op_extbl_ds = 247; + protected static final int op_extw_ds = 247; - protected static final int op_exg_dd_ds = 248; + protected static final int op_extl_ds = 248; - protected static final int op_exg_ad_as = 249; + protected static final int op_extbl_ds = 249; - protected static final int op_exg_dd_as = 250; + protected static final int op_exg_dd_ds = 250; - protected static final int op_scc_b_ds = 251; + protected static final int op_exg_ad_as = 251; - protected static final int op_scc_b_ea = 252; + protected static final int op_exg_dd_as = 252; - protected static final int op_chk_w_ds = 253; + protected static final int op_scc_b_ds = 253; - protected static final int op_chk_w_ea = 254; + protected static final int op_scc_b_ea = 254; - protected static final int op_link_as_imm16 = 255; + protected static final int op_chk_w_ds = 255; - protected static final int op_link_as_imm32 = 257; + protected static final int op_chk_w_ea = 256; - protected static final int op_unlk_as = 259; + protected static final int op_link_as_imm16 = 257; - protected static final int op_move_usp_as = 261; + protected static final int op_link_as_imm32 = 259; - protected static final int op_move_as_usp = 262; + protected static final int op_unlk_as = 261; - protected static final int op_movec_cr_rz = 263; + protected static final int op_move_usp_as = 263; - protected static final int op_movec_rz_cr = 265; + protected static final int op_move_as_usp = 264; - private static final int op_movemw_rr_ea = 267; + protected static final int op_movec_cr_rz = 265; - private static final int op_movemw_rr_pais = 271; + protected static final int op_movec_rz_cr = 267; - private static final int op_moveml_rr_ea = 275; + protected static final int op_movemw_rr_ea = 269; - private static final int op_moveml_rr_pais = 279; + protected static final int op_movemw_rr_pais = 273; - private static final int op_movemw_ea_rr = 283; + protected static final int op_moveml_rr_ea = 277; - private static final int op_movemw_aisp_rr = 288; + protected static final int op_moveml_rr_pais = 281; - private static final int op_moveml_ea_rr = 293; + protected static final int op_movemw_ea_rr = 285; - private static final int op_moveml_aisp_rr = 298; + protected static final int op_movemw_aips_rr = 290; - protected static final int op_bcc8 = 303; + protected static final int op_moveml_ea_rr = 295; - protected static final int op_bra8 = 304; + protected static final int op_moveml_aips_rr = 300; - protected static final int op_bcc16 = 305; + protected static final int op_bcc8 = 305; - protected static final int op_bra16 = 306; + protected static final int op_bra8 = 306; - protected static final int op_bcc32 = 307; + protected static final int op_bcc16 = 307; - protected static final int op_bra32 = 308; + protected static final int op_bra16 = 308; - protected static final int op_bsr8 = 309; + protected static final int op_bcc32 = 309; - protected static final int op_bsr16 = 311; + protected static final int op_bra32 = 310; - protected static final int op_bsr32 = 313; + protected static final int op_bsr8 = 311; - protected static final int op_dbcc = 315; + protected static final int op_bsr16 = 313; - protected static final int op_bkpt = 317; + protected static final int op_bsr32 = 315; - protected static final int op_illegal = 318; + protected static final int op_dbcc = 317; - protected static final int op_jmp = 319; + protected static final int op_bkpt = 319; - protected static final int op_jsr = 320; + protected static final int op_illegal = 320; - protected static final int op_linea = 322; + protected static final int op_jmp = 321; - protected static final int op_linef = 323; + protected static final int op_jsr = 322; - protected static final int op_nop = 324; + protected static final int op_linea = 324; - protected static final int op_rte = 325; + protected static final int op_linef = 325; - private static final int check_vob = 326; + protected static final int op_nop = 326; - private static final int rteill = 327; + protected static final int op_rte = 327; - private static final int exit_trap = 328; + private static final int check_vob = 328; - private static final int rte0000 = 329; + private static final int rteill = 329; - private static final int rte1000 = 330; + private static final int exit_trap = 330; - private static final int rte2000 = 331; + private static final int rte0000 = 331; - private static final int rte8000 = 332; + private static final int rte1000 = 332; - protected static final int op_rtr = 333; + private static final int rte2000 = 333; - protected static final int op_rts = 336; + private static final int rte8000 = 334; - protected static final int op_reset = 338; + protected static final int op_rtr = 335; - protected static final int op_trap = 339; + protected static final int op_rts = 338; - protected static final int op_trapv = 340; + protected static final int op_reset = 340; - protected static final int op_trapcc = 341; + protected static final int op_trap = 341; - protected static final int op_trapcc16 = 342; + protected static final int op_trapv = 342; - protected static final int op_trapcc32 = 343; + protected static final int op_trapcc = 343; - protected static final int gen_orb_dt_ds = 344; + protected static final int op_trapcc16 = 344; - protected static final int gen_orb_im_ea = 345; + protected static final int op_trapcc32 = 345; - protected static final int gen_orw_dt_ds = 346; + protected static final int gen_orb_dt_ds = 346; - protected static final int gen_orw_im_ea = 347; + protected static final int gen_orb_im_ea = 347; - protected static final int gen_orl_dt_ds = 348; + protected static final int gen_orw_dt_ds = 348; - protected static final int gen_orl_im_ea = 349; + protected static final int gen_orw_im_ea = 349; - protected static final int gen_orb_dt_ccr = 350; + protected static final int gen_orl_dt_ds = 350; - protected static final int gen_orw_dt_sr = 351; + protected static final int gen_orl_im_ea = 351; - protected static final int gen_btstl_dd_ds = 352; + protected static final int gen_orb_dt_ccr = 352; - protected static final int gen_btstb_dd_ea = 353; + protected static final int gen_orw_dt_sr = 353; - protected static final int gen_bchgl_dd_ds = 354; + protected static final int gen_btstl_dd_ds = 354; - protected static final int gen_bchgb_dd_ea = 355; + protected static final int gen_btstb_dd_ea = 355; - protected static final int gen_bclrl_dd_ds = 356; + protected static final int gen_bchgl_dd_ds = 356; - protected static final int gen_bclrb_dd_ea = 357; + protected static final int gen_bchgb_dd_ea = 357; - protected static final int gen_bsetl_dd_ds = 358; + protected static final int gen_bclrl_dd_ds = 358; - protected static final int gen_bsetb_dd_ea = 359; + protected static final int gen_bclrb_dd_ea = 359; - protected static final int gen_andb_dt_ds = 360; + protected static final int gen_bsetl_dd_ds = 360; - protected static final int gen_andb_im_ea = 361; + protected static final int gen_bsetb_dd_ea = 361; - protected static final int gen_andw_dt_ds = 362; + protected static final int gen_andb_dt_ds = 362; - protected static final int gen_andw_im_ea = 363; + protected static final int gen_andb_im_ea = 363; - protected static final int gen_andl_dt_ds = 364; + protected static final int gen_andw_dt_ds = 364; - protected static final int gen_andl_im_ea = 365; + protected static final int gen_andw_im_ea = 365; - protected static final int gen_andb_dt_ccr = 366; + protected static final int gen_andl_dt_ds = 366; - protected static final int gen_andw_dt_sr = 367; + protected static final int gen_andl_im_ea = 367; - protected static final int gen_subb_dt_ds = 368; + protected static final int gen_andb_dt_ccr = 368; - protected static final int gen_subb_im_ea = 369; + protected static final int gen_andw_dt_sr = 369; - protected static final int gen_subw_dt_ds = 370; + protected static final int gen_subb_dt_ds = 370; - protected static final int gen_subw_im_ea = 371; + protected static final int gen_subb_im_ea = 371; - protected static final int gen_subl_dt_ds = 372; + protected static final int gen_subw_dt_ds = 372; - protected static final int gen_subl_im_ea = 373; + protected static final int gen_subw_im_ea = 373; - protected static final int gen_addb_dt_ds = 374; + protected static final int gen_subl_dt_ds = 374; - protected static final int gen_addb_im_ea = 375; + protected static final int gen_subl_im_ea = 375; - protected static final int gen_addw_dt_ds = 376; + protected static final int gen_addb_dt_ds = 376; - protected static final int gen_addw_im_ea = 377; + protected static final int gen_addb_im_ea = 377; - protected static final int gen_addl_dt_ds = 378; + protected static final int gen_addw_dt_ds = 378; - protected static final int gen_addl_im_ea = 379; + protected static final int gen_addw_im_ea = 379; - protected static final int gen_btstl_dt_ds = 380; + protected static final int gen_addl_dt_ds = 380; - protected static final int gen_btstb_im_ea = 381; + protected static final int gen_addl_im_ea = 381; - protected static final int gen_bchgl_dt_ds = 382; + protected static final int gen_btstl_dt_ds = 382; - protected static final int gen_bchgb_im_ea = 383; + protected static final int gen_btstb_im_ea = 383; - protected static final int gen_bclrl_dt_ds = 384; + protected static final int gen_bchgl_dt_ds = 384; - protected static final int gen_bclrb_im_ea = 385; + protected static final int gen_bchgb_im_ea = 385; - protected static final int gen_bsetl_dt_ds = 386; + protected static final int gen_bclrl_dt_ds = 386; - protected static final int gen_bsetb_im_ea = 387; + protected static final int gen_bclrb_im_ea = 387; - protected static final int gen_eorb_dt_ds = 388; + protected static final int gen_bsetl_dt_ds = 388; - protected static final int gen_eorb_im_ea = 389; + protected static final int gen_bsetb_im_ea = 389; - protected static final int gen_eorw_dt_ds = 390; + protected static final int gen_eorb_dt_ds = 390; - protected static final int gen_eorw_im_ea = 391; + protected static final int gen_eorb_im_ea = 391; - protected static final int gen_eorl_dt_ds = 392; + protected static final int gen_eorw_dt_ds = 392; - protected static final int gen_eorl_im_ea = 393; + protected static final int gen_eorw_im_ea = 393; - protected static final int gen_eorb_dt_ccr = 394; + protected static final int gen_eorl_dt_ds = 394; - protected static final int gen_eorw_dt_sr = 395; + protected static final int gen_eorl_im_ea = 395; - protected static final int gen_cmpb_dt_ds = 396; + protected static final int gen_eorb_dt_ccr = 396; - protected static final int gen_cmpb_im_ea = 397; + protected static final int gen_eorw_dt_sr = 397; - protected static final int gen_cmpw_dt_ds = 398; + protected static final int gen_cmpb_dt_ds = 398; - protected static final int gen_cmpw_im_ea = 399; + protected static final int gen_cmpb_im_ea = 399; - protected static final int gen_cmpl_dt_ds = 400; + protected static final int gen_cmpw_dt_ds = 400; - protected static final int gen_cmpl_im_ea = 401; + protected static final int gen_cmpw_im_ea = 401; - protected static final int gen_moveb_ds_ea = 402; + protected static final int gen_cmpl_dt_ds = 402; - protected static final int gen_moveb_dt_dd = 403; + protected static final int gen_cmpl_im_ea = 403; - protected static final int gen_moveb_ds_dd = 404; + protected static final int gen_moveb_ds_ea = 404; - protected static final int gen_moveb_dt_ea = 405; + protected static final int gen_moveb_dt_dd = 405; - protected static final int gen_movel_ds_ea = 406; + protected static final int gen_moveb_ds_dd = 406; - protected static final int gen_movel_as_ea = 407; + protected static final int gen_moveb_dt_ea = 407; - protected static final int gen_movel_dt_dd = 408; + protected static final int gen_movel_ds_ea = 408; - protected static final int gen_movel_ds_dd = 409; + protected static final int gen_movel_as_ea = 409; - protected static final int gen_movel_as_dd = 410; + protected static final int gen_movel_dt_dd = 410; - protected static final int gen_movel_dt_ea = 411; + protected static final int gen_movel_ds_dd = 411; - protected static final int gen_movel_ds_ad = 412; + protected static final int gen_movel_as_dd = 412; - protected static final int gen_movel_as_ad = 413; + protected static final int gen_movel_dt_ea = 413; - protected static final int gen_movel_dt_ad = 414; + protected static final int gen_movel_ds_ad = 414; - protected static final int gen_movew_ds_ea = 415; + protected static final int gen_movel_as_ad = 415; - protected static final int gen_movew_as_ea = 416; + protected static final int gen_movel_dt_ad = 416; - protected static final int gen_movew_dt_dd = 417; + protected static final int gen_movew_ds_ea = 417; - protected static final int gen_movew_ds_dd = 418; + protected static final int gen_movew_as_ea = 418; - protected static final int gen_movew_as_dd = 419; + protected static final int gen_movew_dt_dd = 419; - protected static final int gen_movew_dt_ea = 420; + protected static final int gen_movew_ds_dd = 420; - protected static final int gen_movew_ds_ad = 421; + protected static final int gen_movew_as_dd = 421; - protected static final int gen_movew_as_ad = 422; + protected static final int gen_movew_dt_ea = 422; - protected static final int gen_movew_dt_ad = 423; + protected static final int gen_movew_ds_ad = 423; - protected static final int gen_negxb_ds = 424; + protected static final int gen_movew_as_ad = 424; - protected static final int gen_negxb_ea = 425; + protected static final int gen_movew_dt_ad = 425; - protected static final int gen_negxw_ds = 426; + protected static final int gen_negxb_ds = 426; - protected static final int gen_negxw_ea = 427; + protected static final int gen_negxb_ea = 427; - protected static final int gen_negxl_ds = 428; + protected static final int gen_negxw_ds = 428; - protected static final int gen_negxl_ea = 429; + protected static final int gen_negxw_ea = 429; - protected static final int gen_movew_sr_ds = 430; + protected static final int gen_negxl_ds = 430; - protected static final int gen_movew_sr_ea = 431; + protected static final int gen_negxl_ea = 431; - protected static final int gen_movew_ccr_ds = 432; + protected static final int gen_movew_sr_ds = 432; - protected static final int gen_movew_ccr_ea = 433; + protected static final int gen_movew_sr_ea = 433; - protected static final int gen_movew_ds_ccr = 434; + protected static final int gen_movew_ccr_ds = 434; - protected static final int gen_movew_dt_ccr = 435; + protected static final int gen_movew_ccr_ea = 435; - protected static final int gen_movew_ds_sr = 436; + protected static final int gen_movew_ds_ccr = 436; - protected static final int gen_movew_dt_sr = 437; + protected static final int gen_movew_dt_ccr = 437; - protected static final int gen_negb_ds = 438; + protected static final int gen_movew_ds_sr = 438; - protected static final int gen_negb_ea = 439; + protected static final int gen_movew_dt_sr = 439; - protected static final int gen_negw_ds = 440; + protected static final int gen_negb_ds = 440; - protected static final int gen_negl_ea = 441; + protected static final int gen_negb_ea = 441; - protected static final int gen_negl_ds = 442; + protected static final int gen_negw_ds = 442; - protected static final int gen_notb_ds = 443; + protected static final int gen_negl_ea = 443; - protected static final int gen_notb_ea = 444; + protected static final int gen_negl_ds = 444; - protected static final int gen_notw_ds = 445; + protected static final int gen_notb_ds = 445; - protected static final int gen_notw_ea = 446; + protected static final int gen_notb_ea = 446; - protected static final int gen_notl_ds = 447; + protected static final int gen_notw_ds = 447; - protected static final int gen_notl_ea = 448; + protected static final int gen_notw_ea = 448; - protected static final int gen_nbcdb_ds = 449; + protected static final int gen_notl_ds = 449; - protected static final int gen_nbcdb_ea = 450; + protected static final int gen_notl_ea = 450; - protected static final int gen_tstb_ds = 451; + protected static final int gen_nbcdb_ds = 451; - protected static final int gen_tstb_ea = 452; + protected static final int gen_nbcdb_ea = 452; - protected static final int gen_tstw_ds = 453; + protected static final int gen_tstb_ds = 453; - protected static final int gen_tstw_ea = 454; + protected static final int gen_tstb_ea = 454; - protected static final int gen_tstl_ds = 455; + protected static final int gen_tstw_ds = 455; - protected static final int gen_tstl_ea = 456; + protected static final int gen_tstw_ea = 456; - protected static final int gen_addb_ir_ds = 457; + protected static final int gen_tstl_ds = 457; - protected static final int gen_addb_ir_ea = 458; + protected static final int gen_tstl_ea = 458; - protected static final int gen_addw_ir_ds = 459; + protected static final int gen_addb_ir_ds = 459; - protected static final int gen_addw_ir_as = 460; + protected static final int gen_addb_ir_ea = 460; - protected static final int gen_addw_ir_ea = 461; + protected static final int gen_addw_ir_ds = 461; - protected static final int gen_addl_ir_ds = 462; + protected static final int gen_addw_ir_as = 462; - protected static final int gen_addl_ir_as = 463; + protected static final int gen_addw_ir_ea = 463; - protected static final int gen_addl_ir_ea = 464; + protected static final int gen_addl_ir_ds = 464; - protected static final int gen_subb_ir_ds = 465; + protected static final int gen_addl_ir_as = 465; - protected static final int gen_subb_ir_ea = 466; + protected static final int gen_addl_ir_ea = 466; - protected static final int gen_subw_ir_ds = 467; + protected static final int gen_subb_ir_ds = 467; - protected static final int gen_subw_ir_as = 468; + protected static final int gen_subb_ir_ea = 468; - protected static final int gen_subw_ir_ea = 469; + protected static final int gen_subw_ir_ds = 469; - protected static final int gen_subl_ir_ds = 470; + protected static final int gen_subw_ir_as = 470; - protected static final int gen_subl_ir_as = 471; + protected static final int gen_subw_ir_ea = 471; - protected static final int gen_subl_ir_ea = 472; + protected static final int gen_subl_ir_ds = 472; - protected static final int gen_movel_im_dd = 473; + protected static final int gen_subl_ir_as = 473; - protected static final int gen_orb_ds_dd = 474; + protected static final int gen_subl_ir_ea = 474; - protected static final int gen_orb_dt_dd = 475; + protected static final int gen_movel_im_dd = 475; - protected static final int gen_orw_ds_dd = 476; + protected static final int gen_orb_ds_dd = 476; - protected static final int gen_orw_dt_dd = 477; + protected static final int gen_orb_dt_dd = 477; - protected static final int gen_orl_ds_dd = 478; + protected static final int gen_orw_ds_dd = 478; - protected static final int gen_orl_dt_dd = 479; + protected static final int gen_orw_dt_dd = 479; - protected static final int gen_sbcdb_ds_dd = 480; + protected static final int gen_orl_ds_dd = 480; - protected static final int gen_sbcdb_im_ea = 481; + protected static final int gen_orl_dt_dd = 481; - protected static final int gen_orb_dd_ea = 482; + protected static final int gen_sbcdb_ds_dd = 482; - protected static final int gen_orw_dd_ea = 483; + protected static final int gen_sbcdb_im_ea = 483; - protected static final int gen_orl_dd_ea = 484; + protected static final int gen_orb_dd_ea = 484; - protected static final int gen_subb_ds_dd = 485; + protected static final int gen_orw_dd_ea = 485; - protected static final int gen_subb_dt_dd = 486; + protected static final int gen_orl_dd_ea = 486; - protected static final int gen_subw_ds_dd = 487; + protected static final int gen_subb_ds_dd = 487; - protected static final int gen_subw_as_dd = 488; + protected static final int gen_subb_dt_dd = 488; - protected static final int gen_subw_dt_dd = 489; + protected static final int gen_subw_ds_dd = 489; - protected static final int gen_subl_ds_dd = 490; + protected static final int gen_subw_as_dd = 490; - protected static final int gen_subl_as_dd = 491; + protected static final int gen_subw_dt_dd = 491; - protected static final int gen_subl_dt_dd = 492; + protected static final int gen_subl_ds_dd = 492; - protected static final int gen_subb_dd_ea = 493; + protected static final int gen_subl_as_dd = 493; - protected static final int gen_subw_dd_ea = 494; + protected static final int gen_subl_dt_dd = 494; - protected static final int gen_subl_dd_ea = 495; + protected static final int gen_subb_dd_ea = 495; - protected static final int gen_subxb_ds_dd = 496; + protected static final int gen_subw_dd_ea = 496; - protected static final int gen_subxb_im_ea = 497; + protected static final int gen_subl_dd_ea = 497; - protected static final int gen_subxw_ds_dd = 498; + protected static final int gen_subxb_ds_dd = 498; - protected static final int gen_subxw_im_ea = 499; + protected static final int gen_subxb_im_ea = 499; - protected static final int gen_subxl_ds_dd = 500; + protected static final int gen_subxw_ds_dd = 500; - protected static final int gen_subxl_im_ea = 501; + protected static final int gen_subxw_im_ea = 501; - protected static final int gen_subw_ds_ad = 502; + protected static final int gen_subxl_ds_dd = 502; - protected static final int gen_subw_as_ad = 503; + protected static final int gen_subxl_im_ea = 503; - protected static final int gen_subw_dt_ad = 504; + protected static final int gen_subw_ds_ad = 504; - protected static final int gen_subl_ds_ad = 505; + protected static final int gen_subw_as_ad = 505; - protected static final int gen_subl_as_ad = 506; + protected static final int gen_subw_dt_ad = 506; - protected static final int gen_subl_dt_ad = 507; + protected static final int gen_subl_ds_ad = 507; - protected static final int gen_cmpb_ds_dd = 508; + protected static final int gen_subl_as_ad = 508; - protected static final int gen_cmpb_dt_dd = 509; + protected static final int gen_subl_dt_ad = 509; - protected static final int gen_cmpw_ds_dd = 510; + protected static final int gen_cmpb_ds_dd = 510; - protected static final int gen_cmpw_as_dd = 511; + protected static final int gen_cmpb_dt_dd = 511; - protected static final int gen_cmpw_dt_dd = 512; + protected static final int gen_cmpw_ds_dd = 512; - protected static final int gen_cmpl_ds_dd = 513; + protected static final int gen_cmpw_as_dd = 513; - protected static final int gen_cmpl_as_dd = 514; + protected static final int gen_cmpw_dt_dd = 514; - protected static final int gen_cmpl_dt_dd = 515; + protected static final int gen_cmpl_ds_dd = 515; - protected static final int gen_cmpw_ds_ad = 516; + protected static final int gen_cmpl_as_dd = 516; - protected static final int gen_cmpw_as_ad = 517; + protected static final int gen_cmpl_dt_dd = 517; - protected static final int gen_cmpw_dt_ad = 518; + protected static final int gen_cmpw_ds_ad = 518; - protected static final int gen_cmpl_ds_ad = 519; + protected static final int gen_cmpw_as_ad = 519; - protected static final int gen_cmpl_as_ad = 520; + protected static final int gen_cmpw_dt_ad = 520; - protected static final int gen_cmpl_dt_ad = 521; + protected static final int gen_cmpl_ds_ad = 521; - protected static final int gen_cmpmb_im_ea = 522; + protected static final int gen_cmpl_as_ad = 522; - protected static final int gen_cmpmw_im_ea = 523; + protected static final int gen_cmpl_dt_ad = 523; - protected static final int gen_cmpml_im_ea = 524; + protected static final int gen_cmpmb_im_ea = 524; - protected static final int gen_eorb_dd_ds = 525; + protected static final int gen_cmpmw_im_ea = 525; - protected static final int gen_eorb_dd_ea = 526; + protected static final int gen_cmpml_im_ea = 526; - protected static final int gen_eorw_dd_ds = 527; + protected static final int gen_eorb_dd_ds = 527; - protected static final int gen_eorw_dd_ea = 528; + protected static final int gen_eorb_dd_ea = 528; - protected static final int gen_eorl_dd_ds = 529; + protected static final int gen_eorw_dd_ds = 529; - protected static final int gen_eorl_dd_ea = 530; + protected static final int gen_eorw_dd_ea = 530; - protected static final int gen_andb_ds_dd = 531; + protected static final int gen_eorl_dd_ds = 531; - protected static final int gen_andb_dt_dd = 532; + protected static final int gen_eorl_dd_ea = 532; - protected static final int gen_andw_ds_dd = 533; + protected static final int gen_andb_ds_dd = 533; - protected static final int gen_andw_dt_dd = 534; + protected static final int gen_andb_dt_dd = 534; - protected static final int gen_andl_ds_dd = 535; + protected static final int gen_andw_ds_dd = 535; - protected static final int gen_andl_dt_dd = 536; + protected static final int gen_andw_dt_dd = 536; - protected static final int gen_andb_dd_ea = 537; + protected static final int gen_andl_ds_dd = 537; - protected static final int gen_andw_dd_ea = 538; + protected static final int gen_andl_dt_dd = 538; - protected static final int gen_andl_dd_ea = 539; + protected static final int gen_andb_dd_ea = 539; - protected static final int gen_abcdb_ds_dd = 540; + protected static final int gen_andw_dd_ea = 540; - protected static final int gen_abcdb_im_ea = 541; + protected static final int gen_andl_dd_ea = 541; - protected static final int gen_addb_ds_dd = 542; + protected static final int gen_abcdb_ds_dd = 542; - protected static final int gen_addb_dt_dd = 543; + protected static final int gen_abcdb_im_ea = 543; - protected static final int gen_addw_ds_dd = 544; + protected static final int gen_addb_ds_dd = 544; - protected static final int gen_addw_as_dd = 545; + protected static final int gen_addb_dt_dd = 545; - protected static final int gen_addw_dt_dd = 546; + protected static final int gen_addw_ds_dd = 546; - protected static final int gen_addl_ds_dd = 547; + protected static final int gen_addw_as_dd = 547; - protected static final int gen_addl_as_dd = 548; + protected static final int gen_addw_dt_dd = 548; - protected static final int gen_addl_dt_dd = 549; + protected static final int gen_addl_ds_dd = 549; - protected static final int gen_addb_dd_ea = 550; + protected static final int gen_addl_as_dd = 550; - protected static final int gen_addw_dd_ea = 551; + protected static final int gen_addl_dt_dd = 551; - protected static final int gen_addl_dd_ea = 552; + protected static final int gen_addb_dd_ea = 552; - protected static final int gen_addxb_ds_dd = 553; + protected static final int gen_addw_dd_ea = 553; - protected static final int gen_addxb_im_ea = 554; + protected static final int gen_addl_dd_ea = 554; - protected static final int gen_addxw_ds_dd = 555; + protected static final int gen_addxb_ds_dd = 555; - protected static final int gen_addxw_im_ea = 556; + protected static final int gen_addxb_im_ea = 556; - protected static final int gen_addxl_ds_dd = 557; + protected static final int gen_addxw_ds_dd = 557; - protected static final int gen_addxl_im_ea = 558; + protected static final int gen_addxw_im_ea = 558; - protected static final int gen_addw_ds_ad = 559; + protected static final int gen_addxl_ds_dd = 559; - protected static final int gen_addw_as_ad = 560; + protected static final int gen_addxl_im_ea = 560; - protected static final int gen_addw_dt_ad = 561; + protected static final int gen_addw_ds_ad = 561; - protected static final int gen_addl_ds_ad = 562; + protected static final int gen_addw_as_ad = 562; - protected static final int gen_addl_as_ad = 563; + protected static final int gen_addw_dt_ad = 563; - protected static final int gen_addl_dt_ad = 564; + protected static final int gen_addl_ds_ad = 564; - protected static final int gen_asrb_ir_ds = 565; + protected static final int gen_addl_as_ad = 565; - protected static final int gen_asrb_dd_ds = 566; + protected static final int gen_addl_dt_ad = 566; - protected static final int gen_asrw_ir_ds = 567; + protected static final int gen_asrb_ir_ds = 567; - protected static final int gen_asrw_dd_ds = 568; + protected static final int gen_asrb_dd_ds = 568; - protected static final int gen_asrl_ir_ds = 569; + protected static final int gen_asrw_ir_ds = 569; - protected static final int gen_asrl_dd_ds = 570; + protected static final int gen_asrw_dd_ds = 570; - protected static final int gen_asrw_ea = 571; + protected static final int gen_asrl_ir_ds = 571; - protected static final int gen_aslb_ir_ds = 572; + protected static final int gen_asrl_dd_ds = 572; - protected static final int gen_aslb_dd_ds = 573; + protected static final int gen_asrw_ea = 573; - protected static final int gen_aslw_ir_ds = 574; + protected static final int gen_aslb_ir_ds = 574; - protected static final int gen_aslw_dd_ds = 575; + protected static final int gen_aslb_dd_ds = 575; - protected static final int gen_asll_ir_ds = 576; + protected static final int gen_aslw_ir_ds = 576; - protected static final int gen_asll_dd_ds = 577; + protected static final int gen_aslw_dd_ds = 577; - protected static final int gen_aslw_ea = 578; + protected static final int gen_asll_ir_ds = 578; - protected static final int gen_lsrb_ir_ds = 579; + protected static final int gen_asll_dd_ds = 579; - protected static final int gen_lsrb_dd_ds = 580; + protected static final int gen_aslw_ea = 580; - protected static final int gen_lsrw_ir_ds = 581; + protected static final int gen_lsrb_ir_ds = 581; - protected static final int gen_lsrw_dd_ds = 582; + protected static final int gen_lsrb_dd_ds = 582; - protected static final int gen_lsrl_ir_ds = 583; + protected static final int gen_lsrw_ir_ds = 583; - protected static final int gen_lsrl_dd_ds = 584; + protected static final int gen_lsrw_dd_ds = 584; - protected static final int gen_lsrw_ea = 585; + protected static final int gen_lsrl_ir_ds = 585; - protected static final int gen_lslb_ir_ds = 586; + protected static final int gen_lsrl_dd_ds = 586; - protected static final int gen_lslb_dd_ds = 587; + protected static final int gen_lsrw_ea = 587; - protected static final int gen_lslw_ir_ds = 588; + protected static final int gen_lslb_ir_ds = 588; - protected static final int gen_lslw_dd_ds = 589; + protected static final int gen_lslb_dd_ds = 589; - protected static final int gen_lsll_ir_ds = 590; + protected static final int gen_lslw_ir_ds = 590; - protected static final int gen_lsll_dd_ds = 591; + protected static final int gen_lslw_dd_ds = 591; - protected static final int gen_lslw_ea = 592; + protected static final int gen_lsll_ir_ds = 592; - protected static final int gen_rorb_ir_ds = 593; + protected static final int gen_lsll_dd_ds = 593; - protected static final int gen_rorb_dd_ds = 594; + protected static final int gen_lslw_ea = 594; - protected static final int gen_rorw_ir_ds = 595; + protected static final int gen_rorb_ir_ds = 595; - protected static final int gen_rorw_dd_ds = 596; + protected static final int gen_rorb_dd_ds = 596; - protected static final int gen_rorl_ir_ds = 597; + protected static final int gen_rorw_ir_ds = 597; - protected static final int gen_rorl_dd_ds = 598; + protected static final int gen_rorw_dd_ds = 598; - protected static final int gen_rorw_ea = 599; + protected static final int gen_rorl_ir_ds = 599; - protected static final int gen_rolb_ir_ds = 600; + protected static final int gen_rorl_dd_ds = 600; - protected static final int gen_rolb_dd_ds = 601; + protected static final int gen_rorw_ea = 601; - protected static final int gen_rolw_ir_ds = 602; + protected static final int gen_rolb_ir_ds = 602; - protected static final int gen_rolw_dd_ds = 603; + protected static final int gen_rolb_dd_ds = 603; - protected static final int gen_roll_ir_ds = 604; + protected static final int gen_rolw_ir_ds = 604; - protected static final int gen_roll_dd_ds = 605; + protected static final int gen_rolw_dd_ds = 605; - protected static final int gen_rolw_ea = 606; + protected static final int gen_roll_ir_ds = 606; + + protected static final int gen_roll_dd_ds = 607; + + protected static final int gen_rolw_ea = 608; public static final int BKPT_EXIT = 0x00010000; @@ -3018,7 +3022,9 @@ public abstract class Core extends CoreALU { nmpc = decoded.a3; break; case 157: /* ea_dpc32_read */ - nmpc = 158; + sswi |= 0x0800; + case 158: /* ea_dpc32 */ + nmpc = 159; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -3031,12 +3037,17 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 158: + case 159: at = dib; at = ((short) at) + pc; - case 159: /* eapc_read32 */ + if ((sswi & 0x0800) == 0) { + nmpc = decoded.a3; + break; + } + case 160: /* eapc_read32 */ + sswi &= ~0x0800; alub = dt; - nmpc = 160; + nmpc = 161; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; if (((aob = at) & 0x000000001) != 0) { @@ -3048,13 +3059,13 @@ public abstract class Core extends CoreALU { mpc = bevtf32; continue; } - case 160: + case 161: dt = dib; ssw &= ~0xbfe7; nmpc = decoded.a3; break; - case 161: /* ea_dpci8_read */ - nmpc = 162; + case 162: /* ea_dpci8_read */ + nmpc = 163; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -3067,7 +3078,7 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 162: + case 163: ssw &= ~0xbfe7; if ((irb & 0x0100) == 0) { at = (byte) irb; @@ -3103,10 +3114,10 @@ public abstract class Core extends CoreALU { } mpc = ea_daix_imm32; continue; - case 163: /* ea_dpci8_base */ + case 164: /* ea_dpci8_base */ at += dib; ssw &= ~0xbfe7; - case 164: /* ea_dpci8_no_base */ + case 165: /* ea_dpci8_no_base */ if ((irb & 0x0004) == 0) { at += dt; dt = 0; @@ -3115,7 +3126,7 @@ public abstract class Core extends CoreALU { continue; } } - nmpc = 165; + nmpc = 166; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; if (((aob = at) & 0x000000001) != 0) { @@ -3127,7 +3138,7 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 165: + case 166: at = dib; at += dt; ssw &= ~0xbfe7; @@ -3141,17 +3152,17 @@ public abstract class Core extends CoreALU { } mpc = ea_daix_imm32; continue; - case 166: /* ea_dpci8_outer */ + case 167: /* ea_dpci8_outer */ at += dib; ssw &= ~0xbfe7; - case 167: /* ea_dpci8_fetch */ + case 168: /* ea_dpci8_fetch */ elapsed += 2; mpc = eapc_read8; continue; - case 168: /* ea_dpci16_read */ + case 169: /* ea_dpci16_read */ sswi |= 0x0800; - case 169: /* ea_dpci16 */ - nmpc = 170; + case 170: /* ea_dpci16 */ + nmpc = 171; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -3164,7 +3175,7 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 170: + case 171: ssw &= ~0xbfe7; if ((irb & 0x0100) == 0) { at = (byte) irb; @@ -3200,10 +3211,10 @@ public abstract class Core extends CoreALU { } mpc = ea_daix_imm32; continue; - case 171: /* ea_dpci16_base */ + case 172: /* ea_dpci16_base */ at += dib; ssw &= ~0xbfe7; - case 172: /* ea_dpci16_no_base */ + case 173: /* ea_dpci16_no_base */ if ((irb & 0x0004) == 0) { at += dt; dt = 0; @@ -3212,7 +3223,7 @@ public abstract class Core extends CoreALU { continue; } } - nmpc = 173; + nmpc = 174; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; if (((aob = at) & 0x000000001) != 0) { @@ -3224,7 +3235,7 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 173: + case 174: at = dib; at += dt; ssw &= ~0xbfe7; @@ -3238,10 +3249,10 @@ public abstract class Core extends CoreALU { } mpc = ea_daix_imm32; continue; - case 174: /* ea_dpci16_outer */ + case 175: /* ea_dpci16_outer */ at += dib; ssw &= ~0xbfe7; - case 175: /* ea_dpci16_fetch */ + case 176: /* ea_dpci16_fetch */ if ((sswi & 0x0800) == 0) { elapsed += 4; nmpc = decoded.a3; @@ -3250,8 +3261,10 @@ public abstract class Core extends CoreALU { elapsed += 2; mpc = eapc_read16; continue; - case 176: /* ea_dpci32_read */ - nmpc = 177; + case 177: /* ea_dpci32_read */ + sswi |= 0x0800; + case 178: /* ea_dpci32 */ + nmpc = 179; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -3264,7 +3277,7 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 177: + case 179: ssw &= ~0xbfe7; if ((irb & 0x0100) == 0) { at = (byte) irb; @@ -3300,10 +3313,10 @@ public abstract class Core extends CoreALU { } mpc = ea_daix_imm32; continue; - case 178: /* ea_dpci32_base */ + case 180: /* ea_dpci32_base */ at += dib; ssw &= ~0xbfe7; - case 179: /* ea_dpci32_no_base */ + case 181: /* ea_dpci32_no_base */ if ((irb & 0x0004) == 0) { at += dt; dt = 0; @@ -3312,7 +3325,7 @@ public abstract class Core extends CoreALU { continue; } } - nmpc = 180; + nmpc = 182; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; if (((aob = at) & 0x000000001) != 0) { @@ -3324,7 +3337,7 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 180: + case 182: at = dib; at += dt; ssw &= ~0xbfe7; @@ -3338,33 +3351,19 @@ public abstract class Core extends CoreALU { } mpc = ea_daix_imm32; continue; - case 181: /* ea_dpci32_outer */ + case 183: /* ea_dpci32_outer */ at += dib; ssw &= ~0xbfe7; - case 182: /* ea_dpci32_fetch */ + case 184: /* ea_dpci32_fetch */ + if ((sswi & 0x0800) == 0) { + elapsed += 4; + nmpc = decoded.a3; + break; + } elapsed += 2; mpc = eapc_read32; continue; - case 183: /* ea_adr16d8 */ - nmpc = 184; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = fetch16(aob); - scan += 2; - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 184: - ssw &= ~0xbfe7; - at = (short) dib; - nmpc = decoded.a2; - break; - case 185: /* ea_adr16d16 */ + case 185: /* ea_adr16d8 */ nmpc = 186; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; @@ -3383,7 +3382,7 @@ public abstract class Core extends CoreALU { at = (short) dib; nmpc = decoded.a2; break; - case 187: /* ea_adr16d32 */ + case 187: /* ea_adr16d16 */ nmpc = 188; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; @@ -3402,10 +3401,8 @@ public abstract class Core extends CoreALU { at = (short) dib; nmpc = decoded.a2; break; - case 189: /* ea_adr16s8_read */ - sswi |= 0x0800; - case 190: /* ea_adr16s8 */ - nmpc = 191; + case 189: /* ea_adr16d32 */ + nmpc = 190; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -3418,7 +3415,28 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 191: + case 190: + ssw &= ~0xbfe7; + at = (short) dib; + nmpc = decoded.a2; + break; + case 191: /* ea_adr16s8_read */ + sswi |= 0x0800; + case 192: /* ea_adr16s8 */ + nmpc = 193; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 193: at = (short) dib; if ((sswi & 0x0800) == 0) { ssw &= ~0xbfe7; @@ -3427,10 +3445,10 @@ public abstract class Core extends CoreALU { } mpc = ea_read8; continue; - case 192: /* ea_adr16s16_read */ + case 194: /* ea_adr16s16_read */ sswi |= 0x0800; - case 193: /* ea_adr16s16 */ - nmpc = 194; + case 195: /* ea_adr16s16 */ + nmpc = 196; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -3443,7 +3461,7 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 194: + case 196: at = (short) dib; if ((sswi & 0x0800) == 0) { ssw &= ~0xbfe7; @@ -3452,10 +3470,10 @@ public abstract class Core extends CoreALU { } mpc = ea_read16; continue; - case 195: /* ea_adr16s32_read */ + case 197: /* ea_adr16s32_read */ sswi |= 0x0800; - case 196: /* ea_adr16s32 */ - nmpc = 197; + case 198: /* ea_adr16s32 */ + nmpc = 199; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -3468,7 +3486,7 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 197: + case 199: at = (short) dib; if ((sswi & 0x0800) == 0) { ssw &= ~0xbfe7; @@ -3477,10 +3495,10 @@ public abstract class Core extends CoreALU { } mpc = ea_read32; continue; - case 198: /* ea_adr32d8 */ - case 199: /* ea_adr32d16 */ - case 200: /* ea_adr32d32 */ - nmpc = 201; + case 200: /* ea_adr32d8 */ + case 201: /* ea_adr32d16 */ + case 202: /* ea_adr32d32 */ + nmpc = 203; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -3493,15 +3511,15 @@ public abstract class Core extends CoreALU { mpc = bevtf32; continue; } - case 201: + case 203: at = dib; ssw &= ~0xbfe7; nmpc = decoded.a2; break; - case 202: /* ea_adr32s8_read */ + case 204: /* ea_adr32s8_read */ sswi |= 0x0800; - case 203: /* ea_adr32s8 */ - nmpc = 204; + case 205: /* ea_adr32s8 */ + nmpc = 206; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -3514,7 +3532,7 @@ public abstract class Core extends CoreALU { mpc = bevtf32; continue; } - case 204: + case 206: at = dib; if ((sswi & 0x0800) == 0) { ssw &= ~0xbfe7; @@ -3523,10 +3541,10 @@ public abstract class Core extends CoreALU { } mpc = ea_read8; continue; - case 205: /* ea_adr32s16_read */ + case 207: /* ea_adr32s16_read */ sswi |= 0x0800; - case 206: /* ea_adr32s16 */ - nmpc = 207; + case 208: /* ea_adr32s16 */ + nmpc = 209; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -3539,7 +3557,7 @@ public abstract class Core extends CoreALU { mpc = bevtf32; continue; } - case 207: + case 209: at = dib; if ((sswi & 0x0800) == 0) { ssw &= ~0xbfe7; @@ -3548,10 +3566,10 @@ public abstract class Core extends CoreALU { } mpc = ea_read16; continue; - case 208: /* ea_adr32s32_read */ + case 210: /* ea_adr32s32_read */ sswi |= 0x0800; - case 209: /* ea_adr32s32 */ - nmpc = 210; + case 211: /* ea_adr32s32 */ + nmpc = 212; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -3564,7 +3582,7 @@ public abstract class Core extends CoreALU { mpc = bevtf32; continue; } - case 210: + case 212: at = dib; if ((sswi & 0x0800) == 0) { ssw &= ~0xbfe7; @@ -3573,26 +3591,7 @@ public abstract class Core extends CoreALU { } mpc = ea_read32; continue; - case 211: /* ea_imm8_read */ - nmpc = 212; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = fetch16(aob); - scan += 2; - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 212: - ssw &= ~0xbfe7; - dt = (byte) dib; - nmpc = decoded.a3; - break; - case 213: /* ea_imm16_read */ + case 213: /* ea_imm8_read */ nmpc = 214; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; @@ -3608,11 +3607,30 @@ public abstract class Core extends CoreALU { } case 214: ssw &= ~0xbfe7; + dt = (byte) dib; + nmpc = decoded.a3; + break; + case 215: /* ea_imm16_read */ + nmpc = 216; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 216: + ssw &= ~0xbfe7; dt = (short) dib; nmpc = decoded.a3; break; - case 215: /* ea_imm32_read */ - nmpc = 216; + case 217: /* ea_imm32_read */ + nmpc = 218; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -3625,15 +3643,15 @@ public abstract class Core extends CoreALU { mpc = bevtf32; continue; } - case 216: + case 218: dt = dib; ssw &= ~0xbfe7; nmpc = decoded.a3; break; - case 217: /* op_movepw_dd_das */ + case 219: /* op_movepw_dd_das */ rx = (ir >> 9) & 0x0007; dt = dar[rx]; - nmpc = 218; + nmpc = 220; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -3645,8 +3663,8 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 218: - nmpc = 219; + case 220: + nmpc = 221; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; write8(aob = at, dob = dt >> 8); @@ -3654,8 +3672,8 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 219: - nmpc = 220; + case 221: + nmpc = 222; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; write8(aob = at + 0x0002, dob = dt); @@ -3663,12 +3681,12 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 220: + case 222: mpc = resume; continue; - case 221: /* op_movepw_das_dd */ + case 223: /* op_movepw_das_dd */ rx = (ir >> 9) & 0x0007; - nmpc = 222; + nmpc = 224; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9301; dib = read8(aob = at); @@ -3679,9 +3697,9 @@ public abstract class Core extends CoreALU { if ((ssw & 0x0600) == 0x0600) { dib >>= 8; } - case 222: + case 224: dt = dib; - nmpc = 223; + nmpc = 225; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9301; dib = read8(aob = at + 0x0002); @@ -3692,15 +3710,15 @@ public abstract class Core extends CoreALU { if ((ssw & 0x0600) == 0x0600) { dib >>= 8; } - case 223: + case 225: dt = (dt << 8) | (dib & 0xff); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 224: /* op_movepl_dd_das */ + case 226: /* op_movepl_dd_das */ rx = (ir >> 9) & 0x0007; dt = dar[rx]; - nmpc = 225; + nmpc = 227; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -3712,29 +3730,11 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 225: - nmpc = 226; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; - write8(aob = at, dob = dt >> 24); - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 226: - nmpc = 227; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; - write8(aob = at + 0x0002, dob = dt >> 16); - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } case 227: nmpc = 228; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; - write8(aob = at + 0x0004, dob = dt >> 8); + write8(aob = at, dob = dt >> 24); if ((ssw & 0x0030) != 0) { mpc = bevt; continue; @@ -3743,17 +3743,35 @@ public abstract class Core extends CoreALU { nmpc = 229; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; - write8(aob = at + 0x0006, dob = dt); + write8(aob = at + 0x0002, dob = dt >> 16); if ((ssw & 0x0030) != 0) { mpc = bevt; continue; } case 229: + nmpc = 230; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; + write8(aob = at + 0x0004, dob = dt >> 8); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 230: + nmpc = 231; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x8201; + write8(aob = at + 0x0006, dob = dt); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 231: mpc = resume; continue; - case 230: /* op_movepl_das_dd */ + case 232: /* op_movepl_das_dd */ rx = (ir >> 9) & 0x0007; - nmpc = 231; + nmpc = 233; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9301; dib = read8(aob = at); @@ -3764,9 +3782,9 @@ public abstract class Core extends CoreALU { if ((ssw & 0x0600) == 0x0600) { dib >>= 8; } - case 231: + case 233: dt = dib; - nmpc = 232; + nmpc = 234; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9301; dib = read8(aob = at + 0x0002); @@ -3777,9 +3795,9 @@ public abstract class Core extends CoreALU { if ((ssw & 0x0600) == 0x0600) { dib >>= 8; } - case 232: + case 234: dt = (dt << 8) | (dib & 0xff); - nmpc = 233; + nmpc = 235; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9301; dib = read8(aob = at + 0x0004); @@ -3790,9 +3808,9 @@ public abstract class Core extends CoreALU { if ((ssw & 0x0600) == 0x0600) { dib >>= 8; } - case 233: + case 235: dt = (dt << 8) | (dib & 0xff); - nmpc = 234; + nmpc = 236; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9301; dib = read8(aob = at + 0x0006); @@ -3803,48 +3821,48 @@ public abstract class Core extends CoreALU { if ((ssw & 0x0600) == 0x0600) { dib >>= 8; } - case 234: + case 236: dt = (dt << 8) | (dib & 0xff); dar[rx] = dt; mpc = resume_prefetch; continue; - case 235: /* op_clrb_ds */ + case 237: /* op_clrb_ds */ ry = ir & 0x0007; dar[ry] &= ~0xff; mpc = resume_prefetch; continue; - case 236: /* op_clrw_ds */ + case 238: /* op_clrw_ds */ ry = ir & 0x0007; dar[ry] &= ~0xffff; mpc = resume_prefetch; continue; - case 237: /* op_clrl_ds */ + case 239: /* op_clrl_ds */ ry = ir & 0x0007; dar[ry] = 0; mpc = resume_prefetch; continue; - case 238: /* op_clrb_ea */ + case 240: /* op_clrb_ea */ dt = 0; mpc = ea_resume_write8; continue; - case 239: /* op_clrw_ea */ + case 241: /* op_clrw_ea */ dt = 0; mpc = ea_resume_write16; continue; - case 240: /* op_clrl_ea */ + case 242: /* op_clrl_ea */ dt = 0; mpc = ea_resume_write32; continue; - case 241: /* op_lea_ea_ad */ + case 243: /* op_lea_ea_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = at; mpc = resume_prefetch; continue; - case 242: /* op_pea */ + case 244: /* op_pea */ au = dar[sp] - 4; dar[sp] = au; - nmpc = 243; + nmpc = 245; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -3856,34 +3874,34 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 243: + case 245: mpc = resume_prefetch; continue; - case 244: /* op_swap_ds */ + case 246: /* op_swap_ds */ ry = ir & 0x0007; dar[ry] = (dar[ry] << 16) | (dar[ry] >>> 16); long_tst(dar[ry]); mpc = resume_prefetch; continue; - case 245: /* op_extw_ds */ + case 247: /* op_extw_ds */ ry = ir & 0x0007; dar[ry] = (dar[ry] & ~0xffff) | (((byte) dar[ry]) & 0xffff); word_tst(dar[ry]); mpc = resume_prefetch; continue; - case 246: /* op_extl_ds */ + case 248: /* op_extl_ds */ ry = ir & 0x0007; dar[ry] = (short) dar[ry]; long_tst(dar[ry]); mpc = resume_prefetch; continue; - case 247: /* op_extbl_ds */ + case 249: /* op_extbl_ds */ ry = ir & 0x0007; dar[ry] = (byte) dar[ry]; long_tst(dar[ry]); mpc = resume_prefetch; continue; - case 248: /* op_exg_dd_ds */ + case 250: /* op_exg_dd_ds */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dar[rx] ^= dar[ry]; @@ -3891,7 +3909,7 @@ public abstract class Core extends CoreALU { dar[rx] ^= dar[ry]; mpc = resume_prefetch; continue; - case 249: /* op_exg_ad_as */ + case 251: /* op_exg_ad_as */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -3901,7 +3919,7 @@ public abstract class Core extends CoreALU { dar[rx] ^= dar[ry]; mpc = resume_prefetch; continue; - case 250: /* op_exg_dd_as */ + case 252: /* op_exg_dd_as */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -3910,7 +3928,7 @@ public abstract class Core extends CoreALU { dar[rx] ^= dar[ry]; mpc = resume_prefetch; continue; - case 251: /* op_scc_b_ds */ + case 253: /* op_scc_b_ds */ ry = ir & 0x0007; if (testCC((ir & 0x0f00) >> 8)) { dar[ry] |= 0xff; @@ -3919,11 +3937,11 @@ public abstract class Core extends CoreALU { } mpc = resume_prefetch; continue; - case 252: /* op_scc_b_ea */ + case 254: /* op_scc_b_ea */ dt = testCC((ir & 0x0f00) >> 8) ? -1 : 0; mpc = ea_resume_write8; continue; - case 253: /* op_chk_w_ds */ + case 255: /* op_chk_w_ds */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; if (word_chk(dar[ry], dar[rx])) { @@ -3932,7 +3950,7 @@ public abstract class Core extends CoreALU { } mpc = resume_prefetch; continue; - case 254: /* op_chk_w_ea */ + case 256: /* op_chk_w_ea */ rx = (ir >> 9) & 0x0007; if (word_chk(dt, dar[rx])) { tvn = 24; @@ -3940,32 +3958,11 @@ public abstract class Core extends CoreALU { } mpc = resume_prefetch; continue; - case 255: /* op_link_as_imm16 */ + case 257: /* op_link_as_imm16 */ au = dar[sp] - 4; dar[sp] = au + ((short) dt); ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; - nmpc = 256; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; - if (((aob = au) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - write32(aob, dob = dar[ry]); - if ((ssw & 0x0070) != 0x0040) { - mpc = bevtw32; - continue; - } - case 256: - dar[ry] = au; - mpc = resume_prefetch; - continue; - case 257: /* op_link_as_imm32 */ - au = dar[sp] - 4; - dar[sp] = au + dt; - ry = ir & 0x0007; - ry = ry == 7 ? sp : ry | 8; nmpc = 258; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; @@ -3982,12 +3979,33 @@ public abstract class Core extends CoreALU { dar[ry] = au; mpc = resume_prefetch; continue; - case 259: /* op_unlk_as */ + case 259: /* op_link_as_imm32 */ + au = dar[sp] - 4; + dar[sp] = au + dt; + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + nmpc = 260; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; + if (((aob = au) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write32(aob, dob = dar[ry]); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtw32; + continue; + } + case 260: + dar[ry] = au; + mpc = resume_prefetch; + continue; + case 261: /* op_unlk_as */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; au = dar[ry]; dar[sp] = au + 4; - nmpc = 260; + nmpc = 262; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; if (((aob = au) & 0x000000001) != 0) { @@ -3999,11 +4017,11 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 260: + case 262: dar[ry] = dib; mpc = resume_prefetch; continue; - case 261: /* op_move_usp_as */ + case 263: /* op_move_usp_as */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -4015,7 +4033,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[15]; mpc = resume_prefetch; continue; - case 262: /* op_move_as_usp */ + case 264: /* op_move_as_usp */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -4027,53 +4045,7 @@ public abstract class Core extends CoreALU { dar[15] = dar[ry]; mpc = resume_prefetch; continue; - case 263: /* op_movec_cr_rz */ - if ((sr & 0x2000) == 0) { - elapsed += 6; - tvn = 32; - mpc = trapill; - continue; - } - nmpc = 264; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - irb = fetch16(aob); - scan += 2; - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 264: - ssw &= ~0xbfe7; - rz = (irb >> 12) & 0x000f; - if (rz == 0x000f) { - rz = sp; - } - dt = irb & 0x0fff; - if (dt == 0x000) { - dar[rz] = sfc; - } else if (dt == 0x001) { - dar[rz] = dfc; - } else if (dt == 0x800) { - dar[rz] = dar[15]; - } else if (dt == 0x801) { - dar[rz] = vbr; - } else if (dt == 0x803) { - dar[rz] = dar[17]; - } else if (dt == 0x804) { - dar[rz] = dar[16]; - } else { - tvn = 16; - mpc = trapill; - continue; - } - mpc = resume_prefetch; - continue; - case 265: /* op_movec_rz_cr */ + case 265: /* op_movec_cr_rz */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -4100,6 +4072,52 @@ public abstract class Core extends CoreALU { rz = sp; } dt = irb & 0x0fff; + if (dt == 0x000) { + dar[rz] = sfc; + } else if (dt == 0x001) { + dar[rz] = dfc; + } else if (dt == 0x800) { + dar[rz] = dar[15]; + } else if (dt == 0x801) { + dar[rz] = vbr; + } else if (dt == 0x803) { + dar[rz] = dar[17]; + } else if (dt == 0x804) { + dar[rz] = dar[16]; + } else { + tvn = 16; + mpc = trapill; + continue; + } + mpc = resume_prefetch; + continue; + case 267: /* op_movec_rz_cr */ + if ((sr & 0x2000) == 0) { + elapsed += 6; + tvn = 32; + mpc = trapill; + continue; + } + nmpc = 268; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 268: + ssw &= ~0xbfe7; + rz = (irb >> 12) & 0x000f; + if (rz == 0x000f) { + rz = sp; + } + dt = irb & 0x0fff; if (dt == 0x000) { sfc = dar[rz] & 0x7; } else if (dt == 0x001) { @@ -4119,8 +4137,8 @@ public abstract class Core extends CoreALU { } mpc = resume_prefetch; continue; - case 267: /* op_movemw_rr_ea */ - nmpc = 268; + case 269: /* op_movemw_rr_ea */ + nmpc = 270; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4133,9 +4151,9 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 268: + case 270: dt = dib; - nmpc = 269; + nmpc = 271; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4147,17 +4165,17 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 269: + case 271: alub = 0; - nmpc = 270; - case 270: + nmpc = 272; + case 272: if (alub >= 16) { ssw &= ~0xbfe7; mpc = resume; continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 270; + mpc = 272; continue; } rz = alub == 15 ? sp : alub; @@ -4174,10 +4192,10 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - mpc = 270; + mpc = 272; continue; - case 271: /* op_movemw_rr_pais */ - nmpc = 272; + case 273: /* op_movemw_rr_pais */ + nmpc = 274; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4190,9 +4208,9 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 272: + case 274: dt = dib; - nmpc = 273; + nmpc = 275; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4204,10 +4222,10 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 273: + case 275: alub = 0; - nmpc = 274; - case 274: + nmpc = 276; + case 276: if (alub >= 16) { ssw &= ~0xbfe7; ry = ir & 0x0007; @@ -4217,7 +4235,7 @@ public abstract class Core extends CoreALU { continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 274; + mpc = 276; continue; } rz = alub == 0 ? sp : 15 - alub; @@ -4234,10 +4252,10 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - mpc = 274; + mpc = 276; continue; - case 275: /* op_moveml_rr_ea */ - nmpc = 276; + case 277: /* op_moveml_rr_ea */ + nmpc = 278; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4250,9 +4268,9 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 276: + case 278: dt = dib; - nmpc = 277; + nmpc = 279; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4264,17 +4282,17 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 277: + case 279: alub = 0; - nmpc = 278; - case 278: + nmpc = 280; + case 280: if (alub >= 16) { ssw &= ~0xbfe7; mpc = resume; continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 278; + mpc = 280; continue; } rz = alub == 15 ? sp : alub; @@ -4291,10 +4309,10 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - mpc = 278; + mpc = 280; continue; - case 279: /* op_moveml_rr_pais */ - nmpc = 280; + case 281: /* op_moveml_rr_pais */ + nmpc = 282; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4307,9 +4325,9 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 280: + case 282: dt = dib; - nmpc = 281; + nmpc = 283; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4321,10 +4339,10 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 281: + case 283: alub = 0; - nmpc = 282; - case 282: + nmpc = 284; + case 284: if (alub >= 16) { ssw &= ~0xbfe7; ry = ir & 0x0007; @@ -4334,7 +4352,7 @@ public abstract class Core extends CoreALU { continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 282; + mpc = 284; continue; } rz = alub == 0 ? sp : 15 - alub; @@ -4351,10 +4369,10 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - mpc = 282; + mpc = 284; continue; - case 283: /* op_movemw_ea_rr */ - nmpc = 284; + case 285: /* op_movemw_ea_rr */ + nmpc = 286; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4367,9 +4385,9 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 284: + case 286: dt = dib; - nmpc = 285; + nmpc = 287; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4381,84 +4399,21 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 285: - alub = 0; - nmpc = 286; - case 286: - if (alub >= 16) { - ssw &= ~0xbfe7; - mpc = resume; - continue; - } else if ((dt & (1 << alub)) == 0) { - alub += 1; - mpc = 286; - continue; - } - rz = alub == 15 ? sp : alub; - nmpc = 287; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9100; - if (((aob = at) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = read16(aob); - alub += 1; - at += 2; - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } case 287: - dar[rz] = (short) dib; - mpc = 286; - continue; - case 288: /* op_movemw_aisp_rr */ - nmpc = 289; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = fetch16(aob); - scan += 2; - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 289: - dt = dib; - nmpc = 290; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - irb = fetch16(aob); - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 290: alub = 0; - nmpc = 291; - case 291: + nmpc = 288; + case 288: if (alub >= 16) { ssw &= ~0xbfe7; - ry = ir & 0x0007; - ry = ry == 7 ? sp : ry | 8; - dar[ry] = at; mpc = resume; continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 291; + mpc = 288; continue; } rz = alub == 15 ? sp : alub; - nmpc = 292; + nmpc = 289; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9100; if (((aob = at) & 0x000000001) != 0) { @@ -4472,12 +4427,12 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 292: + case 289: dar[rz] = (short) dib; - mpc = 291; + mpc = 288; continue; - case 293: /* op_moveml_ea_rr */ - nmpc = 294; + case 290: /* op_movemw_aips_rr */ + nmpc = 291; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4490,9 +4445,9 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 294: + case 291: dt = dib; - nmpc = 295; + nmpc = 292; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4504,70 +4459,10 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 295: + case 292: alub = 0; - nmpc = 296; - case 296: - if (alub >= 16) { - ssw &= ~0xbfe7; - mpc = resume; - continue; - } else if ((dt & (1 << alub)) == 0) { - alub += 1; - mpc = 296; - continue; - } - rz = alub == 15 ? sp : alub; - nmpc = 297; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c0; - if (((aob = at) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = read32(aob); - alub += 1; - at += 4; - if ((ssw & 0x0070) != 0x0040) { - mpc = bevtr32; - continue; - } - case 297: - dar[rz] = dib; - mpc = 296; - continue; - case 298: /* op_moveml_aisp_rr */ - nmpc = 299; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = fetch16(aob); - scan += 2; - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 299: - dt = dib; - nmpc = 300; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - irb = fetch16(aob); - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 300: - alub = 0; - nmpc = 301; - case 301: + nmpc = 293; + case 293: if (alub >= 16) { ssw &= ~0xbfe7; ry = ir & 0x0007; @@ -4577,11 +4472,71 @@ public abstract class Core extends CoreALU { continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 301; + mpc = 293; continue; } rz = alub == 15 ? sp : alub; - nmpc = 302; + nmpc = 294; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9100; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read16(aob); + alub += 1; + at += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 294: + dar[rz] = (short) dib; + mpc = 293; + continue; + case 295: /* op_moveml_ea_rr */ + nmpc = 296; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 296: + dt = dib; + nmpc = 297; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 297: + alub = 0; + nmpc = 298; + case 298: + if (alub >= 16) { + ssw &= ~0xbfe7; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 298; + continue; + } + rz = alub == 15 ? sp : alub; + nmpc = 299; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c0; if (((aob = at) & 0x000000001) != 0) { @@ -4595,68 +4550,110 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 302: + case 299: dar[rz] = dib; - mpc = 301; + mpc = 298; continue; - case 303: /* op_bcc8 */ - if (!testCC((ir & 0x0f00) >> 8)) { - elapsed += 2; - mpc = resume_prefetch; - continue; - } - case 304: /* op_bra8 */ - elapsed += 2; - scan = pc + ((byte) ir); - sswi |= (sr & 0x4000); - mpc = resume_prefetch; - continue; - case 305: /* op_bcc16 */ - if (!testCC((ir & 0x0f00) >> 8)) { - elapsed += 2; - mpc = resume_prefetch; - continue; - } - case 306: /* op_bra16 */ - elapsed += 2; - scan = pc + dt; - sswi |= (sr & 0x4000); - mpc = resume_prefetch; - continue; - case 307: /* op_bcc32 */ - if (!testCC((ir & 0x0f00) >> 8)) { - elapsed += 2; - mpc = resume_prefetch; - continue; - } - case 308: /* op_bra32 */ - elapsed += 2; - scan = pc + dt; - sswi |= (sr & 0x4000); - mpc = resume_prefetch; - continue; - case 309: /* op_bsr8 */ - elapsed += 2; - au = dar[sp] - 4; - dar[sp] = au; - nmpc = 310; + case 300: /* op_moveml_aips_rr */ + nmpc = 301; elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; - if (((aob = au) & 0x000000001) != 0) { + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + if (((aob = pc + scan) & 0x000000001) != 0) { mpc = aerr; continue; } - write32(aob, dob = pc + scan); - if ((ssw & 0x0070) != 0x0040) { - mpc = bevtw32; + dib = fetch16(aob); + scan += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; continue; } - case 310: + case 301: + dt = dib; + nmpc = 302; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 302: + alub = 0; + nmpc = 303; + case 303: + if (alub >= 16) { + ssw &= ~0xbfe7; + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dar[ry] = at; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 303; + continue; + } + rz = alub == 15 ? sp : alub; + nmpc = 304; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c0; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + alub += 1; + at += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 304: + dar[rz] = dib; + mpc = 303; + continue; + case 305: /* op_bcc8 */ + if (!testCC((ir & 0x0f00) >> 8)) { + elapsed += 2; + mpc = resume_prefetch; + continue; + } + case 306: /* op_bra8 */ + elapsed += 2; scan = pc + ((byte) ir); sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 311: /* op_bsr16 */ + case 307: /* op_bcc16 */ + if (!testCC((ir & 0x0f00) >> 8)) { + elapsed += 2; + mpc = resume_prefetch; + continue; + } + case 308: /* op_bra16 */ + elapsed += 2; + scan = pc + dt; + sswi |= (sr & 0x4000); + mpc = resume_prefetch; + continue; + case 309: /* op_bcc32 */ + if (!testCC((ir & 0x0f00) >> 8)) { + elapsed += 2; + mpc = resume_prefetch; + continue; + } + case 310: /* op_bra32 */ + elapsed += 2; + scan = pc + dt; + sswi |= (sr & 0x4000); + mpc = resume_prefetch; + continue; + case 311: /* op_bsr8 */ elapsed += 2; au = dar[sp] - 4; dar[sp] = au; @@ -4673,11 +4670,11 @@ public abstract class Core extends CoreALU { continue; } case 312: - scan = pc + dt; + scan = pc + ((byte) ir); sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 313: /* op_bsr32 */ + case 313: /* op_bsr16 */ elapsed += 2; au = dar[sp] - 4; dar[sp] = au; @@ -4698,7 +4695,28 @@ public abstract class Core extends CoreALU { sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 315: /* op_dbcc */ + case 315: /* op_bsr32 */ + elapsed += 2; + au = dar[sp] - 4; + dar[sp] = au; + nmpc = 316; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; + if (((aob = au) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write32(aob, dob = pc + scan); + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtw32; + continue; + } + case 316: + scan = pc + dt; + sswi |= (sr & 0x4000); + mpc = resume_prefetch; + continue; + case 317: /* op_dbcc */ if (testCC((ir & 0x0f00) >> 8)) { elapsed += 2; scan += 2; @@ -4713,7 +4731,7 @@ public abstract class Core extends CoreALU { mpc = resume_prefetch; continue; } - nmpc = 316; + nmpc = 318; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4725,12 +4743,12 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 316: + case 318: scan = dib; elapsed += 2; mpc = resume_prefetch; continue; - case 317: /* op_bkpt */ + case 319: /* op_bkpt */ elapsed += 6; hdlr = handle_bkpt(cip, ir & 0x0007); exit |= (hdlr & 0x00010000) != 0; @@ -4744,7 +4762,7 @@ public abstract class Core extends CoreALU { tvn = 16; mpc = trapill; continue; - case 318: /* op_illegal */ + case 320: /* op_illegal */ elapsed += 6; hdlr = handle_illegal(cip, ir); exit |= (hdlr & 0x00010000) != 0; @@ -4757,16 +4775,16 @@ public abstract class Core extends CoreALU { tvn = 16; mpc = trapill; continue; - case 319: /* op_jmp */ + case 321: /* op_jmp */ pc = at; scan = 0; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 320: /* op_jsr */ + case 322: /* op_jsr */ au = dar[sp] - 4; dar[sp] = au; - nmpc = 321; + nmpc = 323; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -4778,13 +4796,13 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 321: + case 323: pc = at; scan = 0; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 322: /* op_linea */ + case 324: /* op_linea */ elapsed += 6; hdlr = handle_linea(cip, ir & 0x0fff); exit |= (hdlr & 0x00010000) != 0; @@ -4797,15 +4815,15 @@ public abstract class Core extends CoreALU { tvn = 40; mpc = trapill; continue; - case 323: /* op_linef */ + case 325: /* op_linef */ elapsed += 6; tvn = 44; mpc = trapill; continue; - case 324: /* op_nop */ + case 326: /* op_nop */ mpc = resume_prefetch; continue; - case 325: /* op_rte */ + case 327: /* op_rte */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -4813,7 +4831,7 @@ public abstract class Core extends CoreALU { continue; } au = dar[sp]; - case 326: /* check_vob */ + case 328: /* check_vob */ elapsed += 4; ssw = (ssw & 0x0018) | 0x9105; if (((aob = au + 0x0006) & 0x000000001) != 0) { @@ -4827,12 +4845,12 @@ public abstract class Core extends CoreALU { } mpc = select_rte(dib); continue; - case 327: /* rteill */ + case 329: /* rteill */ elapsed += 6; tvn = 56; mpc = trapill; continue; - case 328: /* exit_trap */ + case 330: /* exit_trap */ elapsed += 8; ssw = (ssw & 0x0018) | 0x91c5; pc = read32(aob = au + 0x0002); @@ -4852,20 +4870,20 @@ public abstract class Core extends CoreALU { scan = 0; mpc = resume_prefetch; continue; - case 329: /* rte0000 */ + case 331: /* rte0000 */ dar[sp] = au + 8; mpc = exit_trap; continue; - case 330: /* rte1000 */ + case 332: /* rte1000 */ dar[sp] = au + 8; au = dar[sp = spi(sr | 0x1000)]; mpc = check_vob; continue; - case 331: /* rte2000 */ + case 333: /* rte2000 */ dar[sp] = au + 12; mpc = exit_trap; continue; - case 332: /* rte8000 */ + case 334: /* rte8000 */ elapsed += 6; elapsed += 8; ssw = (ssw & 0x0018) | 0x91c5; @@ -5100,9 +5118,9 @@ public abstract class Core extends CoreALU { continue; } break; - case 333: /* op_rtr */ + case 335: /* op_rtr */ au = dar[sp]; - nmpc = 334; + nmpc = 336; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; if (((aob = au + 0x0002) & 0x000000001) != 0) { @@ -5114,9 +5132,9 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 334: + case 336: pc = dib; - nmpc = 335; + nmpc = 337; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9101; dib = read16(aob = au); @@ -5124,7 +5142,7 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 335: + case 337: ssw &= ~0xbfe7; sr = (sr & ~0x001f) | (dib & 0x001f); scan = 0; @@ -5132,9 +5150,9 @@ public abstract class Core extends CoreALU { sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 336: /* op_rts */ + case 338: /* op_rts */ au = dar[sp]; - nmpc = 337; + nmpc = 339; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; if (((aob = au) & 0x000000001) != 0) { @@ -5146,7 +5164,7 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 337: + case 339: pc = dib; ssw &= ~0xbfe7; scan = 0; @@ -5154,16 +5172,16 @@ public abstract class Core extends CoreALU { sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 338: /* op_reset */ + case 340: /* op_reset */ elapsed += 126; mpc = resume_prefetch; continue; - case 339: /* op_trap */ + case 341: /* op_trap */ elapsed += 6; tvn = (32 + (ir & 0x000f)) << 2; mpc = trap0000; continue; - case 340: /* op_trapv */ + case 342: /* op_trapv */ if ((sr & 0x0002) != 0) { elapsed += 4; tvn = 28; @@ -5172,7 +5190,7 @@ public abstract class Core extends CoreALU { } mpc = resume_prefetch; continue; - case 341: /* op_trapcc */ + case 343: /* op_trapcc */ if (!testCC((ir & 0x0f00) >> 8)) { mpc = resume_prefetch; continue; @@ -5181,7 +5199,7 @@ public abstract class Core extends CoreALU { tvn = 28; mpc = trap2000; continue; - case 342: /* op_trapcc16 */ + case 344: /* op_trapcc16 */ scan += 2; if (!testCC((ir & 0x0f00) >> 8)) { mpc = resume_prefetch; @@ -5191,7 +5209,7 @@ public abstract class Core extends CoreALU { tvn = 28; mpc = trap2000; continue; - case 343: /* op_trapcc32 */ + case 345: /* op_trapcc32 */ scan += 4; if (!testCC((ir & 0x0f00) >> 8)) { mpc = resume_prefetch; @@ -5201,41 +5219,41 @@ public abstract class Core extends CoreALU { tvn = 28; mpc = trap2000; continue; - case 344: /* gen_orb_dt_ds */ + case 346: /* gen_orb_dt_ds */ ry = ir & 0x0007; dt = byte_or(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 345: /* gen_orb_im_ea */ + case 347: /* gen_orb_im_ea */ dt = byte_or(alub, dt); mpc = ea_resume_write8; continue; - case 346: /* gen_orw_dt_ds */ + case 348: /* gen_orw_dt_ds */ ry = ir & 0x0007; dt = word_or(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 347: /* gen_orw_im_ea */ + case 349: /* gen_orw_im_ea */ dt = word_or(alub, dt); mpc = ea_resume_write16; continue; - case 348: /* gen_orl_dt_ds */ + case 350: /* gen_orl_dt_ds */ ry = ir & 0x0007; dt = long_or(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 349: /* gen_orl_im_ea */ + case 351: /* gen_orl_im_ea */ dt = long_or(alub, dt); mpc = ea_resume_write32; continue; - case 350: /* gen_orb_dt_ccr */ + case 352: /* gen_orb_dt_ccr */ sr = (sr & ~0xff) | ((sr | dt) & 0x1f); mpc = resume_prefetch; continue; - case 351: /* gen_orw_dt_sr */ + case 353: /* gen_orw_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5245,88 +5263,88 @@ public abstract class Core extends CoreALU { sr = (sr | dt) & 0xf71f; mpc = resume_prefetch; continue; - case 352: /* gen_btstl_dd_ds */ + case 354: /* gen_btstl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; long_btst(dar[rx], dar[ry]); mpc = resume_prefetch; continue; - case 353: /* gen_btstb_dd_ea */ + case 355: /* gen_btstb_dd_ea */ rx = (ir >> 9) & 0x0007; byte_btst(dar[rx], dt); mpc = resume_prefetch; continue; - case 354: /* gen_bchgl_dd_ds */ + case 356: /* gen_bchgl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bchg(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 355: /* gen_bchgb_dd_ea */ + case 357: /* gen_bchgb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_bchg(dar[rx], dt); mpc = ea_resume_write8; continue; - case 356: /* gen_bclrl_dd_ds */ + case 358: /* gen_bclrl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bclr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 357: /* gen_bclrb_dd_ea */ + case 359: /* gen_bclrb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_bclr(dar[rx], dt); mpc = ea_resume_write8; continue; - case 358: /* gen_bsetl_dd_ds */ + case 360: /* gen_bsetl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bset(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 359: /* gen_bsetb_dd_ea */ + case 361: /* gen_bsetb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_bset(dar[rx], dt); mpc = ea_resume_write8; continue; - case 360: /* gen_andb_dt_ds */ + case 362: /* gen_andb_dt_ds */ ry = ir & 0x0007; dt = byte_and(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 361: /* gen_andb_im_ea */ + case 363: /* gen_andb_im_ea */ dt = byte_and(alub, dt); mpc = ea_resume_write8; continue; - case 362: /* gen_andw_dt_ds */ + case 364: /* gen_andw_dt_ds */ ry = ir & 0x0007; dt = word_and(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 363: /* gen_andw_im_ea */ + case 365: /* gen_andw_im_ea */ dt = word_and(alub, dt); mpc = ea_resume_write16; continue; - case 364: /* gen_andl_dt_ds */ + case 366: /* gen_andl_dt_ds */ ry = ir & 0x0007; dt = long_and(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 365: /* gen_andl_im_ea */ + case 367: /* gen_andl_im_ea */ dt = long_and(alub, dt); mpc = ea_resume_write32; continue; - case 366: /* gen_andb_dt_ccr */ + case 368: /* gen_andb_dt_ccr */ sr = (sr & ~0xff) | (sr & dt & 0x1f); mpc = resume_prefetch; continue; - case 367: /* gen_andw_dt_sr */ + case 369: /* gen_andw_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5336,140 +5354,140 @@ public abstract class Core extends CoreALU { sr = sr & dt; mpc = resume_prefetch; continue; - case 368: /* gen_subb_dt_ds */ + case 370: /* gen_subb_dt_ds */ ry = ir & 0x0007; dt = byte_sub(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 369: /* gen_subb_im_ea */ + case 371: /* gen_subb_im_ea */ dt = byte_sub(alub, dt); mpc = ea_resume_write8; continue; - case 370: /* gen_subw_dt_ds */ + case 372: /* gen_subw_dt_ds */ ry = ir & 0x0007; dt = word_sub(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 371: /* gen_subw_im_ea */ + case 373: /* gen_subw_im_ea */ dt = word_sub(alub, dt); mpc = ea_resume_write16; continue; - case 372: /* gen_subl_dt_ds */ + case 374: /* gen_subl_dt_ds */ ry = ir & 0x0007; dt = long_sub(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 373: /* gen_subl_im_ea */ + case 375: /* gen_subl_im_ea */ dt = long_sub(alub, dt); mpc = ea_resume_write32; continue; - case 374: /* gen_addb_dt_ds */ + case 376: /* gen_addb_dt_ds */ ry = ir & 0x0007; dt = byte_add(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 375: /* gen_addb_im_ea */ + case 377: /* gen_addb_im_ea */ dt = byte_add(alub, dt); mpc = ea_resume_write8; continue; - case 376: /* gen_addw_dt_ds */ + case 378: /* gen_addw_dt_ds */ ry = ir & 0x0007; dt = word_add(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 377: /* gen_addw_im_ea */ + case 379: /* gen_addw_im_ea */ dt = word_add(alub, dt); mpc = ea_resume_write16; continue; - case 378: /* gen_addl_dt_ds */ + case 380: /* gen_addl_dt_ds */ ry = ir & 0x0007; dt = long_add(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 379: /* gen_addl_im_ea */ + case 381: /* gen_addl_im_ea */ dt = long_add(alub, dt); mpc = ea_resume_write32; continue; - case 380: /* gen_btstl_dt_ds */ + case 382: /* gen_btstl_dt_ds */ ry = ir & 0x0007; long_btst(dt, dar[ry]); mpc = resume_prefetch; continue; - case 381: /* gen_btstb_im_ea */ + case 383: /* gen_btstb_im_ea */ byte_btst(alub, dt); mpc = resume_prefetch; continue; - case 382: /* gen_bchgl_dt_ds */ + case 384: /* gen_bchgl_dt_ds */ ry = ir & 0x0007; dt = long_bchg(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 383: /* gen_bchgb_im_ea */ + case 385: /* gen_bchgb_im_ea */ dt = byte_bchg(alub, dt); mpc = ea_resume_write8; continue; - case 384: /* gen_bclrl_dt_ds */ + case 386: /* gen_bclrl_dt_ds */ ry = ir & 0x0007; dt = long_bclr(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 385: /* gen_bclrb_im_ea */ + case 387: /* gen_bclrb_im_ea */ dt = byte_bclr(alub, dt); mpc = ea_resume_write8; continue; - case 386: /* gen_bsetl_dt_ds */ + case 388: /* gen_bsetl_dt_ds */ ry = ir & 0x0007; dt = long_bset(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 387: /* gen_bsetb_im_ea */ + case 389: /* gen_bsetb_im_ea */ dt = byte_bset(alub, dt); mpc = ea_resume_write8; continue; - case 388: /* gen_eorb_dt_ds */ + case 390: /* gen_eorb_dt_ds */ ry = ir & 0x0007; dt = byte_eor(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 389: /* gen_eorb_im_ea */ + case 391: /* gen_eorb_im_ea */ dt = byte_eor(alub, dt); mpc = ea_resume_write8; continue; - case 390: /* gen_eorw_dt_ds */ + case 392: /* gen_eorw_dt_ds */ ry = ir & 0x0007; dt = word_eor(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 391: /* gen_eorw_im_ea */ + case 393: /* gen_eorw_im_ea */ dt = word_eor(alub, dt); mpc = ea_resume_write16; continue; - case 392: /* gen_eorl_dt_ds */ + case 394: /* gen_eorl_dt_ds */ ry = ir & 0x0007; dt = long_eor(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 393: /* gen_eorl_im_ea */ + case 395: /* gen_eorl_im_ea */ dt = long_eor(alub, dt); mpc = ea_resume_write32; continue; - case 394: /* gen_eorb_dt_ccr */ + case 396: /* gen_eorb_dt_ccr */ sr = (sr & ~0xff) | ((sr ^ dt) & 0x1f); mpc = resume_prefetch; continue; - case 395: /* gen_eorw_dt_sr */ + case 397: /* gen_eorw_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5479,83 +5497,83 @@ public abstract class Core extends CoreALU { sr = (sr ^ dt) & 0xf71f; mpc = resume_prefetch; continue; - case 396: /* gen_cmpb_dt_ds */ + case 398: /* gen_cmpb_dt_ds */ ry = ir & 0x0007; byte_sub(dt, dar[ry]); mpc = resume_prefetch; continue; - case 397: /* gen_cmpb_im_ea */ + case 399: /* gen_cmpb_im_ea */ byte_sub(alub, dt); mpc = resume_prefetch; continue; - case 398: /* gen_cmpw_dt_ds */ + case 400: /* gen_cmpw_dt_ds */ ry = ir & 0x0007; word_sub(dt, dar[ry]); mpc = resume_prefetch; continue; - case 399: /* gen_cmpw_im_ea */ + case 401: /* gen_cmpw_im_ea */ word_sub(alub, dt); mpc = resume_prefetch; continue; - case 400: /* gen_cmpl_dt_ds */ + case 402: /* gen_cmpl_dt_ds */ ry = ir & 0x0007; long_sub(dt, dar[ry]); mpc = resume_prefetch; continue; - case 401: /* gen_cmpl_im_ea */ + case 403: /* gen_cmpl_im_ea */ long_sub(alub, dt); mpc = resume_prefetch; continue; - case 402: /* gen_moveb_ds_ea */ + case 404: /* gen_moveb_ds_ea */ ry = ir & 0x0007; byte_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write8; continue; - case 403: /* gen_moveb_dt_dd */ + case 405: /* gen_moveb_dt_dd */ rx = (ir >> 9) & 0x0007; byte_tst(dt); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 404: /* gen_moveb_ds_dd */ + case 406: /* gen_moveb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; byte_tst(dar[ry]); dar[rx] = (dar[rx] & ~0xff) | (dar[ry] & 0xff); mpc = resume_prefetch; continue; - case 405: /* gen_moveb_dt_ea */ + case 407: /* gen_moveb_dt_ea */ byte_tst(dt); mpc = ea_resume_write8; continue; - case 406: /* gen_movel_ds_ea */ + case 408: /* gen_movel_ds_ea */ ry = ir & 0x0007; long_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write32; continue; - case 407: /* gen_movel_as_ea */ + case 409: /* gen_movel_as_ea */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; long_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write32; continue; - case 408: /* gen_movel_dt_dd */ + case 410: /* gen_movel_dt_dd */ rx = (ir >> 9) & 0x0007; long_tst(dt); dar[rx] = dt; mpc = resume_prefetch; continue; - case 409: /* gen_movel_ds_dd */ + case 411: /* gen_movel_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; long_tst(dar[ry]); dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 410: /* gen_movel_as_dd */ + case 412: /* gen_movel_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5563,18 +5581,18 @@ public abstract class Core extends CoreALU { dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 411: /* gen_movel_dt_ea */ + case 413: /* gen_movel_dt_ea */ long_tst(dt); mpc = ea_resume_write32; continue; - case 412: /* gen_movel_ds_ad */ + case 414: /* gen_movel_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 413: /* gen_movel_as_ad */ + case 415: /* gen_movel_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5582,39 +5600,39 @@ public abstract class Core extends CoreALU { dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 414: /* gen_movel_dt_ad */ + case 416: /* gen_movel_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dt; mpc = resume_prefetch; continue; - case 415: /* gen_movew_ds_ea */ + case 417: /* gen_movew_ds_ea */ ry = ir & 0x0007; word_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write16; continue; - case 416: /* gen_movew_as_ea */ + case 418: /* gen_movew_as_ea */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; word_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write16; continue; - case 417: /* gen_movew_dt_dd */ + case 419: /* gen_movew_dt_dd */ rx = (ir >> 9) & 0x0007; word_tst(dt); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 418: /* gen_movew_ds_dd */ + case 420: /* gen_movew_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; word_tst(dar[ry]); dar[rx] = (dar[rx] & ~0xffff) | (dar[ry] & 0xffff); mpc = resume_prefetch; continue; - case 419: /* gen_movew_as_dd */ + case 421: /* gen_movew_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5622,18 +5640,18 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dar[ry] & 0xffff); mpc = resume_prefetch; continue; - case 420: /* gen_movew_dt_ea */ + case 422: /* gen_movew_dt_ea */ word_tst(dt); mpc = ea_resume_write16; continue; - case 421: /* gen_movew_ds_ad */ + case 423: /* gen_movew_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = (short) dar[ry]; mpc = resume_prefetch; continue; - case 422: /* gen_movew_as_ad */ + case 424: /* gen_movew_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5641,43 +5659,43 @@ public abstract class Core extends CoreALU { dar[rx] = (short) dar[ry]; mpc = resume_prefetch; continue; - case 423: /* gen_movew_dt_ad */ + case 425: /* gen_movew_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = (short) dt; mpc = resume_prefetch; continue; - case 424: /* gen_negxb_ds */ + case 426: /* gen_negxb_ds */ ry = ir & 0x0007; dt = byte_negx(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 425: /* gen_negxb_ea */ + case 427: /* gen_negxb_ea */ dt = byte_negx(dt); mpc = ea_resume_write8; continue; - case 426: /* gen_negxw_ds */ + case 428: /* gen_negxw_ds */ ry = ir & 0x0007; dt = word_negx(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 427: /* gen_negxw_ea */ + case 429: /* gen_negxw_ea */ dt = word_negx(dt); mpc = ea_resume_write16; continue; - case 428: /* gen_negxl_ds */ + case 430: /* gen_negxl_ds */ ry = ir & 0x0007; dt = long_negx(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 429: /* gen_negxl_ea */ + case 431: /* gen_negxl_ea */ dt = long_negx(dt); mpc = ea_resume_write32; continue; - case 430: /* gen_movew_sr_ds */ + case 432: /* gen_movew_sr_ds */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5688,7 +5706,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (sr & 0xffff); mpc = resume_prefetch; continue; - case 431: /* gen_movew_sr_ea */ + case 433: /* gen_movew_sr_ea */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5698,25 +5716,25 @@ public abstract class Core extends CoreALU { dt = (sr & 0xf71f); mpc = ea_resume_write16; continue; - case 432: /* gen_movew_ccr_ds */ + case 434: /* gen_movew_ccr_ds */ ry = ir & 0x0007; dar[ry] = (dar[ry] & ~0xffff) | (sr & 0x001f); mpc = resume_prefetch; continue; - case 433: /* gen_movew_ccr_ea */ + case 435: /* gen_movew_ccr_ea */ dt = (sr & 0x001f); mpc = ea_resume_write16; continue; - case 434: /* gen_movew_ds_ccr */ + case 436: /* gen_movew_ds_ccr */ ry = ir & 0x0007; sr = (sr & ~0xff) | (dar[ry] & 0x001f); mpc = resume_prefetch; continue; - case 435: /* gen_movew_dt_ccr */ + case 437: /* gen_movew_dt_ccr */ sr = (sr & ~0xff) | (dt & 0x001f); mpc = resume_prefetch; continue; - case 436: /* gen_movew_ds_sr */ + case 438: /* gen_movew_ds_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5727,7 +5745,7 @@ public abstract class Core extends CoreALU { sr = dar[ry] & 0xf71f; mpc = resume_prefetch; continue; - case 437: /* gen_movew_dt_sr */ + case 439: /* gen_movew_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5737,100 +5755,100 @@ public abstract class Core extends CoreALU { sr = dt & 0xf71f; mpc = resume_prefetch; continue; - case 438: /* gen_negb_ds */ + case 440: /* gen_negb_ds */ ry = ir & 0x0007; dt = byte_neg(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 439: /* gen_negb_ea */ + case 441: /* gen_negb_ea */ dt = byte_neg(dt); mpc = ea_resume_write8; continue; - case 440: /* gen_negw_ds */ + case 442: /* gen_negw_ds */ ry = ir & 0x0007; dt = word_neg(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 441: /* gen_negl_ea */ + case 443: /* gen_negl_ea */ dt = long_neg(dt); mpc = ea_resume_write32; continue; - case 442: /* gen_negl_ds */ + case 444: /* gen_negl_ds */ ry = ir & 0x0007; dt = long_neg(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 443: /* gen_notb_ds */ + case 445: /* gen_notb_ds */ ry = ir & 0x0007; dt = byte_not(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 444: /* gen_notb_ea */ + case 446: /* gen_notb_ea */ dt = byte_not(dt); mpc = ea_resume_write8; continue; - case 445: /* gen_notw_ds */ + case 447: /* gen_notw_ds */ ry = ir & 0x0007; dt = word_not(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 446: /* gen_notw_ea */ + case 448: /* gen_notw_ea */ dt = word_not(dt); mpc = ea_resume_write16; continue; - case 447: /* gen_notl_ds */ + case 449: /* gen_notl_ds */ ry = ir & 0x0007; dt = long_not(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 448: /* gen_notl_ea */ + case 450: /* gen_notl_ea */ dt = long_not(dt); mpc = ea_resume_write32; continue; - case 449: /* gen_nbcdb_ds */ + case 451: /* gen_nbcdb_ds */ ry = ir & 0x0007; dt = byte_nbcd(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 450: /* gen_nbcdb_ea */ + case 452: /* gen_nbcdb_ea */ dt = byte_nbcd(dt); mpc = ea_resume_write8; continue; - case 451: /* gen_tstb_ds */ + case 453: /* gen_tstb_ds */ ry = ir & 0x0007; byte_tst(dar[ry]); mpc = resume_prefetch; continue; - case 452: /* gen_tstb_ea */ + case 454: /* gen_tstb_ea */ byte_tst(dt); mpc = resume_prefetch; continue; - case 453: /* gen_tstw_ds */ + case 455: /* gen_tstw_ds */ ry = ir & 0x0007; word_tst(dar[ry]); mpc = resume_prefetch; continue; - case 454: /* gen_tstw_ea */ + case 456: /* gen_tstw_ea */ word_tst(dt); mpc = resume_prefetch; continue; - case 455: /* gen_tstl_ds */ + case 457: /* gen_tstl_ds */ ry = ir & 0x0007; long_tst(dar[ry]); mpc = resume_prefetch; continue; - case 456: /* gen_tstl_ea */ + case 458: /* gen_tstl_ea */ long_tst(dt); mpc = resume_prefetch; continue; - case 457: /* gen_addb_ir_ds */ + case 459: /* gen_addb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5840,7 +5858,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 458: /* gen_addb_ir_ea */ + case 460: /* gen_addb_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5848,7 +5866,7 @@ public abstract class Core extends CoreALU { dt = byte_add(alub, dt); mpc = ea_resume_write8; continue; - case 459: /* gen_addw_ir_ds */ + case 461: /* gen_addw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5858,7 +5876,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 460: /* gen_addw_ir_as */ + case 462: /* gen_addw_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5868,7 +5886,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] + ((short) alub); mpc = resume_prefetch; continue; - case 461: /* gen_addw_ir_ea */ + case 463: /* gen_addw_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5876,7 +5894,7 @@ public abstract class Core extends CoreALU { dt = word_add(alub, dt); mpc = ea_resume_write16; continue; - case 462: /* gen_addl_ir_ds */ + case 464: /* gen_addl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5886,7 +5904,7 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 463: /* gen_addl_ir_as */ + case 465: /* gen_addl_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5896,7 +5914,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] + alub; mpc = resume_prefetch; continue; - case 464: /* gen_addl_ir_ea */ + case 466: /* gen_addl_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5904,7 +5922,7 @@ public abstract class Core extends CoreALU { dt = long_add(alub, dt); mpc = ea_resume_write32; continue; - case 465: /* gen_subb_ir_ds */ + case 467: /* gen_subb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5914,7 +5932,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 466: /* gen_subb_ir_ea */ + case 468: /* gen_subb_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5922,7 +5940,7 @@ public abstract class Core extends CoreALU { dt = byte_sub(alub, dt); mpc = ea_resume_write8; continue; - case 467: /* gen_subw_ir_ds */ + case 469: /* gen_subw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5932,7 +5950,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 468: /* gen_subw_ir_as */ + case 470: /* gen_subw_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5942,7 +5960,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] - ((short) alub); mpc = resume_prefetch; continue; - case 469: /* gen_subw_ir_ea */ + case 471: /* gen_subw_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5950,7 +5968,7 @@ public abstract class Core extends CoreALU { dt = word_sub(alub, dt); mpc = ea_resume_write16; continue; - case 470: /* gen_subl_ir_ds */ + case 472: /* gen_subl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5960,7 +5978,7 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 471: /* gen_subl_ir_as */ + case 473: /* gen_subl_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5970,7 +5988,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] - alub; mpc = resume_prefetch; continue; - case 472: /* gen_subl_ir_ea */ + case 474: /* gen_subl_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5978,99 +5996,99 @@ public abstract class Core extends CoreALU { dt = long_sub(alub, dt); mpc = ea_resume_write32; continue; - case 473: /* gen_movel_im_dd */ + case 475: /* gen_movel_im_dd */ dt = (byte) ir; rx = (ir >> 9) & 0x0007; long_tst(dt); dar[rx] = dt; mpc = resume_prefetch; continue; - case 474: /* gen_orb_ds_dd */ + case 476: /* gen_orb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_or(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 475: /* gen_orb_dt_dd */ + case 477: /* gen_orb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_or(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 476: /* gen_orw_ds_dd */ + case 478: /* gen_orw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_or(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 477: /* gen_orw_dt_dd */ + case 479: /* gen_orw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_or(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 478: /* gen_orl_ds_dd */ + case 480: /* gen_orl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_or(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 479: /* gen_orl_dt_dd */ + case 481: /* gen_orl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_or(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 480: /* gen_sbcdb_ds_dd */ + case 482: /* gen_sbcdb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_sbcd(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 481: /* gen_sbcdb_im_ea */ + case 483: /* gen_sbcdb_im_ea */ dt = byte_sbcd(alub, dt); mpc = ea_resume_write8; continue; - case 482: /* gen_orb_dd_ea */ + case 484: /* gen_orb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_or(dar[rx], dt); mpc = ea_resume_write8; continue; - case 483: /* gen_orw_dd_ea */ + case 485: /* gen_orw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_or(dar[rx], dt); mpc = ea_resume_write16; continue; - case 484: /* gen_orl_dd_ea */ + case 486: /* gen_orl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_or(dar[rx], dt); mpc = ea_resume_write32; continue; - case 485: /* gen_subb_ds_dd */ + case 487: /* gen_subb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_sub(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 486: /* gen_subb_dt_dd */ + case 488: /* gen_subb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_sub(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 487: /* gen_subw_ds_dd */ + case 489: /* gen_subw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_sub(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 488: /* gen_subw_as_dd */ + case 490: /* gen_subw_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6078,20 +6096,20 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 489: /* gen_subw_dt_dd */ + case 491: /* gen_subw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_sub(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 490: /* gen_subl_ds_dd */ + case 492: /* gen_subl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_sub(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 491: /* gen_subl_as_dd */ + case 493: /* gen_subl_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6099,68 +6117,68 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 492: /* gen_subl_dt_dd */ + case 494: /* gen_subl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_sub(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 493: /* gen_subb_dd_ea */ + case 495: /* gen_subb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_sub(dar[rx], dt); mpc = ea_resume_write8; continue; - case 494: /* gen_subw_dd_ea */ + case 496: /* gen_subw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_sub(dar[rx], dt); mpc = ea_resume_write16; continue; - case 495: /* gen_subl_dd_ea */ + case 497: /* gen_subl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_sub(dar[rx], dt); mpc = ea_resume_write32; continue; - case 496: /* gen_subxb_ds_dd */ + case 498: /* gen_subxb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_subx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 497: /* gen_subxb_im_ea */ + case 499: /* gen_subxb_im_ea */ dt = byte_subx(alub, dt); mpc = ea_resume_write8; continue; - case 498: /* gen_subxw_ds_dd */ + case 500: /* gen_subxw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_subx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 499: /* gen_subxw_im_ea */ + case 501: /* gen_subxw_im_ea */ dt = word_subx(alub, dt); mpc = ea_resume_write16; continue; - case 500: /* gen_subxl_ds_dd */ + case 502: /* gen_subxl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_subx(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 501: /* gen_subxl_im_ea */ + case 503: /* gen_subxl_im_ea */ dt = long_subx(alub, dt); mpc = ea_resume_write32; continue; - case 502: /* gen_subw_ds_ad */ + case 504: /* gen_subw_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - ((short) dar[ry]); mpc = resume_prefetch; continue; - case 503: /* gen_subw_as_ad */ + case 505: /* gen_subw_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6168,20 +6186,20 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] - ((short) dar[ry]); mpc = resume_prefetch; continue; - case 504: /* gen_subw_dt_ad */ + case 506: /* gen_subw_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - ((short) dt); mpc = resume_prefetch; continue; - case 505: /* gen_subl_ds_ad */ + case 507: /* gen_subl_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - dar[ry]; mpc = resume_prefetch; continue; - case 506: /* gen_subl_as_ad */ + case 508: /* gen_subl_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6189,67 +6207,67 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] - dar[ry]; mpc = resume_prefetch; continue; - case 507: /* gen_subl_dt_ad */ + case 509: /* gen_subl_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - dt; mpc = resume_prefetch; continue; - case 508: /* gen_cmpb_ds_dd */ + case 510: /* gen_cmpb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; byte_sub(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 509: /* gen_cmpb_dt_dd */ + case 511: /* gen_cmpb_dt_dd */ rx = (ir >> 9) & 0x0007; byte_sub(dt, dar[rx]); mpc = resume_prefetch; continue; - case 510: /* gen_cmpw_ds_dd */ + case 512: /* gen_cmpw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; word_sub(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 511: /* gen_cmpw_as_dd */ + case 513: /* gen_cmpw_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; word_sub(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 512: /* gen_cmpw_dt_dd */ + case 514: /* gen_cmpw_dt_dd */ rx = (ir >> 9) & 0x0007; word_sub(dt, dar[rx]); mpc = resume_prefetch; continue; - case 513: /* gen_cmpl_ds_dd */ + case 515: /* gen_cmpl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; long_sub(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 514: /* gen_cmpl_as_dd */ + case 516: /* gen_cmpl_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; long_sub(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 515: /* gen_cmpl_dt_dd */ + case 517: /* gen_cmpl_dt_dd */ rx = (ir >> 9) & 0x0007; long_sub(dt, dar[rx]); mpc = resume_prefetch; continue; - case 516: /* gen_cmpw_ds_ad */ + case 518: /* gen_cmpw_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_sub((short) dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 517: /* gen_cmpw_as_ad */ + case 519: /* gen_cmpw_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6257,20 +6275,20 @@ public abstract class Core extends CoreALU { long_sub((short) dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 518: /* gen_cmpw_dt_ad */ + case 520: /* gen_cmpw_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_sub((short) dt, dar[rx]); mpc = resume_prefetch; continue; - case 519: /* gen_cmpl_ds_ad */ + case 521: /* gen_cmpl_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_sub(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 520: /* gen_cmpl_as_ad */ + case 522: /* gen_cmpl_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6278,146 +6296,146 @@ public abstract class Core extends CoreALU { long_sub(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 521: /* gen_cmpl_dt_ad */ + case 523: /* gen_cmpl_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_sub(dt, dar[rx]); mpc = resume_prefetch; continue; - case 522: /* gen_cmpmb_im_ea */ + case 524: /* gen_cmpmb_im_ea */ byte_sub(alub, dt); mpc = resume_prefetch; continue; - case 523: /* gen_cmpmw_im_ea */ + case 525: /* gen_cmpmw_im_ea */ word_sub(alub, dt); mpc = resume_prefetch; continue; - case 524: /* gen_cmpml_im_ea */ + case 526: /* gen_cmpml_im_ea */ long_sub(alub, dt); mpc = resume_prefetch; continue; - case 525: /* gen_eorb_dd_ds */ + case 527: /* gen_eorb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_eor(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 526: /* gen_eorb_dd_ea */ + case 528: /* gen_eorb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_eor(dar[rx], dt); mpc = ea_resume_write8; continue; - case 527: /* gen_eorw_dd_ds */ + case 529: /* gen_eorw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_eor(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 528: /* gen_eorw_dd_ea */ + case 530: /* gen_eorw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_eor(dar[rx], dt); mpc = ea_resume_write16; continue; - case 529: /* gen_eorl_dd_ds */ + case 531: /* gen_eorl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_eor(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 530: /* gen_eorl_dd_ea */ + case 532: /* gen_eorl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_eor(dar[rx], dt); mpc = ea_resume_write32; continue; - case 531: /* gen_andb_ds_dd */ + case 533: /* gen_andb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_and(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 532: /* gen_andb_dt_dd */ + case 534: /* gen_andb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_and(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 533: /* gen_andw_ds_dd */ + case 535: /* gen_andw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_and(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 534: /* gen_andw_dt_dd */ + case 536: /* gen_andw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_and(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 535: /* gen_andl_ds_dd */ + case 537: /* gen_andl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_and(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 536: /* gen_andl_dt_dd */ + case 538: /* gen_andl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_and(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 537: /* gen_andb_dd_ea */ + case 539: /* gen_andb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_and(dar[rx], dt); mpc = ea_resume_write8; continue; - case 538: /* gen_andw_dd_ea */ + case 540: /* gen_andw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_and(dar[rx], dt); mpc = ea_resume_write16; continue; - case 539: /* gen_andl_dd_ea */ + case 541: /* gen_andl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_and(dar[rx], dt); mpc = ea_resume_write32; continue; - case 540: /* gen_abcdb_ds_dd */ + case 542: /* gen_abcdb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_abcd(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 541: /* gen_abcdb_im_ea */ + case 543: /* gen_abcdb_im_ea */ dt = byte_abcd(alub, dt); mpc = ea_resume_write8; continue; - case 542: /* gen_addb_ds_dd */ + case 544: /* gen_addb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_add(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 543: /* gen_addb_dt_dd */ + case 545: /* gen_addb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_add(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 544: /* gen_addw_ds_dd */ + case 546: /* gen_addw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_add(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 545: /* gen_addw_as_dd */ + case 547: /* gen_addw_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6425,20 +6443,20 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 546: /* gen_addw_dt_dd */ + case 548: /* gen_addw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_add(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 547: /* gen_addl_ds_dd */ + case 549: /* gen_addl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_add(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 548: /* gen_addl_as_dd */ + case 550: /* gen_addl_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6446,68 +6464,68 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 549: /* gen_addl_dt_dd */ + case 551: /* gen_addl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_add(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 550: /* gen_addb_dd_ea */ + case 552: /* gen_addb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_add(dar[rx], dt); mpc = ea_resume_write8; continue; - case 551: /* gen_addw_dd_ea */ + case 553: /* gen_addw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_add(dar[rx], dt); mpc = ea_resume_write16; continue; - case 552: /* gen_addl_dd_ea */ + case 554: /* gen_addl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_add(dar[rx], dt); mpc = ea_resume_write32; continue; - case 553: /* gen_addxb_ds_dd */ + case 555: /* gen_addxb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_addx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 554: /* gen_addxb_im_ea */ + case 556: /* gen_addxb_im_ea */ dt = byte_addx(alub, dt); mpc = ea_resume_write8; continue; - case 555: /* gen_addxw_ds_dd */ + case 557: /* gen_addxw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_addx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 556: /* gen_addxw_im_ea */ + case 558: /* gen_addxw_im_ea */ dt = word_addx(alub, dt); mpc = ea_resume_write16; continue; - case 557: /* gen_addxl_ds_dd */ + case 559: /* gen_addxl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_addx(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 558: /* gen_addxl_im_ea */ + case 560: /* gen_addxl_im_ea */ dt = long_addx(alub, dt); mpc = ea_resume_write32; continue; - case 559: /* gen_addw_ds_ad */ + case 561: /* gen_addw_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + ((short) dar[ry]); mpc = resume_prefetch; continue; - case 560: /* gen_addw_as_ad */ + case 562: /* gen_addw_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6515,20 +6533,20 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] + ((short) dar[ry]); mpc = resume_prefetch; continue; - case 561: /* gen_addw_dt_ad */ + case 563: /* gen_addw_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + ((short) dt); mpc = resume_prefetch; continue; - case 562: /* gen_addl_ds_ad */ + case 564: /* gen_addl_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + dar[ry]; mpc = resume_prefetch; continue; - case 563: /* gen_addl_as_ad */ + case 565: /* gen_addl_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6536,13 +6554,13 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] + dar[ry]; mpc = resume_prefetch; continue; - case 564: /* gen_addl_dt_ad */ + case 566: /* gen_addl_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + dt; mpc = resume_prefetch; continue; - case 565: /* gen_asrb_ir_ds */ + case 567: /* gen_asrb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6552,14 +6570,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 566: /* gen_asrb_dd_ds */ + case 568: /* gen_asrb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_asr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 567: /* gen_asrw_ir_ds */ + case 569: /* gen_asrw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6569,14 +6587,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 568: /* gen_asrw_dd_ds */ + case 570: /* gen_asrw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_asr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 569: /* gen_asrl_ir_ds */ + case 571: /* gen_asrl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6586,18 +6604,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 570: /* gen_asrl_dd_ds */ + case 572: /* gen_asrl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_asr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 571: /* gen_asrw_ea */ + case 573: /* gen_asrw_ea */ dt = word_asr(1, dt); mpc = ea_resume_write16; continue; - case 572: /* gen_aslb_ir_ds */ + case 574: /* gen_aslb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6607,14 +6625,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 573: /* gen_aslb_dd_ds */ + case 575: /* gen_aslb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_asl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 574: /* gen_aslw_ir_ds */ + case 576: /* gen_aslw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6624,14 +6642,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 575: /* gen_aslw_dd_ds */ + case 577: /* gen_aslw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_asl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 576: /* gen_asll_ir_ds */ + case 578: /* gen_asll_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6641,18 +6659,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 577: /* gen_asll_dd_ds */ + case 579: /* gen_asll_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_asl(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 578: /* gen_aslw_ea */ + case 580: /* gen_aslw_ea */ dt = word_asl(1, dt); mpc = ea_resume_write16; continue; - case 579: /* gen_lsrb_ir_ds */ + case 581: /* gen_lsrb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6662,14 +6680,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 580: /* gen_lsrb_dd_ds */ + case 582: /* gen_lsrb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_lsr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 581: /* gen_lsrw_ir_ds */ + case 583: /* gen_lsrw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6679,14 +6697,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 582: /* gen_lsrw_dd_ds */ + case 584: /* gen_lsrw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_lsr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 583: /* gen_lsrl_ir_ds */ + case 585: /* gen_lsrl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6696,18 +6714,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 584: /* gen_lsrl_dd_ds */ + case 586: /* gen_lsrl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_lsr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 585: /* gen_lsrw_ea */ + case 587: /* gen_lsrw_ea */ dt = word_lsr(1, dt); mpc = ea_resume_write16; continue; - case 586: /* gen_lslb_ir_ds */ + case 588: /* gen_lslb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6717,14 +6735,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 587: /* gen_lslb_dd_ds */ + case 589: /* gen_lslb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_lsl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 588: /* gen_lslw_ir_ds */ + case 590: /* gen_lslw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6734,14 +6752,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 589: /* gen_lslw_dd_ds */ + case 591: /* gen_lslw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_lsl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 590: /* gen_lsll_ir_ds */ + case 592: /* gen_lsll_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6751,18 +6769,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 591: /* gen_lsll_dd_ds */ + case 593: /* gen_lsll_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_lsl(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 592: /* gen_lslw_ea */ + case 594: /* gen_lslw_ea */ dt = word_lsl(1, dt); mpc = ea_resume_write16; continue; - case 593: /* gen_rorb_ir_ds */ + case 595: /* gen_rorb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6772,14 +6790,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 594: /* gen_rorb_dd_ds */ + case 596: /* gen_rorb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_ror(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 595: /* gen_rorw_ir_ds */ + case 597: /* gen_rorw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6789,14 +6807,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 596: /* gen_rorw_dd_ds */ + case 598: /* gen_rorw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_ror(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 597: /* gen_rorl_ir_ds */ + case 599: /* gen_rorl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6806,18 +6824,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 598: /* gen_rorl_dd_ds */ + case 600: /* gen_rorl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_ror(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 599: /* gen_rorw_ea */ + case 601: /* gen_rorw_ea */ dt = word_ror(1, dt); mpc = ea_resume_write16; continue; - case 600: /* gen_rolb_ir_ds */ + case 602: /* gen_rolb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6827,14 +6845,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 601: /* gen_rolb_dd_ds */ + case 603: /* gen_rolb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_rol(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 602: /* gen_rolw_ir_ds */ + case 604: /* gen_rolw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6844,14 +6862,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 603: /* gen_rolw_dd_ds */ + case 605: /* gen_rolw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_rol(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 604: /* gen_roll_ir_ds */ + case 606: /* gen_roll_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6861,14 +6879,14 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 605: /* gen_roll_dd_ds */ + case 607: /* gen_roll_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_rol(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 606: /* gen_rolw_ea */ + case 608: /* gen_rolw_ea */ dt = word_rol(1, dt); mpc = ea_resume_write16; continue; diff --git a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java index bc6e1db..9217062 100644 --- a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java +++ b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java @@ -60,10 +60,12 @@ import static miggy.cpupoet.Core.ea_das8; import static miggy.cpupoet.Core.ea_das8_read; import static miggy.cpupoet.Core.ea_dpc16; import static miggy.cpupoet.Core.ea_dpc16_read; +import static miggy.cpupoet.Core.ea_dpc32; import static miggy.cpupoet.Core.ea_dpc32_read; import static miggy.cpupoet.Core.ea_dpc8_read; import static miggy.cpupoet.Core.ea_dpci16; import static miggy.cpupoet.Core.ea_dpci16_read; +import static miggy.cpupoet.Core.ea_dpci32; import static miggy.cpupoet.Core.ea_dpci32_read; import static miggy.cpupoet.Core.ea_dpci8_read; import static miggy.cpupoet.Core.ea_imm16_read; @@ -383,6 +385,14 @@ import static miggy.cpupoet.Core.op_move_as_usp; import static miggy.cpupoet.Core.op_move_usp_as; import static miggy.cpupoet.Core.op_movec_cr_rz; import static miggy.cpupoet.Core.op_movec_rz_cr; +import static miggy.cpupoet.Core.op_moveml_aips_rr; +import static miggy.cpupoet.Core.op_moveml_ea_rr; +import static miggy.cpupoet.Core.op_moveml_rr_ea; +import static miggy.cpupoet.Core.op_moveml_rr_pais; +import static miggy.cpupoet.Core.op_movemw_aips_rr; +import static miggy.cpupoet.Core.op_movemw_ea_rr; +import static miggy.cpupoet.Core.op_movemw_rr_ea; +import static miggy.cpupoet.Core.op_movemw_rr_pais; import static miggy.cpupoet.Core.op_movepl_das_dd; import static miggy.cpupoet.Core.op_movepl_dd_das; import static miggy.cpupoet.Core.op_movepw_das_dd; @@ -1801,8 +1811,40 @@ public enum MacroPLA { ext_w_ds(0x4880, 0xfff8, op_extw_ds, dbrr, dbrr), + movem_w_list_ais(0x4890, 0xfff8, ea_ais16, dbrr, op_movemw_rr_ea), + + movem_w_listp_pais(0x48a0, 0xfff8, ea_pais16, dbrr, op_movemw_rr_pais), + + movem_w_list_das(0x48a8, 0xfff8, ea_das16, dbrr, op_movemw_rr_ea), + + movem_w_list_dais(0x48b0, 0xfff8, ea_dais16, dbrr, op_movemw_rr_ea), + + movem_w_list_adr16(0x48b8, 0xffff, ea_adr16s16, dbrr, op_movemw_rr_ea), + + movem_w_list_adr32(0x48b9, 0xffff, ea_adr32s16, dbrr, op_movemw_rr_ea), + + movem_w_list_dpc(0x48ba, 0xffff, ea_dpc16, dbrr, op_movemw_rr_ea), + + movem_w_list_dpci(0x48bb, 0xffff, ea_dpci16, dbrr, op_movemw_rr_ea), + ext_l_ds(0x48c0, 0xfff8, op_extl_ds, dbrr, dbrr), + movem_l_list_ais(0x48d0, 0xfff8, ea_ais32, dbrr, op_moveml_rr_ea), + + movem_l_listp_pais(0x48e0, 0xfff8, ea_pais32, dbrr, op_moveml_rr_pais), + + movem_l_list_das(0x48e8, 0xfff8, ea_das32, dbrr, op_moveml_rr_ea), + + movem_l_list_dais(0x48f0, 0xfff8, ea_dais32, dbrr, op_moveml_rr_ea), + + movem_l_list_adr16(0x48f8, 0xffff, ea_adr16s32, dbrr, op_moveml_rr_ea), + + movem_l_list_adr32(0x48f9, 0xffff, ea_adr32s32, dbrr, op_moveml_rr_ea), + + movem_l_list_dpc(0x48fa, 0xffff, ea_dpc32, dbrr, op_moveml_rr_ea), + + movem_l_list_dpci(0x48fb, 0xffff, ea_dpci32, dbrr, op_moveml_rr_ea), + extb_l_ds(0x49c0, 0xfff8, op_extbl_ds, dbrr, dbrr), tst_b_ds(0x4a00, 0xfff8, gen_tstb_ds, dbrr, dbrr), @@ -1855,6 +1897,38 @@ public enum MacroPLA { illegal(0x4afc, 0xffff, op_illegal, dbrr, dbrr), + movem_w_ais_list(0x4c90, 0xfff8, ea_ais16, dbrr, op_movemw_ea_rr), + + movem_w_aips_list(0x4c98, 0xfff8, ea_aips16, dbrr, op_movemw_aips_rr), + + movem_w_das_list(0x4ca8, 0xfff8, ea_das16, dbrr, op_movemw_ea_rr), + + movem_w_dais_list(0x4cb0, 0xfff8, ea_dais16, dbrr, op_movemw_ea_rr), + + movem_w_adr16_list(0x4cb8, 0xffff, ea_adr16s16, dbrr, op_movemw_ea_rr), + + movem_w_adr32_list(0x4cb9, 0xffff, ea_adr32s16, dbrr, op_movemw_ea_rr), + + movem_w_dpc_list(0x4cba, 0xffff, ea_dpc16, dbrr, op_movemw_ea_rr), + + movem_w_dpci_list(0x4cbb, 0xffff, ea_dpci16, dbrr, op_movemw_ea_rr), + + movem_l_ais_list(0x4cd0, 0xfff8, ea_ais32, dbrr, op_moveml_ea_rr), + + movem_l_aips_list(0x4cd8, 0xfff8, ea_aips32, dbrr, op_moveml_aips_rr), + + movem_l_das_list(0x4ce8, 0xfff8, ea_das32, dbrr, op_moveml_ea_rr), + + movem_l_dais_list(0x4cf0, 0xfff8, ea_dais32, dbrr, op_moveml_ea_rr), + + movem_l_adr16_list(0x4cf8, 0xffff, ea_adr16s32, dbrr, op_moveml_ea_rr), + + movem_l_adr32_list(0x4cf9, 0xffff, ea_adr32s32, dbrr, op_moveml_ea_rr), + + movem_l_dpc_list(0x4cfa, 0xffff, ea_dpc32, dbrr, op_moveml_ea_rr), + + movem_l_dpci_list(0x4cfb, 0xffff, ea_dpci32, dbrr, op_moveml_ea_rr), + trap_imm4(0x4e40, 0xfff0, op_trap, dbrr, dbrr), link_as_imm16(0x4e50, 0xfff8, op_imm16, op_link_as_imm16, dbrr),