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126 lines
4.1 KiB
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126 lines
4.1 KiB
Markdown
[← Home](../README.md) · [Exec Kernel](README.md)
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# Interrupts — Levels, INTENA, AddIntServer, CIA Interrupts
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## Overview
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AmigaOS supports 7 hardware interrupt levels (68k IPL0–IPL6) plus a software interrupt mechanism. Custom chip interrupts are filtered through the `INTENA` / `INTREQ` registers; CIA-generated interrupts arrive on level 2 (CIA-A) and level 6 (CIA-B).
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---
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## Interrupt Priority Levels
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| IPL | Source | AmigaOS Use |
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|---|---|---|
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| 1 | TBE, DSKBLK, SOFTINT | Software interrupts (`SoftInt`) |
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| 2 | PORTS (CIA-A) | Keyboard, timer, parallel, floppy motor |
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| 3 | COPER, VERTB, BLIT | Copper, vertical blank, blitter |
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| 4 | AUD0–AUD3 | Audio DMA completion |
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| 5 | RBF, DSKSYNC | Serial receive, disk sync |
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| 6 | EXTER (CIA-B) | External interrupts, CIA-B timers, TOD |
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| 7 | NMI | Non-maskable (unused on stock Amiga) |
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---
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## Custom Chip Interrupt Registers
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| Register | Address | Description |
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|---|---|---|
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| `INTENAR` | `$DFF01C` | Interrupt enable status (read) |
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| `INTENA` | `$DFF09A` | Interrupt enable set/clear (write) |
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| `INTREQR` | `$DFF01E` | Interrupt request status (read) |
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| `INTREQ` | `$DFF09C` | Interrupt request clear/set (write) |
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### INTENA / INTREQ Bit Map
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| Bit | Constant | Source |
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|---|---|---|
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| 0 | `INTF_TBE` | Serial transmit buffer empty |
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| 1 | `INTF_DSKBLK` | Disk DMA block complete |
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| 2 | `INTF_SOFTINT` | Software interrupt |
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| 3 | `INTF_PORTS` | CIA-A interrupt (level 2) |
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| 4 | `INTF_COPER` | Copper interrupt |
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| 5 | `INTF_VERTB` | Vertical blank |
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| 6 | `INTF_BLIT` | Blitter interrupt |
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| 7 | `INTF_AUD0` | Audio channel 0 |
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| 8 | `INTF_AUD1` | Audio channel 1 |
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| 9 | `INTF_AUD2` | Audio channel 2 |
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| 10 | `INTF_AUD3` | Audio channel 3 |
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| 11 | `INTF_RBF` | Serial receive buffer full |
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| 12 | `INTF_DSKSYNC` | Disk sync word match |
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| 13 | `INTF_EXTER` | CIA-B / external interrupt |
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| 14 | `INTF_INTEN` | Master interrupt enable bit |
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To enable vertical blank: write `$C005` to `INTENA` (bit 14 set = enable, bit 5 = VERTB).
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To clear vertical blank request: write `$0020` to `INTREQ`.
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---
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## Adding an Interrupt Server
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```c
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struct Interrupt myVBL = {
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{ NULL, NULL, NT_INTERRUPT, 0, "My VBL" },
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NULL, /* is_Data (passed to handler) */
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myVBLHandler /* is_Code */
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};
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AddIntServer(INTB_VERTB, &myVBL); /* INTB_VERTB = 5 */
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/* ... run ... */
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RemIntServer(INTB_VERTB, &myVBL); /* always remove before exit */
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```
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### Interrupt Handler Rules
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- Handler is called at interrupt level — **no OS calls that Wait()**
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- D0–D1, A0–A1 may be trashed; all others preserved
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- Return D0 = 0 if you did not handle it (pass to next server)
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- Return D0 ≠ 0 if you handled it (stop server chain)
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Handler signature:
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```asm
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myVBLHandler:
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; A1 = is_Data pointer (from struct Interrupt)
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; do fast work only
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MOVEQ #1, D0 ; handled — stop chain
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RTS
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```
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---
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## CIA Interrupts
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CIA-A (at `$BFEC01`) generates level 2 interrupts. CIA-B (at `$BFD000`) generates level 6. Each CIA has an ICR (Interrupt Control Register) with 5 sources:
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| Bit | Source |
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|---|---|
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| 0 | Timer A underflow |
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| 1 | Timer B underflow |
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| 2 | TOD alarm |
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| 3 | Serial register full |
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| 4 | Flag pin / FLG |
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CIA interrupts are serviced via AddIntServer on `INTB_PORTS` (level 2, CIA-A) or `INTB_EXTER` (level 6, CIA-B).
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---
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## Disable / Enable vs Forbid / Permit
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| Function | Effect | Scope |
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|---|---|---|
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| `Forbid()` | Disables task switching | Task-level (interrupts still run) |
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| `Permit()` | Re-enables task switching | Reverses `Forbid()` |
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| `Disable()` | Masks all hardware interrupts | Hardware + task switching |
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| `Enable()` | Unmasks hardware interrupts | Reverses `Disable()` |
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> [!CAUTION]
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> `Disable()` / `Enable()` can be held for only a few microseconds — never do I/O or complex operations inside a `Disable()` section.
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---
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## References
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- NDK39: `hardware/intbits.h`, `hardware/cia.h`
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- ADCD 2.1: `AddIntServer`, `RemIntServer`, `SetIntVector`, `Disable`, `Forbid`
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- [cia_chips.md](../01_hardware/common/cia_chips.md) — CIA timer and ICR details
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- [custom_registers.md](../01_hardware/ocs_a500/custom_registers.md) — INTENA/INTREQ register listing
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