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Comprehensive technical documentation covering: - Hardware: OCS/ECS/AGA custom chip registers, Copper & Blitter deep dives - Boot sequence: cold boot through startup-sequence - Binary format: HUNK executable spec, relocation, debug info - Linking & ABI: .fd files, LVO tables, register calling conventions - Exec kernel: tasks, interrupts, memory, signals, semaphores - AmigaDOS: file I/O, FFS/OFS layout, CLI/Shell scripting - Graphics: planar bitmaps, Copper programming, HAM/EHB modes - Intuition: screens, windows, IDCMP, BOOPSI - Devices: trackdisk, SCSI, serial, timer, audio, keyboard - Libraries: utility, expansion, IFFParse, locale, ARexx - Networking: bsdsocket API, SANA-II, TCP/IP stack comparison - Toolchain: GCC, vasm/vlink, SAS/C, NDK, debugging - Reverse engineering: IDA/Ghidra setup, compiler fingerprints, case studies - CPU & MMU: 68040/060 emulation libs, PMMU, cache management - Driver development: SANA-II, Picasso96/RTG, AHI audio All files include breadcrumb navigation. No local paths or proprietary content.
107 lines
3.7 KiB
Markdown
107 lines
3.7 KiB
Markdown
[← Home](../../README.md) · [Hardware](../README.md) · [OCS](README.md)
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# OCS Chipset Internals
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## Architecture
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The three OCS chips share a common **chip bus** (also called the chip bus or DMA bus). Agnus is the bus master — it arbitrates between the CPU, Copper, Blitter, and DMA channels.
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```mermaid
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block-beta
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columns 3
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CPU["68000 CPU"] Agnus["Agnus\n(DMA Master)"] ChipRAM["Chip RAM\n512 KB"]
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space Paula["Paula\n(Audio/Disk/Serial)"] space
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space Denise["Denise\n(Display)"] space
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CPU-- "bus request" -->Agnus
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Agnus-- "DMA cycles" -->ChipRAM
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Paula-- "DMA req" -->Agnus
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Denise-- "bitplane/sprite data" -->Agnus
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```
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## DMA Channels and Priorities
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Agnus schedules DMA cycles across a fixed priority scheme within each horizontal raster line (228 colour clocks per line, PAL):
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| Priority | DMA Channel | Register Bits |
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|---|---|---|
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| 1 (highest) | Disk | `DMACONR[4]` DSKEN |
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| 2 | Sprite | `DMACONR[2]` SPREN |
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| 3 | Bitplane | `DMACONR[8]` BPLEN |
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| 4 | Copper | `DMACONR[7]` COPEN |
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| 5 | Blitter | `DMACONR[6]` BLTEN |
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| 6 | Audio ch 0–3 | `DMACONR[0..3]` AUD0–AUD3 |
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| 7 (lowest) | CPU | Remaining cycles |
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The CPU only gets cycles not consumed by DMA — this is why heavy DMA usage (e.g., full-screen bitplanes + sprites + audio) can starve the CPU noticeably on OCS.
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## DMACON Register
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Write `$DFF096` (DMACON), read `$DFF002` (DMACONR):
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```
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bit 15: SET/CLR — write: 1=set bits, 0=clear bits (read: always 0)
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bit 14: BBUSY — blitter busy (read only)
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bit 13: BZERO — blitter zero flag (read only)
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bit 10: (reserved)
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bit 9: MASTER — master DMA enable (must be set for any DMA)
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bit 8: BPLEN — bitplane DMA
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bit 7: COPEN — Copper DMA
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bit 6: BLTEN — Blitter DMA
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bit 5: SPREN — Sprite DMA
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bit 4: DSKEN — Disk DMA
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bit 3: AUD3EN — Audio channel 3 DMA
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bit 2: AUD2EN — Audio channel 2 DMA
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bit 1: AUD1EN — Audio channel 1 DMA
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bit 0: AUD0EN — Audio channel 0 DMA
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```
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Enable all standard DMA:
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```asm
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move.w #$8380,DMACON ; SET + MASTER + BPLEN + COPEN
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move.w #$800F,DMACON ; SET + AUD0-3
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```
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## INTENA / INTREQ — Interrupt System
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Write `$DFF09A` (INTENA), read `$DFF01C` (INTENAR):
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Write `$DFF09C` (INTREQ), read `$DFF01E` (INTREQR):
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```
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bit 14: INTEN — global interrupt enable (INTENA only)
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bit 13: EXTER — external/CIA interrupt (IPL6)
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bit 12: DSKSYNC — disk sync (IPL5)
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bit 11: RBF — serial receive buffer full (IPL5)
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bit 10: AUD3 — audio channel 3 (IPL4)
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bit 9: AUD2 — audio channel 2 (IPL4)
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bit 8: AUD1 — audio channel 1 (IPL4)
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bit 7: AUD0 — audio channel 0 (IPL4)
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bit 6: BLIT — blitter finished (IPL3)
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bit 5: VERTB — vertical blank (IPL3)
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bit 4: COPPER — copper interrupt (IPL3)
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bit 3: PORTS — CIA-A port interrupts (IPL2)
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bit 2: SOFT — software interrupt (IPL1)
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bit 1: DSKBLK — disk block finished (IPL1)
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bit 0: TBE — serial transmit buffer empty (IPL1)
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```
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To enable vertical blank interrupt:
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```asm
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move.w #$C020,INTENA ; SET + INTEN + VERTB
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```
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## Agnus: Bitplane DMA Timing
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During each scan line, Agnus fetches bitplane data for the current line. For a 320-pixel wide, 4-bitplane display, Agnus takes 40 DMA cycles per line for bitplane fetch. On a standard PAL line with 227 clock cycles, this leaves ~187 cycles for CPU + other DMA.
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**Bitplane DMA pointers** (set at start of each frame or via Copper):
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```
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BPL1PTH/BPL1PTL $DFF0E0/$DFF0E2 Bitplane 1 pointer (high/low word)
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BPL2PTH/BPL2PTL $DFF0E4/$DFF0E6
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... up to BPL6 for OCS (6 bitplanes max)
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```
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## References
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- ADCD 2.1 Hardware Manual — Agnus/DMA chapters
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- NDK39: `hardware/dmabits.h`, `hardware/intbits.h`, `hardware/custom.h`
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- *Amiga Hardware Reference Manual* 3rd ed.
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