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223 lines
8.4 KiB
Markdown
223 lines
8.4 KiB
Markdown
[← Home](../../README.md) · [Hardware](../README.md)
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# CIA Chips — 8520 MOS Technology
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## Overview
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The Amiga uses **two MOS 8520 CIA** (Complex Interface Adapter) chips, providing timers, parallel/serial I/O ports, a time-of-day clock, and interrupt generation. They are the primary source of hardware timing outside the vertical blank and audio DMA.
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- **CIA-A** at `$BFE001` (even byte addresses)
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- **CIA-B** at `$BFD000` (odd byte addresses)
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Both CIAs are accessed via byte reads/writes; the 68000 byte-lane placement means CIA-A uses even offsets and CIA-B uses odd offsets on the 16-bit bus.
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## Register Map
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Each CIA has 16 registers, spaced 256 bytes apart in the Amiga address space:
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| Offset | Register | CIA-A Function | CIA-B Function |
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|---|---|---|---|
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| $000 | PRA | Parallel port data (input) | Disk control outputs |
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| $100 | PRB | Parallel port data (output) | Disk status inputs |
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| $200 | DDRA | Port A direction (1=output) | Port A direction |
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| $300 | DDRB | Port B direction | Port B direction |
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| $400 | TALO | Timer A low byte | Timer A low byte |
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| $500 | TAHI | Timer A high byte | Timer A high byte |
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| $600 | TBLO | Timer B low byte | Timer B low byte |
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| $700 | TBHI | Timer B high byte | Timer B high byte |
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| $800 | TODLO | TOD clock low (1/60 s) | Disk position (latched) |
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| $900 | TODMID | TOD clock mid | |
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| $A00 | TODHI | TOD clock high | |
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| $B00 | (unused) | — | — |
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| $C00 | SDR | Serial data register | Serial data register |
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| $D00 | ICR | Interrupt control | Interrupt control |
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| $E00 | CRA | Control register A | Control register A |
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| $F00 | CRB | Control register B | Control register B |
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## CIA-A: $BFE001
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CIA-A handles:
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| Bit | Port A (PRA, read $BFE001) |
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|---|---|
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| 7 | `/FIR1` — joystick port 1 button |
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| 6 | `/FIR0` — joystick port 0 button |
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| 5 | `/RDY` — floppy ready |
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| 4 | `/TK0` — track 0 sensor |
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| 3 | `/WPRO` — write-protect |
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| 2 | `/CHNG` — disk change |
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| 1 | `/LED` — power LED (write: 0=bright) |
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| 0 | `/OVL` — Chip RAM overlay (write during boot) |
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Port B (PRB, $BFE101): Parallel port data lines D0–D7.
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**CIA-A interrupts** appear on **CPU IPL level 2** via INTENA bit `INTB_EXTER` — actually CIA is on IPL 6.
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## CIA-B: $BFD000
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CIA-B handles floppy drive motor/selection and disk DMA sync:
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| Bit | Port A (PRA, $BFD000) |
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|---|---|
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| 7 | `/MTR` — motor on/off |
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| 6 | `/SEL3` — drive 3 select |
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| 5 | `/SEL2` — drive 2 select |
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| 4 | `/SEL1` — drive 1 select |
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| 3 | `/SEL0` — drive 0 select |
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| 2 | `/SIDE` — head side (0=upper) |
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| 1 | `/DIR` — step direction |
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| 0 | `/STEP` — step pulse |
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Port B (PRB, $BFD100): Parallel port shadow (less commonly used on B).
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**CIA-B interrupts** appear on **CPU IPL level 6**.
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## Timers
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Each CIA has two 16-bit countdown timers (Timer A and Timer B):
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- Count from a loaded latch value down to zero
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- Can be one-shot or continuous
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- Clock sources: system clock (709 kHz PAL / 715 kHz NTSC), or Timer A output (for Timer B)
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- Timer A can generate `SDR` baud rate for serial output
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**Control Register A (CRA) bits:**
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```
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bit 0: START — 1 = timer running
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bit 1: PBON — 1 = timer output on Port B bit 6
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bit 2: OUTMODE — 0=pulse, 1=toggle
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bit 3: RUNMODE — 0=continuous, 1=one-shot
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bit 4: LOAD — 1 = force load latch into counter
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bit 5: INMODE — 0=clock, 1=count rising edges on CNT pin
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bit 6: SPMODE — 0=SDR input, 1=SDR output
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bit 7: TODIN — 0=60 Hz TOD, 1=50 Hz TOD (PAL)
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```
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## Time-of-Day (TOD) Clock
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24-bit counter, clocked at 60 Hz (NTSC) or 50 Hz (PAL):
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- CIA-A TOD: used by OS as software clock
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- TOD registers latch on read of TODHI — must read TODHI first, then TODMID, then TODLO
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- `ciaa.ciatodhi` → `ciaa.ciatodmid` → `ciaa.ciatodlo`
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- Set by writing TODHI → TODMID → TODLO (halts during write)
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## Interrupt Control Register (ICR)
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Write to enable interrupts, read to see which fired:
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```c
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/* Enable Timer A interrupt */
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ciaa.ciaicr = CIAICRF_SETCLR | CIAICRF_TA;
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/* On read: bits indicate which sources fired */
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UBYTE icr = ciaa.ciaicr;
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if (icr & CIAICRF_TA) { /* Timer A fired */ }
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if (icr & CIAICRF_TB) { /* Timer B fired */ }
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if (icr & CIAICRF_ALRM) { /* TOD alarm fired */ }
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if (icr & CIAICRF_SP) { /* Serial register full/empty */ }
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if (icr & CIAICRF_FLG) { /* /FLAG pin (index pulse on CIA-B) */ }
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```
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Write bit 7 (`CIAICRF_SETCLR`): 1 = set enable bits, 0 = clear enable bits.
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## AmigaOS Timer Device Integration
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AmigaOS's `timer.device` uses CIA timers internally:
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- `UNIT_MICROHZ` — uses CIA-A Timer A for microsecond delays
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- `UNIT_VBLANK` — uses vertical blank interrupt (not CIA)
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- `UNIT_ECLOCK` — uses the E clock (709/715 kHz, same as CIA clock)
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Direct CIA programming should be done with `ciaa`/`ciab` resource claims via `OpenResource("ciaa.resource")` — not by poking CIA registers directly.
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## C Access via NDK Headers
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```c
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#include <hardware/cia.h>
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#include <resources/cia.h>
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/* CIA-A is at fixed address */
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#define ciaa (*((volatile struct CIA *)0xBFE001))
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#define ciab (*((volatile struct CIA *)0xBFD000))
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/* struct CIA fields (hardware/cia.h): */
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/* ciaa.ciapra, ciaa.ciaprb, ciaa.ciaicr, ciaa.ciacra, ... */
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```
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## Per-Model CIA Wiring Variations
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While CIA-A and CIA-B register layouts are identical across all Amigas, the **physical wiring** of their port pins varies by model:
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### CIA-A Port A Differences
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| Bit | Standard (A500/A2000/A1200/A4000) | A1000 | CDTV | CD32 |
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|---|---|---|---|---|
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| 7 | `/FIR1` — joystick 1 fire | Same | Same | **CD32 pad button** (via shift register) |
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| 6 | `/FIR0` — joystick 0 fire | Same | Same | **CD32 pad button** (via shift register) |
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| 5 | `/RDY` — floppy ready | Same | No internal floppy | No floppy |
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| 4 | `/TK0` — track 0 sensor | Same | No internal floppy | No floppy |
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| 3 | `/WPRO` — write protect | Same | No internal floppy | No floppy |
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| 2 | `/CHNG` — disk change | Same | No internal floppy | No floppy |
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| 1 | `/LED` — power LED | Same | Front panel LED | Front panel LED |
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| 0 | `/OVL` — Chip RAM overlay | Same | Same | Same |
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### CIA-A `/FLG` Pin
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| Model | `/FLG` Source |
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|---|---|
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| A500/A2000/A3000 | Directly accessible for parallel port `BUSY` or expansion |
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| A600/A1200 | **Gayle interrupt routing** — IDE and PCMCIA interrupts arrive here |
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| CDTV | **IR remote receiver** — IR data packets trigger `/FLG` |
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| CD32 | **Akiko interrupt routing** — CD-ROM and NVRAM events |
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### CIA-B Port A (Floppy Drive Selection)
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| Bit | Standard | CDTV | CD32 |
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|---|---|---|---|
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| 7 | `/MTR` — motor | N/A (no internal floppy) | N/A |
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| 6–3 | `/SEL3`–`/SEL0` — drive select | External floppy only (`/SEL0`) | N/A |
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| 2 | `/SIDE` — head side | N/A | N/A |
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| 1 | `/DIR` — step direction | N/A | N/A |
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| 0 | `/STEP` — step pulse | N/A | N/A |
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> [!NOTE]
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> On CDTV and CD32, the CIA-B floppy control bits are electrically disconnected from any drive hardware. Writing to them has no effect. If an external floppy is connected (CDTV with external drive, or CD32 with SX-1), only `/SEL0` and related signals are active.
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### CD32 Gamepad — CIA Shift Register Protocol
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The CD32 gamepad uses CIA-A's **Serial Data Register (SDR)** for button reads. The controller contains a shift register that is clocked via the joystick port pin 5:
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```asm
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; Read CD32 gamepad buttons
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; Returns 7 button bits in d0
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move.b #$FF, $BFE301 ; CIA-A DDRA: all outputs (temporarily)
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bset #6, $BFE001 ; Pin 5 high (clock start)
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bclr #6, $BFE001 ; Pin 5 low → latch button state
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; Clock in 7 bits via pin toggling
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moveq #6, d1
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.read_pad:
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bset #6, $BFE001 ; clock pulse high
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btst #0, $BFE001 ; read data bit
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bclr #6, $BFE001 ; clock pulse low
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roxl.b #1, d0 ; shift into result
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dbf d1, .read_pad
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```
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Standard 2-button Atari joysticks ignore the clock signal and remain fully compatible.
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---
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## References
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- MOS Technology 6526/8520 datasheet
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- ADCD 2.1 Hardware Manual — CIA chapter: http://amigadev.elowar.com/read/ADCD_2.1/Hardware_Manual_guide/
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- NDK39: `hardware/cia.h`, `resources/cia.h`
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- Autodocs: `cia` resource — http://amigadev.elowar.com/read/ADCD_2.1/Includes_and_Autodocs_3._guide/node00C7.html
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- See also: [Kickstart Boot Diagnostics](../../02_boot_sequence/kickstart-boot-diagnostics.md) — CIA-A LED blink pattern (coldCrash handler), overlay bit in PRA
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## See Also
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- [Video Signal & Timing](video_timing.md) — E-clock derivation from master crystal, CIA timer implications
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- [DMA Architecture](dma_architecture.md) — scanline slot allocation, bus arbitration
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