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@ -35,9 +35,9 @@ ULONG chip_free = AvailMem(MEMF_CHIP);
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ULONG chip_total = AvailMem(MEMF_CHIP | MEMF_TOTAL);
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```
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The exec memory list is built at boot time from the chip RAM size detected by the ROM initialisation code, which queries Agnus's internal address counter.
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The exec memory list is built at boot time from the chip RAM size detected by the ROM initialization code, which queries Agnus's internal address counter.
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## AmigaOS ROM Initialisation (Exec init)
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## AmigaOS ROM Initialization (Exec init)
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During cold boot, the Kickstart ROM probes Chip RAM size:
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@ -45,7 +45,7 @@ During cold boot, the Kickstart ROM probes Chip RAM size:
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2. Read back — if the value matches, 2 MB Chip RAM is present
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3. The exec `MemHeader` for Chip RAM is extended to $1FFFFF
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This is performed in the `RomBoot()` → `InitCode()` sequence before the exec memory system is fully initialised.
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This is performed in the `RomBoot()` → `InitCode()` sequence before the exec memory system is fully initialized.
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## Implications for Programming
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@ -48,10 +48,10 @@ lsr.w #8, d0 ; shift to get Agnus ID in low byte
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ECS Denise adds to OCS Denise (8362):
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1. **BPLCON3** — new control register for border colour, sprite bank
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1. **BPLCON3** — new control register for border color, sprite bank
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2. **Sub-pixel scrolling** — additional scroll control bits
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3. **Genlock extensions** — improved external sync handling
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4. **Border blank** — BPLCON3 can blank the border area to colour 0
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4. **Border blank** — BPLCON3 can blank the border area to color 0
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### DENISEID — Revision Register
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@ -74,10 +74,10 @@ move.w $DFF07C, d0 ; read DENISEID
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New register at `$DFF106` (ECS only, must not be written on OCS):
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```
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bit 15-13: BANK2-0 — sprite colour bank (AGA: upper 4 bits of colour reg)
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bit 12-10: PF2OF2-0 — playfield 2 colour offset (for dual playfield)
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bit 9: LOCT — low colour enable (AGA HAM8 mode)
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bit 6: BRDRBLNK — border blank: forces border area to colour 0
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bit 15-13: BANK2-0 — sprite color bank (AGA: upper 4 bits of color reg)
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bit 12-10: PF2OF2-0 — playfield 2 color offset (for dual playfield)
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bit 9: LOCT — low color enable (AGA HAM8 mode)
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bit 6: BRDRBLNK — border blank: forces border area to color 0
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bit 5: BRDNTRAN — border not-transparent (disable border transparency)
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bit 4: ZDCLKEN — horizontal/vertical count display
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bit 3: BRDSPRT — sprites in border area enable
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@ -15,7 +15,7 @@ bit 15: HARDDIS — disable hard limits on display window
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bit 14: LPENDIS — disable light pen latch
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bit 13: VARVBEN — enable variable VBlank
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bit 12: LOLDIS — disable long line sync
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bit 11: CSCBEN — composite sync on colour burst
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bit 11: CSCBEN — composite sync on color burst
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bit 10: VARVSYEN — variable vertical sync
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bit 9: VARHSYEN — variable horizontal sync
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bit 8: VARBEAMEN— variable beam enable
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@ -29,7 +29,7 @@ bit 1: HSYTRUE — horizontal sync polarity
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bit 0: MONCSYEN — monochrome composite sync enable
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```
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**Default OCS behaviour** is replicated by writing $0000 to BEAMCON0 on ECS.
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**Default OCS behavior** is replicated by writing $0000 to BEAMCON0 on ECS.
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**PAL/NTSC software switch:**
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```asm
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@ -12,7 +12,7 @@
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- **SCSI interface glue**: Works with the A3000's built-in WD33C93 SCSI controller
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- **ROM decode**: Maps Kickstart ROM into the address space
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Gary is not directly programmable by user software; its configuration is set by hardware strapping and the ROM initialisation sequence.
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Gary is not directly programmable by user software; its configuration is set by hardware strapping and the ROM initialization sequence.
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## Bus Arbitration
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@ -53,7 +53,7 @@ The A4000 does **not** use Gary — it uses a different system controller chip c
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- Commodore A3000 Technical Reference Manual
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- ADCD 2.1 — Hardware Manual, A3000 chapter
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- NDK39: hardware headers (community-documented Gary behaviour)
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- NDK39: hardware headers (community-documented Gary behavior)
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## See Also
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