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Ilia Sharin 2026-04-26 14:46:18 -04:00
parent 5fac29ccd5
commit 8133b3a6cb
90 changed files with 7794 additions and 705 deletions

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@ -35,9 +35,9 @@ ULONG chip_free = AvailMem(MEMF_CHIP);
ULONG chip_total = AvailMem(MEMF_CHIP | MEMF_TOTAL);
```
The exec memory list is built at boot time from the chip RAM size detected by the ROM initialisation code, which queries Agnus's internal address counter.
The exec memory list is built at boot time from the chip RAM size detected by the ROM initialization code, which queries Agnus's internal address counter.
## AmigaOS ROM Initialisation (Exec init)
## AmigaOS ROM Initialization (Exec init)
During cold boot, the Kickstart ROM probes Chip RAM size:
@ -45,7 +45,7 @@ During cold boot, the Kickstart ROM probes Chip RAM size:
2. Read back — if the value matches, 2 MB Chip RAM is present
3. The exec `MemHeader` for Chip RAM is extended to $1FFFFF
This is performed in the `RomBoot()``InitCode()` sequence before the exec memory system is fully initialised.
This is performed in the `RomBoot()``InitCode()` sequence before the exec memory system is fully initialized.
## Implications for Programming

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@ -48,10 +48,10 @@ lsr.w #8, d0 ; shift to get Agnus ID in low byte
ECS Denise adds to OCS Denise (8362):
1. **BPLCON3** — new control register for border colour, sprite bank
1. **BPLCON3** — new control register for border color, sprite bank
2. **Sub-pixel scrolling** — additional scroll control bits
3. **Genlock extensions** — improved external sync handling
4. **Border blank** — BPLCON3 can blank the border area to colour 0
4. **Border blank** — BPLCON3 can blank the border area to color 0
### DENISEID — Revision Register
@ -74,10 +74,10 @@ move.w $DFF07C, d0 ; read DENISEID
New register at `$DFF106` (ECS only, must not be written on OCS):
```
bit 15-13: BANK2-0 — sprite colour bank (AGA: upper 4 bits of colour reg)
bit 12-10: PF2OF2-0 — playfield 2 colour offset (for dual playfield)
bit 9: LOCT — low colour enable (AGA HAM8 mode)
bit 6: BRDRBLNK — border blank: forces border area to colour 0
bit 15-13: BANK2-0 — sprite color bank (AGA: upper 4 bits of color reg)
bit 12-10: PF2OF2-0 — playfield 2 color offset (for dual playfield)
bit 9: LOCT — low color enable (AGA HAM8 mode)
bit 6: BRDRBLNK — border blank: forces border area to color 0
bit 5: BRDNTRAN — border not-transparent (disable border transparency)
bit 4: ZDCLKEN — horizontal/vertical count display
bit 3: BRDSPRT — sprites in border area enable

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@ -15,7 +15,7 @@ bit 15: HARDDIS — disable hard limits on display window
bit 14: LPENDIS — disable light pen latch
bit 13: VARVBEN — enable variable VBlank
bit 12: LOLDIS — disable long line sync
bit 11: CSCBEN — composite sync on colour burst
bit 11: CSCBEN — composite sync on color burst
bit 10: VARVSYEN — variable vertical sync
bit 9: VARHSYEN — variable horizontal sync
bit 8: VARBEAMEN— variable beam enable
@ -29,7 +29,7 @@ bit 1: HSYTRUE — horizontal sync polarity
bit 0: MONCSYEN — monochrome composite sync enable
```
**Default OCS behaviour** is replicated by writing $0000 to BEAMCON0 on ECS.
**Default OCS behavior** is replicated by writing $0000 to BEAMCON0 on ECS.
**PAL/NTSC software switch:**
```asm

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@ -12,7 +12,7 @@
- **SCSI interface glue**: Works with the A3000's built-in WD33C93 SCSI controller
- **ROM decode**: Maps Kickstart ROM into the address space
Gary is not directly programmable by user software; its configuration is set by hardware strapping and the ROM initialisation sequence.
Gary is not directly programmable by user software; its configuration is set by hardware strapping and the ROM initialization sequence.
## Bus Arbitration
@ -53,7 +53,7 @@ The A4000 does **not** use Gary — it uses a different system controller chip c
- Commodore A3000 Technical Reference Manual
- ADCD 2.1 — Hardware Manual, A3000 chapter
- NDK39: hardware headers (community-documented Gary behaviour)
- NDK39: hardware headers (community-documented Gary behavior)
## See Also