More content added

01_hardware/README.md

@@ -10,9 +10,9 @@
 | Denise | 8362 | 8373 (ECS Denise) | Lisa |
 | Paula | 8364 | 8364 (unchanged) | 8364 (unchanged) |
 | Max Chip RAM | 512 KB–1 MB | 1–2 MB | 2 MB |
-| Colours (max normal) | 32 | 32 | 256 |
+| Colors (max normal) | 32 | 32 | 256 |
 | HAM | 12-bit HAM (6bpp) | 12-bit HAM | 24-bit HAM8 (8bpp) |
-| Sprites | 8 × 16px | 8 × 16px | 8 × 64px, 256 colours |
+| Sprites | 8 × 16px | 8 × 16px | 8 × 64px, 256 colors |
 | Blitter bus | 16-bit | 16-bit | 64-bit (FMODE) |
 | Display modes | NTSC/PAL | +Productivity, VGA | +Doublescan, 31kHz |
 | Machines | A500/A1000/A2000/**CDTV** | A600/A3000/A500+ | A1200/A4000/A4000T/**CD32** |
@@ -28,7 +28,7 @@ $DFF000  BLTDDAT   Blitter destination early read
 $DFF002  DMACONR   DMA control (read)
 $DFF004  VPOSR     Vertical position (read, high)
 ...
-$DFF180  COLOR00   Colour register 0
+$DFF180  COLOR00   Color register 0
 ...
 $DFF1FE  (last OCS/ECS register)
 $DFF1FC  BEAMCON0  (ECS+) beam control

01_hardware/aga_a1200_a4000/README.md

@@ -4,14 +4,14 @@
 
 ## Overview
 
-The **Advanced Graphics Architecture** (AGA) is the final custom chipset developed by Commodore, shipping from 1992. It dramatically expands colour depth, palette size, sprite capabilities, and blitter bandwidth while retaining full OCS/ECS backward compatibility.
+The **Advanced Graphics Architecture** (AGA) is the final custom chipset developed by Commodore, shipping from 1992. It dramatically expands color depth, palette size, sprite capabilities, and blitter bandwidth while retaining full OCS/ECS backward compatibility.
 
 ## Chip Summary
 
 | Chip | Name | Changes from ECS |
 |---|---|---|
 | **Alice** | MOS 8374 | Super Agnus successor: 64-bit bus, FMODE register |
-| **Lisa** | (unnamed MOS) | ECS Denise successor: 8-bit palette, 256 colours |
+| **Lisa** | (unnamed MOS) | ECS Denise successor: 8-bit palette, 256 colors |
 | **Paula** | MOS 8364 | Unchanged from OCS/ECS |
 
 ## Contents
@@ -20,8 +20,8 @@ The **Advanced Graphics Architecture** (AGA) is the final custom chipset develop
 |---|---|
 | [chipset_aga.md](chipset_aga.md) | Alice and Lisa internals, AGA architecture |
 | [aga_registers_delta.md](aga_registers_delta.md) | New/changed registers vs ECS |
-| [aga_palette.md](aga_palette.md) | 24-bit colour system, 256 registers |
-| [aga_display_modes.md](aga_display_modes.md) | HAM8, 256-colour, doublescan, VGA |
+| [aga_palette.md](aga_palette.md) | 24-bit color system, 256 registers |
+| [aga_display_modes.md](aga_display_modes.md) | HAM8, 256-color, doublescan, VGA |
 | [aga_blitter.md](aga_blitter.md) | 64-bit blitter bus, FMODE |
 | [aga_copper.md](aga_copper.md) | AGA Copper programming guide |
 | [cpu_030_040.md](cpu_030_040.md) | 68030/040 on A3000/A4000: cache, MMU, FPU |
@@ -32,11 +32,11 @@ The **Advanced Graphics Architecture** (AGA) is the final custom chipset develop
 
 | Feature | ECS | AGA |
 |---|---|---|
-| Colour registers | 32 (12-bit) | **256 (24-bit)** |
-| Max simultaneous colours | 64 EHB / HAM | **256** (or HAM8: 262,144) |
+| Color registers | 32 (12-bit) | **256 (24-bit)** |
+| Max simultaneous colors | 64 EHB / HAM | **256** (or HAM8: 262,144) |
 | Blitter bus | 16-bit | **64-bit** (FMODE) |
 | Sprite width | 16 px | **64 px** |
-| Sprite colours | 3+transparent | **15+transparent** (64-colour attached) |
+| Sprite colors | 3+transparent | **15+transparent** (64-color attached) |
 | Bitplane depth | 6 planes max | **8 planes** |
 | Palette select | 1 bank | **4 bitplane banks, 4 sprite banks** |
 

01_hardware/aga_a1200_a4000/aga_blitter.md

@@ -28,7 +28,7 @@ Think of it as a **hardware GPU for 2D raster operations** — years before PC g
 | No rotation | Cannot rotate — must be pre-rendered in software |
 | No 3D | No perspective, texture mapping, or Z-buffer |
 | No chunky pixels | Operates on **planar** bitplanes only (1 plane at a time) |
-| No colour blending | Pure Boolean logic — no alpha, no transparency gradients |
+| No color blending | Pure Boolean logic — no alpha, no transparency gradients |
 | Word-aligned width | Minimum operation width is 16 pixels (1 word) |
 
 ### How Software Uses It
@@ -70,7 +70,7 @@ move.w  #$0300, $DFF1FC    ; BLT_FMODE = 10 (64-bit)
 ```
 
 > [!IMPORTANT]
-> FMODE must be set **before** loading blitter registers and starting the blit. Changing FMODE mid-blit causes undefined behaviour.
+> FMODE must be set **before** loading blitter registers and starting the blit. Changing FMODE mid-blit causes undefined behavior.
 
 ## Width Calculation with FMODE
 

01_hardware/aga_a1200_a4000/aga_copper.md

@@ -4,13 +4,13 @@
 
 ## What Is the Copper?
 
-The **Copper** (Co-Processor) is one of the most distinctive pieces of hardware in any computer ever built. It is a tiny, ultra-simple programmable DMA engine that executes a program — called a **copper list** — in perfect synchronisation with the video beam as it sweeps across the screen.
+The **Copper** (Co-Processor) is one of the most distinctive pieces of hardware in any computer ever built. It is a tiny, ultra-simple programmable DMA engine that executes a program — called a **copper list** — in perfect synchronization with the video beam as it sweeps across the screen.
 
 The Copper watches the beam position and can **write any value to any custom chip register at any specific screen position**. This single capability enables an astonishing range of visual effects.
 
 ### Why Does It Matter?
 
-On a conventional computer, changing display parameters (colours, scroll positions, resolutions) requires the CPU to execute code at precisely the right moment. This is fragile, wastes CPU time, and is limited by interrupt latency.
+On a conventional computer, changing display parameters (colors, scroll positions, resolutions) requires the CPU to execute code at precisely the right moment. This is fragile, wastes CPU time, and is limited by interrupt latency.
 
 The Copper does this **automatically, for free, with perfect timing** — every single frame, without any CPU involvement at all.
 
@@ -50,20 +50,20 @@ The Copper does this **automatically, for free, with perfect timing** — every
 │        │                  │                        │                │
 │  ┌─────┴──────────────────┴────────────────────────┴─────────┐      │
 │  │              BEAM COUNTER (V count, H count)              │      │
-│  │    Increments every colour clock, resets each frame       │      │
+│  │    Increments every color clock, resets each frame        │      │
 │  │    PAL: 312 lines × 227 clocks   NTSC: 262 × 227          │      │
 │  └───────────────────────────────────────────────────────────┘      │
-└──────────┬─────────────────────────────────────────────────────────┘
+└──────────┬──────────────────────────────────────────────────────────┘
            │ register writes ($DFF000–$DFF1FE)
            ▼
 ┌─────────────────────────────────────────────────────────────────────┐
 │                    DENISE / LISA  (Video Encoder)                   │
 │                                                                     │
-│  Receives bitplane data + sprite data + colour register values      │
+│  Receives bitplane data + sprite data + color register values       │
 │  Composites them into a final pixel stream:                         │
 │                                                                     │
 │  ┌────────────┐  ┌──────────┐  ┌──────────┐  ┌──────────────────┐   │
-│  │ Bitplane   │  │ Sprite   │  │ Colour   │  │ Playfield        │   │
+│  │ Bitplane   │  │ Sprite   │  │ Color    │  │ Playfield        │   │
 │  │ Decode     │→ │ Priority │→ │ Palette  │→ │ Priority &       │   │
 │  │ (planar→   │  │ Merge    │  │ Lookup   │  │ Genlock Control  │   │
 │  │  index)    │  │          │  │ (32/256) │  │                  │   │
@@ -90,10 +90,10 @@ The Copper does this **automatically, for free, with perfect timing** — every
 ### Component Interactions
 
 **Copper ↔ Chip RAM:**
-The Copper fetches its program (the copper list) from Chip RAM via DMA. It reads one instruction (2 words = 4 bytes) every 4 colour clocks. The copper list **must** reside in Chip RAM — it cannot be in Fast RAM because only Chip RAM is DMA-accessible.
+The Copper fetches its program (the copper list) from Chip RAM via DMA. It reads one instruction (2 words = 4 bytes) every 4 color clocks. The copper list **must** reside in Chip RAM — it cannot be in Fast RAM because only Chip RAM is DMA-accessible.
 
 **Copper ↔ Custom Registers:**
-When the Copper executes a MOVE instruction, it writes directly to a custom chip register (`$DFF000`–`$DFF1FE`). This is the exact same register space the CPU writes to. The Copper can set colours, bitplane pointers, sprite pointers, display window, scroll offsets, DMA control, and audio parameters.
+When the Copper executes a MOVE instruction, it writes directly to a custom chip register (`$DFF000`–`$DFF1FE`). This is the exact same register space the CPU writes to. The Copper can set colors, bitplane pointers, sprite pointers, display window, scroll offsets, DMA control, and audio parameters.
 
 **Copper ↔ Beam Counter:**
 The Copper continuously compares the current beam position (V count, H count) against WAIT instructions. When the beam reaches or passes the specified position, execution continues. This is a hardware comparator — no polling loop, no interrupt latency.
@@ -117,12 +117,12 @@ A WAIT instruction with bit 15 of the mask word cleared becomes a "blitter-finis
 
 | Effect | How | Used In |
 |---|---|---|
-| **Per-line colour changes** | WAIT for line, MOVE colour register | Gradient skies, rainbow bars |
+| **Per-line color changes** | WAIT for line, MOVE color register | Gradient skies, rainbow bars |
 | **Split screens** | Change bitplane pointers mid-frame | Status bar + scrolling playfield |
 | **Parallax scrolling** | Change BPLCON1 (scroll offset) at different lines | Multi-layer side-scrollers |
 | **Resolution changes** | Change BPLCON0 mid-frame | HiRes menu + LoRes game area |
 | **Sprite multiplexing** | Repoint sprite DMA pointers after sprite finishes | More than 8 sprites per frame |
-| **Palette animation** | Modify colour registers each frame | Cycling colours, water shimmer |
+| **Palette animation** | Modify color registers each frame | Cycling colors, water shimmer |
 | **Display window tricks** | Change DIWSTRT/DIWSTOP | Overscan, letterbox |
 | **Interlace tricks** | Toggle LOF bit | Custom interlace effects |
 
@@ -134,7 +134,7 @@ A WAIT instruction with bit 15 of the mask word cleared becomes a "blitter-finis
 | No memory read | Can only WRITE to registers, never read |
 | Write-only to custom regs | Cannot write to CPU memory, CIA, or Fast RAM |
 | Limited register set | Protected registers ($000–$03E) need `COPCON` unlock |
-| No sub-pixel timing | Horizontal resolution is 4 colour clocks (~8 low-res pixels) |
+| No sub-pixel timing | Horizontal resolution is 4 color clocks (~8 low-res pixels) |
 | Vertical wrapping | V counter wraps at 255; PAL lines 256+ need two WAITs |
 
 ---
@@ -191,7 +191,7 @@ Example: Skip next if beam is past line 200:
 
 ## Your First Copper List
 
-Here's the simplest possible copper list — it changes the background colour at line 128:
+Here's the simplest possible copper list — it changes the background color at line 128:
 
 ```asm
     SECTION copperlist,DATA_C    ; *** MUST be in Chip RAM! ***
@@ -220,7 +220,7 @@ To activate it:
 
 ---
 
-## Rainbow Gradient (Colour Per Scanline)
+## Rainbow Gradient (Color Per Scanline)
 
 ```asm
 RainbowCopper:
@@ -242,7 +242,7 @@ RainbowCopper:
     dc.w    $FFFF,$FFFE
 ```
 
-This produces a smooth colour gradient down the screen — **zero CPU cost**.
+This produces a smooth color gradient down the screen — **zero CPU cost**.
 
 ---
 
@@ -325,23 +325,23 @@ AGA (Alice chip) keeps the same 3-instruction Copper but gains access to the **e
 
 | AGA Feature | Copper Can Set |
 |---|---|
-| 256-colour palette | `COLOR00–COLOR255` via BPLCON3 bank select |
-| Extended sprites | 64-colour sprites via palette banks |
+| 256-color palette | `COLOR00–COLOR255` via BPLCON3 bank select |
+| Extended sprites | 64-color sprites via palette banks |
 | FMODE | DMA fetch width (but careful — affects in-progress DMA) |
 | BPLCON3/BPLCON4 | AGA-specific bitplane/sprite control |
 
 ### AGA Palette via Copper
 
-AGA has 256 colours but still only 32 colour registers visible at a time. To load all 256 colours, the Copper uses BPLCON3 to select palette banks:
+AGA has 256 colors but still only 32 color registers visible at a time. To load all 256 colors, the Copper uses BPLCON3 to select palette banks:
 
 ```asm
-    ; Load colours 0–31 (bank 0)
+    ; Load colors 0–31 (bank 0)
     dc.w    $0106,$0000         ; BPLCON3: bank 0
     dc.w    $0180,$0000         ; COLOR00
     dc.w    $0182,$0111         ; COLOR01
-    ; ... all 32 colours ...
-
-    ; Switch to bank 1 (colours 32–63)
+    ; ... all 32 colors ...
+    
+    ; Switch to bank 1 (colors 32–63)
     dc.w    $0106,$2000         ; BPLCON3: bank 1
     dc.w    $0180,$0222         ; COLOR32
     dc.w    $0182,$0333         ; COLOR33
@@ -354,9 +354,9 @@ AGA has 256 colours but still only 32 colour registers visible at a time. To loa
 
 | Parameter | Value |
 |---|---|
-| Instruction time | 4 colour clocks (= 8 lo-res pixels = ~1.12 µs) |
+| Instruction time | 4 color clocks (= 8 lo-res pixels = ~1.12 µs) |
 | Max instructions per line | ~112 (NTSC) / ~114 (PAL) |
-| Horizontal resolution | 4 colour clocks (~8 lo-res pixels) |
+| Horizontal resolution | 4 color clocks (~8 lo-res pixels) |
 | Vertical range | 0–255 (wraps; use double-WAIT for PAL lines 256+) |
 | PAL visible lines | 44–300 (256 visible) |
 | NTSC visible lines | 44–244 (200 visible) |

01_hardware/aga_a1200_a4000/aga_display_modes.md

@@ -36,7 +36,7 @@ Mode flags (lower 16 bits):
 
 ## Standard AGA Modes
 
-| Mode ID | Resolution | Colours | H rate |
+| Mode ID | Resolution | Colors | H rate |
 |---|---|---|---|
 | `PAL_MONITOR_ID \| LORES_KEY` | 320×256 | 256 | 15.6 kHz |
 | `PAL_MONITOR_ID \| HIRES_KEY` | 640×256 | 256 | 15.6 kHz |
@@ -55,13 +55,13 @@ Mode flags (lower 16 bits):
 
 struct Screen *scr;
 
-/* 256-colour AGA screen, PAL, 320×256 */
+/* 256-color AGA screen, PAL, 320×256 */
 scr = OpenScreenTags(NULL,
     SA_DisplayID,  PAL_MONITOR_ID | LORES_KEY,
     SA_Width,      320,
     SA_Height,     256,
-    SA_Depth,      8,           /* 8 bitplanes = 256 colours */
-    SA_Colors32,   (ULONG)colour_table,  /* LoadRGB32 format */
+    SA_Depth,      8,           /* 8 bitplanes = 256 colors */
+    SA_Colors32,   (ULONG)color_table,  /* LoadRGB32 format */
     SA_Title,      (ULONG)"My AGA Screen",
     SA_Quiet,      TRUE,
     TAG_DONE);
@@ -79,7 +79,7 @@ scr = OpenScreenTags(NULL,
 ```
 
 > [!NOTE]
-> HAM8 screens require 8 bitplanes. The display system automatically programmes BPLCON0 with HAM=1. The first 64 colour registers are used as the HAM8 index palette.
+> HAM8 screens require 8 bitplanes. The display system automatically programmes BPLCON0 with HAM=1. The first 64 color registers are used as the HAM8 index palette.
 
 ## BestModeID() — Querying Available Modes
 

01_hardware/aga_a1200_a4000/aga_palette.md

@@ -1,12 +1,12 @@
 [← Home](../../README.md) · [Hardware](../README.md) · [AGA](README.md)
 
-# AGA Palette & Colour System
+# AGA Palette & Color System
 
 ## Overview
 
-AGA provides **256 colour registers** (COLOR00–COLOR255), each **24-bit RGB** (8 bits per channel). This replaces OCS/ECS's 32 registers with 12-bit colour.
+AGA provides **256 color registers** (COLOR00–COLOR255), each **24-bit RGB** (8 bits per channel). This replaces OCS/ECS's 32 registers with 12-bit color.
 
-## Colour Register Layout
+## Color Register Layout
 
 ```
 ADDRESS:  $DFF180 + (n × 2)    for register n (0–255)
@@ -18,11 +18,11 @@ $DFF180–$DFF1BE  COLOR00–COLOR31   (same addresses as OCS/ECS)
 $DFF180–$DFF3BE  COLOR00–COLOR255  (full AGA range — needs BPLCON4 bank select)
 ```
 
-The 256 colour registers are accessed in 64-register **banks** selected by `BPLCON4`.
+The 256 color registers are accessed in 64-register **banks** selected by `BPLCON4`.
 
-## Writing 24-bit Colours
+## Writing 24-bit Colors
 
-Each colour register holds 12 bits directly (OCS/ECS compatible). The upper 12 bits (the "low nibble") are written via a second access with `LOCT` set in BPLCON3.
+Each color register holds 12 bits directly (OCS/ECS compatible). The upper 12 bits (the "low nibble") are written via a second access with `LOCT` set in BPLCON3.
 
 ### Manual 24-bit write sequence:
 
@@ -52,7 +52,7 @@ The preferred OS call:
 
 /* Table: count, index, then 0x00RRGGBB values, terminated by ~0 */
 ULONG table[] = {
-    4, 0,             /* 4 colours starting at index 0 */
+    4, 0,             /* 4 colors starting at index 0 */
     0x00FF0000,       /* COLOR00: red   */
     0x0000FF00,       /* COLOR01: green */
     0x000000FF,       /* COLOR02: blue  */
@@ -62,13 +62,13 @@ ULONG table[] = {
 LoadRGB32(viewport, table);
 ```
 
-`LoadRGB32()` (graphics.library LVO -$192) is the AGA-correct way to set colours. It handles the two-write LOCT protocol internally and is available from OS 3.0+.
+`LoadRGB32()` (graphics.library LVO -$192) is the AGA-correct way to set colors. It handles the two-write LOCT protocol internally and is available from OS 3.0+.
 
 ### Using LoadRGB4() — OCS/ECS compatible (12-bit)
 
 ```c
-UWORD colours[32] = { 0x000, 0xF00, 0x0F0, ... };
-LoadRGB4(viewport, colours, 32);  /* sets 32 colours from 12-bit table */
+UWORD colors[32] = { 0x000, 0xF00, 0x0F0, ... };
+LoadRGB4(viewport, colors, 32);  /* sets 32 colors from 12-bit table */
 ```
 
 `LoadRGB4()` is safe on all chipsets but only provides 12-bit precision on AGA.
@@ -82,9 +82,9 @@ HAM8 is the AGA extension of OCS's HAM6. It uses 8 bitplanes:
   - `01` = modify blue channel
   - `10` = modify red channel
   - `11` = modify green channel
-- **Bits 5-0**: 6-bit value for the selected channel (or 6-bit colour index)
+- **Bits 5-0**: 6-bit value for the selected channel (or 6-bit color index)
 
-Result: 2^18 = **262,144 simultaneous colours** from adjacent-pixel modification.
+Result: 2^18 = **262,144 simultaneous colors** from adjacent-pixel modification.
 
 Enabling HAM8:
 ```asm
@@ -92,19 +92,19 @@ Enabling HAM8:
 move.w  #$9811, BPLCON0+custom
 ```
 
-## Colour Modes Summary
+## Color Modes Summary
 
-| Mode | Planes | Colours | Method |
+| Mode | Planes | Colors | Method |
 |---|---|---|---|
 | Standard | 1–8 | 2–256 | Direct palette lookup |
 | EHB | 6 | 64 | Extra Half-Brite (OCS/ECS compat) |
 | HAM6 | 6 | 4096 | Hold-and-modify 4-bit channels |
 | HAM8 | 8 | 262,144 | Hold-and-modify 6-bit channels |
-| Dual Playfield | 3+3 | 8+8 | Two independent 8-colour layers |
+| Dual Playfield | 3+3 | 8+8 | Two independent 8-color layers |
 
-## Colour Bank Selection (BPLCON4)
+## Color Bank Selection (BPLCON4)
 
-The 256 colour registers are split into 4 banks of 64:
+The 256 color registers are split into 4 banks of 64:
 
 | BPLAM | Bank | Registers |
 |---|---|---|
@@ -113,15 +113,15 @@ The 256 colour registers are split into 4 banks of 64:
 | $80 | 2 | COLOR128–COLOR191 |
 | $C0 | 3 | COLOR192–COLOR255 |
 
-Dual playfield can use BPLCON4 to give each playfield a different 64-colour bank.
+Dual playfield can use BPLCON4 to give each playfield a different 64-color bank.
 
-## OS Colour Management
+## OS Color Management
 
 `graphics.library` manages palette via the `ColorMap` structure attached to a `ViewPort`:
 
 ```c
 struct ColorMap *cm = GetColorMap(256);     /* allocate 256-entry AGA map */
-SetRGB32(vp, n, r, g, b);                  /* set one colour (24-bit each) */
+SetRGB32(vp, n, r, g, b);                  /* set one color (24-bit each) */
 LoadRGB32(vp, table);                       /* bulk load */
 FreeColorMap(cm);
 ```
@@ -131,4 +131,4 @@ FreeColorMap(cm);
 - NDK39: `graphics/view.h` — ColorMap, LoadRGB32
 - ADCD 2.1 Autodocs: graphics — LoadRGB32, SetRGB32
 - http://amigadev.elowar.com/read/ADCD_2.1/Libraries_Manual_guide/node02B4.html
-- AmigaMail Vol. 2 — AGA colour system articles
+- AmigaMail Vol. 2 — AGA color system articles

01_hardware/aga_a1200_a4000/aga_registers_delta.md

@@ -10,16 +10,16 @@ DMA fetch mode — see [chipset_aga.md](chipset_aga.md) for full description.
 
 ### BPLCON4 — $DFF10C (AGA only)
 
-Bitplane and sprite colour bank selection:
+Bitplane and sprite color bank selection:
 
 ```
-bits 15-8:  BPLAM7-0  — Bitplane XOR pattern (AGA colour bank XOR)
-bits  7-4:  ESPRM7-4  — Even sprite colour bank (bits 7:4 of colour reg index)
-bits  3-0:  OSPRM7-4  — Odd sprite colour bank
+bits 15-8:  BPLAM7-0  — Bitplane XOR pattern (AGA color bank XOR)
+bits  7-4:  ESPRM7-4  — Even sprite color bank (bits 7:4 of color reg index)
+bits  3-0:  OSPRM7-4  — Odd sprite color bank
 ```
 
 **Bitplane bank select via BPLAM:**
-- BPLAM provides an XOR mask applied to the 8-bit colour index before palette lookup
+- BPLAM provides an XOR mask applied to the 8-bit color index before palette lookup
 - BPLAM = $00 → use COLOR00–COLOR63 (bank 0)
 - BPLAM = $40 → use COLOR64–COLOR127 (bank 1)
 - BPLAM = $80 → use COLOR128–COLOR191 (bank 2)
@@ -27,14 +27,14 @@ bits  3-0:  OSPRM7-4  — Odd sprite colour bank
 
 ### COLOR00–COLOR255 — $DFF180–$DFF3BE (AGA)
 
-AGA extends the colour table from 32 registers (OCS/ECS) to **256 registers**.
+AGA extends the color table from 32 registers (OCS/ECS) to **256 registers**.
 
-Each AGA colour register is 32 bits (accessed as two word writes via BPLCON3 latch):
+Each AGA color register is 32 bits (accessed as two word writes via BPLCON3 latch):
 
 ```asm
-; Write 24-bit colour to COLOR00:
+; Write 24-bit color to COLOR00:
 ; First write sets high nibble, second sets low nibble
-move.w  #$0000, BPLCON3+custom      ; set LACE=0, select low colour word
+move.w  #$0000, BPLCON3+custom      ; set LACE=0, select low color word
 move.w  #$0FFF, COLOR00+custom      ; write $RGB (high 12 bits)
 bset    #9, BPLCON3_shadow           ; set LOCT (low nibble enable)
 move.w  #$0FFF, COLOR00+custom      ; write low nibble of each channel
@@ -47,7 +47,7 @@ The standard `LoadRGB32()` and `LoadRGB4()` graphics library calls manage this t
 ### BPLCON2 — $DFF104 (AGA extended)
 
 ```
-bits 14-9:  KILLEHB  — kill EHB mode (AGA replaces EHB with 256 colour)
+bits 14-9:  KILLEHB  — kill EHB mode (AGA replaces EHB with 256 color)
 bit    6:   RDRAM    — read bitplane data from RAM (not registered in Lisa)
 bits   5-3: PF2PRI   — playfield 2 priority
 bits   2-0: PF1PRI   — playfield 1 priority + sprite priority
@@ -57,7 +57,7 @@ bits   2-0: PF1PRI   — playfield 1 priority + sprite priority
 
 Additional AGA bits:
 ```
-bit 9:    LOCT  — low colour write enable (for 24-bit colour access)
+bit 9:    LOCT  — low color write enable (for 24-bit color access)
 bit 3:    BRDSPRT — sprites visible in border
 ```
 
@@ -65,28 +65,28 @@ bit 3:    BRDSPRT — sprites visible in border
 
 See [chipset_aga.md](chipset_aga.md) — bit 4 is the MSB of the bitplane count for 7/8-plane modes.
 
-## Colour Register Access — Low Nibble Protocol
+## Color Register Access — Low Nibble Protocol
 
-Writing 24-bit colour to AGA registers requires two steps per colour:
+Writing 24-bit color to AGA registers requires two steps per color:
 
 1. **Write high nibble** (standard): `COLOR00 = $0RGB` (bits [11:0] = R[3:0], G[3:0], B[3:0])
 2. **Set LOCT** in BPLCON3 (bit 9)
 3. **Write low nibble**: `COLOR00 = $0rgb` (bits [11:0] = R[3:0], G[3:0], B[3:0], these are the low 4 bits)
 
-This two-write sequence gives 8 bits per channel (R[7:0], G[7:0], B[7:0]) = 24-bit colour.
+This two-write sequence gives 8 bits per channel (R[7:0], G[7:0], B[7:0]) = 24-bit color.
 
 `LoadRGB32()` does this automatically:
 ```c
-/* AGA 32-bit colour table format:
-   Count, then pairs: [colour_index, 0x00RRGGBB] */
-ULONG colour_table[] = {
-    32,   0,         /* 32 colours starting at index 0 */
+/* AGA 32-bit color table format:
+   Count, then pairs: [color_index, 0x00RRGGBB] */
+ULONG color_table[] = {
+    32,   0,         /* 32 colors starting at index 0 */
     0x00FF0000,      /* COLOR00 = red */
     0x0000FF00,      /* COLOR01 = green */
     /* ... */
     ~0UL             /* terminator */
 };
-LoadRGB32(vp, colour_table);
+LoadRGB32(vp, color_table);
 ```
 
 ## References
@@ -94,4 +94,4 @@ LoadRGB32(vp, colour_table);
 - ADCD 2.1 Hardware Manual — AGA register appendix
 - NDK39: `hardware/custom.h`, `graphics/view.h`
 - Commodore A1200/A4000 Technical Reference Manuals
-- AmigaMail Vol. 2 — AGA colour programming
+- AmigaMail Vol. 2 — AGA color programming

01_hardware/aga_a1200_a4000/akiko_cd32.md

@@ -98,7 +98,7 @@ Output: 8 longwords of planar data  (1 longword per bitplane × 8 planes)
     move.l  (a1), (a2)+         ; bitplane 7
 ```
 
-#### Optimised Loop (MOVEM)
+#### Optimized Loop (MOVEM)
 
 In practice, the entire 32-pixel conversion is done with two MOVEM instructions:
 
@@ -119,7 +119,7 @@ In practice, the entire 32-pixel conversion is done with two MOVEM instructions:
 
 #### Full-Screen Conversion Example
 
-For a 320×256 screen at 8 bitplanes (256 colours):
+For a 320×256 screen at 8 bitplanes (256 colors):
 
 ```asm
 ; Total pixels = 320 × 256 = 81,920
@@ -203,9 +203,9 @@ Communication with the drive is command/response based through the Akiko registe
 
 The CD32 boots exclusively from CD-ROM (no floppy drive). The boot sequence:
 
-1. Kickstart 3.1 initialises from ROM (`$F80000`)
+1. Kickstart 3.1 initializes from ROM (`$F80000`)
 2. Extended ROM at `$E00000` provides `cd.device` and the CD filesystem
-3. Akiko initialises the CD-ROM drive
+3. Akiko initializes the CD-ROM drive
 4. The system reads the TOC and looks for a boot block (Amiga executable format)
 5. If found, the boot executable is loaded and run — this is the game/application entry point
 

01_hardware/aga_a1200_a4000/chipset_aga.md

@@ -12,10 +12,10 @@ Alice is the successor to Super Agnus and is the DMA controller and Copper/Blitt
 Alice can fetch 2 or 4 words per DMA cycle via the `FMODE` register ($DFF1FC). This dramatically increases the bandwidth available to the blitter and bitplane DMA.
 
 **Extended bitplane depth:**
-Alice supports up to **8 bitplanes** (256 colours), compared to OCS/ECS's 6-plane limit.
+Alice supports up to **8 bitplanes** (256 colors), compared to OCS/ECS's 6-plane limit.
 
 **BPLCON4:**
-Alice adds `BPLCON4` to control bitplane bank selection — which 64-entry block of the 256-entry colour table is used by the bitplanes.
+Alice adds `BPLCON4` to control bitplane bank selection — which 64-entry block of the 256-entry color table is used by the bitplanes.
 
 ### ALICE_ID
 
@@ -34,18 +34,18 @@ lsr.w   #8, d0
 
 ## Lisa (AGA Denise)
 
-Lisa is the display chip successor to ECS Denise, providing 8-bit colour output (256 colour registers) and extended sprite capabilities.
+Lisa is the display chip successor to ECS Denise, providing 8-bit color output (256 color registers) and extended sprite capabilities.
 
 ### Key Enhancements over ECS Denise
 
-**256 colour registers:**
+**256 color registers:**
 Lisa provides COLOR00–COLOR255, each 24-bit (32-bit register with low byte unused).
 
-**4 colour banks for bitplanes:**
-`BPLCON4` selects which 64-register bank (0–3) the bitplanes use for lookup. This allows dual-playfield each using a different 64-colour palette.
+**4 color banks for bitplanes:**
+`BPLCON4` selects which 64-register bank (0–3) the bitplanes use for lookup. This allows dual-playfield each using a different 64-color palette.
 
 **Sprite bank selection:**
-`BPLCON3` bits select which colour bank sprite pairs use.
+`BPLCON3` bits select which color bank sprite pairs use.
 
 **Extended sprite width:**
 Sprites can be 16 or 64 pixels wide in AGA mode.
@@ -105,7 +105,7 @@ bits 14-12: BPU2-0 — lower 3 bits of bitplane count
 bit   4:    BPU3   — MSB of bitplane count (AGA: allows 7, 8 planes)
 ```
 
-To use 8 bitplanes (256 colours):
+To use 8 bitplanes (256 colors):
 ```asm
 move.w  #$9411, BPLCON0+custom  ; HIRES=1 (if needed), BPU=8 (BPU3=1, BPU2-0=000), ECSENA=1
 ```
@@ -123,4 +123,4 @@ move.w  #$9411, BPLCON0+custom  ; HIRES=1 (if needed), BPU=8 (BPU3=1, BPU2-0=000
 
 - [Akiko — CD32 Custom Chip](akiko_cd32.md) — CD32-exclusive ASIC (C2P, CD-ROM, NVRAM) that sits alongside Alice/Lisa/Paula
 - [AGA Blitter](aga_blitter.md) — 64-bit FMODE blitter details
-- [AGA Palette](aga_palette.md) — 256-register 24-bit colour system
+- [AGA Palette](aga_palette.md) — 256-register 24-bit color system

01_hardware/common/memory_types.md

@@ -304,7 +304,7 @@ When no Fast RAM is available, everything competes for the same 512 KB–2 MB:
 ```c
 if (!hasFastRAM) {
     /* All memory is Chip RAM — conserve aggressively */
-    numBitplanes = 4;               /* Use 16 colours instead of 32 */
+    numBitplanes = 4;               /* Use 16 colors instead of 32 */
     useDoubleBuffer = FALSE;        /* Single buffer saves 40 KB per plane */
     maxBOBs = 8;                    /* Fewer sprites = less Blitter work */
     musicQuality = QUALITY_LOW;     /* 4-bit 11 kHz samples save Chip RAM */
@@ -312,7 +312,7 @@ if (!hasFastRAM) {
 }
 ```
 
-**Why**: On a Chip-only system, the CPU, Blitter, display, and audio all share one bus. Reducing display complexity (fewer bitplanes) frees DMA slots for the Blitter AND frees Chip RAM for audio/game data. This is why many A500 games use 4 bitplanes (16 colours) while the same game on an accelerated A1200 uses 5 or even 8.
+**Why**: On a Chip-only system, the CPU, Blitter, display, and audio all share one bus. Reducing display complexity (fewer bitplanes) frees DMA slots for the Blitter AND frees Chip RAM for audio/game data. This is why many A500 games use 4 bitplanes (16 colors) while the same game on an accelerated A1200 uses 5 or even 8.
 
 ### Strategy: Chip + Fast RAM Mode (Accelerated Systems)
 
@@ -321,7 +321,7 @@ When Fast RAM is available, the architecture unlocks true parallelism:
 ```c
 if (hasFastRAM) {
     /* CPU runs from Fast RAM at full speed; Chip RAM for DMA only */
-    numBitplanes = 5;                /* 32 colours — display looks better */
+    numBitplanes = 5;                /* 32 colors — display looks better */
     useDoubleBuffer = TRUE;          /* Flicker-free, worth the Chip RAM */
     maxBOBs = 24;                    /* More BOBs — CPU can compute while Blitter blits */
     musicQuality = QUALITY_HIGH;     /* 8-bit 22 kHz — Chip RAM freed by code in Fast RAM */

01_hardware/ecs_a600_a3000/chip_ram_expansion.md

@@ -35,9 +35,9 @@ ULONG chip_free  = AvailMem(MEMF_CHIP);
 ULONG chip_total = AvailMem(MEMF_CHIP | MEMF_TOTAL);
 ```
 
-The exec memory list is built at boot time from the chip RAM size detected by the ROM initialisation code, which queries Agnus's internal address counter.
+The exec memory list is built at boot time from the chip RAM size detected by the ROM initialization code, which queries Agnus's internal address counter.
 
-## AmigaOS ROM Initialisation (Exec init)
+## AmigaOS ROM Initialization (Exec init)
 
 During cold boot, the Kickstart ROM probes Chip RAM size:
 
@@ -45,7 +45,7 @@ During cold boot, the Kickstart ROM probes Chip RAM size:
 2. Read back — if the value matches, 2 MB Chip RAM is present
 3. The exec `MemHeader` for Chip RAM is extended to $1FFFFF
 
-This is performed in the `RomBoot()` → `InitCode()` sequence before the exec memory system is fully initialised.
+This is performed in the `RomBoot()` → `InitCode()` sequence before the exec memory system is fully initialized.
 
 ## Implications for Programming
 

01_hardware/ecs_a600_a3000/chipset_ecs.md

@@ -48,10 +48,10 @@ lsr.w   #8, d0              ; shift to get Agnus ID in low byte
 
 ECS Denise adds to OCS Denise (8362):
 
-1. **BPLCON3** — new control register for border colour, sprite bank
+1. **BPLCON3** — new control register for border color, sprite bank
 2. **Sub-pixel scrolling** — additional scroll control bits
 3. **Genlock extensions** — improved external sync handling
-4. **Border blank** — BPLCON3 can blank the border area to colour 0
+4. **Border blank** — BPLCON3 can blank the border area to color 0
 
 ### DENISEID — Revision Register
 
@@ -74,10 +74,10 @@ move.w  $DFF07C, d0   ; read DENISEID
 New register at `$DFF106` (ECS only, must not be written on OCS):
 
 ```
-bit 15-13: BANK2-0    — sprite colour bank (AGA: upper 4 bits of colour reg)
-bit 12-10: PF2OF2-0   — playfield 2 colour offset (for dual playfield)
-bit  9:    LOCT       — low colour enable (AGA HAM8 mode)
-bit  6:    BRDRBLNK   — border blank: forces border area to colour 0
+bit 15-13: BANK2-0    — sprite color bank (AGA: upper 4 bits of color reg)
+bit 12-10: PF2OF2-0   — playfield 2 color offset (for dual playfield)
+bit  9:    LOCT       — low color enable (AGA HAM8 mode)
+bit  6:    BRDRBLNK   — border blank: forces border area to color 0
 bit  5:    BRDNTRAN   — border not-transparent (disable border transparency)
 bit  4:    ZDCLKEN     — horizontal/vertical count display
 bit  3:    BRDSPRT    — sprites in border area enable

01_hardware/ecs_a600_a3000/ecs_registers_delta.md

@@ -15,7 +15,7 @@ bit 15: HARDDIS  — disable hard limits on display window
 bit 14: LPENDIS  — disable light pen latch
 bit 13: VARVBEN  — enable variable VBlank
 bit 12: LOLDIS   — disable long line sync
-bit 11: CSCBEN   — composite sync on colour burst
+bit 11: CSCBEN   — composite sync on color burst
 bit 10: VARVSYEN — variable vertical sync
 bit  9: VARHSYEN — variable horizontal sync
 bit  8: VARBEAMEN— variable beam enable
@@ -29,7 +29,7 @@ bit  1: HSYTRUE  — horizontal sync polarity
 bit  0: MONCSYEN — monochrome composite sync enable
 ```
 
-**Default OCS behaviour** is replicated by writing $0000 to BEAMCON0 on ECS.
+**Default OCS behavior** is replicated by writing $0000 to BEAMCON0 on ECS.
 
 **PAL/NTSC software switch:**
 ```asm

01_hardware/ecs_a600_a3000/gary_system_controller.md

@@ -12,7 +12,7 @@
 - **SCSI interface glue**: Works with the A3000's built-in WD33C93 SCSI controller
 - **ROM decode**: Maps Kickstart ROM into the address space
 
-Gary is not directly programmable by user software; its configuration is set by hardware strapping and the ROM initialisation sequence.
+Gary is not directly programmable by user software; its configuration is set by hardware strapping and the ROM initialization sequence.
 
 ## Bus Arbitration
 
@@ -53,7 +53,7 @@ The A4000 does **not** use Gary — it uses a different system controller chip c
 
 - Commodore A3000 Technical Reference Manual
 - ADCD 2.1 — Hardware Manual, A3000 chapter
-- NDK39: hardware headers (community-documented Gary behaviour)
+- NDK39: hardware headers (community-documented Gary behavior)
 
 ## See Also
 

01_hardware/ocs_a500/README.md

@@ -11,7 +11,7 @@ The **Original Chip Set** (OCS) ships in the Amiga 1000 (1985), A500 (1987), and
 | Chip | MOS Part | Primary Responsibilities |
 |---|---|---|
 | **Agnus** | 8361 (PAL), 8367 (NTSC) | DMA controller, Copper coprocessor, Blitter, address generation |
-| **Denise** | 8362 | Display: bitplane fetch decode, sprite decode, colour output |
+| **Denise** | 8362 | Display: bitplane fetch decode, sprite decode, color output |
 | **Paula** | 8364 | Audio DMA (4 channels), floppy disk I/O, serial port, interrupts |
 
 ## Contents
@@ -90,7 +90,7 @@ The CDTV is an A500-class OCS computer in a consumer set-top box form factor. Se
 - Max **512 KB Chip RAM** on A500 rev 5 and earlier (Agnus 8361/8367 addresses 512 KB only)
 - A500 rev 6+ allows 1 MB with Fat Agnus (part of later OCS run)
 - No productivity display modes (ECS adds BEAMCON0)
-- 32 colours max (or 64 EHB, or HAM 12-bit) in standard bitplane modes
+- 32 colors max (or 64 EHB, or HAM 12-bit) in standard bitplane modes
 - Blitter is 16-bit; no 64-bit fetch (AGA adds FMODE)
 - No ECS Denise border features
 

01_hardware/ocs_a500/cdtv_hardware.md

@@ -128,8 +128,8 @@ The Extended ROM is **not present** on standard A500/A2000 machines. Software th
 ### Boot Sequence
 
 1. Kickstart 1.3 loads from ROM (`$F80000`)
-2. Extended ROM at `$E00000` is detected and initialised
-3. `scsi.device` from Extended ROM initialises DMAC + WD33C93
+2. Extended ROM at `$E00000` is detected and initialized
+3. `scsi.device` from Extended ROM initializes DMAC + WD33C93
 4. CD-ROM drive is probed for a bootable disc
 5. If a valid Amiga boot block is found on the CD → boot from CD
 6. If no CD → fall through to standard floppy boot (if external floppy present)

01_hardware/ocs_a500/chipset_ocs.md

@@ -20,7 +20,7 @@ block-beta
 
 ## DMA Channels and Priorities
 
-Agnus schedules DMA cycles across a fixed priority scheme within each horizontal raster line (228 colour clocks per line, PAL):
+Agnus schedules DMA cycles across a fixed priority scheme within each horizontal raster line (228 color clocks per line, PAL):
 
 | Priority | DMA Channel | Register Bits |
 |---|---|---|

01_hardware/ocs_a500/copper.md

@@ -6,7 +6,7 @@
 
 The **Copper** (co-processor) is built into Agnus. It executes a simple instruction list (the **copperlist**) in sync with the video beam, allowing precise per-scanline changes to any writable custom register — without CPU intervention.
 
-The Copper can only write to custom registers (it cannot access Chip RAM directly), but it can change bitplane pointers, colours, BPLCON0, sprite pointers, and any other `$DFF0xx` register on a cycle-accurate basis.
+The Copper can only write to custom registers (it cannot access Chip RAM directly), but it can change bitplane pointers, colors, BPLCON0, sprite pointers, and any other `$DFF0xx` register on a cycle-accurate basis.
 
 ## Copper Instruction Set
 
@@ -59,7 +59,7 @@ A copperlist is an array of 32-bit instruction pairs in **Chip RAM**, terminated
 DC.W  $FFFF, $FFFE
 ```
 
-Example — colour cycle on vertical blank:
+Example — color cycle on vertical blank:
 ```asm
 Copperlist:
     DC.W  $0180, $0000   ; COLOR00 = black
@@ -110,7 +110,7 @@ Common copper techniques:
 
 **BPLCON0 mid-screen:** Switch between `HIRES` and `LORES`, or between 6-plane and 4-plane modes, on different lines.
 
-**Raster bars:** Write a different colour to COLOR00 on every scanline using sequential WAIT+MOVE pairs.
+**Raster bars:** Write a different color to COLOR00 on every scanline using sequential WAIT+MOVE pairs.
 
 ## Graphics Library vs Direct Copper
 

01_hardware/ocs_a500/custom_registers.md

@@ -103,7 +103,7 @@ bit 15:    HIRES  (1 = 640 pixel wide)
 bit 14-12: BPU2-0 (number of bitplanes: 0–6)
 bit 11:    HAM    (1 = Hold-And-Modify mode)
 bit 10:    DPF    (dual playfield)
-bit  9:    COLOR  (0 = monochrome, 1 = colour)
+bit  9:    COLOR  (0 = monochrome, 1 = color)
 bit  8:    GAUD   (genlock audio)
 bit  7-4:  (various, OCS = 0)
 bit  1:    ERSY   (external sync)
@@ -165,16 +165,16 @@ bit  0:    ECSENA (ECS enable — must be 0 on OCS)
 | $09E | ADKCON | W | Audio / disk control (write) |
 | $07C | DSKSYNC | W | Disk sync word |
 
-## Colour Registers
+## Color Registers
 
 | Offset | Name | Dir | Description |
 |---|---|---|---|
-| $180 | COLOR00 | W | Background / colour 0 |
-| $182 | COLOR01 | W | Colour 1 |
+| $180 | COLOR00 | W | Background / color 0 |
+| $182 | COLOR01 | W | Color 1 |
 | ... | | | |
-| $1BE | COLOR31 | W | Colour 31 |
+| $1BE | COLOR31 | W | Color 31 |
 
-OCS colours: 12-bit RGB (4 bits per component, $0RGB format).
+OCS colors: 12-bit RGB (4 bits per component, $0RGB format).
 
 ## References
 

01_hardware/ocs_a500/sprites.md

@@ -13,9 +13,9 @@ The OCS/ECS chipset provides **8 hardware sprites**, each 16 pixels wide and arb
 | Count | 8 sprites |
 | Width | 16 pixels fixed |
 | Height | Programmable (any number of lines) |
-| Colours | 3 (+1 transparent) per sprite |
-| Colour source | Sprite colour registers (COLOR16–COLOR31) |
-| Attach mode | Pairs 0/1, 2/3, 4/5, 6/7 → 15 colours |
+| Colors | 3 (+1 transparent) per sprite |
+| Color source | Sprite color registers (COLOR16–COLOR31) |
+| Attach mode | Pairs 0/1, 2/3, 4/5, 6/7 → 15 colors |
 
 ## Sprite Registers
 
@@ -60,14 +60,14 @@ Each line of the sprite consists of two 16-bit words (DATA and DATB) fetched fro
 
 ```
 For each scanline of sprite:
-  Word 1 (DATA): bit 15..0 → pixel bit 1 (colour bit 1)
-  Word 2 (DATB): bit 15..0 → pixel bit 0 (colour bit 0)
+  Word 1 (DATA): bit 15..0 → pixel bit 1 (color bit 1)
+  Word 2 (DATB): bit 15..0 → pixel bit 0 (color bit 0)
 
-Pixel colour:
+Pixel color:
   DATA[bit] = 0, DATB[bit] = 0  → transparent
-  DATA[bit] = 0, DATB[bit] = 1  → colour 1 (COLOR17 for sprite 0)
-  DATA[bit] = 1, DATB[bit] = 0  → colour 2 (COLOR18)
-  DATA[bit] = 1, DATB[bit] = 1  → colour 3 (COLOR19)
+  DATA[bit] = 0, DATB[bit] = 1  → color 1 (COLOR17 for sprite 0)
+  DATA[bit] = 1, DATB[bit] = 0  → color 2 (COLOR18)
+  DATA[bit] = 1, DATB[bit] = 1  → color 3 (COLOR19)
 ```
 
 ## Sprite Data in Memory
@@ -85,29 +85,29 @@ Agnus DMA reads the sprite from a memory block structured as:
   Word: $0000   (SPRnCTL = 0)
 ```
 
-## Colour Mapping
+## Color Mapping
 
-Sprites share colour registers with bitplanes:
+Sprites share color registers with bitplanes:
 
-| Sprites | Colour Registers |
+| Sprites | Color Registers |
 |---|---|
 | 0 and 1 | COLOR16–COLOR19 |
 | 2 and 3 | COLOR20–COLOR23 |
 | 4 and 5 | COLOR24–COLOR27 |
 | 6 and 7 | COLOR28–COLOR31 |
 
-COLOR16 (the first colour of sprite pair 0/1) is always transparent — the sprite background. Only COLOR17–COLOR19 are visible for sprites 0/1.
+COLOR16 (the first color of sprite pair 0/1) is always transparent — the sprite background. Only COLOR17–COLOR19 are visible for sprites 0/1.
 
-## Attached Sprites (15 Colours)
+## Attached Sprites (15 Colors)
 
-Pairing two sprites (`ATT` bit in SPRnCTL of the even sprite) combines their DATA/DATB bits to produce a 4-bit colour index (16 colours, one transparent):
+Pairing two sprites (`ATT` bit in SPRnCTL of the even sprite) combines their DATA/DATB bits to produce a 4-bit color index (16 colors, one transparent):
 
 ```
-4-bit colour = {SPR_even.DATA[bit], SPR_even.DATB[bit],
+4-bit color = {SPR_even.DATA[bit], SPR_even.DATB[bit],
                 SPR_odd.DATA[bit],  SPR_odd.DATB[bit]}
 ```
 
-This gives 15 visible colours per pair, using COLOR16–COLOR31 for pair 0/1.
+This gives 15 visible colors per pair, using COLOR16–COLOR31 for pair 0/1.
 
 ## BPLCON2 — Sprite Priority
 
@@ -122,7 +122,7 @@ Default: sprites appear in front of all bitplanes.
 
 ## OS Mouse Pointer
 
-AmigaOS's Intuition uses sprite 0 (and 1 in attached mode for colour pointer) for the mouse pointer. Intuition calls `SetPointer()` / `ClearPointer()` on a Window to install custom pointer sprites.
+AmigaOS's Intuition uses sprite 0 (and 1 in attached mode for color pointer) for the mouse pointer. Intuition calls `SetPointer()` / `ClearPointer()` on a Window to install custom pointer sprites.
 
 ```c
 SetPointer(window, pointer_data, height, width, x_offset, y_offset);