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Minor fixes in layout and indexing

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Ilia Sharin 2026-04-25 14:58:33 -04:00
parent a5b49d073f
commit 2eb8321d00
2 changed files with 8 additions and 9 deletions
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1
08_graphics/README.md
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@ -21,4 +21,3 @@ The Amiga graphics system is built on custom DMA-driven hardware (Agnus/Alice +
| [views.md](views.md) | View, ViewPort, MakeVPort, display construction |
| [text_fonts.md](text_fonts.md) | TextFont bitmap layout, baseline rendering, algorithmic styles, AvailFonts enumeration |
| [animation.md](animation.md) | GEL system deep dive: BOBs, VSprites, AnimObs, hardware foundation (Blitter/Copper/Sprite interaction), collision detection, double buffering, performance tuning |
| [pixel_conversion.md](pixel_conversion.md) | Chunky↔Planar conversion: butterfly algorithm, Akiko C2P, Blitter-assisted, RTG bypass; SoA/AoS parallels to GPU/SIMD |

16
08_graphics/pixel_conversion.md
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@ -71,14 +71,14 @@ The downside only became critical as rendering algorithms evolved past 2D sprite
C2P is a **bit matrix transposition**. Given 32 chunky pixels (each 8 bits wide), you have a 32×8 bit matrix (32 rows × 8 columns). C2P transposes this to an 8×32 matrix (8 bitplanes × 32 bits each):
```
Input (chunky): Output (planar):
32 pixels × 8 bits 8 bitplanes × 32 bits
┌─────────────────┐ ┌──────────────────────────────┐
│ P0: b7 b6 b5 b4 b3 b2 b1 b0 │ │ Plane 0: p0.b0 p1.b0 p2.b0 ... p31.b0 │
│ P1: b7 b6 b5 b4 b3 b2 b1 b0 │ │ Plane 1: p0.b1 p1.b1 p2.b1 ... p31.b1 │
│ ... │ │ ... │
│ P31: b7 b6 b5 b4 b3 b2 b1 b0 │ │ Plane 7: p0.b7 p1.b7 p2.b7 ... p31.b7 │
└─────────────────┘ └──────────────────────────────┘
Input (chunky): Output (planar):
32 pixels × 8 bits 8 bitplanes × 32 bits
┌──────────────────────────────┐ ┌────────────────────────────────────────┐
│ P0: b7 b6 b5 b4 b3 b2 b1 b0 │ │ Plane 0: p0.b0 p1.b0 p2.b0 ... p31.b0 │
│ P1: b7 b6 b5 b4 b3 b2 b1 b0 │ │ Plane 1: p0.b1 p1.b1 p2.b1 ... p31.b1 │
│ ... │ │ ... │
│ P31: b7 b6 b5 b4 b3 b2 b1 b0 │ │ Plane 7: p0.b7 p1.b7 p2.b7 ... p31.b7 │
└──────────────────────────────┘ └────────────────────────────────────────┘
```
This is equivalent to a 90° bit rotation. On a modern CPU with SIMD, this is trivial. On a 68020 with 8 data registers and no bit-parallel instructions, it is an algorithmic challenge that consumed thousands of programmer-hours across the demoscene.