diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java
index 562fd88..2c470a1 100644
--- a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java
+++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java
@@ -2358,10 +2358,12 @@ public class CoreGenerator {
 					if ("dd".equals(dst)) {
 						if ("b".equals(size)) {
 							addFormattedMicroInsn("dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff)"); // update register with result
-						} else if ("w".equals(size)) {
-							addFormattedMicroInsn("dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff)"); // update register with result
 						} else if ("l".equals(size)) {
 							addFormattedMicroInsn("dar[rx] = dt"); // update register with result
+						} else if ("w".equals(size) && ("mulu".equals(op) || "muls".equals(op))) {
+							addFormattedMicroInsn("dar[rx] = dt"); // update register with result
+						} else if ("w".equals(size)) {
+							addFormattedMicroInsn("dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff)"); // update register with result
 						} else {
 							throw new IllegalStateException();
 						}
diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java
index c250f6b..e92a601 100644
--- a/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java
+++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java
@@ -769,6 +769,20 @@ public class CorePLAGenerator {
 				appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "and", "l", "ea", "dd"));
 			}
 		});
+		appendOP_eas(0xc0c0, 0xf1c0, "mulu_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "mulu", "w", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> {
+			if ((mode & EA_ALL ) == 0) {
+				appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr");
+			} else {
+				appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "mulu", "w", "ea", "dd"));
+			}
+		});
+		appendOP_eas(0xc1c0, 0xf1c0, "muls_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "muls", "w", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> {
+			if ((mode & EA_ALL ) == 0) {
+				appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr");
+			} else {
+				appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "muls", "w", "ea", "dd"));
+			}
+		});
 
 		appendOP(gen, entries, array, 0xc140, 0xf1f8, "exg_dd_ds", "op_exg_dd_ds", "dbrr", "dbrr");
 		appendOP(gen, entries, array, 0xc148, 0xf1f8, "exg_ad_as", "op_exg_ad_as", "dbrr", "dbrr");
diff --git a/miggy-emu/src/main/java/miggy/cpupoet/Core.java b/miggy-emu/src/main/java/miggy/cpupoet/Core.java
index 960ee6e..8e28dc0 100644
--- a/miggy-emu/src/main/java/miggy/cpupoet/Core.java
+++ b/miggy-emu/src/main/java/miggy/cpupoet/Core.java
@@ -847,145 +847,153 @@ public abstract class Core extends CoreALU {
 
   protected static final int gen_andl_dt_dd = 534;
 
-  protected static final int gen_andb_dd_ea = 535;
+  protected static final int gen_muluw_ds_dd = 535;
 
-  protected static final int gen_andw_dd_ea = 536;
+  protected static final int gen_muluw_dt_dd = 536;
 
-  protected static final int gen_andl_dd_ea = 537;
+  protected static final int gen_mulsw_ds_dd = 537;
 
-  protected static final int gen_abcdb_ds_dd = 538;
+  protected static final int gen_mulsw_dt_dd = 538;
 
-  protected static final int gen_abcdb_im_ea = 539;
+  protected static final int gen_andb_dd_ea = 539;
 
-  protected static final int gen_addb_ds_dd = 540;
+  protected static final int gen_andw_dd_ea = 540;
 
-  protected static final int gen_addb_dt_dd = 541;
+  protected static final int gen_andl_dd_ea = 541;
 
-  protected static final int gen_addw_ds_dd = 542;
+  protected static final int gen_abcdb_ds_dd = 542;
 
-  protected static final int gen_addw_as_dd = 543;
+  protected static final int gen_abcdb_im_ea = 543;
 
-  protected static final int gen_addw_dt_dd = 544;
+  protected static final int gen_addb_ds_dd = 544;
 
-  protected static final int gen_addl_ds_dd = 545;
+  protected static final int gen_addb_dt_dd = 545;
 
-  protected static final int gen_addl_as_dd = 546;
+  protected static final int gen_addw_ds_dd = 546;
 
-  protected static final int gen_addl_dt_dd = 547;
+  protected static final int gen_addw_as_dd = 547;
 
-  protected static final int gen_addb_dd_ea = 548;
+  protected static final int gen_addw_dt_dd = 548;
 
-  protected static final int gen_addw_dd_ea = 549;
+  protected static final int gen_addl_ds_dd = 549;
 
-  protected static final int gen_addl_dd_ea = 550;
+  protected static final int gen_addl_as_dd = 550;
 
-  protected static final int gen_addxb_ds_dd = 551;
+  protected static final int gen_addl_dt_dd = 551;
 
-  protected static final int gen_addxb_im_ea = 552;
+  protected static final int gen_addb_dd_ea = 552;
 
-  protected static final int gen_addxw_ds_dd = 553;
+  protected static final int gen_addw_dd_ea = 553;
 
-  protected static final int gen_addxw_im_ea = 554;
+  protected static final int gen_addl_dd_ea = 554;
 
-  protected static final int gen_addxl_ds_dd = 555;
+  protected static final int gen_addxb_ds_dd = 555;
 
-  protected static final int gen_addxl_im_ea = 556;
+  protected static final int gen_addxb_im_ea = 556;
 
-  protected static final int gen_addw_ds_ad = 557;
+  protected static final int gen_addxw_ds_dd = 557;
 
-  protected static final int gen_addw_as_ad = 558;
+  protected static final int gen_addxw_im_ea = 558;
 
-  protected static final int gen_addw_dt_ad = 559;
+  protected static final int gen_addxl_ds_dd = 559;
 
-  protected static final int gen_addl_ds_ad = 560;
+  protected static final int gen_addxl_im_ea = 560;
 
-  protected static final int gen_addl_as_ad = 561;
+  protected static final int gen_addw_ds_ad = 561;
 
-  protected static final int gen_addl_dt_ad = 562;
+  protected static final int gen_addw_as_ad = 562;
 
-  protected static final int gen_asrb_ir_ds = 563;
+  protected static final int gen_addw_dt_ad = 563;
 
-  protected static final int gen_asrb_dd_ds = 564;
+  protected static final int gen_addl_ds_ad = 564;
 
-  protected static final int gen_asrw_ir_ds = 565;
+  protected static final int gen_addl_as_ad = 565;
 
-  protected static final int gen_asrw_dd_ds = 566;
+  protected static final int gen_addl_dt_ad = 566;
 
-  protected static final int gen_asrl_ir_ds = 567;
+  protected static final int gen_asrb_ir_ds = 567;
 
-  protected static final int gen_asrl_dd_ds = 568;
+  protected static final int gen_asrb_dd_ds = 568;
 
-  protected static final int gen_asrw_ea = 569;
+  protected static final int gen_asrw_ir_ds = 569;
 
-  protected static final int gen_aslb_ir_ds = 570;
+  protected static final int gen_asrw_dd_ds = 570;
 
-  protected static final int gen_aslb_dd_ds = 571;
+  protected static final int gen_asrl_ir_ds = 571;
 
-  protected static final int gen_aslw_ir_ds = 572;
+  protected static final int gen_asrl_dd_ds = 572;
 
-  protected static final int gen_aslw_dd_ds = 573;
+  protected static final int gen_asrw_ea = 573;
 
-  protected static final int gen_asll_ir_ds = 574;
+  protected static final int gen_aslb_ir_ds = 574;
 
-  protected static final int gen_asll_dd_ds = 575;
+  protected static final int gen_aslb_dd_ds = 575;
 
-  protected static final int gen_aslw_ea = 576;
+  protected static final int gen_aslw_ir_ds = 576;
 
-  protected static final int gen_lsrb_ir_ds = 577;
+  protected static final int gen_aslw_dd_ds = 577;
 
-  protected static final int gen_lsrb_dd_ds = 578;
+  protected static final int gen_asll_ir_ds = 578;
 
-  protected static final int gen_lsrw_ir_ds = 579;
+  protected static final int gen_asll_dd_ds = 579;
 
-  protected static final int gen_lsrw_dd_ds = 580;
+  protected static final int gen_aslw_ea = 580;
 
-  protected static final int gen_lsrl_ir_ds = 581;
+  protected static final int gen_lsrb_ir_ds = 581;
 
-  protected static final int gen_lsrl_dd_ds = 582;
+  protected static final int gen_lsrb_dd_ds = 582;
 
-  protected static final int gen_lsrw_ea = 583;
+  protected static final int gen_lsrw_ir_ds = 583;
 
-  protected static final int gen_lslb_ir_ds = 584;
+  protected static final int gen_lsrw_dd_ds = 584;
 
-  protected static final int gen_lslb_dd_ds = 585;
+  protected static final int gen_lsrl_ir_ds = 585;
 
-  protected static final int gen_lslw_ir_ds = 586;
+  protected static final int gen_lsrl_dd_ds = 586;
 
-  protected static final int gen_lslw_dd_ds = 587;
+  protected static final int gen_lsrw_ea = 587;
 
-  protected static final int gen_lsll_ir_ds = 588;
+  protected static final int gen_lslb_ir_ds = 588;
 
-  protected static final int gen_lsll_dd_ds = 589;
+  protected static final int gen_lslb_dd_ds = 589;
 
-  protected static final int gen_lslw_ea = 590;
+  protected static final int gen_lslw_ir_ds = 590;
 
-  protected static final int gen_rorb_ir_ds = 591;
+  protected static final int gen_lslw_dd_ds = 591;
 
-  protected static final int gen_rorb_dd_ds = 592;
+  protected static final int gen_lsll_ir_ds = 592;
 
-  protected static final int gen_rorw_ir_ds = 593;
+  protected static final int gen_lsll_dd_ds = 593;
 
-  protected static final int gen_rorw_dd_ds = 594;
+  protected static final int gen_lslw_ea = 594;
 
-  protected static final int gen_rorl_ir_ds = 595;
+  protected static final int gen_rorb_ir_ds = 595;
 
-  protected static final int gen_rorl_dd_ds = 596;
+  protected static final int gen_rorb_dd_ds = 596;
 
-  protected static final int gen_rorw_ea = 597;
+  protected static final int gen_rorw_ir_ds = 597;
 
-  protected static final int gen_rolb_ir_ds = 598;
+  protected static final int gen_rorw_dd_ds = 598;
 
-  protected static final int gen_rolb_dd_ds = 599;
+  protected static final int gen_rorl_ir_ds = 599;
 
-  protected static final int gen_rolw_ir_ds = 600;
+  protected static final int gen_rorl_dd_ds = 600;
 
-  protected static final int gen_rolw_dd_ds = 601;
+  protected static final int gen_rorw_ea = 601;
 
-  protected static final int gen_roll_ir_ds = 602;
+  protected static final int gen_rolb_ir_ds = 602;
 
-  protected static final int gen_roll_dd_ds = 603;
+  protected static final int gen_rolb_dd_ds = 603;
 
-  protected static final int gen_rolw_ea = 604;
+  protected static final int gen_rolw_ir_ds = 604;
+
+  protected static final int gen_rolw_dd_ds = 605;
+
+  protected static final int gen_roll_ir_ds = 606;
+
+  protected static final int gen_roll_dd_ds = 607;
+
+  protected static final int gen_rolw_ea = 608;
 
   public static final int BKPT_EXIT = 0x00010000;
 
@@ -6397,53 +6405,79 @@ public abstract class Core extends CoreALU {
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 535: /* gen_andb_dd_ea */
+          case 535: /* gen_muluw_ds_dd */
+          ry = ir & 0x0007;
+          rx = (ir >> 9) & 0x0007;
+          dt = word_mulu(dar[ry], dar[rx]);
+          dar[rx] = dt;
+          mpc = resume_prefetch;
+          continue;
+          case 536: /* gen_muluw_dt_dd */
+          rx = (ir >> 9) & 0x0007;
+          dt = word_mulu(dt, dar[rx]);
+          dar[rx] = dt;
+          mpc = resume_prefetch;
+          continue;
+          case 537: /* gen_mulsw_ds_dd */
+          ry = ir & 0x0007;
+          rx = (ir >> 9) & 0x0007;
+          dt = word_muls(dar[ry], dar[rx]);
+          dar[rx] = dt;
+          mpc = resume_prefetch;
+          continue;
+          case 538: /* gen_mulsw_dt_dd */
+          rx = (ir >> 9) & 0x0007;
+          dt = word_muls(dt, dar[rx]);
+          dar[rx] = dt;
+          mpc = resume_prefetch;
+          continue;
+          case 539: /* gen_andb_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = byte_and(dar[rx], dt);
           mpc = ea_resume_write8;
           continue;
-          case 536: /* gen_andw_dd_ea */
+          case 540: /* gen_andw_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = word_and(dar[rx], dt);
           mpc = ea_resume_write16;
           continue;
-          case 537: /* gen_andl_dd_ea */
+          case 541: /* gen_andl_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = long_and(dar[rx], dt);
           mpc = ea_resume_write32;
           continue;
-          case 538: /* gen_abcdb_ds_dd */
+          case 542: /* gen_abcdb_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = byte_abcd(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 539: /* gen_abcdb_im_ea */
+          case 543: /* gen_abcdb_im_ea */
           dt = byte_abcd(alub, dt);
           mpc = ea_resume_write8;
           continue;
-          case 540: /* gen_addb_ds_dd */
+          case 544: /* gen_addb_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = byte_add(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 541: /* gen_addb_dt_dd */
+          case 545: /* gen_addb_dt_dd */
           rx = (ir >> 9) & 0x0007;
           dt = byte_add(dt, dar[rx]);
           dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 542: /* gen_addw_ds_dd */
+          case 546: /* gen_addw_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = word_add(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 543: /* gen_addw_as_dd */
+          case 547: /* gen_addw_as_dd */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
@@ -6451,20 +6485,20 @@ public abstract class Core extends CoreALU {
           dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 544: /* gen_addw_dt_dd */
+          case 548: /* gen_addw_dt_dd */
           rx = (ir >> 9) & 0x0007;
           dt = word_add(dt, dar[rx]);
           dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 545: /* gen_addl_ds_dd */
+          case 549: /* gen_addl_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = long_add(dar[ry], dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 546: /* gen_addl_as_dd */
+          case 550: /* gen_addl_as_dd */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
@@ -6472,68 +6506,68 @@ public abstract class Core extends CoreALU {
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 547: /* gen_addl_dt_dd */
+          case 551: /* gen_addl_dt_dd */
           rx = (ir >> 9) & 0x0007;
           dt = long_add(dt, dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 548: /* gen_addb_dd_ea */
+          case 552: /* gen_addb_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = byte_add(dar[rx], dt);
           mpc = ea_resume_write8;
           continue;
-          case 549: /* gen_addw_dd_ea */
+          case 553: /* gen_addw_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = word_add(dar[rx], dt);
           mpc = ea_resume_write16;
           continue;
-          case 550: /* gen_addl_dd_ea */
+          case 554: /* gen_addl_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = long_add(dar[rx], dt);
           mpc = ea_resume_write32;
           continue;
-          case 551: /* gen_addxb_ds_dd */
+          case 555: /* gen_addxb_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = byte_addx(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 552: /* gen_addxb_im_ea */
+          case 556: /* gen_addxb_im_ea */
           dt = byte_addx(alub, dt);
           mpc = ea_resume_write8;
           continue;
-          case 553: /* gen_addxw_ds_dd */
+          case 557: /* gen_addxw_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = word_addx(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 554: /* gen_addxw_im_ea */
+          case 558: /* gen_addxw_im_ea */
           dt = word_addx(alub, dt);
           mpc = ea_resume_write16;
           continue;
-          case 555: /* gen_addxl_ds_dd */
+          case 559: /* gen_addxl_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = long_addx(dar[ry], dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 556: /* gen_addxl_im_ea */
+          case 560: /* gen_addxl_im_ea */
           dt = long_addx(alub, dt);
           mpc = ea_resume_write32;
           continue;
-          case 557: /* gen_addw_ds_ad */
+          case 561: /* gen_addw_ds_ad */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           dar[rx] = dar[rx] + ((short) dar[ry]);
           mpc = resume_prefetch;
           continue;
-          case 558: /* gen_addw_as_ad */
+          case 562: /* gen_addw_as_ad */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
@@ -6541,20 +6575,20 @@ public abstract class Core extends CoreALU {
           dar[rx] = dar[rx] + ((short) dar[ry]);
           mpc = resume_prefetch;
           continue;
-          case 559: /* gen_addw_dt_ad */
+          case 563: /* gen_addw_dt_ad */
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           dar[rx] = dar[rx] + ((short) dt);
           mpc = resume_prefetch;
           continue;
-          case 560: /* gen_addl_ds_ad */
+          case 564: /* gen_addl_ds_ad */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           dar[rx] = dar[rx] + dar[ry];
           mpc = resume_prefetch;
           continue;
-          case 561: /* gen_addl_as_ad */
+          case 565: /* gen_addl_as_ad */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
@@ -6562,13 +6596,13 @@ public abstract class Core extends CoreALU {
           dar[rx] = dar[rx] + dar[ry];
           mpc = resume_prefetch;
           continue;
-          case 562: /* gen_addl_dt_ad */
+          case 566: /* gen_addl_dt_ad */
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           dar[rx] = dar[rx] + dt;
           mpc = resume_prefetch;
           continue;
-          case 563: /* gen_asrb_ir_ds */
+          case 567: /* gen_asrb_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6578,14 +6612,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 564: /* gen_asrb_dd_ds */
+          case 568: /* gen_asrb_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = byte_asr(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 565: /* gen_asrw_ir_ds */
+          case 569: /* gen_asrw_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6595,14 +6629,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 566: /* gen_asrw_dd_ds */
+          case 570: /* gen_asrw_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = word_asr(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 567: /* gen_asrl_ir_ds */
+          case 571: /* gen_asrl_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6612,18 +6646,18 @@ public abstract class Core extends CoreALU {
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 568: /* gen_asrl_dd_ds */
+          case 572: /* gen_asrl_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = long_asr(dar[rx], dar[ry]);
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 569: /* gen_asrw_ea */
+          case 573: /* gen_asrw_ea */
           dt = word_asr(1, dt);
           mpc = ea_resume_write16;
           continue;
-          case 570: /* gen_aslb_ir_ds */
+          case 574: /* gen_aslb_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6633,14 +6667,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 571: /* gen_aslb_dd_ds */
+          case 575: /* gen_aslb_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = byte_asl(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 572: /* gen_aslw_ir_ds */
+          case 576: /* gen_aslw_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6650,14 +6684,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 573: /* gen_aslw_dd_ds */
+          case 577: /* gen_aslw_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = word_asl(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 574: /* gen_asll_ir_ds */
+          case 578: /* gen_asll_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6667,18 +6701,18 @@ public abstract class Core extends CoreALU {
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 575: /* gen_asll_dd_ds */
+          case 579: /* gen_asll_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = long_asl(dar[rx], dar[ry]);
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 576: /* gen_aslw_ea */
+          case 580: /* gen_aslw_ea */
           dt = word_asl(1, dt);
           mpc = ea_resume_write16;
           continue;
-          case 577: /* gen_lsrb_ir_ds */
+          case 581: /* gen_lsrb_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6688,14 +6722,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 578: /* gen_lsrb_dd_ds */
+          case 582: /* gen_lsrb_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = byte_lsr(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 579: /* gen_lsrw_ir_ds */
+          case 583: /* gen_lsrw_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6705,14 +6739,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 580: /* gen_lsrw_dd_ds */
+          case 584: /* gen_lsrw_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = word_lsr(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 581: /* gen_lsrl_ir_ds */
+          case 585: /* gen_lsrl_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6722,18 +6756,18 @@ public abstract class Core extends CoreALU {
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 582: /* gen_lsrl_dd_ds */
+          case 586: /* gen_lsrl_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = long_lsr(dar[rx], dar[ry]);
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 583: /* gen_lsrw_ea */
+          case 587: /* gen_lsrw_ea */
           dt = word_lsr(1, dt);
           mpc = ea_resume_write16;
           continue;
-          case 584: /* gen_lslb_ir_ds */
+          case 588: /* gen_lslb_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6743,14 +6777,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 585: /* gen_lslb_dd_ds */
+          case 589: /* gen_lslb_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = byte_lsl(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 586: /* gen_lslw_ir_ds */
+          case 590: /* gen_lslw_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6760,14 +6794,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 587: /* gen_lslw_dd_ds */
+          case 591: /* gen_lslw_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = word_lsl(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 588: /* gen_lsll_ir_ds */
+          case 592: /* gen_lsll_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6777,18 +6811,18 @@ public abstract class Core extends CoreALU {
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 589: /* gen_lsll_dd_ds */
+          case 593: /* gen_lsll_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = long_lsl(dar[rx], dar[ry]);
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 590: /* gen_lslw_ea */
+          case 594: /* gen_lslw_ea */
           dt = word_lsl(1, dt);
           mpc = ea_resume_write16;
           continue;
-          case 591: /* gen_rorb_ir_ds */
+          case 595: /* gen_rorb_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6798,14 +6832,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 592: /* gen_rorb_dd_ds */
+          case 596: /* gen_rorb_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = byte_ror(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 593: /* gen_rorw_ir_ds */
+          case 597: /* gen_rorw_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6815,14 +6849,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 594: /* gen_rorw_dd_ds */
+          case 598: /* gen_rorw_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = word_ror(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 595: /* gen_rorl_ir_ds */
+          case 599: /* gen_rorl_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6832,18 +6866,18 @@ public abstract class Core extends CoreALU {
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 596: /* gen_rorl_dd_ds */
+          case 600: /* gen_rorl_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = long_ror(dar[rx], dar[ry]);
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 597: /* gen_rorw_ea */
+          case 601: /* gen_rorw_ea */
           dt = word_ror(1, dt);
           mpc = ea_resume_write16;
           continue;
-          case 598: /* gen_rolb_ir_ds */
+          case 602: /* gen_rolb_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6853,14 +6887,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 599: /* gen_rolb_dd_ds */
+          case 603: /* gen_rolb_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = byte_rol(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 600: /* gen_rolw_ir_ds */
+          case 604: /* gen_rolw_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6870,14 +6904,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 601: /* gen_rolw_dd_ds */
+          case 605: /* gen_rolw_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = word_rol(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 602: /* gen_roll_ir_ds */
+          case 606: /* gen_roll_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6887,14 +6921,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 603: /* gen_roll_dd_ds */
+          case 607: /* gen_roll_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = long_rol(dar[rx], dar[ry]);
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 604: /* gen_rolw_ea */
+          case 608: /* gen_rolw_ea */
           dt = word_rol(1, dt);
           mpc = ea_resume_write16;
           continue;
diff --git a/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java b/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java
index 38f1df1..dc6beff 100644
--- a/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java
+++ b/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java
@@ -1461,6 +1461,34 @@ public class CoreALU {
 		return byte_sbcd(dst, 0);
 	}
 
+	public final int word_muls(int src, int dst) {
+		src = (short) src;
+		dst = (short) dst;
+
+		int res = dst * src;
+
+		int n = (res >> 28) & FL_N;
+		int z = (~((res | -res) >> 31)) & FL_Z;
+
+		sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N);
+
+		return res;
+	}
+
+	public final int word_mulu(int src, int dst) {
+		src = src & 0xffff;
+		dst = dst & 0xffff;
+
+		int res = dst * src;
+
+		int n = (res >> 28) & FL_N;
+		int z = (~((res | -res) >> 31)) & FL_Z;
+
+		sr ^= (sr ^ (z | n)) & (FL_C | FL_V | FL_Z | FL_N);
+
+		return res;
+	}
+
 	public final short word_nbcd(int dst) {
 		return word_sbcd(dst, 0);
 	}
diff --git a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java
index f248020..37f598f 100644
--- a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java
+++ b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java
@@ -250,6 +250,10 @@ import static miggy.cpupoet.Core.gen_movew_dt_ea;
 import static miggy.cpupoet.Core.gen_movew_dt_sr;
 import static miggy.cpupoet.Core.gen_movew_sr_ds;
 import static miggy.cpupoet.Core.gen_movew_sr_ea;
+import static miggy.cpupoet.Core.gen_mulsw_ds_dd;
+import static miggy.cpupoet.Core.gen_mulsw_dt_dd;
+import static miggy.cpupoet.Core.gen_muluw_ds_dd;
+import static miggy.cpupoet.Core.gen_muluw_dt_dd;
 import static miggy.cpupoet.Core.gen_nbcdb_ds;
 import static miggy.cpupoet.Core.gen_nbcdb_ea;
 import static miggy.cpupoet.Core.gen_negb_ds;
@@ -2657,6 +2661,28 @@ public enum MacroPLA {
 
   and_l_imm32_dd(0xc0bc, 0xf1ff, ea_imm32_read, dbrr, gen_andl_dt_dd),
 
+  mulu_w_ds(0xc0c0, 0xf1f8, gen_muluw_ds_dd, dbrr, dbrr),
+
+  mulu_w_ais(0xc0d0, 0xf1f8, ea_ais16_read, dbrr, gen_muluw_dt_dd),
+
+  mulu_w_aips(0xc0d8, 0xf1f8, ea_aips16_read, dbrr, gen_muluw_dt_dd),
+
+  mulu_w_pais(0xc0e0, 0xf1f8, ea_pais16_read, dbrr, gen_muluw_dt_dd),
+
+  mulu_w_das(0xc0e8, 0xf1f8, ea_das16_read, dbrr, gen_muluw_dt_dd),
+
+  mulu_w_dais(0xc0f0, 0xf1f8, ea_dais16_read, dbrr, gen_muluw_dt_dd),
+
+  mulu_w_adr16(0xc0f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_muluw_dt_dd),
+
+  mulu_w_adr32(0xc0f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_muluw_dt_dd),
+
+  mulu_w_dpc(0xc0fa, 0xf1ff, ea_dpc16_read, dbrr, gen_muluw_dt_dd),
+
+  mulu_w_dpci(0xc0fb, 0xf1ff, ea_dpci16_read, dbrr, gen_muluw_dt_dd),
+
+  mulu_w_imm16(0xc0fc, 0xf1ff, ea_imm16_read, dbrr, gen_muluw_dt_dd),
+
   abcd_ds_dd(0xc100, 0xf1f8, gen_abcdb_ds_dd, dbrr, dbrr),
 
   abcd_pais_paid(0xc108, 0xf1f8, ea_pais8_read, gen_abcdb_im_ea, ea_paid8_read),
@@ -2709,6 +2735,28 @@ public enum MacroPLA {
 
   and_l_dd_adr32(0xc1b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_andl_dd_ea),
 
+  muls_w_ds(0xc1c0, 0xf1f8, gen_mulsw_ds_dd, dbrr, dbrr),
+
+  muls_w_ais(0xc1d0, 0xf1f8, ea_ais16_read, dbrr, gen_mulsw_dt_dd),
+
+  muls_w_aips(0xc1d8, 0xf1f8, ea_aips16_read, dbrr, gen_mulsw_dt_dd),
+
+  muls_w_pais(0xc1e0, 0xf1f8, ea_pais16_read, dbrr, gen_mulsw_dt_dd),
+
+  muls_w_das(0xc1e8, 0xf1f8, ea_das16_read, dbrr, gen_mulsw_dt_dd),
+
+  muls_w_dais(0xc1f0, 0xf1f8, ea_dais16_read, dbrr, gen_mulsw_dt_dd),
+
+  muls_w_adr16(0xc1f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_mulsw_dt_dd),
+
+  muls_w_adr32(0xc1f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_mulsw_dt_dd),
+
+  muls_w_dpc(0xc1fa, 0xf1ff, ea_dpc16_read, dbrr, gen_mulsw_dt_dd),
+
+  muls_w_dpci(0xc1fb, 0xf1ff, ea_dpci16_read, dbrr, gen_mulsw_dt_dd),
+
+  muls_w_imm16(0xc1fc, 0xf1ff, ea_imm16_read, dbrr, gen_mulsw_dt_dd),
+
   add_b_ds_dd(0xd000, 0xf1f8, gen_addb_ds_dd, dbrr, dbrr),
 
   add_b_ais_dd(0xd010, 0xf1f8, ea_ais8_read, dbrr, gen_addb_dt_dd),
diff --git a/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java b/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java
index f70dc83..c9dede4 100644
--- a/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java
+++ b/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java
@@ -15,6 +15,13 @@ public class InstructionTests extends TestCase {
 		test.executeBinTest("SBCD");
 	}
 
+	public void testMUL() {
+		CoreTest test = new CoreTest(0xffffff + 1, true);
+
+		test.executeBinTest("MULU");
+		test.executeBinTest("MULS");
+	}
+
 	public void testADD() {
 		CoreTest test = new CoreTest(0xffffff + 1, true);
 
diff --git a/miggy-emu/src/test/resources/miggy/cpupoet/MULS.json.bin b/miggy-emu/src/test/resources/miggy/cpupoet/MULS.json.bin
new file mode 100644
index 0000000..d4ac3ca
Binary files /dev/null and b/miggy-emu/src/test/resources/miggy/cpupoet/MULS.json.bin differ
diff --git a/miggy-emu/src/test/resources/miggy/cpupoet/MULU.json.bin b/miggy-emu/src/test/resources/miggy/cpupoet/MULU.json.bin
new file mode 100644
index 0000000..20ebc6c
Binary files /dev/null and b/miggy-emu/src/test/resources/miggy/cpupoet/MULU.json.bin differ