From 93831dd1166d254d8df3541468d8a57f9e712701 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rodolphe=20de=20Saint=20L=C3=A9ger?= Date: Mon, 19 May 2025 18:02:33 +0200 Subject: [PATCH] Changed MOVE.w/l as, implementation to reflect real behavior --- .../java/miggy/cpu/genpoet/CoreGenerator.java | 6 + .../miggy/cpu/genpoet/CorePLAGenerator.java | 206 +- .../src/main/java/miggy/cpupoet/Core.java | 1666 ++++++++--------- .../src/main/java/miggy/cpupoet/MacroPLA.java | 31 +- .../java/miggy/cpupoet/InstructionTests.java | 12 +- 5 files changed, 957 insertions(+), 964 deletions(-) diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java index 63d2bd2..562fd88 100644 --- a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java +++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java @@ -1481,6 +1481,12 @@ public class CoreGenerator { } private void misc_microcode() { + addState("ea_as_dt"); + decode_ay(); + addFormattedMicroInsn("dt = dar[ry]"); + addFormattedMicroInsn("nmpc = decoded.a3"); + addFormattedMicroInsn("break"); + addState("op_clrb_ds"); decode_dy(); addFormattedMicroInsn("dar[ry] &= ~0xff"); diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java index 0222907..c250f6b 100644 --- a/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java +++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java @@ -34,6 +34,8 @@ public class CorePLAGenerator { private static final int EA_DPC = 0x0080; private static final int EA_DPCI = 0x0100; private static final int EA_IMM = 0x0200; /* always fetched, no address */ + private static final int EA_AS = 0x0400; + private static final int EA_DS = 0x0800; private static final int EA_FETCH = 0x8000; private static final int EA_ALL = EA_AIS | EA_AIPS | EA_PAIS | EA_DAS | EA_DAIS | EA_ADR16 | EA_ADR32 | EA_DPC @@ -64,118 +66,118 @@ public class CorePLAGenerator { public static void fillops(CoreGenerator gen, List entries, MacroEntry[] array) { appendOP_eas(0x0000, 0xffc0, "ori_b_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "or", "b", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "or", "b", "imm8", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "or", "b", "imm8", "ea")); }); appendOP_eas(0x0040, 0xffc0, "ori_w_imm16", EA_FETCH | EA_MALT, "16", dyadic(gen, "or", "w", "imm16", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "or", "w", "imm16", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "or", "w", "imm16", "ea")); }); appendOP_eas(0x0080, 0xffc0, "ori_l_imm32", EA_FETCH | EA_MALT, "32", dyadic(gen, "or", "l", "imm32", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, mode == 0 ? "dbrr" : dyadic(gen, "or", "l", "imm32", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "or", "l", "imm32", "ea")); }); appendOP(gen, entries, array, 0x003c, 0xffff, "ori_imm8_ccr", "op_imm16", dyadic(gen, "or", "b", "imm8", "ccr"), "dbrr"); appendOP(gen, entries, array, 0x007c, 0xffff, "ori_i16u_sr", "op_imm16", dyadic(gen, "or", "w", "imm16", "sr"), "dbrr"); appendOP_eas(0x0100, 0xf1c0, "btst_dd", EA_FETCH | EA_ALL, "8", dyadic(gen, "btst", "l", "dd", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", mode == 0 ? "dbrr" : dyadic(gen, "btst", "b", "dd", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "btst", "b", "dd", "ea")); }); appendOP(gen, entries, array, 0x0108, 0xf1f8, "movep_w_das_dd", "ea_das16", "dbrr", "op_movepw_das_dd"); appendOP_eas(0x0140, 0xf1c0, "bchg_dd", EA_FETCH | EA_MALT, "8", dyadic(gen, "bchg", "l", "dd", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", mode == 0 ? "dbrr" : dyadic(gen, "bchg", "b", "dd", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "bchg", "b", "dd", "ea")); }); appendOP(gen, entries, array, 0x0148, 0xf1f8, "movep_l_das_dd", "ea_das32", "dbrr", "op_movepl_das_dd"); appendOP_eas(0x0180, 0xf1c0, "bclr_dd", EA_FETCH | EA_MALT, "8", dyadic(gen, "bclr", "l", "dd", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", mode == 0 ? "dbrr" : dyadic(gen, "bclr", "b", "dd", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "bclr", "b", "dd", "ea")); }); appendOP(gen, entries, array, 0x0188, 0xf1f8, "movep_w_dd_das", "ea_das16", "dbrr", "op_movepw_dd_das"); appendOP_eas(0x01c0, 0xf1c0, "bset_dd", EA_FETCH | EA_MALT, "8", dyadic(gen, "bset", "l", "dd", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", mode == 0 ? "dbrr" : dyadic(gen, "bset", "b", "dd", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "bset", "b", "dd", "ea")); }); appendOP(gen, entries, array, 0x01c8, 0xf1f8, "movep_l_dd_das", "ea_das32", "dbrr", "op_movepl_dd_das"); appendOP_eas(0x0200, 0xffc0, "andi_b_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "and", "b", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "and", "b", "imm8", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "and", "b", "imm8", "ea")); }); appendOP_eas(0x0240, 0xffc0, "andi_w_imm16", EA_FETCH | EA_MALT, "16", dyadic(gen, "and", "w", "imm16", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "and", "w", "imm16", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "and", "w", "imm16", "ea")); }); appendOP_eas(0x0280, 0xffc0, "andi_l_imm32", EA_FETCH | EA_MALT, "32", dyadic(gen, "and", "l", "imm32", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, mode == 0 ? "dbrr" : dyadic(gen, "and", "l", "imm32", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "and", "l", "imm32", "ea")); }); appendOP(gen, entries, array, 0x023c, 0xffff, "andi_imm8_ccr", "op_imm16", dyadic(gen, "and", "b", "imm8", "ccr"), "dbrr"); appendOP(gen, entries, array, 0x027c, 0xffff, "andi_i16u_sr", "op_imm16", dyadic(gen, "and", "w", "imm16", "sr"), "dbrr"); appendOP_eas(0x0400, 0xffc0, "subi_b_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "sub", "b", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "sub", "b", "imm8", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "sub", "b", "imm8", "ea")); }); appendOP_eas(0x0440, 0xffc0, "subi_w_imm16", EA_FETCH | EA_MALT, "16", dyadic(gen, "sub", "w", "imm16", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "sub", "w", "imm16", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "sub", "w", "imm16", "ea")); }); appendOP_eas(0x0480, 0xffc0, "subi_l_imm32", EA_FETCH | EA_MALT, "32", dyadic(gen, "sub", "l", "imm32", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, mode == 0 ? "dbrr" : dyadic(gen, "sub", "l", "imm32", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "sub", "l", "imm32", "ea")); }); appendOP_eas(0x0600, 0xffc0, "addi_b_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "add", "b", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "add", "b", "imm8", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "add", "b", "imm8", "ea")); }); appendOP_eas(0x0640, 0xffc0, "addi_w_imm16", EA_FETCH | EA_MALT, "16", dyadic(gen, "add", "w", "imm16", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "add", "w", "imm16", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "add", "w", "imm16", "ea")); }); appendOP_eas(0x0680, 0xffc0, "addi_l_imm32", EA_FETCH | EA_MALT, "32", dyadic(gen, "add", "l", "imm32", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, mode == 0 ? "dbrr" : dyadic(gen, "add", "l", "imm32", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "add", "l", "imm32", "ea")); }); appendOP_eas(0x0800, 0xffc0, "btst_imm8", EA_FETCH | EA_MEM, "8", dyadic(gen, "btst", "l", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "btst", "b", "imm8", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "btst", "b", "imm8", "ea")); }); appendOP_eas(0x0840, 0xffc0, "bchg_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "bchg", "l", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "bchg", "b", "imm8", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "bchg", "b", "imm8", "ea")); }); appendOP_eas(0x0880, 0xffc0, "bclr_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "bclr", "l", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "bclr", "b", "imm8", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "bclr", "b", "imm8", "ea")); }); appendOP_eas(0x08c0, 0xffc0, "bset_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "bset", "l", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "bset", "b", "imm8", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "bset", "b", "imm8", "ea")); }); appendOP_eas(0x0a00, 0xffc0, "eori_b_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "eor", "b", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "eor", "b", "imm8", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "eor", "b", "imm8", "ea")); }); appendOP_eas(0x0a40, 0xffc0, "eori_w_imm16", EA_FETCH | EA_MALT, "16", dyadic(gen, "eor", "w", "imm16", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "eor", "w", "imm16", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "eor", "w", "imm16", "ea")); }); appendOP_eas(0x0a80, 0xffc0, "eori_l_imm32", EA_FETCH | EA_MALT, "32", dyadic(gen, "eor", "l", "imm32", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, mode == 0 ? "dbrr" : dyadic(gen, "eor", "l", "imm32", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "eor", "l", "imm32", "ea")); }); appendOP(gen, entries, array, 0x0a3c, 0xffff, "eori_imm8_ccr", "op_imm16", dyadic(gen, "eor", "b", "imm8", "ccr"), "dbrr"); appendOP(gen, entries, array, 0x0a7c, 0xffff, "eori_i16u_sr", "op_imm16", dyadic(gen, "eor", "w", "imm8", "sr"), "dbrr"); appendOP_eas(0x0c00, 0xffc0, "cmpi_b_imm8", EA_FETCH | EA_MALT, "8", dyadic(gen, "cmp", "b", "imm8", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "cmp", "b", "imm8", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "cmp", "b", "imm8", "ea")); }); appendOP_eas(0x0c40, 0xffc0, "cmpi_w_imm16", EA_FETCH | EA_MALT, "16", dyadic(gen, "cmp", "w", "imm16", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, mode == 0 ? "dbrr" : dyadic(gen, "cmp", "w", "imm16", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "cmp", "w", "imm16", "ea")); }); appendOP_eas(0x0c80, 0xffc0, "cmpi_l_imm32", EA_FETCH | EA_MALT, "32", dyadic(gen, "cmp", "l", "imm32", "ds"), null, (opcode, opmask, opname, n2, mode) -> { - appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, mode == 0 ? "dbrr" : dyadic(gen, "cmp", "l", "imm32", "ea")); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm32", n2, (mode & EA_ALL ) == 0 ? "dbrr" : dyadic(gen, "cmp", "l", "imm32", "ea")); }); appendOP_eas(0x1000, 0xf000, "move_b", EA_FETCH | EA_ALL, "8", move(gen , "b", "ds", "ea"), null, (scode, smask, sname, n1, smode) -> { appendOP_ead(scode, smask, sname, EA_MALT, "8", move(gen , "b", "ea", "dd"), null, (opcode, opmask, opname, n3, dmode) -> { - if ((smode == 0) && (dmode == 0)) { + if ((smode == EA_DS) && (dmode == EA_DS)) { appendOP(gen, entries, array, opcode, opmask, opname, move(gen , "b", "ds", "dd"), "dbrr", "dbrr"); - } else if (smode == 0) { + } else if (smode == EA_DS) { appendOP(gen, entries, array, opcode, opmask, opname, n3, n1, "dbrr"); - } else if (dmode == 0) { + } else if (dmode == EA_DS) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", n3); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, move(gen , "b", "ea", "ea"), n3); @@ -183,13 +185,15 @@ public class CorePLAGenerator { }); }); - appendOP_eas(0x2000, 0xf000, "move_l", EA_FETCH | EA_ALL, "32", move(gen , "l", "ds", "ea"), move(gen , "l", "as", "ea"), (scode, smask, sname, n1, smode) -> { + appendOP_eas(0x2000, 0xf000, "move_l", EA_FETCH | EA_ALL, "32", move(gen , "l", "ds", "ea"), move(gen , "l", "ea", "ea"), (scode, smask, sname, n1, smode) -> { appendOP_ead(scode, smask, sname, EA_MALT, "32", move(gen , "l", "ea", "dd"), null, (opcode, opmask, opname, n3, dmode) -> { - if ((smode == 0) && (dmode == 0)) { - appendOP(gen, entries, array, opcode, opmask, opname, move(gen , "l", (opcode & 0x38) == 8 ? "as" : "ds", "dd"), "dbrr", "dbrr"); - } else if (smode == 0) { + if (((smode & (EA_DS | EA_AS)) != 0) && (dmode == EA_DS)) { + appendOP(gen, entries, array, opcode, opmask, opname, move(gen , "l", smode == EA_AS ? "as" : "ds", "dd"), "dbrr", "dbrr"); + } else if (smode == EA_DS) { appendOP(gen, entries, array, opcode, opmask, opname, n3, n1, "dbrr"); - } else if (dmode == 0) { + } else if (smode == EA_AS) { + appendOP(gen, entries, array, opcode, opmask, opname, "ea_as_dt", move(gen , "l", "ea", "ea"), n3); + } else if ((dmode & (EA_DS | EA_AS)) != 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", n3); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, move(gen , "l", "ea", "ea"), n3); @@ -200,20 +204,22 @@ public class CorePLAGenerator { appendOP_eas(0x2040, 0xf1c0, "movea_l", EA_FETCH | EA_ALL, "32", move(gen , "l", "ds", "ad"), move(gen , "l", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_ad", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", move(gen , "l", "ea", "ad")); } }); - appendOP_eas(0x3000, 0xf000, "move_w", EA_FETCH | EA_ALL, "16", move(gen , "w", "ds", "ea"), move(gen , "w", "as", "ea"), (scode, smask, sname, n1, smode) -> { + appendOP_eas(0x3000, 0xf000, "move_w", EA_FETCH | EA_ALL, "16", move(gen , "w", "ds", "ea"), move(gen , "w", "ea", "ea"), (scode, smask, sname, n1, smode) -> { appendOP_ead(scode, smask, sname, EA_MALT, "16", move(gen , "w", "ea", "dd"), null, (opcode, opmask, opname, n3, dmode) -> { - if ((smode == 0) && (dmode == 0)) { - appendOP(gen, entries, array, opcode, opmask, opname, move(gen , "w", (opcode & 0x38) == 8 ? "as" : "ds", "dd"), "dbrr", "dbrr"); - } else if (smode == 0) { + if (((smode & (EA_DS | EA_AS)) != 0) && (dmode == EA_DS)) { + appendOP(gen, entries, array, opcode, opmask, opname, move(gen , "w", smode == EA_AS ? "as" : "ds", "dd"), "dbrr", "dbrr"); + } else if (smode == EA_DS) { appendOP(gen, entries, array, opcode, opmask, opname, n3, n1, "dbrr"); - } else if (dmode == 0) { + } else if (smode == EA_AS) { + appendOP(gen, entries, array, opcode, opmask, opname, "ea_as_dt", move(gen , "w", "ea", "ea"), n3); + } else if ((dmode & (EA_DS | EA_AS)) != 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", n3); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, move(gen , "w", "ea", "ea"), n3); @@ -224,7 +230,7 @@ public class CorePLAGenerator { appendOP_eas(0x3040, 0xf1c0, "movea_w", EA_FETCH | EA_ALL, "16", move(gen , "w", "ds", "ad"), move(gen , "w", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_ad", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", move(gen , "w", "ea", "ad")); @@ -232,21 +238,21 @@ public class CorePLAGenerator { }); appendOP_eas(0x4000, 0xffc0, "negx_b", EA_FETCH | EA_MALT, "8", monadic(gen, "negx", "b", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "negx", "b", "ea")); } }); appendOP_eas(0x4040, 0xffc0, "negx_w", EA_FETCH | EA_MALT, "16", monadic(gen, "negx", "w", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "negx", "w", "ea")); } }); appendOP_eas(0x4080, 0xffc0, "negx_l", EA_FETCH | EA_MALT, "32", monadic(gen, "negx", "l", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "negx", "l", "ea")); @@ -254,7 +260,7 @@ public class CorePLAGenerator { }); appendOP_eas(0x40c0, 0xffc0, "move_sr", EA_MALT, "16", move(gen , "w", "sr", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", move(gen , "w", "sr", "ea")); @@ -264,11 +270,11 @@ public class CorePLAGenerator { appendOP_eas(0x4180, 0xf1c0, "chk_w", EA_FETCH | EA_ALL, "16", "op_chk_w_ds", null, (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", mode == 0 ? "dbrr" : "op_chk_w_ea"); + appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", (mode & EA_ALL ) == 0 ? "dbrr" : "op_chk_w_ea"); }); appendOP_eas(0x42c0, 0xffc0, "move_ccr", EA_MALT, "16", move(gen , "w", "ccr", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", move(gen , "w", "ccr", "ea")); @@ -278,7 +284,7 @@ public class CorePLAGenerator { appendOP_eas(0x44c0, 0xffc0, "move", EA_FETCH | EA_ALL, "16", move(gen , "w", "ds", "ccr"), null, (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_ccr", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", move(gen , "w", "ea", "ccr")); @@ -288,7 +294,7 @@ public class CorePLAGenerator { appendOP_eas(0x46c0, 0xffc0, "move", EA_FETCH | EA_ALL, "16", move(gen , "w", "ds", "sr"), null, (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_sr", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", move(gen , "w", "ea", "sr")); @@ -302,21 +308,21 @@ public class CorePLAGenerator { }); appendOP_eas(0x4200, 0xffc0, "clr_b", EA_MALT, "8", "op_clrb_ds", null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_clrb_ea"); } }); appendOP_eas(0x4240, 0xffc0, "clr_w", EA_MALT, "16", "op_clrw_ds", null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_clrw_ea"); } }); appendOP_eas(0x4280, 0xffc0, "clr_l", EA_MALT, "32", "op_clrl_ds", null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_clrl_ea"); @@ -324,21 +330,21 @@ public class CorePLAGenerator { }); appendOP_eas(0x4400, 0xffc0, "neg_b", EA_FETCH | EA_MALT, "8", monadic(gen, "neg", "b", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "neg", "b", "ea")); } }); appendOP_eas(0x4440, 0xffc0, "neg_w", EA_FETCH | EA_MALT, "16", monadic(gen, "neg", "w", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "neg", "w", "ea")); } }); appendOP_eas(0x4480, 0xffc0, "neg_l", EA_FETCH | EA_MALT, "32", monadic(gen, "neg", "l", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "neg", "l", "ea")); @@ -346,21 +352,21 @@ public class CorePLAGenerator { }); appendOP_eas(0x4600, 0xffc0, "not_b", EA_FETCH | EA_MALT, "8", monadic(gen, "not", "b", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "not", "b", "ea")); } }); appendOP_eas(0x4640, 0xffc0, "not_w", EA_FETCH | EA_MALT, "16", monadic(gen, "not", "w", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "not", "w", "ea")); } }); appendOP_eas(0x4680, 0xffc0, "not_l", EA_FETCH | EA_MALT, "32", monadic(gen, "not", "l", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "not", "l", "ea")); @@ -368,7 +374,7 @@ public class CorePLAGenerator { }); appendOP_eas(0x4800, 0xffc0, "nbcd_b", EA_FETCH | EA_MALT, "8", monadic(gen, "nbcd", "b", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "nbcd", "b", "ea")); @@ -386,21 +392,21 @@ public class CorePLAGenerator { appendOP(gen, entries, array, 0x49c0, 0xfff8, "extb_l_ds", "op_extbl_ds", "dbrr", "dbrr"); appendOP_eas(0x4a00, 0xffc0, "tst_b", EA_FETCH | EA_MALT, "8", monadic(gen, "tst", "b", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "tst", "b", "ea")); } }); appendOP_eas(0x4a40, 0xffc0, "tst_w", EA_FETCH | EA_MALT, "16", monadic(gen, "tst", "w", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "tst", "w", "ea")); } }); appendOP_eas(0x4a80, 0xffc0, "tst_l", EA_FETCH | EA_MALT, "32", monadic(gen, "tst", "l", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", monadic(gen, "tst", "l", "ea")); @@ -486,21 +492,21 @@ public class CorePLAGenerator { }); appendOP_eas(0x5000, 0xf1c0, "addq_b_imm3", EA_FETCH | EA_MALT, "8", dyadic(gen, "add", "b", "imm3", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "b", "imm3", "ea")); } }); appendOP_eas(0x5040, 0xf1c0, "addq_w_imm3", EA_FETCH | EA_MALT, "16", dyadic(gen, "add", "w", "imm3", "ds"), dyadic(gen, "add", "w", "imm3", "as"), (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "w", "imm3", "ea")); } }); appendOP_eas(0x5080, 0xf1c0, "addq_l_imm3", EA_FETCH | EA_MALT, "32", dyadic(gen, "add", "l", "imm3", "ds"), dyadic(gen, "add", "l", "imm3", "as"), (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "l", "imm3", "ea")); @@ -510,21 +516,21 @@ public class CorePLAGenerator { appendOP(gen, entries, array, 0x50c8, 0xf0f8, "dbcc", "op_dbcc", "dbrr", "dbrr"); appendOP_eas(0x5100, 0xf1c0, "subq_b_imm3", EA_FETCH | EA_MALT, "8", dyadic(gen, "sub", "b", "imm3", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "b", "imm3", "ea")); } }); appendOP_eas(0x5140, 0xf1c0, "subq_w_imm3", EA_FETCH | EA_MALT, "16", dyadic(gen, "sub", "w", "imm3", "ds"), dyadic(gen, "sub", "w", "imm3", "as"), (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "w", "imm3", "ea")); } }); appendOP_eas(0x5180, 0xf1c0, "subq_l_imm3", EA_FETCH | EA_MALT, "32", dyadic(gen, "sub", "l", "imm3", "ds"), dyadic(gen, "sub", "l", "imm3", "as"), (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "l", "imm3", "ea")); @@ -532,7 +538,7 @@ public class CorePLAGenerator { }); appendOP_eas(0x50c0, 0xf0c0, "scc_b", EA_MALT, "8", "op_scc_b_ds", null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_scc_b_ea"); @@ -558,7 +564,7 @@ public class CorePLAGenerator { appendOP_eas(0x8000, 0xf1c0, "or_b", EA_FETCH | EA_ALL, "8", dyadic(gen, "or", "b", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "or", "b", "ea", "dd")); @@ -567,7 +573,7 @@ public class CorePLAGenerator { appendOP_eas(0x8040, 0xf1c0, "or_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "or", "w", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "or", "w", "ea", "dd")); @@ -576,7 +582,7 @@ public class CorePLAGenerator { appendOP_eas(0x8080, 0xf1c0, "or_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "or", "l", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "or", "l", "ea", "dd")); @@ -599,7 +605,7 @@ public class CorePLAGenerator { appendOP_eas(0x9000, 0xf1c0, "sub_b", EA_FETCH | EA_ALL, "8", dyadic(gen, "sub", "b", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "b", "ea", "dd")); @@ -608,7 +614,7 @@ public class CorePLAGenerator { appendOP_eas(0x9040, 0xf1c0, "sub_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "sub", "w", "ds", "dd"), dyadic(gen, "sub", "w", "as", "dd"), (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "w", "ea", "dd")); @@ -617,7 +623,7 @@ public class CorePLAGenerator { appendOP_eas(0x9080, 0xf1c0, "sub_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "sub", "l", "ds", "dd"), dyadic(gen, "sub", "l", "as", "dd"), (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "l", "ea", "dd")); @@ -645,7 +651,7 @@ public class CorePLAGenerator { appendOP_eas(0x90c0, 0xf1c0, "suba_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "sub", "w", "ds", "ad"), dyadic(gen, "sub", "w", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_ad", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "w", "ea", "ad")); @@ -654,7 +660,7 @@ public class CorePLAGenerator { appendOP_eas(0x91c0, 0xf1c0, "suba_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "sub", "l", "ds", "ad"), dyadic(gen, "sub", "l", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_ad", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "sub", "l", "ea", "ad")); @@ -666,7 +672,7 @@ public class CorePLAGenerator { appendOP_eas(0xb000, 0xf1c0, "cmp_b", EA_FETCH | EA_ALL, "8", dyadic(gen, "cmp", "b", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "cmp", "b", "ea", "dd")); @@ -675,7 +681,7 @@ public class CorePLAGenerator { appendOP_eas(0xb040, 0xf1c0, "cmp_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "cmp", "w", "ds", "dd"), dyadic(gen, "cmp", "w", "as", "dd"), (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "cmp", "w", "ea", "dd")); @@ -684,7 +690,7 @@ public class CorePLAGenerator { appendOP_eas(0xb080, 0xf1c0, "cmp_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "cmp", "l", "ds", "dd"), dyadic(gen, "cmp", "l", "as", "dd"), (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "cmp", "l", "ea", "dd")); @@ -694,7 +700,7 @@ public class CorePLAGenerator { appendOP_eas(0xb0c0, 0xf1c0, "cmpa_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "cmp", "w", "ds", "ad"), dyadic(gen, "cmp", "w", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_ad", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "cmp", "w", "ea", "ad")); @@ -703,7 +709,7 @@ public class CorePLAGenerator { appendOP_eas(0xb1c0, 0xf1c0, "cmpa_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "cmp", "l", "ds", "ad"), dyadic(gen, "cmp", "l", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_ad", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "cmp", "l", "ea", "ad")); @@ -715,21 +721,21 @@ public class CorePLAGenerator { appendOP(gen, entries, array, 0xb188, 0xf1f8, "cmpm_l_aips_aipd", "ea_aips32_read", dyadic(gen, "cmpm", "l", "ea", "ea"), "ea_aipd32_read"); appendOP_eas(0xb100, 0xf1c0, "eor_b_dd", EA_FETCH | EA_MALT, "8", dyadic(gen, "eor", "b", "dd", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "eor", "b", "dd", "ea")); } }); appendOP_eas(0xb140, 0xf1c0, "eor_w_dd", EA_FETCH | EA_MALT, "16", dyadic(gen, "eor", "w", "dd", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "eor", "w", "dd", "ea")); } }); appendOP_eas(0xb180, 0xf1c0, "eor_l_dd", EA_FETCH | EA_MALT, "32", dyadic(gen, "eor", "l", "dd", "ds"), null, (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "eor", "l", "dd", "ea")); @@ -739,7 +745,7 @@ public class CorePLAGenerator { appendOP_eas(0xc000, 0xf1c0, "and_b", EA_FETCH | EA_ALL, "8", dyadic(gen, "and", "b", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "and", "b", "ea", "dd")); @@ -748,7 +754,7 @@ public class CorePLAGenerator { appendOP_eas(0xc040, 0xf1c0, "and_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "and", "w", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "and", "w", "ea", "dd")); @@ -757,7 +763,7 @@ public class CorePLAGenerator { appendOP_eas(0xc080, 0xf1c0, "and_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "and", "l", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "and", "l", "ea", "dd")); @@ -769,21 +775,21 @@ public class CorePLAGenerator { appendOP(gen, entries, array, 0xc188, 0xf1f8, "exg_dd_as", "op_exg_dd_as", "dbrr", "dbrr"); appendOP_eas(0xc100, 0xf1c0, "and_b_dd", EA_FETCH | EA_MALT, "8", (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "and", "b", "dd", "ea")); } }); appendOP_eas(0xc140, 0xf1c0, "and_w_dd", EA_FETCH | EA_MALT, "16", (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "and", "w", "dd", "ea")); } }); appendOP_eas(0xc180, 0xf1c0, "and_l_dd", EA_FETCH | EA_MALT, "32", (opcode, opmask, opname, n1, mode) -> { - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "and", "l", "dd", "ea")); @@ -796,7 +802,7 @@ public class CorePLAGenerator { appendOP_eas(0xd000, 0xf1c0, "add_b", EA_FETCH | EA_ALL, "8", dyadic(gen, "add", "b", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "b", "ea", "dd")); @@ -805,7 +811,7 @@ public class CorePLAGenerator { appendOP_eas(0xd040, 0xf1c0, "add_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "add", "w", "ds", "dd"), dyadic(gen, "add", "w", "as", "dd"), (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "w", "ea", "dd")); @@ -814,7 +820,7 @@ public class CorePLAGenerator { appendOP_eas(0xd080, 0xf1c0, "add_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "add", "l", "ds", "dd"), dyadic(gen, "add", "l", "as", "dd"), (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_dd", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "l", "ea", "dd")); @@ -842,7 +848,7 @@ public class CorePLAGenerator { appendOP_eas(0xd0c0, 0xf1c0, "adda_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "add", "w", "ds", "ad"), dyadic(gen, "add", "w", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_ad", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "w", "ea", "ad")); @@ -851,7 +857,7 @@ public class CorePLAGenerator { appendOP_eas(0xd1c0, 0xf1c0, "adda_l", EA_FETCH | EA_ALL, "32", dyadic(gen, "add", "l", "ds", "ad"), dyadic(gen, "add", "l", "as", "ad"), (opcode, opmask, opname, n1, mode) -> { opname = String.format("%s_ad", opname); - if (mode == 0) { + if ((mode & EA_ALL ) == 0) { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr"); } else { appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "add", "l", "ea", "ad")); @@ -1066,11 +1072,11 @@ public class CorePLAGenerator { public static void appendOP_ead(int opcode, int mask, String opname, int ea, String size, String ds, String as, EAConsumer consumer) { if (ds != null) { - consumer.append((opcode & 0xfe3f) | 0x0000, (mask & 0xfe3f) | 0x01c0, String.format("%s_dd", opname), ds, 0x0000); + consumer.append((opcode & 0xfe3f) | 0x0000, (mask & 0xfe3f) | 0x01c0, String.format("%s_dd", opname), ds, EA_DS); } if (as != null) { - consumer.append((opcode & 0xfe3f) | 0x0040, (mask & 0xfe3f) | 0x01c0, String.format("%s_ad", opname), as, 0x0000); + consumer.append((opcode & 0xfe3f) | 0x0040, (mask & 0xfe3f) | 0x01c0, String.format("%s_ad", opname), as, EA_AS); } appendOP_ead(opcode, mask, opname, ea, size, consumer); @@ -1116,11 +1122,11 @@ public class CorePLAGenerator { public static void appendOP_eas(int opcode, int mask, String opname, int ea, String size, String ds, String as, EAConsumer consumer) { if (ds != null) { - consumer.append((opcode & 0xffc0) | 0x0000, (mask & 0xffc0) | 0x0038, String.format("%s_ds", opname), ds, 0x0000); + consumer.append((opcode & 0xffc0) | 0x0000, (mask & 0xffc0) | 0x0038, String.format("%s_ds", opname), ds, EA_DS); } if (as != null) { - consumer.append((opcode & 0xffc0) | 0x0008, (mask & 0xffc0) | 0x0038, String.format("%s_as", opname), as, 0x0000); + consumer.append((opcode & 0xffc0) | 0x0008, (mask & 0xffc0) | 0x0038, String.format("%s_as", opname), as, EA_AS); } appendOP_eas(opcode, mask, opname, ea, size, consumer); diff --git a/miggy-emu/src/main/java/miggy/cpupoet/Core.java b/miggy-emu/src/main/java/miggy/cpupoet/Core.java index 67e7a6f..960ee6e 100644 --- a/miggy-emu/src/main/java/miggy/cpupoet/Core.java +++ b/miggy-emu/src/main/java/miggy/cpupoet/Core.java @@ -327,275 +327,275 @@ public abstract class Core extends CoreALU { protected static final int op_movepl_das_dd = 232; - protected static final int op_clrb_ds = 237; + protected static final int ea_as_dt = 237; - protected static final int op_clrw_ds = 238; + protected static final int op_clrb_ds = 238; - protected static final int op_clrl_ds = 239; + protected static final int op_clrw_ds = 239; - protected static final int op_clrb_ea = 240; + protected static final int op_clrl_ds = 240; - protected static final int op_clrw_ea = 241; + protected static final int op_clrb_ea = 241; - protected static final int op_clrl_ea = 242; + protected static final int op_clrw_ea = 242; - protected static final int op_lea_ea_ad = 243; + protected static final int op_clrl_ea = 243; - protected static final int op_pea = 244; + protected static final int op_lea_ea_ad = 244; - protected static final int op_swap_ds = 246; + protected static final int op_pea = 245; - protected static final int op_extw_ds = 247; + protected static final int op_swap_ds = 247; - protected static final int op_extl_ds = 248; + protected static final int op_extw_ds = 248; - protected static final int op_extbl_ds = 249; + protected static final int op_extl_ds = 249; - protected static final int op_exg_dd_ds = 250; + protected static final int op_extbl_ds = 250; - protected static final int op_exg_ad_as = 251; + protected static final int op_exg_dd_ds = 251; - protected static final int op_exg_dd_as = 252; + protected static final int op_exg_ad_as = 252; - protected static final int op_scc_b_ds = 253; + protected static final int op_exg_dd_as = 253; - protected static final int op_scc_b_ea = 254; + protected static final int op_scc_b_ds = 254; - protected static final int op_chk_w_ds = 255; + protected static final int op_scc_b_ea = 255; - protected static final int op_chk_w_ea = 256; + protected static final int op_chk_w_ds = 256; - protected static final int op_link_as_imm16 = 257; + protected static final int op_chk_w_ea = 257; - protected static final int op_link_as_imm32 = 259; + protected static final int op_link_as_imm16 = 258; - protected static final int op_unlk_as = 261; + protected static final int op_link_as_imm32 = 260; - protected static final int op_move_usp_as = 263; + protected static final int op_unlk_as = 262; - protected static final int op_move_as_usp = 264; + protected static final int op_move_usp_as = 264; - protected static final int op_movec_cr_rz = 265; + protected static final int op_move_as_usp = 265; - protected static final int op_movec_rz_cr = 267; + protected static final int op_movec_cr_rz = 266; - protected static final int op_movemw_rr_ea = 269; + protected static final int op_movec_rz_cr = 268; - protected static final int op_movemw_rr_pais = 272; + protected static final int op_movemw_rr_ea = 270; - protected static final int op_moveml_rr_ea = 275; + protected static final int op_movemw_rr_pais = 273; - protected static final int op_moveml_rr_pais = 278; + protected static final int op_moveml_rr_ea = 276; - protected static final int op_movemw_ea_rr = 281; + protected static final int op_moveml_rr_pais = 279; - protected static final int op_movemw_aips_rr = 285; + protected static final int op_movemw_ea_rr = 282; - protected static final int op_moveml_ea_rr = 289; + protected static final int op_movemw_aips_rr = 286; - protected static final int op_moveml_aips_rr = 293; + protected static final int op_moveml_ea_rr = 290; - protected static final int op_bcc8 = 297; + protected static final int op_moveml_aips_rr = 294; - protected static final int op_bra8 = 298; + protected static final int op_bcc8 = 298; - protected static final int op_bcc16 = 299; + protected static final int op_bra8 = 299; - protected static final int op_bra16 = 300; + protected static final int op_bcc16 = 300; - protected static final int op_bcc32 = 302; + protected static final int op_bra16 = 301; - protected static final int op_bra32 = 303; + protected static final int op_bcc32 = 303; - protected static final int op_bsr8 = 305; + protected static final int op_bra32 = 304; - protected static final int op_bsr16 = 307; + protected static final int op_bsr8 = 306; - protected static final int op_bsr32 = 310; + protected static final int op_bsr16 = 308; - protected static final int op_dbcc = 313; + protected static final int op_bsr32 = 311; - protected static final int op_bkpt = 315; + protected static final int op_dbcc = 314; - protected static final int op_illegal = 316; + protected static final int op_bkpt = 316; - protected static final int op_jmp = 317; + protected static final int op_illegal = 317; - protected static final int op_jsr = 318; + protected static final int op_jmp = 318; - protected static final int op_linea = 320; + protected static final int op_jsr = 319; - protected static final int op_linef = 321; + protected static final int op_linea = 321; - protected static final int op_nop = 322; + protected static final int op_linef = 322; - protected static final int op_rte = 323; + protected static final int op_nop = 323; - private static final int check_vob = 324; + protected static final int op_rte = 324; - private static final int rteill = 325; + private static final int check_vob = 325; - private static final int exit_trap = 326; + private static final int rteill = 326; - private static final int rte0000 = 327; + private static final int exit_trap = 327; - private static final int rte1000 = 328; + private static final int rte0000 = 328; - private static final int rte2000 = 329; + private static final int rte1000 = 329; - private static final int rte8000 = 330; + private static final int rte2000 = 330; - protected static final int op_rtr = 331; + private static final int rte8000 = 331; - protected static final int op_rts = 334; + protected static final int op_rtr = 332; - protected static final int op_reset = 336; + protected static final int op_rts = 335; - protected static final int op_trap = 337; + protected static final int op_reset = 337; - protected static final int op_trapv = 338; + protected static final int op_trap = 338; - protected static final int op_trapcc = 339; + protected static final int op_trapv = 339; - protected static final int op_trapcc16 = 340; + protected static final int op_trapcc = 340; - protected static final int op_trapcc32 = 341; + protected static final int op_trapcc16 = 341; - protected static final int gen_orb_dt_ds = 342; + protected static final int op_trapcc32 = 342; - protected static final int gen_orb_im_ea = 343; + protected static final int gen_orb_dt_ds = 343; - protected static final int gen_orw_dt_ds = 344; + protected static final int gen_orb_im_ea = 344; - protected static final int gen_orw_im_ea = 345; + protected static final int gen_orw_dt_ds = 345; - protected static final int gen_orl_dt_ds = 346; + protected static final int gen_orw_im_ea = 346; - protected static final int gen_orl_im_ea = 347; + protected static final int gen_orl_dt_ds = 347; - protected static final int gen_orb_dt_ccr = 348; + protected static final int gen_orl_im_ea = 348; - protected static final int gen_orw_dt_sr = 349; + protected static final int gen_orb_dt_ccr = 349; - protected static final int gen_btstl_dd_ds = 350; + protected static final int gen_orw_dt_sr = 350; - protected static final int gen_btstb_dd_ea = 351; + protected static final int gen_btstl_dd_ds = 351; - protected static final int gen_bchgl_dd_ds = 352; + protected static final int gen_btstb_dd_ea = 352; - protected static final int gen_bchgb_dd_ea = 353; + protected static final int gen_bchgl_dd_ds = 353; - protected static final int gen_bclrl_dd_ds = 354; + protected static final int gen_bchgb_dd_ea = 354; - protected static final int gen_bclrb_dd_ea = 355; + protected static final int gen_bclrl_dd_ds = 355; - protected static final int gen_bsetl_dd_ds = 356; + protected static final int gen_bclrb_dd_ea = 356; - protected static final int gen_bsetb_dd_ea = 357; + protected static final int gen_bsetl_dd_ds = 357; - protected static final int gen_andb_dt_ds = 358; + protected static final int gen_bsetb_dd_ea = 358; - protected static final int gen_andb_im_ea = 359; + protected static final int gen_andb_dt_ds = 359; - protected static final int gen_andw_dt_ds = 360; + protected static final int gen_andb_im_ea = 360; - protected static final int gen_andw_im_ea = 361; + protected static final int gen_andw_dt_ds = 361; - protected static final int gen_andl_dt_ds = 362; + protected static final int gen_andw_im_ea = 362; - protected static final int gen_andl_im_ea = 363; + protected static final int gen_andl_dt_ds = 363; - protected static final int gen_andb_dt_ccr = 364; + protected static final int gen_andl_im_ea = 364; - protected static final int gen_andw_dt_sr = 365; + protected static final int gen_andb_dt_ccr = 365; - protected static final int gen_subb_dt_ds = 366; + protected static final int gen_andw_dt_sr = 366; - protected static final int gen_subb_im_ea = 367; + protected static final int gen_subb_dt_ds = 367; - protected static final int gen_subw_dt_ds = 368; + protected static final int gen_subb_im_ea = 368; - protected static final int gen_subw_im_ea = 369; + protected static final int gen_subw_dt_ds = 369; - protected static final int gen_subl_dt_ds = 370; + protected static final int gen_subw_im_ea = 370; - protected static final int gen_subl_im_ea = 371; + protected static final int gen_subl_dt_ds = 371; - protected static final int gen_addb_dt_ds = 372; + protected static final int gen_subl_im_ea = 372; - protected static final int gen_addb_im_ea = 373; + protected static final int gen_addb_dt_ds = 373; - protected static final int gen_addw_dt_ds = 374; + protected static final int gen_addb_im_ea = 374; - protected static final int gen_addw_im_ea = 375; + protected static final int gen_addw_dt_ds = 375; - protected static final int gen_addl_dt_ds = 376; + protected static final int gen_addw_im_ea = 376; - protected static final int gen_addl_im_ea = 377; + protected static final int gen_addl_dt_ds = 377; - protected static final int gen_btstl_dt_ds = 378; + protected static final int gen_addl_im_ea = 378; - protected static final int gen_btstb_im_ea = 379; + protected static final int gen_btstl_dt_ds = 379; - protected static final int gen_bchgl_dt_ds = 380; + protected static final int gen_btstb_im_ea = 380; - protected static final int gen_bchgb_im_ea = 381; + protected static final int gen_bchgl_dt_ds = 381; - protected static final int gen_bclrl_dt_ds = 382; + protected static final int gen_bchgb_im_ea = 382; - protected static final int gen_bclrb_im_ea = 383; + protected static final int gen_bclrl_dt_ds = 383; - protected static final int gen_bsetl_dt_ds = 384; + protected static final int gen_bclrb_im_ea = 384; - protected static final int gen_bsetb_im_ea = 385; + protected static final int gen_bsetl_dt_ds = 385; - protected static final int gen_eorb_dt_ds = 386; + protected static final int gen_bsetb_im_ea = 386; - protected static final int gen_eorb_im_ea = 387; + protected static final int gen_eorb_dt_ds = 387; - protected static final int gen_eorw_dt_ds = 388; + protected static final int gen_eorb_im_ea = 388; - protected static final int gen_eorw_im_ea = 389; + protected static final int gen_eorw_dt_ds = 389; - protected static final int gen_eorl_dt_ds = 390; + protected static final int gen_eorw_im_ea = 390; - protected static final int gen_eorl_im_ea = 391; + protected static final int gen_eorl_dt_ds = 391; - protected static final int gen_eorb_dt_ccr = 392; + protected static final int gen_eorl_im_ea = 392; - protected static final int gen_eorw_dt_sr = 393; + protected static final int gen_eorb_dt_ccr = 393; - protected static final int gen_cmpb_dt_ds = 394; + protected static final int gen_eorw_dt_sr = 394; - protected static final int gen_cmpb_im_ea = 395; + protected static final int gen_cmpb_dt_ds = 395; - protected static final int gen_cmpw_dt_ds = 396; + protected static final int gen_cmpb_im_ea = 396; - protected static final int gen_cmpw_im_ea = 397; + protected static final int gen_cmpw_dt_ds = 397; - protected static final int gen_cmpl_dt_ds = 398; + protected static final int gen_cmpw_im_ea = 398; - protected static final int gen_cmpl_im_ea = 399; + protected static final int gen_cmpl_dt_ds = 399; - protected static final int gen_moveb_ds_ea = 400; + protected static final int gen_cmpl_im_ea = 400; - protected static final int gen_moveb_dt_dd = 401; + protected static final int gen_moveb_ds_ea = 401; - protected static final int gen_moveb_ds_dd = 402; + protected static final int gen_moveb_dt_dd = 402; - protected static final int gen_moveb_dt_ea = 403; + protected static final int gen_moveb_ds_dd = 403; - protected static final int gen_movel_ds_ea = 404; + protected static final int gen_moveb_dt_ea = 404; - protected static final int gen_movel_as_ea = 405; + protected static final int gen_movel_ds_ea = 405; - protected static final int gen_movel_dt_dd = 406; + protected static final int gen_movel_dt_ea = 406; - protected static final int gen_movel_ds_dd = 407; + protected static final int gen_movel_dt_dd = 407; - protected static final int gen_movel_as_dd = 408; + protected static final int gen_movel_ds_dd = 408; - protected static final int gen_movel_dt_ea = 409; + protected static final int gen_movel_as_dd = 409; protected static final int gen_movel_ds_ad = 410; @@ -605,7 +605,7 @@ public abstract class Core extends CoreALU { protected static final int gen_movew_ds_ea = 413; - protected static final int gen_movew_as_ea = 414; + protected static final int gen_movew_dt_ea = 414; protected static final int gen_movew_dt_dd = 415; @@ -613,381 +613,379 @@ public abstract class Core extends CoreALU { protected static final int gen_movew_as_dd = 417; - protected static final int gen_movew_dt_ea = 418; + protected static final int gen_movew_ds_ad = 418; - protected static final int gen_movew_ds_ad = 419; + protected static final int gen_movew_as_ad = 419; - protected static final int gen_movew_as_ad = 420; + protected static final int gen_movew_dt_ad = 420; - protected static final int gen_movew_dt_ad = 421; + protected static final int gen_negxb_ds = 421; - protected static final int gen_negxb_ds = 422; + protected static final int gen_negxb_ea = 422; - protected static final int gen_negxb_ea = 423; + protected static final int gen_negxw_ds = 423; - protected static final int gen_negxw_ds = 424; + protected static final int gen_negxw_ea = 424; - protected static final int gen_negxw_ea = 425; + protected static final int gen_negxl_ds = 425; - protected static final int gen_negxl_ds = 426; + protected static final int gen_negxl_ea = 426; - protected static final int gen_negxl_ea = 427; + protected static final int gen_movew_sr_ds = 427; - protected static final int gen_movew_sr_ds = 428; + protected static final int gen_movew_sr_ea = 428; - protected static final int gen_movew_sr_ea = 429; + protected static final int gen_movew_ccr_ds = 429; - protected static final int gen_movew_ccr_ds = 430; + protected static final int gen_movew_ccr_ea = 430; - protected static final int gen_movew_ccr_ea = 431; + protected static final int gen_movew_ds_ccr = 431; - protected static final int gen_movew_ds_ccr = 432; + protected static final int gen_movew_dt_ccr = 432; - protected static final int gen_movew_dt_ccr = 433; + protected static final int gen_movew_ds_sr = 433; - protected static final int gen_movew_ds_sr = 434; + protected static final int gen_movew_dt_sr = 434; - protected static final int gen_movew_dt_sr = 435; + protected static final int gen_negb_ds = 435; - protected static final int gen_negb_ds = 436; + protected static final int gen_negb_ea = 436; - protected static final int gen_negb_ea = 437; + protected static final int gen_negw_ds = 437; - protected static final int gen_negw_ds = 438; + protected static final int gen_negw_ea = 438; - protected static final int gen_negw_ea = 439; + protected static final int gen_negl_ds = 439; - protected static final int gen_negl_ds = 440; + protected static final int gen_negl_ea = 440; - protected static final int gen_negl_ea = 441; + protected static final int gen_notb_ds = 441; - protected static final int gen_notb_ds = 442; + protected static final int gen_notb_ea = 442; - protected static final int gen_notb_ea = 443; + protected static final int gen_notw_ds = 443; - protected static final int gen_notw_ds = 444; + protected static final int gen_notw_ea = 444; - protected static final int gen_notw_ea = 445; + protected static final int gen_notl_ds = 445; - protected static final int gen_notl_ds = 446; + protected static final int gen_notl_ea = 446; - protected static final int gen_notl_ea = 447; + protected static final int gen_nbcdb_ds = 447; - protected static final int gen_nbcdb_ds = 448; + protected static final int gen_nbcdb_ea = 448; - protected static final int gen_nbcdb_ea = 449; + protected static final int gen_tstb_ds = 449; - protected static final int gen_tstb_ds = 450; + protected static final int gen_tstb_ea = 450; - protected static final int gen_tstb_ea = 451; + protected static final int gen_tstw_ds = 451; - protected static final int gen_tstw_ds = 452; + protected static final int gen_tstw_ea = 452; - protected static final int gen_tstw_ea = 453; + protected static final int gen_tstl_ds = 453; - protected static final int gen_tstl_ds = 454; + protected static final int gen_tstl_ea = 454; - protected static final int gen_tstl_ea = 455; + protected static final int gen_addb_ir_ds = 455; - protected static final int gen_addb_ir_ds = 456; + protected static final int gen_addb_ir_ea = 456; - protected static final int gen_addb_ir_ea = 457; + protected static final int gen_addw_ir_ds = 457; - protected static final int gen_addw_ir_ds = 458; + protected static final int gen_addw_ir_as = 458; - protected static final int gen_addw_ir_as = 459; + protected static final int gen_addw_ir_ea = 459; - protected static final int gen_addw_ir_ea = 460; + protected static final int gen_addl_ir_ds = 460; - protected static final int gen_addl_ir_ds = 461; + protected static final int gen_addl_ir_as = 461; - protected static final int gen_addl_ir_as = 462; + protected static final int gen_addl_ir_ea = 462; - protected static final int gen_addl_ir_ea = 463; + protected static final int gen_subb_ir_ds = 463; - protected static final int gen_subb_ir_ds = 464; + protected static final int gen_subb_ir_ea = 464; - protected static final int gen_subb_ir_ea = 465; + protected static final int gen_subw_ir_ds = 465; - protected static final int gen_subw_ir_ds = 466; + protected static final int gen_subw_ir_as = 466; - protected static final int gen_subw_ir_as = 467; + protected static final int gen_subw_ir_ea = 467; - protected static final int gen_subw_ir_ea = 468; + protected static final int gen_subl_ir_ds = 468; - protected static final int gen_subl_ir_ds = 469; + protected static final int gen_subl_ir_as = 469; - protected static final int gen_subl_ir_as = 470; + protected static final int gen_subl_ir_ea = 470; - protected static final int gen_subl_ir_ea = 471; + protected static final int gen_movel_im_dd = 471; - protected static final int gen_movel_im_dd = 472; + protected static final int gen_orb_ds_dd = 472; - protected static final int gen_orb_ds_dd = 473; + protected static final int gen_orb_dt_dd = 473; - protected static final int gen_orb_dt_dd = 474; + protected static final int gen_orw_ds_dd = 474; - protected static final int gen_orw_ds_dd = 475; + protected static final int gen_orw_dt_dd = 475; - protected static final int gen_orw_dt_dd = 476; + protected static final int gen_orl_ds_dd = 476; - protected static final int gen_orl_ds_dd = 477; + protected static final int gen_orl_dt_dd = 477; - protected static final int gen_orl_dt_dd = 478; + protected static final int gen_sbcdb_ds_dd = 478; - protected static final int gen_sbcdb_ds_dd = 479; + protected static final int gen_sbcdb_im_ea = 479; - protected static final int gen_sbcdb_im_ea = 480; + protected static final int gen_orb_dd_ea = 480; - protected static final int gen_orb_dd_ea = 481; + protected static final int gen_orw_dd_ea = 481; - protected static final int gen_orw_dd_ea = 482; + protected static final int gen_orl_dd_ea = 482; - protected static final int gen_orl_dd_ea = 483; + protected static final int gen_subb_ds_dd = 483; - protected static final int gen_subb_ds_dd = 484; + protected static final int gen_subb_dt_dd = 484; - protected static final int gen_subb_dt_dd = 485; + protected static final int gen_subw_ds_dd = 485; - protected static final int gen_subw_ds_dd = 486; + protected static final int gen_subw_as_dd = 486; - protected static final int gen_subw_as_dd = 487; + protected static final int gen_subw_dt_dd = 487; - protected static final int gen_subw_dt_dd = 488; + protected static final int gen_subl_ds_dd = 488; - protected static final int gen_subl_ds_dd = 489; + protected static final int gen_subl_as_dd = 489; - protected static final int gen_subl_as_dd = 490; + protected static final int gen_subl_dt_dd = 490; - protected static final int gen_subl_dt_dd = 491; + protected static final int gen_subb_dd_ea = 491; - protected static final int gen_subb_dd_ea = 492; + protected static final int gen_subw_dd_ea = 492; - protected static final int gen_subw_dd_ea = 493; + protected static final int gen_subl_dd_ea = 493; - protected static final int gen_subl_dd_ea = 494; + protected static final int gen_subxb_ds_dd = 494; - protected static final int gen_subxb_ds_dd = 495; + protected static final int gen_subxb_im_ea = 495; - protected static final int gen_subxb_im_ea = 496; + protected static final int gen_subxw_ds_dd = 496; - protected static final int gen_subxw_ds_dd = 497; + protected static final int gen_subxw_im_ea = 497; - protected static final int gen_subxw_im_ea = 498; + protected static final int gen_subxl_ds_dd = 498; - protected static final int gen_subxl_ds_dd = 499; + protected static final int gen_subxl_im_ea = 499; - protected static final int gen_subxl_im_ea = 500; + protected static final int gen_subw_ds_ad = 500; - protected static final int gen_subw_ds_ad = 501; + protected static final int gen_subw_as_ad = 501; - protected static final int gen_subw_as_ad = 502; + protected static final int gen_subw_dt_ad = 502; - protected static final int gen_subw_dt_ad = 503; + protected static final int gen_subl_ds_ad = 503; - protected static final int gen_subl_ds_ad = 504; + protected static final int gen_subl_as_ad = 504; - protected static final int gen_subl_as_ad = 505; + protected static final int gen_subl_dt_ad = 505; - protected static final int gen_subl_dt_ad = 506; + protected static final int gen_cmpb_ds_dd = 506; - protected static final int gen_cmpb_ds_dd = 507; + protected static final int gen_cmpb_dt_dd = 507; - protected static final int gen_cmpb_dt_dd = 508; + protected static final int gen_cmpw_ds_dd = 508; - protected static final int gen_cmpw_ds_dd = 509; + protected static final int gen_cmpw_as_dd = 509; - protected static final int gen_cmpw_as_dd = 510; + protected static final int gen_cmpw_dt_dd = 510; - protected static final int gen_cmpw_dt_dd = 511; + protected static final int gen_cmpl_ds_dd = 511; - protected static final int gen_cmpl_ds_dd = 512; + protected static final int gen_cmpl_as_dd = 512; - protected static final int gen_cmpl_as_dd = 513; + protected static final int gen_cmpl_dt_dd = 513; - protected static final int gen_cmpl_dt_dd = 514; + protected static final int gen_cmpw_ds_ad = 514; - protected static final int gen_cmpw_ds_ad = 515; + protected static final int gen_cmpw_as_ad = 515; - protected static final int gen_cmpw_as_ad = 516; + protected static final int gen_cmpw_dt_ad = 516; - protected static final int gen_cmpw_dt_ad = 517; + protected static final int gen_cmpl_ds_ad = 517; - protected static final int gen_cmpl_ds_ad = 518; + protected static final int gen_cmpl_as_ad = 518; - protected static final int gen_cmpl_as_ad = 519; + protected static final int gen_cmpl_dt_ad = 519; - protected static final int gen_cmpl_dt_ad = 520; + protected static final int gen_cmpmb_im_ea = 520; - protected static final int gen_cmpmb_im_ea = 521; + protected static final int gen_cmpmw_im_ea = 521; - protected static final int gen_cmpmw_im_ea = 522; + protected static final int gen_cmpml_im_ea = 522; - protected static final int gen_cmpml_im_ea = 523; + protected static final int gen_eorb_dd_ds = 523; - protected static final int gen_eorb_dd_ds = 524; + protected static final int gen_eorb_dd_ea = 524; - protected static final int gen_eorb_dd_ea = 525; + protected static final int gen_eorw_dd_ds = 525; - protected static final int gen_eorw_dd_ds = 526; + protected static final int gen_eorw_dd_ea = 526; - protected static final int gen_eorw_dd_ea = 527; + protected static final int gen_eorl_dd_ds = 527; - protected static final int gen_eorl_dd_ds = 528; + protected static final int gen_eorl_dd_ea = 528; - protected static final int gen_eorl_dd_ea = 529; + protected static final int gen_andb_ds_dd = 529; - protected static final int gen_andb_ds_dd = 530; + protected static final int gen_andb_dt_dd = 530; - protected static final int gen_andb_dt_dd = 531; + protected static final int gen_andw_ds_dd = 531; - protected static final int gen_andw_ds_dd = 532; + protected static final int gen_andw_dt_dd = 532; - protected static final int gen_andw_dt_dd = 533; + protected static final int gen_andl_ds_dd = 533; - protected static final int gen_andl_ds_dd = 534; + protected static final int gen_andl_dt_dd = 534; - protected static final int gen_andl_dt_dd = 535; + protected static final int gen_andb_dd_ea = 535; - protected static final int gen_andb_dd_ea = 536; + protected static final int gen_andw_dd_ea = 536; - protected static final int gen_andw_dd_ea = 537; + protected static final int gen_andl_dd_ea = 537; - protected static final int gen_andl_dd_ea = 538; + protected static final int gen_abcdb_ds_dd = 538; - protected static final int gen_abcdb_ds_dd = 539; + protected static final int gen_abcdb_im_ea = 539; - protected static final int gen_abcdb_im_ea = 540; + protected static final int gen_addb_ds_dd = 540; - protected static final int gen_addb_ds_dd = 541; + protected static final int gen_addb_dt_dd = 541; - protected static final int gen_addb_dt_dd = 542; + protected static final int gen_addw_ds_dd = 542; - protected static final int gen_addw_ds_dd = 543; + protected static final int gen_addw_as_dd = 543; - protected static final int gen_addw_as_dd = 544; + protected static final int gen_addw_dt_dd = 544; - protected static final int gen_addw_dt_dd = 545; + protected static final int gen_addl_ds_dd = 545; - protected static final int gen_addl_ds_dd = 546; + protected static final int gen_addl_as_dd = 546; - protected static final int gen_addl_as_dd = 547; + protected static final int gen_addl_dt_dd = 547; - protected static final int gen_addl_dt_dd = 548; + protected static final int gen_addb_dd_ea = 548; - protected static final int gen_addb_dd_ea = 549; + protected static final int gen_addw_dd_ea = 549; - protected static final int gen_addw_dd_ea = 550; + protected static final int gen_addl_dd_ea = 550; - protected static final int gen_addl_dd_ea = 551; + protected static final int gen_addxb_ds_dd = 551; - protected static final int gen_addxb_ds_dd = 552; + protected static final int gen_addxb_im_ea = 552; - protected static final int gen_addxb_im_ea = 553; + protected static final int gen_addxw_ds_dd = 553; - protected static final int gen_addxw_ds_dd = 554; + protected static final int gen_addxw_im_ea = 554; - protected static final int gen_addxw_im_ea = 555; + protected static final int gen_addxl_ds_dd = 555; - protected static final int gen_addxl_ds_dd = 556; + protected static final int gen_addxl_im_ea = 556; - protected static final int gen_addxl_im_ea = 557; + protected static final int gen_addw_ds_ad = 557; - protected static final int gen_addw_ds_ad = 558; + protected static final int gen_addw_as_ad = 558; - protected static final int gen_addw_as_ad = 559; + protected static final int gen_addw_dt_ad = 559; - protected static final int gen_addw_dt_ad = 560; + protected static final int gen_addl_ds_ad = 560; - protected static final int gen_addl_ds_ad = 561; + protected static final int gen_addl_as_ad = 561; - protected static final int gen_addl_as_ad = 562; + protected static final int gen_addl_dt_ad = 562; - protected static final int gen_addl_dt_ad = 563; + protected static final int gen_asrb_ir_ds = 563; - protected static final int gen_asrb_ir_ds = 564; + protected static final int gen_asrb_dd_ds = 564; - protected static final int gen_asrb_dd_ds = 565; + protected static final int gen_asrw_ir_ds = 565; - protected static final int gen_asrw_ir_ds = 566; + protected static final int gen_asrw_dd_ds = 566; - protected static final int gen_asrw_dd_ds = 567; + protected static final int gen_asrl_ir_ds = 567; - protected static final int gen_asrl_ir_ds = 568; + protected static final int gen_asrl_dd_ds = 568; - protected static final int gen_asrl_dd_ds = 569; + protected static final int gen_asrw_ea = 569; - protected static final int gen_asrw_ea = 570; + protected static final int gen_aslb_ir_ds = 570; - protected static final int gen_aslb_ir_ds = 571; + protected static final int gen_aslb_dd_ds = 571; - protected static final int gen_aslb_dd_ds = 572; + protected static final int gen_aslw_ir_ds = 572; - protected static final int gen_aslw_ir_ds = 573; + protected static final int gen_aslw_dd_ds = 573; - protected static final int gen_aslw_dd_ds = 574; + protected static final int gen_asll_ir_ds = 574; - protected static final int gen_asll_ir_ds = 575; + protected static final int gen_asll_dd_ds = 575; - protected static final int gen_asll_dd_ds = 576; + protected static final int gen_aslw_ea = 576; - protected static final int gen_aslw_ea = 577; + protected static final int gen_lsrb_ir_ds = 577; - protected static final int gen_lsrb_ir_ds = 578; + protected static final int gen_lsrb_dd_ds = 578; - protected static final int gen_lsrb_dd_ds = 579; + protected static final int gen_lsrw_ir_ds = 579; - protected static final int gen_lsrw_ir_ds = 580; + protected static final int gen_lsrw_dd_ds = 580; - protected static final int gen_lsrw_dd_ds = 581; + protected static final int gen_lsrl_ir_ds = 581; - protected static final int gen_lsrl_ir_ds = 582; + protected static final int gen_lsrl_dd_ds = 582; - protected static final int gen_lsrl_dd_ds = 583; + protected static final int gen_lsrw_ea = 583; - protected static final int gen_lsrw_ea = 584; + protected static final int gen_lslb_ir_ds = 584; - protected static final int gen_lslb_ir_ds = 585; + protected static final int gen_lslb_dd_ds = 585; - protected static final int gen_lslb_dd_ds = 586; + protected static final int gen_lslw_ir_ds = 586; - protected static final int gen_lslw_ir_ds = 587; + protected static final int gen_lslw_dd_ds = 587; - protected static final int gen_lslw_dd_ds = 588; + protected static final int gen_lsll_ir_ds = 588; - protected static final int gen_lsll_ir_ds = 589; + protected static final int gen_lsll_dd_ds = 589; - protected static final int gen_lsll_dd_ds = 590; + protected static final int gen_lslw_ea = 590; - protected static final int gen_lslw_ea = 591; + protected static final int gen_rorb_ir_ds = 591; - protected static final int gen_rorb_ir_ds = 592; + protected static final int gen_rorb_dd_ds = 592; - protected static final int gen_rorb_dd_ds = 593; + protected static final int gen_rorw_ir_ds = 593; - protected static final int gen_rorw_ir_ds = 594; + protected static final int gen_rorw_dd_ds = 594; - protected static final int gen_rorw_dd_ds = 595; + protected static final int gen_rorl_ir_ds = 595; - protected static final int gen_rorl_ir_ds = 596; + protected static final int gen_rorl_dd_ds = 596; - protected static final int gen_rorl_dd_ds = 597; + protected static final int gen_rorw_ea = 597; - protected static final int gen_rorw_ea = 598; + protected static final int gen_rolb_ir_ds = 598; - protected static final int gen_rolb_ir_ds = 599; + protected static final int gen_rolb_dd_ds = 599; - protected static final int gen_rolb_dd_ds = 600; + protected static final int gen_rolw_ir_ds = 600; - protected static final int gen_rolw_ir_ds = 601; + protected static final int gen_rolw_dd_ds = 601; - protected static final int gen_rolw_dd_ds = 602; + protected static final int gen_roll_ir_ds = 602; - protected static final int gen_roll_ir_ds = 603; + protected static final int gen_roll_dd_ds = 603; - protected static final int gen_roll_dd_ds = 604; - - protected static final int gen_rolw_ea = 605; + protected static final int gen_rolw_ea = 604; public static final int BKPT_EXIT = 0x00010000; @@ -3875,49 +3873,55 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 237: /* op_clrb_ds */ + case 237: /* ea_as_dt */ + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dt = dar[ry]; + nmpc = decoded.a3; + break; + case 238: /* op_clrb_ds */ ry = ir & 0x0007; dar[ry] &= ~0xff; sr = (sr & ~0x000b) | 0x0004; mpc = resume_prefetch; continue; - case 238: /* op_clrw_ds */ + case 239: /* op_clrw_ds */ ry = ir & 0x0007; dar[ry] &= ~0xffff; sr = (sr & ~0x000b) | 0x0004; mpc = resume_prefetch; continue; - case 239: /* op_clrl_ds */ + case 240: /* op_clrl_ds */ ry = ir & 0x0007; dar[ry] = 0; sr = (sr & ~0x000b) | 0x0004; mpc = resume_prefetch; continue; - case 240: /* op_clrb_ea */ + case 241: /* op_clrb_ea */ dt = 0; sr = (sr & ~0x000b) | 0x0004; mpc = ea_resume_write8; continue; - case 241: /* op_clrw_ea */ + case 242: /* op_clrw_ea */ dt = 0; sr = (sr & ~0x000b) | 0x0004; mpc = ea_resume_write16; continue; - case 242: /* op_clrl_ea */ + case 243: /* op_clrl_ea */ dt = 0; sr = (sr & ~0x000b) | 0x0004; mpc = ea_resume_write32; continue; - case 243: /* op_lea_ea_ad */ + case 244: /* op_lea_ea_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = at; mpc = resume_prefetch; continue; - case 244: /* op_pea */ + case 245: /* op_pea */ au = dar[sp] - 4; dar[sp] = au; - nmpc = 245; + nmpc = 246; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -3929,34 +3933,34 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 245: + case 246: mpc = resume_prefetch; continue; - case 246: /* op_swap_ds */ + case 247: /* op_swap_ds */ ry = ir & 0x0007; dar[ry] = (dar[ry] << 16) | (dar[ry] >>> 16); long_tst(dar[ry]); mpc = resume_prefetch; continue; - case 247: /* op_extw_ds */ + case 248: /* op_extw_ds */ ry = ir & 0x0007; dar[ry] = (dar[ry] & ~0xffff) | (((byte) dar[ry]) & 0xffff); word_tst(dar[ry]); mpc = resume_prefetch; continue; - case 248: /* op_extl_ds */ + case 249: /* op_extl_ds */ ry = ir & 0x0007; dar[ry] = (short) dar[ry]; long_tst(dar[ry]); mpc = resume_prefetch; continue; - case 249: /* op_extbl_ds */ + case 250: /* op_extbl_ds */ ry = ir & 0x0007; dar[ry] = (byte) dar[ry]; long_tst(dar[ry]); mpc = resume_prefetch; continue; - case 250: /* op_exg_dd_ds */ + case 251: /* op_exg_dd_ds */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = dar[ry]; @@ -3964,7 +3968,7 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 251: /* op_exg_ad_as */ + case 252: /* op_exg_ad_as */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -3974,7 +3978,7 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 252: /* op_exg_dd_as */ + case 253: /* op_exg_dd_as */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -3983,7 +3987,7 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 253: /* op_scc_b_ds */ + case 254: /* op_scc_b_ds */ ry = ir & 0x0007; if (testCC((ir & 0x0f00) >> 8)) { dar[ry] |= 0xff; @@ -3992,11 +3996,11 @@ public abstract class Core extends CoreALU { } mpc = resume_prefetch; continue; - case 254: /* op_scc_b_ea */ + case 255: /* op_scc_b_ea */ dt = testCC((ir & 0x0f00) >> 8) ? -1 : 0; mpc = ea_resume_write8; continue; - case 255: /* op_chk_w_ds */ + case 256: /* op_chk_w_ds */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; if (word_chk(dar[ry], dar[rx])) { @@ -4006,7 +4010,7 @@ public abstract class Core extends CoreALU { } mpc = resume_prefetch; continue; - case 256: /* op_chk_w_ea */ + case 257: /* op_chk_w_ea */ rx = (ir >> 9) & 0x0007; if (word_chk(dt, dar[rx])) { tvn = 24; @@ -4015,11 +4019,11 @@ public abstract class Core extends CoreALU { } mpc = resume_prefetch; continue; - case 257: /* op_link_as_imm16 */ + case 258: /* op_link_as_imm16 */ au = dar[sp] - 4; ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; - nmpc = 258; + nmpc = 259; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -4031,16 +4035,16 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 258: + case 259: dar[ry] = au; dar[sp] = au + ((short) dt); mpc = resume_prefetch; continue; - case 259: /* op_link_as_imm32 */ + case 260: /* op_link_as_imm32 */ au = dar[sp] - 4; ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; - nmpc = 260; + nmpc = 261; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -4052,16 +4056,16 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 260: + case 261: dar[ry] = au; dar[sp] = au + dt; mpc = resume_prefetch; continue; - case 261: /* op_unlk_as */ + case 262: /* op_unlk_as */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; au = dar[ry]; - nmpc = 262; + nmpc = 263; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; if (((aob = au) & 0x000000001) != 0) { @@ -4073,12 +4077,12 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 262: + case 263: dar[sp] = au + 4; dar[ry] = dib; mpc = resume_prefetch; continue; - case 263: /* op_move_usp_as */ + case 264: /* op_move_usp_as */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -4090,7 +4094,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[15]; mpc = resume_prefetch; continue; - case 264: /* op_move_as_usp */ + case 265: /* op_move_as_usp */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -4102,14 +4106,14 @@ public abstract class Core extends CoreALU { dar[15] = dar[ry]; mpc = resume_prefetch; continue; - case 265: /* op_movec_cr_rz */ + case 266: /* op_movec_cr_rz */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; mpc = trapill; continue; } - nmpc = 266; + nmpc = 267; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4122,7 +4126,7 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 266: + case 267: ssw &= ~0xbfe7; rz = (irb >> 12) & 0x000f; if (rz == 0x000f) { @@ -4148,14 +4152,14 @@ public abstract class Core extends CoreALU { } mpc = resume_prefetch; continue; - case 267: /* op_movec_rz_cr */ + case 268: /* op_movec_rz_cr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; mpc = trapill; continue; } - nmpc = 268; + nmpc = 269; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4168,7 +4172,7 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 268: + case 269: ssw &= ~0xbfe7; rz = (irb >> 12) & 0x000f; if (rz == 0x000f) { @@ -4194,8 +4198,8 @@ public abstract class Core extends CoreALU { } mpc = resume_prefetch; continue; - case 269: /* op_movemw_rr_ea */ - nmpc = 270; + case 270: /* op_movemw_rr_ea */ + nmpc = 271; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4207,17 +4211,17 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 270: - alub = 0; - nmpc = 271; case 271: + alub = 0; + nmpc = 272; + case 272: if (alub >= 16) { ssw &= ~0xbfe7; mpc = resume; continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 271; + mpc = 272; continue; } rz = alub == 15 ? sp : alub; @@ -4234,10 +4238,10 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - mpc = 271; + mpc = 272; continue; - case 272: /* op_movemw_rr_pais */ - nmpc = 273; + case 273: /* op_movemw_rr_pais */ + nmpc = 274; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4249,10 +4253,10 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 273: - alub = 0; - nmpc = 274; case 274: + alub = 0; + nmpc = 275; + case 275: if (alub >= 16) { ssw &= ~0xbfe7; ry = ir & 0x0007; @@ -4262,7 +4266,7 @@ public abstract class Core extends CoreALU { continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 274; + mpc = 275; continue; } rz = alub == 0 ? sp : 15 - alub; @@ -4279,10 +4283,10 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - mpc = 274; + mpc = 275; continue; - case 275: /* op_moveml_rr_ea */ - nmpc = 276; + case 276: /* op_moveml_rr_ea */ + nmpc = 277; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4294,17 +4298,17 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 276: - alub = 0; - nmpc = 277; case 277: + alub = 0; + nmpc = 278; + case 278: if (alub >= 16) { ssw &= ~0xbfe7; mpc = resume; continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 277; + mpc = 278; continue; } rz = alub == 15 ? sp : alub; @@ -4321,10 +4325,10 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - mpc = 277; + mpc = 278; continue; - case 278: /* op_moveml_rr_pais */ - nmpc = 279; + case 279: /* op_moveml_rr_pais */ + nmpc = 280; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4336,10 +4340,10 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 279: - alub = 0; - nmpc = 280; case 280: + alub = 0; + nmpc = 281; + case 281: if (alub >= 16) { ssw &= ~0xbfe7; ry = ir & 0x0007; @@ -4349,7 +4353,7 @@ public abstract class Core extends CoreALU { continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 280; + mpc = 281; continue; } rz = alub == 0 ? sp : 15 - alub; @@ -4366,84 +4370,36 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - mpc = 280; + mpc = 281; continue; - case 281: /* op_movemw_ea_rr */ - nmpc = 282; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - irb = fetch16(aob); - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 282: - alub = 0; + case 282: /* op_movemw_ea_rr */ nmpc = 283; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } case 283: - if (alub >= 16) { - ssw &= ~0xbfe7; - mpc = resume; - continue; - } else if ((dt & (1 << alub)) == 0) { - alub += 1; - mpc = 283; - continue; - } - rz = alub == 15 ? sp : alub; + alub = 0; nmpc = 284; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9100; - if (((aob = at) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = read16(aob); - alub += 1; - at += 2; - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } case 284: - dar[rz] = (short) dib; - mpc = 283; - continue; - case 285: /* op_movemw_aips_rr */ - nmpc = 286; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - irb = fetch16(aob); - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 286: - alub = 0; - nmpc = 287; - case 287: if (alub >= 16) { ssw &= ~0xbfe7; - ry = ir & 0x0007; - ry = ry == 7 ? sp : ry | 8; - dar[ry] = at; mpc = resume; continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 287; + mpc = 284; continue; } rz = alub == 15 ? sp : alub; - nmpc = 288; + nmpc = 285; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9100; if (((aob = at) & 0x000000001) != 0) { @@ -4457,12 +4413,12 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 288: + case 285: dar[rz] = (short) dib; - mpc = 287; + mpc = 284; continue; - case 289: /* op_moveml_ea_rr */ - nmpc = 290; + case 286: /* op_movemw_aips_rr */ + nmpc = 287; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4474,55 +4430,10 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 290: + case 287: alub = 0; - nmpc = 291; - case 291: - if (alub >= 16) { - ssw &= ~0xbfe7; - mpc = resume; - continue; - } else if ((dt & (1 << alub)) == 0) { - alub += 1; - mpc = 291; - continue; - } - rz = alub == 15 ? sp : alub; - nmpc = 292; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c0; - if (((aob = at) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = read32(aob); - alub += 1; - at += 4; - if ((ssw & 0x0070) != 0x0040) { - mpc = bevtr32; - continue; - } - case 292: - dar[rz] = dib; - mpc = 291; - continue; - case 293: /* op_moveml_aips_rr */ - nmpc = 294; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - irb = fetch16(aob); - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 294: - alub = 0; - nmpc = 295; - case 295: + nmpc = 288; + case 288: if (alub >= 16) { ssw &= ~0xbfe7; ry = ir & 0x0007; @@ -4532,11 +4443,56 @@ public abstract class Core extends CoreALU { continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 295; + mpc = 288; continue; } rz = alub == 15 ? sp : alub; - nmpc = 296; + nmpc = 289; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9100; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read16(aob); + alub += 1; + at += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 289: + dar[rz] = (short) dib; + mpc = 288; + continue; + case 290: /* op_moveml_ea_rr */ + nmpc = 291; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 291: + alub = 0; + nmpc = 292; + case 292: + if (alub >= 16) { + ssw &= ~0xbfe7; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 292; + continue; + } + rz = alub == 15 ? sp : alub; + nmpc = 293; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c0; if (((aob = at) & 0x000000001) != 0) { @@ -4550,31 +4506,79 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 296: + case 293: dar[rz] = dib; - mpc = 295; + mpc = 292; continue; - case 297: /* op_bcc8 */ + case 294: /* op_moveml_aips_rr */ + nmpc = 295; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 295: + alub = 0; + nmpc = 296; + case 296: + if (alub >= 16) { + ssw &= ~0xbfe7; + ry = ir & 0x0007; + ry = ry == 7 ? sp : ry | 8; + dar[ry] = at; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 296; + continue; + } + rz = alub == 15 ? sp : alub; + nmpc = 297; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c0; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + alub += 1; + at += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 297: + dar[rz] = dib; + mpc = 296; + continue; + case 298: /* op_bcc8 */ if (!testCC((ir & 0x0f00) >> 8)) { elapsed += 2; mpc = resume_prefetch; continue; } - case 298: /* op_bra8 */ + case 299: /* op_bra8 */ elapsed += 2; scan = (byte) ir; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 299: /* op_bcc16 */ + case 300: /* op_bcc16 */ if (!testCC((ir & 0x0f00) >> 8)) { scan += 2; elapsed += 2; mpc = resume_prefetch; continue; } - case 300: /* op_bra16 */ - nmpc = 301; + case 301: /* op_bra16 */ + nmpc = 302; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4586,14 +4590,14 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 301: + case 302: dt = dib; elapsed += 2; scan = (short) dt; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 302: /* op_bcc32 */ + case 303: /* op_bcc32 */ if (!testCC((ir & 0x0f00) >> 8)) { if ((sswi & 0x0020) == 0) { scan += 4; @@ -4602,12 +4606,12 @@ public abstract class Core extends CoreALU { mpc = resume_prefetch; continue; } - case 303: /* op_bra32 */ + case 304: /* op_bra32 */ if ((sswi & 0x0020) != 0) { mpc = op_bra8; continue; } - nmpc = 304; + nmpc = 305; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4619,18 +4623,18 @@ public abstract class Core extends CoreALU { mpc = bevtf32; continue; } - case 304: + case 305: dt = dib; elapsed += 2; scan = dt; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 305: /* op_bsr8 */ + case 306: /* op_bsr8 */ elapsed += 2; au = dar[sp] - 4; dar[sp] = au; - nmpc = 306; + nmpc = 307; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -4642,13 +4646,13 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 306: + case 307: scan = (byte) ir; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 307: /* op_bsr16 */ - nmpc = 308; + case 308: /* op_bsr16 */ + nmpc = 309; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4661,12 +4665,12 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 308: + case 309: dt = dib; elapsed += 2; au = dar[sp] - 4; dar[sp] = au; - nmpc = 309; + nmpc = 310; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -4678,17 +4682,17 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 309: + case 310: scan = (short) dt; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 310: /* op_bsr32 */ + case 311: /* op_bsr32 */ if ((sswi & 0x0020) != 0) { mpc = op_bsr8; continue; } - nmpc = 311; + nmpc = 312; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c2; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4701,12 +4705,12 @@ public abstract class Core extends CoreALU { mpc = bevtf32; continue; } - case 311: + case 312: dt = dib; elapsed += 2; au = dar[sp] - 4; dar[sp] = au; - nmpc = 312; + nmpc = 313; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -4718,12 +4722,12 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 312: + case 313: scan = dt; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 313: /* op_dbcc */ + case 314: /* op_dbcc */ if (testCC((ir & 0x0f00) >> 8)) { elapsed += 2; scan += 2; @@ -4738,7 +4742,7 @@ public abstract class Core extends CoreALU { mpc = resume_prefetch; continue; } - nmpc = 314; + nmpc = 315; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4750,12 +4754,12 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 314: + case 315: scan += (short) dib; elapsed += 2; mpc = resume_prefetch; continue; - case 315: /* op_bkpt */ + case 316: /* op_bkpt */ elapsed += 6; hdlr = handle_bkpt(cip, ir & 0x0007); exit |= (hdlr & 0x00010000) != 0; @@ -4769,7 +4773,7 @@ public abstract class Core extends CoreALU { tvn = 16; mpc = trapill; continue; - case 316: /* op_illegal */ + case 317: /* op_illegal */ elapsed += 6; hdlr = handle_illegal(cip, ir); exit |= (hdlr & 0x00010000) != 0; @@ -4782,16 +4786,16 @@ public abstract class Core extends CoreALU { tvn = 16; mpc = trapill; continue; - case 317: /* op_jmp */ + case 318: /* op_jmp */ pc = at; scan = 0; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 318: /* op_jsr */ + case 319: /* op_jsr */ au = dar[sp] - 4; dar[sp] = au; - nmpc = 319; + nmpc = 320; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -4803,13 +4807,13 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 319: + case 320: pc = at; scan = 0; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 320: /* op_linea */ + case 321: /* op_linea */ elapsed += 6; hdlr = handle_linea(cip, ir & 0x0fff); exit |= (hdlr & 0x00010000) != 0; @@ -4822,15 +4826,15 @@ public abstract class Core extends CoreALU { tvn = 40; mpc = trapill; continue; - case 321: /* op_linef */ + case 322: /* op_linef */ elapsed += 6; tvn = 44; mpc = trapill; continue; - case 322: /* op_nop */ + case 323: /* op_nop */ mpc = resume_prefetch; continue; - case 323: /* op_rte */ + case 324: /* op_rte */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -4838,7 +4842,7 @@ public abstract class Core extends CoreALU { continue; } au = dar[sp]; - case 324: /* check_vob */ + case 325: /* check_vob */ elapsed += 4; ssw = (ssw & 0x0018) | 0x9105; if (((aob = au + 0x0006) & 0x000000001) != 0) { @@ -4852,12 +4856,12 @@ public abstract class Core extends CoreALU { } mpc = select_rte(dib); continue; - case 325: /* rteill */ + case 326: /* rteill */ elapsed += 6; tvn = 56; mpc = trapill; continue; - case 326: /* exit_trap */ + case 327: /* exit_trap */ elapsed += 8; ssw = (ssw & 0x0018) | 0x91c5; pc = read32(aob = au + 0x0002); @@ -4877,20 +4881,20 @@ public abstract class Core extends CoreALU { scan = 0; mpc = resume_prefetch; continue; - case 327: /* rte0000 */ + case 328: /* rte0000 */ dar[sp] = au + 8; mpc = exit_trap; continue; - case 328: /* rte1000 */ + case 329: /* rte1000 */ dar[sp] = au + 8; au = dar[sp = spi(sr | 0x1000)]; mpc = check_vob; continue; - case 329: /* rte2000 */ + case 330: /* rte2000 */ dar[sp] = au + 12; mpc = exit_trap; continue; - case 330: /* rte8000 */ + case 331: /* rte8000 */ elapsed += 6; elapsed += 8; ssw = (ssw & 0x0018) | 0x91c5; @@ -5125,9 +5129,9 @@ public abstract class Core extends CoreALU { continue; } break; - case 331: /* op_rtr */ + case 332: /* op_rtr */ au = dar[sp]; - nmpc = 332; + nmpc = 333; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; if (((aob = au + 0x0002) & 0x000000001) != 0) { @@ -5139,9 +5143,9 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 332: + case 333: pc = dib; - nmpc = 333; + nmpc = 334; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9101; dib = read16(aob = au); @@ -5149,7 +5153,7 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 333: + case 334: ssw &= ~0xbfe7; sr = (sr & ~0x001f) | (dib & 0x001f); scan = 0; @@ -5157,9 +5161,9 @@ public abstract class Core extends CoreALU { sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 334: /* op_rts */ + case 335: /* op_rts */ au = dar[sp]; - nmpc = 335; + nmpc = 336; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; if (((aob = au) & 0x000000001) != 0) { @@ -5171,7 +5175,7 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 335: + case 336: pc = dib; ssw &= ~0xbfe7; scan = 0; @@ -5179,7 +5183,7 @@ public abstract class Core extends CoreALU { sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 336: /* op_reset */ + case 337: /* op_reset */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5190,12 +5194,12 @@ public abstract class Core extends CoreALU { handle_reset(); mpc = resume_prefetch; continue; - case 337: /* op_trap */ + case 338: /* op_trap */ elapsed += 6; tvn = (32 + (ir & 0x000f)) << 2; mpc = trap0000; continue; - case 338: /* op_trapv */ + case 339: /* op_trapv */ if ((sr & 0x0002) != 0) { elapsed += 4; tvn = 28; @@ -5204,7 +5208,7 @@ public abstract class Core extends CoreALU { } mpc = resume_prefetch; continue; - case 339: /* op_trapcc */ + case 340: /* op_trapcc */ if (!testCC((ir & 0x0f00) >> 8)) { mpc = resume_prefetch; continue; @@ -5213,7 +5217,7 @@ public abstract class Core extends CoreALU { tvn = 28; mpc = trap2000; continue; - case 340: /* op_trapcc16 */ + case 341: /* op_trapcc16 */ scan += 2; if (!testCC((ir & 0x0f00) >> 8)) { mpc = resume_prefetch; @@ -5223,7 +5227,7 @@ public abstract class Core extends CoreALU { tvn = 28; mpc = trap2000; continue; - case 341: /* op_trapcc32 */ + case 342: /* op_trapcc32 */ scan += 4; if (!testCC((ir & 0x0f00) >> 8)) { mpc = resume_prefetch; @@ -5233,41 +5237,41 @@ public abstract class Core extends CoreALU { tvn = 28; mpc = trap2000; continue; - case 342: /* gen_orb_dt_ds */ + case 343: /* gen_orb_dt_ds */ ry = ir & 0x0007; dt = byte_or(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 343: /* gen_orb_im_ea */ + case 344: /* gen_orb_im_ea */ dt = byte_or(alub, dt); mpc = ea_resume_write8; continue; - case 344: /* gen_orw_dt_ds */ + case 345: /* gen_orw_dt_ds */ ry = ir & 0x0007; dt = word_or(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 345: /* gen_orw_im_ea */ + case 346: /* gen_orw_im_ea */ dt = word_or(alub, dt); mpc = ea_resume_write16; continue; - case 346: /* gen_orl_dt_ds */ + case 347: /* gen_orl_dt_ds */ ry = ir & 0x0007; dt = long_or(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 347: /* gen_orl_im_ea */ + case 348: /* gen_orl_im_ea */ dt = long_or(alub, dt); mpc = ea_resume_write32; continue; - case 348: /* gen_orb_dt_ccr */ + case 349: /* gen_orb_dt_ccr */ sr = (sr & ~0xff) | ((sr | dt) & 0x1f); mpc = resume_prefetch; continue; - case 349: /* gen_orw_dt_sr */ + case 350: /* gen_orw_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5277,88 +5281,88 @@ public abstract class Core extends CoreALU { sr = (sr | dt) & 0xf71f; mpc = resume_prefetch; continue; - case 350: /* gen_btstl_dd_ds */ + case 351: /* gen_btstl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; long_btst(dar[rx], dar[ry]); mpc = resume_prefetch; continue; - case 351: /* gen_btstb_dd_ea */ + case 352: /* gen_btstb_dd_ea */ rx = (ir >> 9) & 0x0007; byte_btst(dar[rx], dt); mpc = resume_prefetch; continue; - case 352: /* gen_bchgl_dd_ds */ + case 353: /* gen_bchgl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bchg(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 353: /* gen_bchgb_dd_ea */ + case 354: /* gen_bchgb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_bchg(dar[rx], dt); mpc = ea_resume_write8; continue; - case 354: /* gen_bclrl_dd_ds */ + case 355: /* gen_bclrl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bclr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 355: /* gen_bclrb_dd_ea */ + case 356: /* gen_bclrb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_bclr(dar[rx], dt); mpc = ea_resume_write8; continue; - case 356: /* gen_bsetl_dd_ds */ + case 357: /* gen_bsetl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bset(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 357: /* gen_bsetb_dd_ea */ + case 358: /* gen_bsetb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_bset(dar[rx], dt); mpc = ea_resume_write8; continue; - case 358: /* gen_andb_dt_ds */ + case 359: /* gen_andb_dt_ds */ ry = ir & 0x0007; dt = byte_and(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 359: /* gen_andb_im_ea */ + case 360: /* gen_andb_im_ea */ dt = byte_and(alub, dt); mpc = ea_resume_write8; continue; - case 360: /* gen_andw_dt_ds */ + case 361: /* gen_andw_dt_ds */ ry = ir & 0x0007; dt = word_and(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 361: /* gen_andw_im_ea */ + case 362: /* gen_andw_im_ea */ dt = word_and(alub, dt); mpc = ea_resume_write16; continue; - case 362: /* gen_andl_dt_ds */ + case 363: /* gen_andl_dt_ds */ ry = ir & 0x0007; dt = long_and(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 363: /* gen_andl_im_ea */ + case 364: /* gen_andl_im_ea */ dt = long_and(alub, dt); mpc = ea_resume_write32; continue; - case 364: /* gen_andb_dt_ccr */ + case 365: /* gen_andb_dt_ccr */ sr = (sr & ~0xff) | (sr & dt & 0x1f); mpc = resume_prefetch; continue; - case 365: /* gen_andw_dt_sr */ + case 366: /* gen_andw_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5368,140 +5372,140 @@ public abstract class Core extends CoreALU { sr = sr & dt; mpc = resume_prefetch; continue; - case 366: /* gen_subb_dt_ds */ + case 367: /* gen_subb_dt_ds */ ry = ir & 0x0007; dt = byte_sub(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 367: /* gen_subb_im_ea */ + case 368: /* gen_subb_im_ea */ dt = byte_sub(alub, dt); mpc = ea_resume_write8; continue; - case 368: /* gen_subw_dt_ds */ + case 369: /* gen_subw_dt_ds */ ry = ir & 0x0007; dt = word_sub(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 369: /* gen_subw_im_ea */ + case 370: /* gen_subw_im_ea */ dt = word_sub(alub, dt); mpc = ea_resume_write16; continue; - case 370: /* gen_subl_dt_ds */ + case 371: /* gen_subl_dt_ds */ ry = ir & 0x0007; dt = long_sub(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 371: /* gen_subl_im_ea */ + case 372: /* gen_subl_im_ea */ dt = long_sub(alub, dt); mpc = ea_resume_write32; continue; - case 372: /* gen_addb_dt_ds */ + case 373: /* gen_addb_dt_ds */ ry = ir & 0x0007; dt = byte_add(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 373: /* gen_addb_im_ea */ + case 374: /* gen_addb_im_ea */ dt = byte_add(alub, dt); mpc = ea_resume_write8; continue; - case 374: /* gen_addw_dt_ds */ + case 375: /* gen_addw_dt_ds */ ry = ir & 0x0007; dt = word_add(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 375: /* gen_addw_im_ea */ + case 376: /* gen_addw_im_ea */ dt = word_add(alub, dt); mpc = ea_resume_write16; continue; - case 376: /* gen_addl_dt_ds */ + case 377: /* gen_addl_dt_ds */ ry = ir & 0x0007; dt = long_add(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 377: /* gen_addl_im_ea */ + case 378: /* gen_addl_im_ea */ dt = long_add(alub, dt); mpc = ea_resume_write32; continue; - case 378: /* gen_btstl_dt_ds */ + case 379: /* gen_btstl_dt_ds */ ry = ir & 0x0007; long_btst(dt, dar[ry]); mpc = resume_prefetch; continue; - case 379: /* gen_btstb_im_ea */ + case 380: /* gen_btstb_im_ea */ byte_btst(alub, dt); mpc = resume_prefetch; continue; - case 380: /* gen_bchgl_dt_ds */ + case 381: /* gen_bchgl_dt_ds */ ry = ir & 0x0007; dt = long_bchg(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 381: /* gen_bchgb_im_ea */ + case 382: /* gen_bchgb_im_ea */ dt = byte_bchg(alub, dt); mpc = ea_resume_write8; continue; - case 382: /* gen_bclrl_dt_ds */ + case 383: /* gen_bclrl_dt_ds */ ry = ir & 0x0007; dt = long_bclr(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 383: /* gen_bclrb_im_ea */ + case 384: /* gen_bclrb_im_ea */ dt = byte_bclr(alub, dt); mpc = ea_resume_write8; continue; - case 384: /* gen_bsetl_dt_ds */ + case 385: /* gen_bsetl_dt_ds */ ry = ir & 0x0007; dt = long_bset(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 385: /* gen_bsetb_im_ea */ + case 386: /* gen_bsetb_im_ea */ dt = byte_bset(alub, dt); mpc = ea_resume_write8; continue; - case 386: /* gen_eorb_dt_ds */ + case 387: /* gen_eorb_dt_ds */ ry = ir & 0x0007; dt = byte_eor(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 387: /* gen_eorb_im_ea */ + case 388: /* gen_eorb_im_ea */ dt = byte_eor(alub, dt); mpc = ea_resume_write8; continue; - case 388: /* gen_eorw_dt_ds */ + case 389: /* gen_eorw_dt_ds */ ry = ir & 0x0007; dt = word_eor(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 389: /* gen_eorw_im_ea */ + case 390: /* gen_eorw_im_ea */ dt = word_eor(alub, dt); mpc = ea_resume_write16; continue; - case 390: /* gen_eorl_dt_ds */ + case 391: /* gen_eorl_dt_ds */ ry = ir & 0x0007; dt = long_eor(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 391: /* gen_eorl_im_ea */ + case 392: /* gen_eorl_im_ea */ dt = long_eor(alub, dt); mpc = ea_resume_write32; continue; - case 392: /* gen_eorb_dt_ccr */ + case 393: /* gen_eorb_dt_ccr */ sr = (sr & ~0xff) | ((sr ^ dt) & 0x1f); mpc = resume_prefetch; continue; - case 393: /* gen_eorw_dt_sr */ + case 394: /* gen_eorw_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5511,83 +5515,80 @@ public abstract class Core extends CoreALU { sr = (sr ^ dt) & 0xf71f; mpc = resume_prefetch; continue; - case 394: /* gen_cmpb_dt_ds */ + case 395: /* gen_cmpb_dt_ds */ ry = ir & 0x0007; byte_cmp(dt, dar[ry]); mpc = resume_prefetch; continue; - case 395: /* gen_cmpb_im_ea */ + case 396: /* gen_cmpb_im_ea */ byte_cmp(alub, dt); mpc = resume_prefetch; continue; - case 396: /* gen_cmpw_dt_ds */ + case 397: /* gen_cmpw_dt_ds */ ry = ir & 0x0007; word_cmp(dt, dar[ry]); mpc = resume_prefetch; continue; - case 397: /* gen_cmpw_im_ea */ + case 398: /* gen_cmpw_im_ea */ word_cmp(alub, dt); mpc = resume_prefetch; continue; - case 398: /* gen_cmpl_dt_ds */ + case 399: /* gen_cmpl_dt_ds */ ry = ir & 0x0007; long_cmp(dt, dar[ry]); mpc = resume_prefetch; continue; - case 399: /* gen_cmpl_im_ea */ + case 400: /* gen_cmpl_im_ea */ long_cmp(alub, dt); mpc = resume_prefetch; continue; - case 400: /* gen_moveb_ds_ea */ + case 401: /* gen_moveb_ds_ea */ ry = ir & 0x0007; byte_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write8; continue; - case 401: /* gen_moveb_dt_dd */ + case 402: /* gen_moveb_dt_dd */ rx = (ir >> 9) & 0x0007; byte_tst(dt); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 402: /* gen_moveb_ds_dd */ + case 403: /* gen_moveb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; byte_tst(dar[ry]); dar[rx] = (dar[rx] & ~0xff) | (dar[ry] & 0xff); mpc = resume_prefetch; continue; - case 403: /* gen_moveb_dt_ea */ + case 404: /* gen_moveb_dt_ea */ byte_tst(dt); mpc = ea_resume_write8; continue; - case 404: /* gen_movel_ds_ea */ + case 405: /* gen_movel_ds_ea */ ry = ir & 0x0007; long_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write32; continue; - case 405: /* gen_movel_as_ea */ - ry = ir & 0x0007; - ry = ry == 7 ? sp : ry | 8; - long_tst(dar[ry]); - dt = dar[ry]; + case 406: /* gen_movel_dt_ea */ + long_tst(dt); mpc = ea_resume_write32; continue; - case 406: /* gen_movel_dt_dd */ + case 407: /* gen_movel_dt_dd */ rx = (ir >> 9) & 0x0007; long_tst(dt); dar[rx] = dt; mpc = resume_prefetch; continue; - case 407: /* gen_movel_ds_dd */ + case 408: /* gen_movel_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; long_tst(dar[ry]); dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 408: /* gen_movel_as_dd */ + case 409: /* gen_movel_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5595,10 +5596,6 @@ public abstract class Core extends CoreALU { dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 409: /* gen_movel_dt_ea */ - long_tst(dt); - mpc = ea_resume_write32; - continue; case 410: /* gen_movel_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; @@ -5626,11 +5623,8 @@ public abstract class Core extends CoreALU { dt = dar[ry]; mpc = ea_resume_write16; continue; - case 414: /* gen_movew_as_ea */ - ry = ir & 0x0007; - ry = ry == 7 ? sp : ry | 8; - word_tst(dar[ry]); - dt = dar[ry]; + case 414: /* gen_movew_dt_ea */ + word_tst(dt); mpc = ea_resume_write16; continue; case 415: /* gen_movew_dt_dd */ @@ -5654,18 +5648,14 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dar[ry] & 0xffff); mpc = resume_prefetch; continue; - case 418: /* gen_movew_dt_ea */ - word_tst(dt); - mpc = ea_resume_write16; - continue; - case 419: /* gen_movew_ds_ad */ + case 418: /* gen_movew_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = (short) dar[ry]; mpc = resume_prefetch; continue; - case 420: /* gen_movew_as_ad */ + case 419: /* gen_movew_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5673,43 +5663,43 @@ public abstract class Core extends CoreALU { dar[rx] = (short) dar[ry]; mpc = resume_prefetch; continue; - case 421: /* gen_movew_dt_ad */ + case 420: /* gen_movew_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = (short) dt; mpc = resume_prefetch; continue; - case 422: /* gen_negxb_ds */ + case 421: /* gen_negxb_ds */ ry = ir & 0x0007; dt = byte_negx(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 423: /* gen_negxb_ea */ + case 422: /* gen_negxb_ea */ dt = byte_negx(dt); mpc = ea_resume_write8; continue; - case 424: /* gen_negxw_ds */ + case 423: /* gen_negxw_ds */ ry = ir & 0x0007; dt = word_negx(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 425: /* gen_negxw_ea */ + case 424: /* gen_negxw_ea */ dt = word_negx(dt); mpc = ea_resume_write16; continue; - case 426: /* gen_negxl_ds */ + case 425: /* gen_negxl_ds */ ry = ir & 0x0007; dt = long_negx(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 427: /* gen_negxl_ea */ + case 426: /* gen_negxl_ea */ dt = long_negx(dt); mpc = ea_resume_write32; continue; - case 428: /* gen_movew_sr_ds */ + case 427: /* gen_movew_sr_ds */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5720,7 +5710,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (sr & 0xffff); mpc = resume_prefetch; continue; - case 429: /* gen_movew_sr_ea */ + case 428: /* gen_movew_sr_ea */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5730,25 +5720,25 @@ public abstract class Core extends CoreALU { dt = (sr & 0xf71f); mpc = ea_resume_write16; continue; - case 430: /* gen_movew_ccr_ds */ + case 429: /* gen_movew_ccr_ds */ ry = ir & 0x0007; dar[ry] = (dar[ry] & ~0xffff) | (sr & 0x001f); mpc = resume_prefetch; continue; - case 431: /* gen_movew_ccr_ea */ + case 430: /* gen_movew_ccr_ea */ dt = (sr & 0x001f); mpc = ea_resume_write16; continue; - case 432: /* gen_movew_ds_ccr */ + case 431: /* gen_movew_ds_ccr */ ry = ir & 0x0007; sr = (sr & ~0xff) | (dar[ry] & 0x001f); mpc = resume_prefetch; continue; - case 433: /* gen_movew_dt_ccr */ + case 432: /* gen_movew_dt_ccr */ sr = (sr & ~0xff) | (dt & 0x001f); mpc = resume_prefetch; continue; - case 434: /* gen_movew_ds_sr */ + case 433: /* gen_movew_ds_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5759,7 +5749,7 @@ public abstract class Core extends CoreALU { sr = dar[ry] & 0xf71f; mpc = resume_prefetch; continue; - case 435: /* gen_movew_dt_sr */ + case 434: /* gen_movew_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5769,104 +5759,104 @@ public abstract class Core extends CoreALU { sr = dt & 0xf71f; mpc = resume_prefetch; continue; - case 436: /* gen_negb_ds */ + case 435: /* gen_negb_ds */ ry = ir & 0x0007; dt = byte_neg(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 437: /* gen_negb_ea */ + case 436: /* gen_negb_ea */ dt = byte_neg(dt); mpc = ea_resume_write8; continue; - case 438: /* gen_negw_ds */ + case 437: /* gen_negw_ds */ ry = ir & 0x0007; dt = word_neg(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 439: /* gen_negw_ea */ + case 438: /* gen_negw_ea */ dt = word_neg(dt); mpc = ea_resume_write16; continue; - case 440: /* gen_negl_ds */ + case 439: /* gen_negl_ds */ ry = ir & 0x0007; dt = long_neg(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 441: /* gen_negl_ea */ + case 440: /* gen_negl_ea */ dt = long_neg(dt); mpc = ea_resume_write32; continue; - case 442: /* gen_notb_ds */ + case 441: /* gen_notb_ds */ ry = ir & 0x0007; dt = byte_not(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 443: /* gen_notb_ea */ + case 442: /* gen_notb_ea */ dt = byte_not(dt); mpc = ea_resume_write8; continue; - case 444: /* gen_notw_ds */ + case 443: /* gen_notw_ds */ ry = ir & 0x0007; dt = word_not(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 445: /* gen_notw_ea */ + case 444: /* gen_notw_ea */ dt = word_not(dt); mpc = ea_resume_write16; continue; - case 446: /* gen_notl_ds */ + case 445: /* gen_notl_ds */ ry = ir & 0x0007; dt = long_not(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 447: /* gen_notl_ea */ + case 446: /* gen_notl_ea */ dt = long_not(dt); mpc = ea_resume_write32; continue; - case 448: /* gen_nbcdb_ds */ + case 447: /* gen_nbcdb_ds */ ry = ir & 0x0007; dt = byte_nbcd(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 449: /* gen_nbcdb_ea */ + case 448: /* gen_nbcdb_ea */ dt = byte_nbcd(dt); mpc = ea_resume_write8; continue; - case 450: /* gen_tstb_ds */ + case 449: /* gen_tstb_ds */ ry = ir & 0x0007; byte_tst(dar[ry]); mpc = resume_prefetch; continue; - case 451: /* gen_tstb_ea */ + case 450: /* gen_tstb_ea */ byte_tst(dt); mpc = resume_prefetch; continue; - case 452: /* gen_tstw_ds */ + case 451: /* gen_tstw_ds */ ry = ir & 0x0007; word_tst(dar[ry]); mpc = resume_prefetch; continue; - case 453: /* gen_tstw_ea */ + case 452: /* gen_tstw_ea */ word_tst(dt); mpc = resume_prefetch; continue; - case 454: /* gen_tstl_ds */ + case 453: /* gen_tstl_ds */ ry = ir & 0x0007; long_tst(dar[ry]); mpc = resume_prefetch; continue; - case 455: /* gen_tstl_ea */ + case 454: /* gen_tstl_ea */ long_tst(dt); mpc = resume_prefetch; continue; - case 456: /* gen_addb_ir_ds */ + case 455: /* gen_addb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5876,7 +5866,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 457: /* gen_addb_ir_ea */ + case 456: /* gen_addb_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5884,7 +5874,7 @@ public abstract class Core extends CoreALU { dt = byte_add(alub, dt); mpc = ea_resume_write8; continue; - case 458: /* gen_addw_ir_ds */ + case 457: /* gen_addw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5894,7 +5884,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 459: /* gen_addw_ir_as */ + case 458: /* gen_addw_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5904,7 +5894,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] + ((short) alub); mpc = resume_prefetch; continue; - case 460: /* gen_addw_ir_ea */ + case 459: /* gen_addw_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5912,7 +5902,7 @@ public abstract class Core extends CoreALU { dt = word_add(alub, dt); mpc = ea_resume_write16; continue; - case 461: /* gen_addl_ir_ds */ + case 460: /* gen_addl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5922,7 +5912,7 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 462: /* gen_addl_ir_as */ + case 461: /* gen_addl_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5932,7 +5922,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] + alub; mpc = resume_prefetch; continue; - case 463: /* gen_addl_ir_ea */ + case 462: /* gen_addl_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5940,7 +5930,7 @@ public abstract class Core extends CoreALU { dt = long_add(alub, dt); mpc = ea_resume_write32; continue; - case 464: /* gen_subb_ir_ds */ + case 463: /* gen_subb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5950,7 +5940,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 465: /* gen_subb_ir_ea */ + case 464: /* gen_subb_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5958,7 +5948,7 @@ public abstract class Core extends CoreALU { dt = byte_sub(alub, dt); mpc = ea_resume_write8; continue; - case 466: /* gen_subw_ir_ds */ + case 465: /* gen_subw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5968,7 +5958,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 467: /* gen_subw_ir_as */ + case 466: /* gen_subw_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5978,7 +5968,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] - ((short) alub); mpc = resume_prefetch; continue; - case 468: /* gen_subw_ir_ea */ + case 467: /* gen_subw_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5986,7 +5976,7 @@ public abstract class Core extends CoreALU { dt = word_sub(alub, dt); mpc = ea_resume_write16; continue; - case 469: /* gen_subl_ir_ds */ + case 468: /* gen_subl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5996,7 +5986,7 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 470: /* gen_subl_ir_as */ + case 469: /* gen_subl_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6006,7 +5996,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] - alub; mpc = resume_prefetch; continue; - case 471: /* gen_subl_ir_ea */ + case 470: /* gen_subl_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6014,99 +6004,99 @@ public abstract class Core extends CoreALU { dt = long_sub(alub, dt); mpc = ea_resume_write32; continue; - case 472: /* gen_movel_im_dd */ + case 471: /* gen_movel_im_dd */ dt = (byte) ir; rx = (ir >> 9) & 0x0007; long_tst(dt); dar[rx] = dt; mpc = resume_prefetch; continue; - case 473: /* gen_orb_ds_dd */ + case 472: /* gen_orb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_or(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 474: /* gen_orb_dt_dd */ + case 473: /* gen_orb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_or(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 475: /* gen_orw_ds_dd */ + case 474: /* gen_orw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_or(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 476: /* gen_orw_dt_dd */ + case 475: /* gen_orw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_or(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 477: /* gen_orl_ds_dd */ + case 476: /* gen_orl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_or(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 478: /* gen_orl_dt_dd */ + case 477: /* gen_orl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_or(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 479: /* gen_sbcdb_ds_dd */ + case 478: /* gen_sbcdb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_sbcd(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 480: /* gen_sbcdb_im_ea */ + case 479: /* gen_sbcdb_im_ea */ dt = byte_sbcd(alub, dt); mpc = ea_resume_write8; continue; - case 481: /* gen_orb_dd_ea */ + case 480: /* gen_orb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_or(dar[rx], dt); mpc = ea_resume_write8; continue; - case 482: /* gen_orw_dd_ea */ + case 481: /* gen_orw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_or(dar[rx], dt); mpc = ea_resume_write16; continue; - case 483: /* gen_orl_dd_ea */ + case 482: /* gen_orl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_or(dar[rx], dt); mpc = ea_resume_write32; continue; - case 484: /* gen_subb_ds_dd */ + case 483: /* gen_subb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_sub(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 485: /* gen_subb_dt_dd */ + case 484: /* gen_subb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_sub(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 486: /* gen_subw_ds_dd */ + case 485: /* gen_subw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_sub(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 487: /* gen_subw_as_dd */ + case 486: /* gen_subw_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6114,20 +6104,20 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 488: /* gen_subw_dt_dd */ + case 487: /* gen_subw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_sub(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 489: /* gen_subl_ds_dd */ + case 488: /* gen_subl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_sub(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 490: /* gen_subl_as_dd */ + case 489: /* gen_subl_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6135,68 +6125,68 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 491: /* gen_subl_dt_dd */ + case 490: /* gen_subl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_sub(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 492: /* gen_subb_dd_ea */ + case 491: /* gen_subb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_sub(dar[rx], dt); mpc = ea_resume_write8; continue; - case 493: /* gen_subw_dd_ea */ + case 492: /* gen_subw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_sub(dar[rx], dt); mpc = ea_resume_write16; continue; - case 494: /* gen_subl_dd_ea */ + case 493: /* gen_subl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_sub(dar[rx], dt); mpc = ea_resume_write32; continue; - case 495: /* gen_subxb_ds_dd */ + case 494: /* gen_subxb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_subx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 496: /* gen_subxb_im_ea */ + case 495: /* gen_subxb_im_ea */ dt = byte_subx(alub, dt); mpc = ea_resume_write8; continue; - case 497: /* gen_subxw_ds_dd */ + case 496: /* gen_subxw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_subx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 498: /* gen_subxw_im_ea */ + case 497: /* gen_subxw_im_ea */ dt = word_subx(alub, dt); mpc = ea_resume_write16; continue; - case 499: /* gen_subxl_ds_dd */ + case 498: /* gen_subxl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_subx(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 500: /* gen_subxl_im_ea */ + case 499: /* gen_subxl_im_ea */ dt = long_subx(alub, dt); mpc = ea_resume_write32; continue; - case 501: /* gen_subw_ds_ad */ + case 500: /* gen_subw_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - ((short) dar[ry]); mpc = resume_prefetch; continue; - case 502: /* gen_subw_as_ad */ + case 501: /* gen_subw_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6204,20 +6194,20 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] - ((short) dar[ry]); mpc = resume_prefetch; continue; - case 503: /* gen_subw_dt_ad */ + case 502: /* gen_subw_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - ((short) dt); mpc = resume_prefetch; continue; - case 504: /* gen_subl_ds_ad */ + case 503: /* gen_subl_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - dar[ry]; mpc = resume_prefetch; continue; - case 505: /* gen_subl_as_ad */ + case 504: /* gen_subl_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6225,67 +6215,67 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] - dar[ry]; mpc = resume_prefetch; continue; - case 506: /* gen_subl_dt_ad */ + case 505: /* gen_subl_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - dt; mpc = resume_prefetch; continue; - case 507: /* gen_cmpb_ds_dd */ + case 506: /* gen_cmpb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; byte_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 508: /* gen_cmpb_dt_dd */ + case 507: /* gen_cmpb_dt_dd */ rx = (ir >> 9) & 0x0007; byte_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 509: /* gen_cmpw_ds_dd */ + case 508: /* gen_cmpw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; word_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 510: /* gen_cmpw_as_dd */ + case 509: /* gen_cmpw_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; word_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 511: /* gen_cmpw_dt_dd */ + case 510: /* gen_cmpw_dt_dd */ rx = (ir >> 9) & 0x0007; word_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 512: /* gen_cmpl_ds_dd */ + case 511: /* gen_cmpl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 513: /* gen_cmpl_as_dd */ + case 512: /* gen_cmpl_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 514: /* gen_cmpl_dt_dd */ + case 513: /* gen_cmpl_dt_dd */ rx = (ir >> 9) & 0x0007; long_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 515: /* gen_cmpw_ds_ad */ + case 514: /* gen_cmpw_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp((short) dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 516: /* gen_cmpw_as_ad */ + case 515: /* gen_cmpw_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6293,20 +6283,20 @@ public abstract class Core extends CoreALU { long_cmp((short) dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 517: /* gen_cmpw_dt_ad */ + case 516: /* gen_cmpw_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp((short) dt, dar[rx]); mpc = resume_prefetch; continue; - case 518: /* gen_cmpl_ds_ad */ + case 517: /* gen_cmpl_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 519: /* gen_cmpl_as_ad */ + case 518: /* gen_cmpl_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6314,146 +6304,146 @@ public abstract class Core extends CoreALU { long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 520: /* gen_cmpl_dt_ad */ + case 519: /* gen_cmpl_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 521: /* gen_cmpmb_im_ea */ + case 520: /* gen_cmpmb_im_ea */ byte_cmp(alub, dt); mpc = resume_prefetch; continue; - case 522: /* gen_cmpmw_im_ea */ + case 521: /* gen_cmpmw_im_ea */ word_cmp(alub, dt); mpc = resume_prefetch; continue; - case 523: /* gen_cmpml_im_ea */ + case 522: /* gen_cmpml_im_ea */ long_cmp(alub, dt); mpc = resume_prefetch; continue; - case 524: /* gen_eorb_dd_ds */ + case 523: /* gen_eorb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_eor(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 525: /* gen_eorb_dd_ea */ + case 524: /* gen_eorb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_eor(dar[rx], dt); mpc = ea_resume_write8; continue; - case 526: /* gen_eorw_dd_ds */ + case 525: /* gen_eorw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_eor(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 527: /* gen_eorw_dd_ea */ + case 526: /* gen_eorw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_eor(dar[rx], dt); mpc = ea_resume_write16; continue; - case 528: /* gen_eorl_dd_ds */ + case 527: /* gen_eorl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_eor(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 529: /* gen_eorl_dd_ea */ + case 528: /* gen_eorl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_eor(dar[rx], dt); mpc = ea_resume_write32; continue; - case 530: /* gen_andb_ds_dd */ + case 529: /* gen_andb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_and(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 531: /* gen_andb_dt_dd */ + case 530: /* gen_andb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_and(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 532: /* gen_andw_ds_dd */ + case 531: /* gen_andw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_and(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 533: /* gen_andw_dt_dd */ + case 532: /* gen_andw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_and(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 534: /* gen_andl_ds_dd */ + case 533: /* gen_andl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_and(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 535: /* gen_andl_dt_dd */ + case 534: /* gen_andl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_and(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 536: /* gen_andb_dd_ea */ + case 535: /* gen_andb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_and(dar[rx], dt); mpc = ea_resume_write8; continue; - case 537: /* gen_andw_dd_ea */ + case 536: /* gen_andw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_and(dar[rx], dt); mpc = ea_resume_write16; continue; - case 538: /* gen_andl_dd_ea */ + case 537: /* gen_andl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_and(dar[rx], dt); mpc = ea_resume_write32; continue; - case 539: /* gen_abcdb_ds_dd */ + case 538: /* gen_abcdb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_abcd(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 540: /* gen_abcdb_im_ea */ + case 539: /* gen_abcdb_im_ea */ dt = byte_abcd(alub, dt); mpc = ea_resume_write8; continue; - case 541: /* gen_addb_ds_dd */ + case 540: /* gen_addb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_add(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 542: /* gen_addb_dt_dd */ + case 541: /* gen_addb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_add(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 543: /* gen_addw_ds_dd */ + case 542: /* gen_addw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_add(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 544: /* gen_addw_as_dd */ + case 543: /* gen_addw_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6461,20 +6451,20 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 545: /* gen_addw_dt_dd */ + case 544: /* gen_addw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_add(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 546: /* gen_addl_ds_dd */ + case 545: /* gen_addl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_add(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 547: /* gen_addl_as_dd */ + case 546: /* gen_addl_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6482,68 +6472,68 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 548: /* gen_addl_dt_dd */ + case 547: /* gen_addl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_add(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 549: /* gen_addb_dd_ea */ + case 548: /* gen_addb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_add(dar[rx], dt); mpc = ea_resume_write8; continue; - case 550: /* gen_addw_dd_ea */ + case 549: /* gen_addw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_add(dar[rx], dt); mpc = ea_resume_write16; continue; - case 551: /* gen_addl_dd_ea */ + case 550: /* gen_addl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_add(dar[rx], dt); mpc = ea_resume_write32; continue; - case 552: /* gen_addxb_ds_dd */ + case 551: /* gen_addxb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_addx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 553: /* gen_addxb_im_ea */ + case 552: /* gen_addxb_im_ea */ dt = byte_addx(alub, dt); mpc = ea_resume_write8; continue; - case 554: /* gen_addxw_ds_dd */ + case 553: /* gen_addxw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_addx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 555: /* gen_addxw_im_ea */ + case 554: /* gen_addxw_im_ea */ dt = word_addx(alub, dt); mpc = ea_resume_write16; continue; - case 556: /* gen_addxl_ds_dd */ + case 555: /* gen_addxl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_addx(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 557: /* gen_addxl_im_ea */ + case 556: /* gen_addxl_im_ea */ dt = long_addx(alub, dt); mpc = ea_resume_write32; continue; - case 558: /* gen_addw_ds_ad */ + case 557: /* gen_addw_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + ((short) dar[ry]); mpc = resume_prefetch; continue; - case 559: /* gen_addw_as_ad */ + case 558: /* gen_addw_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6551,20 +6541,20 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] + ((short) dar[ry]); mpc = resume_prefetch; continue; - case 560: /* gen_addw_dt_ad */ + case 559: /* gen_addw_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + ((short) dt); mpc = resume_prefetch; continue; - case 561: /* gen_addl_ds_ad */ + case 560: /* gen_addl_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + dar[ry]; mpc = resume_prefetch; continue; - case 562: /* gen_addl_as_ad */ + case 561: /* gen_addl_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6572,13 +6562,13 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] + dar[ry]; mpc = resume_prefetch; continue; - case 563: /* gen_addl_dt_ad */ + case 562: /* gen_addl_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + dt; mpc = resume_prefetch; continue; - case 564: /* gen_asrb_ir_ds */ + case 563: /* gen_asrb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6588,14 +6578,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 565: /* gen_asrb_dd_ds */ + case 564: /* gen_asrb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_asr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 566: /* gen_asrw_ir_ds */ + case 565: /* gen_asrw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6605,14 +6595,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 567: /* gen_asrw_dd_ds */ + case 566: /* gen_asrw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_asr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 568: /* gen_asrl_ir_ds */ + case 567: /* gen_asrl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6622,18 +6612,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 569: /* gen_asrl_dd_ds */ + case 568: /* gen_asrl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_asr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 570: /* gen_asrw_ea */ + case 569: /* gen_asrw_ea */ dt = word_asr(1, dt); mpc = ea_resume_write16; continue; - case 571: /* gen_aslb_ir_ds */ + case 570: /* gen_aslb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6643,14 +6633,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 572: /* gen_aslb_dd_ds */ + case 571: /* gen_aslb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_asl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 573: /* gen_aslw_ir_ds */ + case 572: /* gen_aslw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6660,14 +6650,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 574: /* gen_aslw_dd_ds */ + case 573: /* gen_aslw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_asl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 575: /* gen_asll_ir_ds */ + case 574: /* gen_asll_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6677,18 +6667,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 576: /* gen_asll_dd_ds */ + case 575: /* gen_asll_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_asl(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 577: /* gen_aslw_ea */ + case 576: /* gen_aslw_ea */ dt = word_asl(1, dt); mpc = ea_resume_write16; continue; - case 578: /* gen_lsrb_ir_ds */ + case 577: /* gen_lsrb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6698,14 +6688,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 579: /* gen_lsrb_dd_ds */ + case 578: /* gen_lsrb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_lsr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 580: /* gen_lsrw_ir_ds */ + case 579: /* gen_lsrw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6715,14 +6705,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 581: /* gen_lsrw_dd_ds */ + case 580: /* gen_lsrw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_lsr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 582: /* gen_lsrl_ir_ds */ + case 581: /* gen_lsrl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6732,18 +6722,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 583: /* gen_lsrl_dd_ds */ + case 582: /* gen_lsrl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_lsr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 584: /* gen_lsrw_ea */ + case 583: /* gen_lsrw_ea */ dt = word_lsr(1, dt); mpc = ea_resume_write16; continue; - case 585: /* gen_lslb_ir_ds */ + case 584: /* gen_lslb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6753,14 +6743,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 586: /* gen_lslb_dd_ds */ + case 585: /* gen_lslb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_lsl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 587: /* gen_lslw_ir_ds */ + case 586: /* gen_lslw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6770,14 +6760,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 588: /* gen_lslw_dd_ds */ + case 587: /* gen_lslw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_lsl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 589: /* gen_lsll_ir_ds */ + case 588: /* gen_lsll_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6787,18 +6777,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 590: /* gen_lsll_dd_ds */ + case 589: /* gen_lsll_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_lsl(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 591: /* gen_lslw_ea */ + case 590: /* gen_lslw_ea */ dt = word_lsl(1, dt); mpc = ea_resume_write16; continue; - case 592: /* gen_rorb_ir_ds */ + case 591: /* gen_rorb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6808,14 +6798,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 593: /* gen_rorb_dd_ds */ + case 592: /* gen_rorb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_ror(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 594: /* gen_rorw_ir_ds */ + case 593: /* gen_rorw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6825,14 +6815,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 595: /* gen_rorw_dd_ds */ + case 594: /* gen_rorw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_ror(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 596: /* gen_rorl_ir_ds */ + case 595: /* gen_rorl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6842,18 +6832,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 597: /* gen_rorl_dd_ds */ + case 596: /* gen_rorl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_ror(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 598: /* gen_rorw_ea */ + case 597: /* gen_rorw_ea */ dt = word_ror(1, dt); mpc = ea_resume_write16; continue; - case 599: /* gen_rolb_ir_ds */ + case 598: /* gen_rolb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6863,14 +6853,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 600: /* gen_rolb_dd_ds */ + case 599: /* gen_rolb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_rol(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 601: /* gen_rolw_ir_ds */ + case 600: /* gen_rolw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6880,14 +6870,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 602: /* gen_rolw_dd_ds */ + case 601: /* gen_rolw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_rol(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 603: /* gen_roll_ir_ds */ + case 602: /* gen_roll_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6897,14 +6887,14 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 604: /* gen_roll_dd_ds */ + case 603: /* gen_roll_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_rol(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 605: /* gen_rolw_ea */ + case 604: /* gen_rolw_ea */ dt = word_rol(1, dt); mpc = ea_resume_write16; continue; diff --git a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java index 16767a2..f248020 100644 --- a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java +++ b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java @@ -40,6 +40,7 @@ import static miggy.cpupoet.Core.ea_ais32; import static miggy.cpupoet.Core.ea_ais32_read; import static miggy.cpupoet.Core.ea_ais8; import static miggy.cpupoet.Core.ea_ais8_read; +import static miggy.cpupoet.Core.ea_as_dt; import static miggy.cpupoet.Core.ea_dad16; import static miggy.cpupoet.Core.ea_dad32; import static miggy.cpupoet.Core.ea_dad8; @@ -226,7 +227,6 @@ import static miggy.cpupoet.Core.gen_moveb_dt_dd; import static miggy.cpupoet.Core.gen_moveb_dt_ea; import static miggy.cpupoet.Core.gen_movel_as_ad; import static miggy.cpupoet.Core.gen_movel_as_dd; -import static miggy.cpupoet.Core.gen_movel_as_ea; import static miggy.cpupoet.Core.gen_movel_ds_ad; import static miggy.cpupoet.Core.gen_movel_ds_dd; import static miggy.cpupoet.Core.gen_movel_ds_ea; @@ -236,7 +236,6 @@ import static miggy.cpupoet.Core.gen_movel_dt_ea; import static miggy.cpupoet.Core.gen_movel_im_dd; import static miggy.cpupoet.Core.gen_movew_as_ad; import static miggy.cpupoet.Core.gen_movew_as_dd; -import static miggy.cpupoet.Core.gen_movew_as_ea; import static miggy.cpupoet.Core.gen_movew_ccr_ds; import static miggy.cpupoet.Core.gen_movew_ccr_ea; import static miggy.cpupoet.Core.gen_movew_ds_ad; @@ -1088,7 +1087,7 @@ public enum MacroPLA { move_l_ds_aid(0x2080, 0xf1f8, ea_aid32, gen_movel_ds_ea, dbrr), - move_l_as_aid(0x2088, 0xf1f8, ea_aid32, gen_movel_as_ea, dbrr), + move_l_as_aid(0x2088, 0xf1f8, ea_as_dt, gen_movel_dt_ea, ea_aid32), move_l_ais_aid(0x2090, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_aid32), @@ -1112,7 +1111,7 @@ public enum MacroPLA { move_l_ds_aipd(0x20c0, 0xf1f8, ea_aipd32, gen_movel_ds_ea, dbrr), - move_l_as_aipd(0x20c8, 0xf1f8, ea_aipd32, gen_movel_as_ea, dbrr), + move_l_as_aipd(0x20c8, 0xf1f8, ea_as_dt, gen_movel_dt_ea, ea_aipd32), move_l_ais_aipd(0x20d0, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_aipd32), @@ -1136,7 +1135,7 @@ public enum MacroPLA { move_l_ds_paid(0x2100, 0xf1f8, ea_paid32, gen_movel_ds_ea, dbrr), - move_l_as_paid(0x2108, 0xf1f8, ea_paid32, gen_movel_as_ea, dbrr), + move_l_as_paid(0x2108, 0xf1f8, ea_as_dt, gen_movel_dt_ea, ea_paid32), move_l_ais_paid(0x2110, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_paid32), @@ -1160,7 +1159,7 @@ public enum MacroPLA { move_l_ds_dad(0x2140, 0xf1f8, ea_dad32, gen_movel_ds_ea, dbrr), - move_l_as_dad(0x2148, 0xf1f8, ea_dad32, gen_movel_as_ea, dbrr), + move_l_as_dad(0x2148, 0xf1f8, ea_as_dt, gen_movel_dt_ea, ea_dad32), move_l_ais_dad(0x2150, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_dad32), @@ -1184,7 +1183,7 @@ public enum MacroPLA { move_l_ds_daid(0x2180, 0xf1f8, ea_daid32, gen_movel_ds_ea, dbrr), - move_l_as_daid(0x2188, 0xf1f8, ea_daid32, gen_movel_as_ea, dbrr), + move_l_as_daid(0x2188, 0xf1f8, ea_as_dt, gen_movel_dt_ea, ea_daid32), move_l_ais_daid(0x2190, 0xf1f8, ea_ais32_read, gen_movel_dt_ea, ea_daid32), @@ -1208,7 +1207,7 @@ public enum MacroPLA { move_l_ds_adr16(0x21c0, 0xfff8, ea_adr16d32, gen_movel_ds_ea, dbrr), - move_l_as_adr16(0x21c8, 0xfff8, ea_adr16d32, gen_movel_as_ea, dbrr), + move_l_as_adr16(0x21c8, 0xfff8, ea_as_dt, gen_movel_dt_ea, ea_adr16d32), move_l_ais_adr16(0x21d0, 0xfff8, ea_ais32_read, gen_movel_dt_ea, ea_adr16d32), @@ -1232,7 +1231,7 @@ public enum MacroPLA { move_l_ds_adr32(0x23c0, 0xfff8, ea_adr32d32, gen_movel_ds_ea, dbrr), - move_l_as_adr32(0x23c8, 0xfff8, ea_adr32d32, gen_movel_as_ea, dbrr), + move_l_as_adr32(0x23c8, 0xfff8, ea_as_dt, gen_movel_dt_ea, ea_adr32d32), move_l_ais_adr32(0x23d0, 0xfff8, ea_ais32_read, gen_movel_dt_ea, ea_adr32d32), @@ -1304,7 +1303,7 @@ public enum MacroPLA { move_w_ds_aid(0x3080, 0xf1f8, ea_aid16, gen_movew_ds_ea, dbrr), - move_w_as_aid(0x3088, 0xf1f8, ea_aid16, gen_movew_as_ea, dbrr), + move_w_as_aid(0x3088, 0xf1f8, ea_as_dt, gen_movew_dt_ea, ea_aid16), move_w_ais_aid(0x3090, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_aid16), @@ -1328,7 +1327,7 @@ public enum MacroPLA { move_w_ds_aipd(0x30c0, 0xf1f8, ea_aipd16, gen_movew_ds_ea, dbrr), - move_w_as_aipd(0x30c8, 0xf1f8, ea_aipd16, gen_movew_as_ea, dbrr), + move_w_as_aipd(0x30c8, 0xf1f8, ea_as_dt, gen_movew_dt_ea, ea_aipd16), move_w_ais_aipd(0x30d0, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_aipd16), @@ -1352,7 +1351,7 @@ public enum MacroPLA { move_w_ds_paid(0x3100, 0xf1f8, ea_paid16, gen_movew_ds_ea, dbrr), - move_w_as_paid(0x3108, 0xf1f8, ea_paid16, gen_movew_as_ea, dbrr), + move_w_as_paid(0x3108, 0xf1f8, ea_as_dt, gen_movew_dt_ea, ea_paid16), move_w_ais_paid(0x3110, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_paid16), @@ -1376,7 +1375,7 @@ public enum MacroPLA { move_w_ds_dad(0x3140, 0xf1f8, ea_dad16, gen_movew_ds_ea, dbrr), - move_w_as_dad(0x3148, 0xf1f8, ea_dad16, gen_movew_as_ea, dbrr), + move_w_as_dad(0x3148, 0xf1f8, ea_as_dt, gen_movew_dt_ea, ea_dad16), move_w_ais_dad(0x3150, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_dad16), @@ -1400,7 +1399,7 @@ public enum MacroPLA { move_w_ds_daid(0x3180, 0xf1f8, ea_daid16, gen_movew_ds_ea, dbrr), - move_w_as_daid(0x3188, 0xf1f8, ea_daid16, gen_movew_as_ea, dbrr), + move_w_as_daid(0x3188, 0xf1f8, ea_as_dt, gen_movew_dt_ea, ea_daid16), move_w_ais_daid(0x3190, 0xf1f8, ea_ais16_read, gen_movew_dt_ea, ea_daid16), @@ -1424,7 +1423,7 @@ public enum MacroPLA { move_w_ds_adr16(0x31c0, 0xfff8, ea_adr16d16, gen_movew_ds_ea, dbrr), - move_w_as_adr16(0x31c8, 0xfff8, ea_adr16d16, gen_movew_as_ea, dbrr), + move_w_as_adr16(0x31c8, 0xfff8, ea_as_dt, gen_movew_dt_ea, ea_adr16d16), move_w_ais_adr16(0x31d0, 0xfff8, ea_ais16_read, gen_movew_dt_ea, ea_adr16d16), @@ -1448,7 +1447,7 @@ public enum MacroPLA { move_w_ds_adr32(0x33c0, 0xfff8, ea_adr32d16, gen_movew_ds_ea, dbrr), - move_w_as_adr32(0x33c8, 0xfff8, ea_adr32d16, gen_movew_as_ea, dbrr), + move_w_as_adr32(0x33c8, 0xfff8, ea_as_dt, gen_movew_dt_ea, ea_adr32d16), move_w_ais_adr32(0x33d0, 0xfff8, ea_ais16_read, gen_movew_dt_ea, ea_adr32d16), diff --git a/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java b/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java index 6c94a37..f70dc83 100644 --- a/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java +++ b/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java @@ -169,16 +169,8 @@ public class InstructionTests extends TestCase { CoreTest test = new CoreTest(0xffffff + 1, true); test.executeBinTest("MOVE.b"); - /* - * skipped cases are incompatible (move address register to pre/post - * dec/increment with same address register) - */ - test.executeBinTest("MOVE.w", 295, 342, 494, 994, 1225, 1846); - /* - * skipped cases are incompatible (move address register to pre/post - * dec/increment with same address register) - */ - test.executeBinTest("MOVE.l", 217, 502, 1152, 1691, 1830, 2057, 2135); + test.executeBinTest("MOVE.w"); + test.executeBinTest("MOVE.l"); test.executeBinTest("MOVE.q"); test.executeBinTest("MOVEP.w");