diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java
index 2c470a1..f6d29e0 100644
--- a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java
+++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java
@@ -2202,7 +2202,7 @@ public class CoreGenerator {
 		if ("imm3".equals(src)) {
 			addFormattedMicroInsn("alub = (ir >> 9) & 0x0007"); // retrieve immediate data
 			addBeginFormattedControlFlow("if (alub == 0)");
-			addFormattedMicroInsn("alub = 8"); // when immediate data if zero... use 8
+			addFormattedMicroInsn("alub = 8"); // when immediate data is zero... use 8
 			addEndControlFlow();
 
 			rsrc = "alub";
@@ -2338,6 +2338,13 @@ public class CoreGenerator {
 			} else if ("w".equals(size) && exsrc) {
 				addFormattedMicroInsn("dt = long_%s((short) %s, %s)", op, rsrc, rdst); // perform long word operation
 			} else if ("w".equals(size)) {
+				if ("w".equals(size) && ("divu".equals(op) || "divs".equals(op))) {
+					addBeginFormattedControlFlow("if ((%s & 0xffff) == 0)", rsrc);
+					settvn(5); // set div by zero exception trap
+					addFormattedMicroInsn("mpc = (sswi & 0x%04x) != 0 ? trap2000 : trap0000", SSWI_FMT2);
+					addFormattedMicroInsn("continue"); // branch to trap subroutine
+					addEndControlFlow();
+				}
 				addFormattedMicroInsn("dt = word_%s(%s, %s)", op, rsrc, rdst); // perform word operation
 			} else {
 				throw new IllegalStateException();
@@ -2360,7 +2367,7 @@ public class CoreGenerator {
 							addFormattedMicroInsn("dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff)"); // update register with result
 						} else if ("l".equals(size)) {
 							addFormattedMicroInsn("dar[rx] = dt"); // update register with result
-						} else if ("w".equals(size) && ("mulu".equals(op) || "muls".equals(op))) {
+						} else if ("w".equals(size) && ("mulu".equals(op) || "muls".equals(op) || "divu".equals(op) || "divs".equals(op))) {
 							addFormattedMicroInsn("dar[rx] = dt"); // update register with result
 						} else if ("w".equals(size)) {
 							addFormattedMicroInsn("dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff)"); // update register with result
diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java
index e92a601..db6a6af 100644
--- a/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java
+++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java
@@ -601,6 +601,20 @@ public class CorePLAGenerator {
 		appendOP_eas(0x8180, 0xf1c0, "or_l_dd", EA_FETCH | EA_MALT, "32", (opcode, opmask, opname, n1, mode) -> {
 			appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "or", "l", "dd", "ea"));
 		});
+		appendOP_eas(0x80c0, 0xf1c0, "divu_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "divu", "w", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> {
+			if ((mode & EA_ALL ) == 0) {
+				appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr");
+			} else {
+				appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "divu", "w", "ea", "dd"));
+			}
+		});
+		appendOP_eas(0x81c0, 0xf1c0, "divs_w", EA_FETCH | EA_ALL, "16", dyadic(gen, "divs", "w", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> {
+			if ((mode & EA_ALL ) == 0) {
+				appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "dbrr");
+			} else {
+				appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", dyadic(gen, "divs", "w", "ea", "dd"));
+			}
+		});
 
 		appendOP_eas(0x9000, 0xf1c0, "sub_b", EA_FETCH | EA_ALL, "8", dyadic(gen, "sub", "b", "ds", "dd"), null, (opcode, opmask, opname, n1, mode) -> {
 			opname = String.format("%s_dd", opname);
diff --git a/miggy-emu/src/main/java/miggy/cpupoet/Core.java b/miggy-emu/src/main/java/miggy/cpupoet/Core.java
index 8e28dc0..5939e1c 100644
--- a/miggy-emu/src/main/java/miggy/cpupoet/Core.java
+++ b/miggy-emu/src/main/java/miggy/cpupoet/Core.java
@@ -743,257 +743,265 @@ public abstract class Core extends CoreALU {
 
   protected static final int gen_orl_dd_ea = 482;
 
-  protected static final int gen_subb_ds_dd = 483;
+  protected static final int gen_divuw_ds_dd = 483;
 
-  protected static final int gen_subb_dt_dd = 484;
+  protected static final int gen_divuw_dt_dd = 484;
 
-  protected static final int gen_subw_ds_dd = 485;
+  protected static final int gen_divsw_ds_dd = 485;
 
-  protected static final int gen_subw_as_dd = 486;
+  protected static final int gen_divsw_dt_dd = 486;
 
-  protected static final int gen_subw_dt_dd = 487;
+  protected static final int gen_subb_ds_dd = 487;
 
-  protected static final int gen_subl_ds_dd = 488;
+  protected static final int gen_subb_dt_dd = 488;
 
-  protected static final int gen_subl_as_dd = 489;
+  protected static final int gen_subw_ds_dd = 489;
 
-  protected static final int gen_subl_dt_dd = 490;
+  protected static final int gen_subw_as_dd = 490;
 
-  protected static final int gen_subb_dd_ea = 491;
+  protected static final int gen_subw_dt_dd = 491;
 
-  protected static final int gen_subw_dd_ea = 492;
+  protected static final int gen_subl_ds_dd = 492;
 
-  protected static final int gen_subl_dd_ea = 493;
+  protected static final int gen_subl_as_dd = 493;
 
-  protected static final int gen_subxb_ds_dd = 494;
+  protected static final int gen_subl_dt_dd = 494;
 
-  protected static final int gen_subxb_im_ea = 495;
+  protected static final int gen_subb_dd_ea = 495;
 
-  protected static final int gen_subxw_ds_dd = 496;
+  protected static final int gen_subw_dd_ea = 496;
 
-  protected static final int gen_subxw_im_ea = 497;
+  protected static final int gen_subl_dd_ea = 497;
 
-  protected static final int gen_subxl_ds_dd = 498;
+  protected static final int gen_subxb_ds_dd = 498;
 
-  protected static final int gen_subxl_im_ea = 499;
+  protected static final int gen_subxb_im_ea = 499;
 
-  protected static final int gen_subw_ds_ad = 500;
+  protected static final int gen_subxw_ds_dd = 500;
 
-  protected static final int gen_subw_as_ad = 501;
+  protected static final int gen_subxw_im_ea = 501;
 
-  protected static final int gen_subw_dt_ad = 502;
+  protected static final int gen_subxl_ds_dd = 502;
 
-  protected static final int gen_subl_ds_ad = 503;
+  protected static final int gen_subxl_im_ea = 503;
 
-  protected static final int gen_subl_as_ad = 504;
+  protected static final int gen_subw_ds_ad = 504;
 
-  protected static final int gen_subl_dt_ad = 505;
+  protected static final int gen_subw_as_ad = 505;
 
-  protected static final int gen_cmpb_ds_dd = 506;
+  protected static final int gen_subw_dt_ad = 506;
 
-  protected static final int gen_cmpb_dt_dd = 507;
+  protected static final int gen_subl_ds_ad = 507;
 
-  protected static final int gen_cmpw_ds_dd = 508;
+  protected static final int gen_subl_as_ad = 508;
 
-  protected static final int gen_cmpw_as_dd = 509;
+  protected static final int gen_subl_dt_ad = 509;
 
-  protected static final int gen_cmpw_dt_dd = 510;
+  protected static final int gen_cmpb_ds_dd = 510;
 
-  protected static final int gen_cmpl_ds_dd = 511;
+  protected static final int gen_cmpb_dt_dd = 511;
 
-  protected static final int gen_cmpl_as_dd = 512;
+  protected static final int gen_cmpw_ds_dd = 512;
 
-  protected static final int gen_cmpl_dt_dd = 513;
+  protected static final int gen_cmpw_as_dd = 513;
 
-  protected static final int gen_cmpw_ds_ad = 514;
+  protected static final int gen_cmpw_dt_dd = 514;
 
-  protected static final int gen_cmpw_as_ad = 515;
+  protected static final int gen_cmpl_ds_dd = 515;
 
-  protected static final int gen_cmpw_dt_ad = 516;
+  protected static final int gen_cmpl_as_dd = 516;
 
-  protected static final int gen_cmpl_ds_ad = 517;
+  protected static final int gen_cmpl_dt_dd = 517;
 
-  protected static final int gen_cmpl_as_ad = 518;
+  protected static final int gen_cmpw_ds_ad = 518;
 
-  protected static final int gen_cmpl_dt_ad = 519;
+  protected static final int gen_cmpw_as_ad = 519;
 
-  protected static final int gen_cmpmb_im_ea = 520;
+  protected static final int gen_cmpw_dt_ad = 520;
 
-  protected static final int gen_cmpmw_im_ea = 521;
+  protected static final int gen_cmpl_ds_ad = 521;
 
-  protected static final int gen_cmpml_im_ea = 522;
+  protected static final int gen_cmpl_as_ad = 522;
 
-  protected static final int gen_eorb_dd_ds = 523;
+  protected static final int gen_cmpl_dt_ad = 523;
 
-  protected static final int gen_eorb_dd_ea = 524;
+  protected static final int gen_cmpmb_im_ea = 524;
 
-  protected static final int gen_eorw_dd_ds = 525;
+  protected static final int gen_cmpmw_im_ea = 525;
 
-  protected static final int gen_eorw_dd_ea = 526;
+  protected static final int gen_cmpml_im_ea = 526;
 
-  protected static final int gen_eorl_dd_ds = 527;
+  protected static final int gen_eorb_dd_ds = 527;
 
-  protected static final int gen_eorl_dd_ea = 528;
+  protected static final int gen_eorb_dd_ea = 528;
 
-  protected static final int gen_andb_ds_dd = 529;
+  protected static final int gen_eorw_dd_ds = 529;
 
-  protected static final int gen_andb_dt_dd = 530;
+  protected static final int gen_eorw_dd_ea = 530;
 
-  protected static final int gen_andw_ds_dd = 531;
+  protected static final int gen_eorl_dd_ds = 531;
 
-  protected static final int gen_andw_dt_dd = 532;
+  protected static final int gen_eorl_dd_ea = 532;
 
-  protected static final int gen_andl_ds_dd = 533;
+  protected static final int gen_andb_ds_dd = 533;
 
-  protected static final int gen_andl_dt_dd = 534;
+  protected static final int gen_andb_dt_dd = 534;
 
-  protected static final int gen_muluw_ds_dd = 535;
+  protected static final int gen_andw_ds_dd = 535;
 
-  protected static final int gen_muluw_dt_dd = 536;
+  protected static final int gen_andw_dt_dd = 536;
 
-  protected static final int gen_mulsw_ds_dd = 537;
+  protected static final int gen_andl_ds_dd = 537;
 
-  protected static final int gen_mulsw_dt_dd = 538;
+  protected static final int gen_andl_dt_dd = 538;
 
-  protected static final int gen_andb_dd_ea = 539;
+  protected static final int gen_muluw_ds_dd = 539;
 
-  protected static final int gen_andw_dd_ea = 540;
+  protected static final int gen_muluw_dt_dd = 540;
 
-  protected static final int gen_andl_dd_ea = 541;
+  protected static final int gen_mulsw_ds_dd = 541;
 
-  protected static final int gen_abcdb_ds_dd = 542;
+  protected static final int gen_mulsw_dt_dd = 542;
 
-  protected static final int gen_abcdb_im_ea = 543;
+  protected static final int gen_andb_dd_ea = 543;
 
-  protected static final int gen_addb_ds_dd = 544;
+  protected static final int gen_andw_dd_ea = 544;
 
-  protected static final int gen_addb_dt_dd = 545;
+  protected static final int gen_andl_dd_ea = 545;
 
-  protected static final int gen_addw_ds_dd = 546;
+  protected static final int gen_abcdb_ds_dd = 546;
 
-  protected static final int gen_addw_as_dd = 547;
+  protected static final int gen_abcdb_im_ea = 547;
 
-  protected static final int gen_addw_dt_dd = 548;
+  protected static final int gen_addb_ds_dd = 548;
 
-  protected static final int gen_addl_ds_dd = 549;
+  protected static final int gen_addb_dt_dd = 549;
 
-  protected static final int gen_addl_as_dd = 550;
+  protected static final int gen_addw_ds_dd = 550;
 
-  protected static final int gen_addl_dt_dd = 551;
+  protected static final int gen_addw_as_dd = 551;
 
-  protected static final int gen_addb_dd_ea = 552;
+  protected static final int gen_addw_dt_dd = 552;
 
-  protected static final int gen_addw_dd_ea = 553;
+  protected static final int gen_addl_ds_dd = 553;
 
-  protected static final int gen_addl_dd_ea = 554;
+  protected static final int gen_addl_as_dd = 554;
 
-  protected static final int gen_addxb_ds_dd = 555;
+  protected static final int gen_addl_dt_dd = 555;
 
-  protected static final int gen_addxb_im_ea = 556;
+  protected static final int gen_addb_dd_ea = 556;
 
-  protected static final int gen_addxw_ds_dd = 557;
+  protected static final int gen_addw_dd_ea = 557;
 
-  protected static final int gen_addxw_im_ea = 558;
+  protected static final int gen_addl_dd_ea = 558;
 
-  protected static final int gen_addxl_ds_dd = 559;
+  protected static final int gen_addxb_ds_dd = 559;
 
-  protected static final int gen_addxl_im_ea = 560;
+  protected static final int gen_addxb_im_ea = 560;
 
-  protected static final int gen_addw_ds_ad = 561;
+  protected static final int gen_addxw_ds_dd = 561;
 
-  protected static final int gen_addw_as_ad = 562;
+  protected static final int gen_addxw_im_ea = 562;
 
-  protected static final int gen_addw_dt_ad = 563;
+  protected static final int gen_addxl_ds_dd = 563;
 
-  protected static final int gen_addl_ds_ad = 564;
+  protected static final int gen_addxl_im_ea = 564;
 
-  protected static final int gen_addl_as_ad = 565;
+  protected static final int gen_addw_ds_ad = 565;
 
-  protected static final int gen_addl_dt_ad = 566;
+  protected static final int gen_addw_as_ad = 566;
 
-  protected static final int gen_asrb_ir_ds = 567;
+  protected static final int gen_addw_dt_ad = 567;
 
-  protected static final int gen_asrb_dd_ds = 568;
+  protected static final int gen_addl_ds_ad = 568;
 
-  protected static final int gen_asrw_ir_ds = 569;
+  protected static final int gen_addl_as_ad = 569;
 
-  protected static final int gen_asrw_dd_ds = 570;
+  protected static final int gen_addl_dt_ad = 570;
 
-  protected static final int gen_asrl_ir_ds = 571;
+  protected static final int gen_asrb_ir_ds = 571;
 
-  protected static final int gen_asrl_dd_ds = 572;
+  protected static final int gen_asrb_dd_ds = 572;
 
-  protected static final int gen_asrw_ea = 573;
+  protected static final int gen_asrw_ir_ds = 573;
 
-  protected static final int gen_aslb_ir_ds = 574;
+  protected static final int gen_asrw_dd_ds = 574;
 
-  protected static final int gen_aslb_dd_ds = 575;
+  protected static final int gen_asrl_ir_ds = 575;
 
-  protected static final int gen_aslw_ir_ds = 576;
+  protected static final int gen_asrl_dd_ds = 576;
 
-  protected static final int gen_aslw_dd_ds = 577;
+  protected static final int gen_asrw_ea = 577;
 
-  protected static final int gen_asll_ir_ds = 578;
+  protected static final int gen_aslb_ir_ds = 578;
 
-  protected static final int gen_asll_dd_ds = 579;
+  protected static final int gen_aslb_dd_ds = 579;
 
-  protected static final int gen_aslw_ea = 580;
+  protected static final int gen_aslw_ir_ds = 580;
 
-  protected static final int gen_lsrb_ir_ds = 581;
+  protected static final int gen_aslw_dd_ds = 581;
 
-  protected static final int gen_lsrb_dd_ds = 582;
+  protected static final int gen_asll_ir_ds = 582;
 
-  protected static final int gen_lsrw_ir_ds = 583;
+  protected static final int gen_asll_dd_ds = 583;
 
-  protected static final int gen_lsrw_dd_ds = 584;
+  protected static final int gen_aslw_ea = 584;
 
-  protected static final int gen_lsrl_ir_ds = 585;
+  protected static final int gen_lsrb_ir_ds = 585;
 
-  protected static final int gen_lsrl_dd_ds = 586;
+  protected static final int gen_lsrb_dd_ds = 586;
 
-  protected static final int gen_lsrw_ea = 587;
+  protected static final int gen_lsrw_ir_ds = 587;
 
-  protected static final int gen_lslb_ir_ds = 588;
+  protected static final int gen_lsrw_dd_ds = 588;
 
-  protected static final int gen_lslb_dd_ds = 589;
+  protected static final int gen_lsrl_ir_ds = 589;
 
-  protected static final int gen_lslw_ir_ds = 590;
+  protected static final int gen_lsrl_dd_ds = 590;
 
-  protected static final int gen_lslw_dd_ds = 591;
+  protected static final int gen_lsrw_ea = 591;
 
-  protected static final int gen_lsll_ir_ds = 592;
+  protected static final int gen_lslb_ir_ds = 592;
 
-  protected static final int gen_lsll_dd_ds = 593;
+  protected static final int gen_lslb_dd_ds = 593;
 
-  protected static final int gen_lslw_ea = 594;
+  protected static final int gen_lslw_ir_ds = 594;
 
-  protected static final int gen_rorb_ir_ds = 595;
+  protected static final int gen_lslw_dd_ds = 595;
 
-  protected static final int gen_rorb_dd_ds = 596;
+  protected static final int gen_lsll_ir_ds = 596;
 
-  protected static final int gen_rorw_ir_ds = 597;
+  protected static final int gen_lsll_dd_ds = 597;
 
-  protected static final int gen_rorw_dd_ds = 598;
+  protected static final int gen_lslw_ea = 598;
 
-  protected static final int gen_rorl_ir_ds = 599;
+  protected static final int gen_rorb_ir_ds = 599;
 
-  protected static final int gen_rorl_dd_ds = 600;
+  protected static final int gen_rorb_dd_ds = 600;
 
-  protected static final int gen_rorw_ea = 601;
+  protected static final int gen_rorw_ir_ds = 601;
 
-  protected static final int gen_rolb_ir_ds = 602;
+  protected static final int gen_rorw_dd_ds = 602;
 
-  protected static final int gen_rolb_dd_ds = 603;
+  protected static final int gen_rorl_ir_ds = 603;
 
-  protected static final int gen_rolw_ir_ds = 604;
+  protected static final int gen_rorl_dd_ds = 604;
 
-  protected static final int gen_rolw_dd_ds = 605;
+  protected static final int gen_rorw_ea = 605;
 
-  protected static final int gen_roll_ir_ds = 606;
+  protected static final int gen_rolb_ir_ds = 606;
 
-  protected static final int gen_roll_dd_ds = 607;
+  protected static final int gen_rolb_dd_ds = 607;
 
-  protected static final int gen_rolw_ea = 608;
+  protected static final int gen_rolw_ir_ds = 608;
+
+  protected static final int gen_rolw_dd_ds = 609;
+
+  protected static final int gen_roll_ir_ds = 610;
+
+  protected static final int gen_roll_dd_ds = 611;
+
+  protected static final int gen_rolw_ea = 612;
 
   public static final int BKPT_EXIT = 0x00010000;
 
@@ -6084,27 +6092,73 @@ public abstract class Core extends CoreALU {
           dt = long_or(dar[rx], dt);
           mpc = ea_resume_write32;
           continue;
-          case 483: /* gen_subb_ds_dd */
+          case 483: /* gen_divuw_ds_dd */
+          ry = ir & 0x0007;
+          rx = (ir >> 9) & 0x0007;
+          if ((dar[ry] & 0xffff) == 0) {
+            tvn = 20;
+            mpc = (sswi & 0x0008) != 0 ? trap2000 : trap0000;
+            continue;
+          }
+          dt = word_divu(dar[ry], dar[rx]);
+          dar[rx] = dt;
+          mpc = resume_prefetch;
+          continue;
+          case 484: /* gen_divuw_dt_dd */
+          rx = (ir >> 9) & 0x0007;
+          if ((dt & 0xffff) == 0) {
+            tvn = 20;
+            mpc = (sswi & 0x0008) != 0 ? trap2000 : trap0000;
+            continue;
+          }
+          dt = word_divu(dt, dar[rx]);
+          dar[rx] = dt;
+          mpc = resume_prefetch;
+          continue;
+          case 485: /* gen_divsw_ds_dd */
+          ry = ir & 0x0007;
+          rx = (ir >> 9) & 0x0007;
+          if ((dar[ry] & 0xffff) == 0) {
+            tvn = 20;
+            mpc = (sswi & 0x0008) != 0 ? trap2000 : trap0000;
+            continue;
+          }
+          dt = word_divs(dar[ry], dar[rx]);
+          dar[rx] = dt;
+          mpc = resume_prefetch;
+          continue;
+          case 486: /* gen_divsw_dt_dd */
+          rx = (ir >> 9) & 0x0007;
+          if ((dt & 0xffff) == 0) {
+            tvn = 20;
+            mpc = (sswi & 0x0008) != 0 ? trap2000 : trap0000;
+            continue;
+          }
+          dt = word_divs(dt, dar[rx]);
+          dar[rx] = dt;
+          mpc = resume_prefetch;
+          continue;
+          case 487: /* gen_subb_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = byte_sub(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 484: /* gen_subb_dt_dd */
+          case 488: /* gen_subb_dt_dd */
           rx = (ir >> 9) & 0x0007;
           dt = byte_sub(dt, dar[rx]);
           dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 485: /* gen_subw_ds_dd */
+          case 489: /* gen_subw_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = word_sub(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 486: /* gen_subw_as_dd */
+          case 490: /* gen_subw_as_dd */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
@@ -6112,20 +6166,20 @@ public abstract class Core extends CoreALU {
           dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 487: /* gen_subw_dt_dd */
+          case 491: /* gen_subw_dt_dd */
           rx = (ir >> 9) & 0x0007;
           dt = word_sub(dt, dar[rx]);
           dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 488: /* gen_subl_ds_dd */
+          case 492: /* gen_subl_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = long_sub(dar[ry], dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 489: /* gen_subl_as_dd */
+          case 493: /* gen_subl_as_dd */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
@@ -6133,68 +6187,68 @@ public abstract class Core extends CoreALU {
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 490: /* gen_subl_dt_dd */
+          case 494: /* gen_subl_dt_dd */
           rx = (ir >> 9) & 0x0007;
           dt = long_sub(dt, dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 491: /* gen_subb_dd_ea */
+          case 495: /* gen_subb_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = byte_sub(dar[rx], dt);
           mpc = ea_resume_write8;
           continue;
-          case 492: /* gen_subw_dd_ea */
+          case 496: /* gen_subw_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = word_sub(dar[rx], dt);
           mpc = ea_resume_write16;
           continue;
-          case 493: /* gen_subl_dd_ea */
+          case 497: /* gen_subl_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = long_sub(dar[rx], dt);
           mpc = ea_resume_write32;
           continue;
-          case 494: /* gen_subxb_ds_dd */
+          case 498: /* gen_subxb_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = byte_subx(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 495: /* gen_subxb_im_ea */
+          case 499: /* gen_subxb_im_ea */
           dt = byte_subx(alub, dt);
           mpc = ea_resume_write8;
           continue;
-          case 496: /* gen_subxw_ds_dd */
+          case 500: /* gen_subxw_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = word_subx(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 497: /* gen_subxw_im_ea */
+          case 501: /* gen_subxw_im_ea */
           dt = word_subx(alub, dt);
           mpc = ea_resume_write16;
           continue;
-          case 498: /* gen_subxl_ds_dd */
+          case 502: /* gen_subxl_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = long_subx(dar[ry], dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 499: /* gen_subxl_im_ea */
+          case 503: /* gen_subxl_im_ea */
           dt = long_subx(alub, dt);
           mpc = ea_resume_write32;
           continue;
-          case 500: /* gen_subw_ds_ad */
+          case 504: /* gen_subw_ds_ad */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           dar[rx] = dar[rx] - ((short) dar[ry]);
           mpc = resume_prefetch;
           continue;
-          case 501: /* gen_subw_as_ad */
+          case 505: /* gen_subw_as_ad */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
@@ -6202,20 +6256,20 @@ public abstract class Core extends CoreALU {
           dar[rx] = dar[rx] - ((short) dar[ry]);
           mpc = resume_prefetch;
           continue;
-          case 502: /* gen_subw_dt_ad */
+          case 506: /* gen_subw_dt_ad */
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           dar[rx] = dar[rx] - ((short) dt);
           mpc = resume_prefetch;
           continue;
-          case 503: /* gen_subl_ds_ad */
+          case 507: /* gen_subl_ds_ad */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           dar[rx] = dar[rx] - dar[ry];
           mpc = resume_prefetch;
           continue;
-          case 504: /* gen_subl_as_ad */
+          case 508: /* gen_subl_as_ad */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
@@ -6223,67 +6277,67 @@ public abstract class Core extends CoreALU {
           dar[rx] = dar[rx] - dar[ry];
           mpc = resume_prefetch;
           continue;
-          case 505: /* gen_subl_dt_ad */
+          case 509: /* gen_subl_dt_ad */
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           dar[rx] = dar[rx] - dt;
           mpc = resume_prefetch;
           continue;
-          case 506: /* gen_cmpb_ds_dd */
+          case 510: /* gen_cmpb_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           byte_cmp(dar[ry], dar[rx]);
           mpc = resume_prefetch;
           continue;
-          case 507: /* gen_cmpb_dt_dd */
+          case 511: /* gen_cmpb_dt_dd */
           rx = (ir >> 9) & 0x0007;
           byte_cmp(dt, dar[rx]);
           mpc = resume_prefetch;
           continue;
-          case 508: /* gen_cmpw_ds_dd */
+          case 512: /* gen_cmpw_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           word_cmp(dar[ry], dar[rx]);
           mpc = resume_prefetch;
           continue;
-          case 509: /* gen_cmpw_as_dd */
+          case 513: /* gen_cmpw_as_dd */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
           word_cmp(dar[ry], dar[rx]);
           mpc = resume_prefetch;
           continue;
-          case 510: /* gen_cmpw_dt_dd */
+          case 514: /* gen_cmpw_dt_dd */
           rx = (ir >> 9) & 0x0007;
           word_cmp(dt, dar[rx]);
           mpc = resume_prefetch;
           continue;
-          case 511: /* gen_cmpl_ds_dd */
+          case 515: /* gen_cmpl_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           long_cmp(dar[ry], dar[rx]);
           mpc = resume_prefetch;
           continue;
-          case 512: /* gen_cmpl_as_dd */
+          case 516: /* gen_cmpl_as_dd */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
           long_cmp(dar[ry], dar[rx]);
           mpc = resume_prefetch;
           continue;
-          case 513: /* gen_cmpl_dt_dd */
+          case 517: /* gen_cmpl_dt_dd */
           rx = (ir >> 9) & 0x0007;
           long_cmp(dt, dar[rx]);
           mpc = resume_prefetch;
           continue;
-          case 514: /* gen_cmpw_ds_ad */
+          case 518: /* gen_cmpw_ds_ad */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           long_cmp((short) dar[ry], dar[rx]);
           mpc = resume_prefetch;
           continue;
-          case 515: /* gen_cmpw_as_ad */
+          case 519: /* gen_cmpw_as_ad */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
@@ -6291,20 +6345,20 @@ public abstract class Core extends CoreALU {
           long_cmp((short) dar[ry], dar[rx]);
           mpc = resume_prefetch;
           continue;
-          case 516: /* gen_cmpw_dt_ad */
+          case 520: /* gen_cmpw_dt_ad */
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           long_cmp((short) dt, dar[rx]);
           mpc = resume_prefetch;
           continue;
-          case 517: /* gen_cmpl_ds_ad */
+          case 521: /* gen_cmpl_ds_ad */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           long_cmp(dar[ry], dar[rx]);
           mpc = resume_prefetch;
           continue;
-          case 518: /* gen_cmpl_as_ad */
+          case 522: /* gen_cmpl_as_ad */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
@@ -6312,172 +6366,172 @@ public abstract class Core extends CoreALU {
           long_cmp(dar[ry], dar[rx]);
           mpc = resume_prefetch;
           continue;
-          case 519: /* gen_cmpl_dt_ad */
+          case 523: /* gen_cmpl_dt_ad */
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           long_cmp(dt, dar[rx]);
           mpc = resume_prefetch;
           continue;
-          case 520: /* gen_cmpmb_im_ea */
+          case 524: /* gen_cmpmb_im_ea */
           byte_cmp(alub, dt);
           mpc = resume_prefetch;
           continue;
-          case 521: /* gen_cmpmw_im_ea */
+          case 525: /* gen_cmpmw_im_ea */
           word_cmp(alub, dt);
           mpc = resume_prefetch;
           continue;
-          case 522: /* gen_cmpml_im_ea */
+          case 526: /* gen_cmpml_im_ea */
           long_cmp(alub, dt);
           mpc = resume_prefetch;
           continue;
-          case 523: /* gen_eorb_dd_ds */
+          case 527: /* gen_eorb_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = byte_eor(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 524: /* gen_eorb_dd_ea */
+          case 528: /* gen_eorb_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = byte_eor(dar[rx], dt);
           mpc = ea_resume_write8;
           continue;
-          case 525: /* gen_eorw_dd_ds */
+          case 529: /* gen_eorw_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = word_eor(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 526: /* gen_eorw_dd_ea */
+          case 530: /* gen_eorw_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = word_eor(dar[rx], dt);
           mpc = ea_resume_write16;
           continue;
-          case 527: /* gen_eorl_dd_ds */
+          case 531: /* gen_eorl_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = long_eor(dar[rx], dar[ry]);
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 528: /* gen_eorl_dd_ea */
+          case 532: /* gen_eorl_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = long_eor(dar[rx], dt);
           mpc = ea_resume_write32;
           continue;
-          case 529: /* gen_andb_ds_dd */
+          case 533: /* gen_andb_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = byte_and(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 530: /* gen_andb_dt_dd */
+          case 534: /* gen_andb_dt_dd */
           rx = (ir >> 9) & 0x0007;
           dt = byte_and(dt, dar[rx]);
           dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 531: /* gen_andw_ds_dd */
+          case 535: /* gen_andw_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = word_and(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 532: /* gen_andw_dt_dd */
+          case 536: /* gen_andw_dt_dd */
           rx = (ir >> 9) & 0x0007;
           dt = word_and(dt, dar[rx]);
           dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 533: /* gen_andl_ds_dd */
+          case 537: /* gen_andl_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = long_and(dar[ry], dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 534: /* gen_andl_dt_dd */
+          case 538: /* gen_andl_dt_dd */
           rx = (ir >> 9) & 0x0007;
           dt = long_and(dt, dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 535: /* gen_muluw_ds_dd */
+          case 539: /* gen_muluw_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = word_mulu(dar[ry], dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 536: /* gen_muluw_dt_dd */
+          case 540: /* gen_muluw_dt_dd */
           rx = (ir >> 9) & 0x0007;
           dt = word_mulu(dt, dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 537: /* gen_mulsw_ds_dd */
+          case 541: /* gen_mulsw_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = word_muls(dar[ry], dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 538: /* gen_mulsw_dt_dd */
+          case 542: /* gen_mulsw_dt_dd */
           rx = (ir >> 9) & 0x0007;
           dt = word_muls(dt, dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 539: /* gen_andb_dd_ea */
+          case 543: /* gen_andb_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = byte_and(dar[rx], dt);
           mpc = ea_resume_write8;
           continue;
-          case 540: /* gen_andw_dd_ea */
+          case 544: /* gen_andw_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = word_and(dar[rx], dt);
           mpc = ea_resume_write16;
           continue;
-          case 541: /* gen_andl_dd_ea */
+          case 545: /* gen_andl_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = long_and(dar[rx], dt);
           mpc = ea_resume_write32;
           continue;
-          case 542: /* gen_abcdb_ds_dd */
+          case 546: /* gen_abcdb_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = byte_abcd(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 543: /* gen_abcdb_im_ea */
+          case 547: /* gen_abcdb_im_ea */
           dt = byte_abcd(alub, dt);
           mpc = ea_resume_write8;
           continue;
-          case 544: /* gen_addb_ds_dd */
+          case 548: /* gen_addb_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = byte_add(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 545: /* gen_addb_dt_dd */
+          case 549: /* gen_addb_dt_dd */
           rx = (ir >> 9) & 0x0007;
           dt = byte_add(dt, dar[rx]);
           dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 546: /* gen_addw_ds_dd */
+          case 550: /* gen_addw_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = word_add(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 547: /* gen_addw_as_dd */
+          case 551: /* gen_addw_as_dd */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
@@ -6485,20 +6539,20 @@ public abstract class Core extends CoreALU {
           dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 548: /* gen_addw_dt_dd */
+          case 552: /* gen_addw_dt_dd */
           rx = (ir >> 9) & 0x0007;
           dt = word_add(dt, dar[rx]);
           dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 549: /* gen_addl_ds_dd */
+          case 553: /* gen_addl_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = long_add(dar[ry], dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 550: /* gen_addl_as_dd */
+          case 554: /* gen_addl_as_dd */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
@@ -6506,68 +6560,68 @@ public abstract class Core extends CoreALU {
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 551: /* gen_addl_dt_dd */
+          case 555: /* gen_addl_dt_dd */
           rx = (ir >> 9) & 0x0007;
           dt = long_add(dt, dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 552: /* gen_addb_dd_ea */
+          case 556: /* gen_addb_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = byte_add(dar[rx], dt);
           mpc = ea_resume_write8;
           continue;
-          case 553: /* gen_addw_dd_ea */
+          case 557: /* gen_addw_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = word_add(dar[rx], dt);
           mpc = ea_resume_write16;
           continue;
-          case 554: /* gen_addl_dd_ea */
+          case 558: /* gen_addl_dd_ea */
           rx = (ir >> 9) & 0x0007;
           dt = long_add(dar[rx], dt);
           mpc = ea_resume_write32;
           continue;
-          case 555: /* gen_addxb_ds_dd */
+          case 559: /* gen_addxb_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = byte_addx(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 556: /* gen_addxb_im_ea */
+          case 560: /* gen_addxb_im_ea */
           dt = byte_addx(alub, dt);
           mpc = ea_resume_write8;
           continue;
-          case 557: /* gen_addxw_ds_dd */
+          case 561: /* gen_addxw_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = word_addx(dar[ry], dar[rx]);
           dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 558: /* gen_addxw_im_ea */
+          case 562: /* gen_addxw_im_ea */
           dt = word_addx(alub, dt);
           mpc = ea_resume_write16;
           continue;
-          case 559: /* gen_addxl_ds_dd */
+          case 563: /* gen_addxl_ds_dd */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           dt = long_addx(dar[ry], dar[rx]);
           dar[rx] = dt;
           mpc = resume_prefetch;
           continue;
-          case 560: /* gen_addxl_im_ea */
+          case 564: /* gen_addxl_im_ea */
           dt = long_addx(alub, dt);
           mpc = ea_resume_write32;
           continue;
-          case 561: /* gen_addw_ds_ad */
+          case 565: /* gen_addw_ds_ad */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           dar[rx] = dar[rx] + ((short) dar[ry]);
           mpc = resume_prefetch;
           continue;
-          case 562: /* gen_addw_as_ad */
+          case 566: /* gen_addw_as_ad */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
@@ -6575,20 +6629,20 @@ public abstract class Core extends CoreALU {
           dar[rx] = dar[rx] + ((short) dar[ry]);
           mpc = resume_prefetch;
           continue;
-          case 563: /* gen_addw_dt_ad */
+          case 567: /* gen_addw_dt_ad */
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           dar[rx] = dar[rx] + ((short) dt);
           mpc = resume_prefetch;
           continue;
-          case 564: /* gen_addl_ds_ad */
+          case 568: /* gen_addl_ds_ad */
           ry = ir & 0x0007;
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           dar[rx] = dar[rx] + dar[ry];
           mpc = resume_prefetch;
           continue;
-          case 565: /* gen_addl_as_ad */
+          case 569: /* gen_addl_as_ad */
           ry = ir & 0x0007;
           ry = ry == 7 ? sp : ry | 8;
           rx = (ir >> 9) & 0x0007;
@@ -6596,13 +6650,13 @@ public abstract class Core extends CoreALU {
           dar[rx] = dar[rx] + dar[ry];
           mpc = resume_prefetch;
           continue;
-          case 566: /* gen_addl_dt_ad */
+          case 570: /* gen_addl_dt_ad */
           rx = (ir >> 9) & 0x0007;
           rx = rx == 7 ? sp : rx | 8;
           dar[rx] = dar[rx] + dt;
           mpc = resume_prefetch;
           continue;
-          case 567: /* gen_asrb_ir_ds */
+          case 571: /* gen_asrb_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6612,14 +6666,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 568: /* gen_asrb_dd_ds */
+          case 572: /* gen_asrb_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = byte_asr(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 569: /* gen_asrw_ir_ds */
+          case 573: /* gen_asrw_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6629,14 +6683,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 570: /* gen_asrw_dd_ds */
+          case 574: /* gen_asrw_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = word_asr(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 571: /* gen_asrl_ir_ds */
+          case 575: /* gen_asrl_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6646,18 +6700,18 @@ public abstract class Core extends CoreALU {
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 572: /* gen_asrl_dd_ds */
+          case 576: /* gen_asrl_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = long_asr(dar[rx], dar[ry]);
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 573: /* gen_asrw_ea */
+          case 577: /* gen_asrw_ea */
           dt = word_asr(1, dt);
           mpc = ea_resume_write16;
           continue;
-          case 574: /* gen_aslb_ir_ds */
+          case 578: /* gen_aslb_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6667,14 +6721,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 575: /* gen_aslb_dd_ds */
+          case 579: /* gen_aslb_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = byte_asl(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 576: /* gen_aslw_ir_ds */
+          case 580: /* gen_aslw_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6684,14 +6738,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 577: /* gen_aslw_dd_ds */
+          case 581: /* gen_aslw_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = word_asl(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 578: /* gen_asll_ir_ds */
+          case 582: /* gen_asll_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6701,18 +6755,18 @@ public abstract class Core extends CoreALU {
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 579: /* gen_asll_dd_ds */
+          case 583: /* gen_asll_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = long_asl(dar[rx], dar[ry]);
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 580: /* gen_aslw_ea */
+          case 584: /* gen_aslw_ea */
           dt = word_asl(1, dt);
           mpc = ea_resume_write16;
           continue;
-          case 581: /* gen_lsrb_ir_ds */
+          case 585: /* gen_lsrb_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6722,14 +6776,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 582: /* gen_lsrb_dd_ds */
+          case 586: /* gen_lsrb_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = byte_lsr(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 583: /* gen_lsrw_ir_ds */
+          case 587: /* gen_lsrw_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6739,14 +6793,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 584: /* gen_lsrw_dd_ds */
+          case 588: /* gen_lsrw_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = word_lsr(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 585: /* gen_lsrl_ir_ds */
+          case 589: /* gen_lsrl_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6756,18 +6810,18 @@ public abstract class Core extends CoreALU {
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 586: /* gen_lsrl_dd_ds */
+          case 590: /* gen_lsrl_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = long_lsr(dar[rx], dar[ry]);
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 587: /* gen_lsrw_ea */
+          case 591: /* gen_lsrw_ea */
           dt = word_lsr(1, dt);
           mpc = ea_resume_write16;
           continue;
-          case 588: /* gen_lslb_ir_ds */
+          case 592: /* gen_lslb_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6777,14 +6831,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 589: /* gen_lslb_dd_ds */
+          case 593: /* gen_lslb_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = byte_lsl(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 590: /* gen_lslw_ir_ds */
+          case 594: /* gen_lslw_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6794,14 +6848,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 591: /* gen_lslw_dd_ds */
+          case 595: /* gen_lslw_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = word_lsl(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 592: /* gen_lsll_ir_ds */
+          case 596: /* gen_lsll_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6811,18 +6865,18 @@ public abstract class Core extends CoreALU {
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 593: /* gen_lsll_dd_ds */
+          case 597: /* gen_lsll_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = long_lsl(dar[rx], dar[ry]);
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 594: /* gen_lslw_ea */
+          case 598: /* gen_lslw_ea */
           dt = word_lsl(1, dt);
           mpc = ea_resume_write16;
           continue;
-          case 595: /* gen_rorb_ir_ds */
+          case 599: /* gen_rorb_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6832,14 +6886,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 596: /* gen_rorb_dd_ds */
+          case 600: /* gen_rorb_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = byte_ror(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 597: /* gen_rorw_ir_ds */
+          case 601: /* gen_rorw_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6849,14 +6903,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 598: /* gen_rorw_dd_ds */
+          case 602: /* gen_rorw_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = word_ror(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 599: /* gen_rorl_ir_ds */
+          case 603: /* gen_rorl_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6866,18 +6920,18 @@ public abstract class Core extends CoreALU {
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 600: /* gen_rorl_dd_ds */
+          case 604: /* gen_rorl_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = long_ror(dar[rx], dar[ry]);
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 601: /* gen_rorw_ea */
+          case 605: /* gen_rorw_ea */
           dt = word_ror(1, dt);
           mpc = ea_resume_write16;
           continue;
-          case 602: /* gen_rolb_ir_ds */
+          case 606: /* gen_rolb_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6887,14 +6941,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 603: /* gen_rolb_dd_ds */
+          case 607: /* gen_rolb_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = byte_rol(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff);
           mpc = resume_prefetch;
           continue;
-          case 604: /* gen_rolw_ir_ds */
+          case 608: /* gen_rolw_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6904,14 +6958,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 605: /* gen_rolw_dd_ds */
+          case 609: /* gen_rolw_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = word_rol(dar[rx], dar[ry]);
           dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff);
           mpc = resume_prefetch;
           continue;
-          case 606: /* gen_roll_ir_ds */
+          case 610: /* gen_roll_ir_ds */
           alub = (ir >> 9) & 0x0007;
           if (alub == 0) {
             alub = 8;
@@ -6921,14 +6975,14 @@ public abstract class Core extends CoreALU {
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 607: /* gen_roll_dd_ds */
+          case 611: /* gen_roll_dd_ds */
           rx = (ir >> 9) & 0x0007;
           ry = ir & 0x0007;
           dt = long_rol(dar[rx], dar[ry]);
           dar[ry] = dt;
           mpc = resume_prefetch;
           continue;
-          case 608: /* gen_rolw_ea */
+          case 612: /* gen_rolw_ea */
           dt = word_rol(1, dt);
           mpc = ea_resume_write16;
           continue;
diff --git a/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java b/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java
index dc6beff..ac15008 100644
--- a/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java
+++ b/miggy-emu/src/main/java/miggy/cpupoet/CoreALU.java
@@ -1240,6 +1240,50 @@ public class CoreALU {
 		sr ^= (sr ^ (c | v | z | n)) & (FL_C | FL_V | FL_Z | FL_N);
 	}
 
+	public final int word_divs(int src, int dst) {
+		src = (short) src;
+
+		int q = dst / src;
+		int v = q == (short) q ? 0 : FL_V;
+		
+		if (v == 0) {
+			int r = dst % src;
+			int n = (q >> 28) & FL_N;
+			int z = (~((q | -q) >> 31)) & FL_Z;
+			
+			sr ^= (sr ^ (v | z | n)) & (FL_C | FL_V | FL_Z | FL_N);
+
+			return (r << 16) | (q & 0xffff);
+		}
+		
+		sr ^= (sr ^ (v | FL_N)) & (FL_C | FL_V | FL_Z | FL_N);
+
+		return dst;
+	}
+
+	public final int word_divu(int src, int dst) {
+		src = src & 0xffff;
+
+		int q = Integer.divideUnsigned(dst, src);
+		int v = q == (q & 0xffff) ? 0 : FL_V;
+		
+		if (v == 0) {
+			q = (short) q;
+
+			int r = Integer.remainderUnsigned(dst, src);
+			int n = (q >> 28) & FL_N;
+			int z = (~((q | -q) >> 31)) & FL_Z;
+			
+			sr ^= (sr ^ (v | z | n)) & (FL_C | FL_V | FL_Z | FL_N);
+
+			return (r << 16) | (q & 0xffff);
+		}
+		
+		sr ^= (sr ^ (v | FL_N)) & (FL_C | FL_V | FL_Z | FL_N);
+
+		return dst;
+	}
+
 	public final byte byte_eor(int src, int dst) {
 		src = (byte) src;
 		dst = (byte) dst;
diff --git a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java
index 37f598f..938a151 100644
--- a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java
+++ b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java
@@ -193,6 +193,10 @@ import static miggy.cpupoet.Core.gen_cmpw_dt_ad;
 import static miggy.cpupoet.Core.gen_cmpw_dt_dd;
 import static miggy.cpupoet.Core.gen_cmpw_dt_ds;
 import static miggy.cpupoet.Core.gen_cmpw_im_ea;
+import static miggy.cpupoet.Core.gen_divsw_ds_dd;
+import static miggy.cpupoet.Core.gen_divsw_dt_dd;
+import static miggy.cpupoet.Core.gen_divuw_ds_dd;
+import static miggy.cpupoet.Core.gen_divuw_dt_dd;
 import static miggy.cpupoet.Core.gen_eorb_dd_ds;
 import static miggy.cpupoet.Core.gen_eorb_dd_ea;
 import static miggy.cpupoet.Core.gen_eorb_dt_ccr;
@@ -2203,6 +2207,28 @@ public enum MacroPLA {
 
   or_l_imm32_dd(0x80bc, 0xf1ff, ea_imm32_read, dbrr, gen_orl_dt_dd),
 
+  divu_w_ds(0x80c0, 0xf1f8, gen_divuw_ds_dd, dbrr, dbrr),
+
+  divu_w_ais(0x80d0, 0xf1f8, ea_ais16_read, dbrr, gen_divuw_dt_dd),
+
+  divu_w_aips(0x80d8, 0xf1f8, ea_aips16_read, dbrr, gen_divuw_dt_dd),
+
+  divu_w_pais(0x80e0, 0xf1f8, ea_pais16_read, dbrr, gen_divuw_dt_dd),
+
+  divu_w_das(0x80e8, 0xf1f8, ea_das16_read, dbrr, gen_divuw_dt_dd),
+
+  divu_w_dais(0x80f0, 0xf1f8, ea_dais16_read, dbrr, gen_divuw_dt_dd),
+
+  divu_w_adr16(0x80f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_divuw_dt_dd),
+
+  divu_w_adr32(0x80f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_divuw_dt_dd),
+
+  divu_w_dpc(0x80fa, 0xf1ff, ea_dpc16_read, dbrr, gen_divuw_dt_dd),
+
+  divu_w_dpci(0x80fb, 0xf1ff, ea_dpci16_read, dbrr, gen_divuw_dt_dd),
+
+  divu_w_imm16(0x80fc, 0xf1ff, ea_imm16_read, dbrr, gen_divuw_dt_dd),
+
   sbcd_ds_dd(0x8100, 0xf1f8, gen_sbcdb_ds_dd, dbrr, dbrr),
 
   sbcd_pais_paid(0x8108, 0xf1f8, ea_pais8_read, gen_sbcdb_im_ea, ea_paid8_read),
@@ -2249,6 +2275,28 @@ public enum MacroPLA {
 
   or_l_dd_adr32(0x81b9, 0xf1ff, ea_adr32s32_read, dbrr, gen_orl_dd_ea),
 
+  divs_w_ds(0x81c0, 0xf1f8, gen_divsw_ds_dd, dbrr, dbrr),
+
+  divs_w_ais(0x81d0, 0xf1f8, ea_ais16_read, dbrr, gen_divsw_dt_dd),
+
+  divs_w_aips(0x81d8, 0xf1f8, ea_aips16_read, dbrr, gen_divsw_dt_dd),
+
+  divs_w_pais(0x81e0, 0xf1f8, ea_pais16_read, dbrr, gen_divsw_dt_dd),
+
+  divs_w_das(0x81e8, 0xf1f8, ea_das16_read, dbrr, gen_divsw_dt_dd),
+
+  divs_w_dais(0x81f0, 0xf1f8, ea_dais16_read, dbrr, gen_divsw_dt_dd),
+
+  divs_w_adr16(0x81f8, 0xf1ff, ea_adr16s16_read, dbrr, gen_divsw_dt_dd),
+
+  divs_w_adr32(0x81f9, 0xf1ff, ea_adr32s16_read, dbrr, gen_divsw_dt_dd),
+
+  divs_w_dpc(0x81fa, 0xf1ff, ea_dpc16_read, dbrr, gen_divsw_dt_dd),
+
+  divs_w_dpci(0x81fb, 0xf1ff, ea_dpci16_read, dbrr, gen_divsw_dt_dd),
+
+  divs_w_imm16(0x81fc, 0xf1ff, ea_imm16_read, dbrr, gen_divsw_dt_dd),
+
   sub_b_ds_dd(0x9000, 0xf1f8, gen_subb_ds_dd, dbrr, dbrr),
 
   sub_b_ais_dd(0x9010, 0xf1f8, ea_ais8_read, dbrr, gen_subb_dt_dd),
diff --git a/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java b/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java
index c9dede4..9c50b4b 100644
--- a/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java
+++ b/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java
@@ -20,6 +20,8 @@ public class InstructionTests extends TestCase {
 
 		test.executeBinTest("MULU");
 		test.executeBinTest("MULS");
+		test.executeBinTest("DIVU");
+		test.executeBinTest("DIVS");
 	}
 
 	public void testADD() {
diff --git a/miggy-emu/src/test/resources/miggy/cpupoet/DIVS.json.bin b/miggy-emu/src/test/resources/miggy/cpupoet/DIVS.json.bin
new file mode 100644
index 0000000..5e28ce6
Binary files /dev/null and b/miggy-emu/src/test/resources/miggy/cpupoet/DIVS.json.bin differ
diff --git a/miggy-emu/src/test/resources/miggy/cpupoet/DIVU.json.bin b/miggy-emu/src/test/resources/miggy/cpupoet/DIVU.json.bin
new file mode 100644
index 0000000..1845465
Binary files /dev/null and b/miggy-emu/src/test/resources/miggy/cpupoet/DIVU.json.bin differ