diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java index 8e56293..bc9bb89 100644 --- a/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java +++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CoreGenerator.java @@ -1703,9 +1703,9 @@ public class CoreGenerator { private void op_movem_microcode() { addState("op_movemw_rr_ea"); // read extension word - anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { - addFormattedMicroInsn("scan += 2"); - }); + //anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + // addFormattedMicroInsn("scan += 2"); + //}); prefetchir(0, false); addFormattedMicroInsn("alub = 0"); int loop = blocks.size(); @@ -1731,9 +1731,9 @@ public class CoreGenerator { addState("op_movemw_rr_pais"); // read extension word - anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { - addFormattedMicroInsn("scan += 2"); - }); + //anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + // addFormattedMicroInsn("scan += 2"); + //}); prefetchir(0, false); addFormattedMicroInsn("alub = 0"); loop = blocks.size(); @@ -1762,9 +1762,9 @@ public class CoreGenerator { addState("op_moveml_rr_ea"); // read extension word - anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { - addFormattedMicroInsn("scan += 2"); - }); + //anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + // addFormattedMicroInsn("scan += 2"); + //}); prefetchir(0, false); addFormattedMicroInsn("alub = 0"); loop = blocks.size(); @@ -1790,9 +1790,9 @@ public class CoreGenerator { addState("op_moveml_rr_pais"); // read extension word - anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { - addFormattedMicroInsn("scan += 2"); - }); + //anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + // addFormattedMicroInsn("scan += 2"); + //}); prefetchir(0, false); addFormattedMicroInsn("alub = 0"); loop = blocks.size(); @@ -1821,9 +1821,9 @@ public class CoreGenerator { // XXX should have another entry for dpc/dpci to have ssw program function code addState("op_movemw_ea_rr"); // read extension word - anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { - addFormattedMicroInsn("scan += 2"); - }); + //anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + // addFormattedMicroInsn("scan += 2"); + //}); prefetchir(0, false); addFormattedMicroInsn("alub = 0"); loop = blocks.size(); @@ -1850,9 +1850,9 @@ public class CoreGenerator { addState("op_movemw_aips_rr"); // read extension word - anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { - addFormattedMicroInsn("scan += 2"); - }); + //anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + // addFormattedMicroInsn("scan += 2"); + //}); prefetchir(0, false); addFormattedMicroInsn("alub = 0"); loop = blocks.size(); @@ -1882,9 +1882,9 @@ public class CoreGenerator { // XXX should have another entry for dpc/dpci to have ssw program function code addState("op_moveml_ea_rr"); // read extension word - anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { - addFormattedMicroInsn("scan += 2"); - }); + //anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + // addFormattedMicroInsn("scan += 2"); + //}); prefetchir(0, false); addFormattedMicroInsn("alub = 0"); loop = blocks.size(); @@ -1911,9 +1911,9 @@ public class CoreGenerator { addState("op_moveml_aips_rr"); // read extension word - anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { - addFormattedMicroInsn("scan += 2"); - }); + //anyread16("dt", SSW_DF | SSW_P, "pc + scan", 0, false, () -> { + // addFormattedMicroInsn("scan += 2"); + //}); prefetchir(0, false); addFormattedMicroInsn("alub = 0"); loop = blocks.size(); @@ -3038,7 +3038,7 @@ public class CoreGenerator { if (block.name != null) { FieldSpec field = null; - if ((imports == null) || (imports.contains(block.name))) { + if ((imports == null) || (imports.contains(block.name) || "execute_trap".equals(block.name))) { field = FieldSpec.builder(int.class, block.name, PROTECTED, STATIC, FINAL).initializer("$L", i) .build(); } else { diff --git a/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java b/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java index dc16214..37c5351 100644 --- a/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java +++ b/miggy-emu/src/main/java/miggy/cpu/genpoet/CorePLAGenerator.java @@ -425,52 +425,52 @@ public class CorePLAGenerator { appendOP(gen, entries, array, 0x4e7a, 0xffff, "movec_cr_rz", "op_movec_cr_rz", "dbrr", "dbrr"); appendOP(gen, entries, array, 0x4e7b, 0xffff, "movec_rz_cr", "op_movec_rz_cr", "dbrr", "dbrr"); - appendOP_eas(0x4890, 0xffc0, "movem_w_list", EA_CTRL, "16", (opcode, opmask, opname, n1, mode) -> { + appendOP_eas(0x4890, 0xffc0, "movem_w_list", EA_CTRL, "16", (opcode, opmask, opname, n2, mode) -> { //opname = String.format("%s", opname); - appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_movemw_rr_ea"); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, "op_movemw_rr_ea"); }); - appendOP_eas(0x4890, 0xffc0, "movem_w_listp", EA_PAIS, "16", (opcode, opmask, opname, n1, mode) -> { + appendOP_eas(0x4890, 0xffc0, "movem_w_listp", EA_PAIS, "16", (opcode, opmask, opname, n2, mode) -> { //opname = String.format("%s", opname); - appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_movemw_rr_pais"); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", "ea_ais16", "op_movemw_rr_pais"); }); - appendOP_eas(0x48d0, 0xffc0, "movem_l_list", EA_CTRL, "32", (opcode, opmask, opname, n1, mode) -> { + appendOP_eas(0x48d0, 0xffc0, "movem_l_list", EA_CTRL, "32", (opcode, opmask, opname, n2, mode) -> { //opname = String.format("%s", opname); - appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_moveml_rr_ea"); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, "op_moveml_rr_ea"); }); - appendOP_eas(0x48d0, 0xffc0, "movem_l_listp", EA_PAIS, "32", (opcode, opmask, opname, n1, mode) -> { + appendOP_eas(0x48d0, 0xffc0, "movem_l_listp", EA_PAIS, "32", (opcode, opmask, opname, n2, mode) -> { //opname = String.format("%s", opname); - appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_moveml_rr_pais"); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", "ea_ais32", "op_moveml_rr_pais"); }); - appendOP_eas(0x4c90, 0xffc0, "movem_w", EA_CTRL, "16", (opcode, opmask, opname, n1, mode) -> { + appendOP_eas(0x4c90, 0xffc0, "movem_w", EA_CTRL, "16", (opcode, opmask, opname, n2, mode) -> { opname = String.format("%s_list", opname); - appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_movemw_ea_rr"); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, "op_movemw_ea_rr"); }); - appendOP_eas(0x4c90, 0xffc0, "movem_w", EA_AIPS, "16", (opcode, opmask, opname, n1, mode) -> { + appendOP_eas(0x4c90, 0xffc0, "movem_w", EA_AIPS, "16", (opcode, opmask, opname, n2, mode) -> { opname = String.format("%s_list", opname); - appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_movemw_aips_rr"); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", "ea_ais16", "op_movemw_aips_rr"); }); - appendOP_eas(0x4cd0, 0xffc0, "movem_l", EA_CTRL, "32", (opcode, opmask, opname, n1, mode) -> { + appendOP_eas(0x4cd0, 0xffc0, "movem_l", EA_CTRL, "32", (opcode, opmask, opname, n2, mode) -> { opname = String.format("%s_list", opname); - appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_moveml_ea_rr"); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", n2, "op_moveml_ea_rr"); }); - appendOP_eas(0x4cd0, 0xffc0, "movem_l", EA_AIPS, "32", (opcode, opmask, opname, n1, mode) -> { + appendOP_eas(0x4cd0, 0xffc0, "movem_l", EA_AIPS, "32", (opcode, opmask, opname, n2, mode) -> { opname = String.format("%s_list", opname); - appendOP(gen, entries, array, opcode, opmask, opname, n1, "dbrr", "op_moveml_aips_rr"); + appendOP(gen, entries, array, opcode, opmask, opname, "op_imm16", "ea_ais32", "op_moveml_aips_rr"); }); appendOP_eas(0x4e90, 0xffc0, "jsr", EA_CTRL, "16", (opcode, opmask, opname, n1, mode) -> { diff --git a/miggy-emu/src/main/java/miggy/cpupoet/Core.java b/miggy-emu/src/main/java/miggy/cpupoet/Core.java index e35771e..826b485 100644 --- a/miggy-emu/src/main/java/miggy/cpupoet/Core.java +++ b/miggy-emu/src/main/java/miggy/cpupoet/Core.java @@ -39,7 +39,7 @@ public abstract class Core extends CoreALU { private static final int enter_irq = 21; - private static final int execute_trap = 22; + protected static final int execute_trap = 22; private static final int resume_prefetch = 23; @@ -381,613 +381,613 @@ public abstract class Core extends CoreALU { protected static final int op_movemw_rr_ea = 269; - protected static final int op_movemw_rr_pais = 273; + protected static final int op_movemw_rr_pais = 272; - protected static final int op_moveml_rr_ea = 277; + protected static final int op_moveml_rr_ea = 275; - protected static final int op_moveml_rr_pais = 281; + protected static final int op_moveml_rr_pais = 278; - protected static final int op_movemw_ea_rr = 285; + protected static final int op_movemw_ea_rr = 281; - protected static final int op_movemw_aips_rr = 290; + protected static final int op_movemw_aips_rr = 285; - protected static final int op_moveml_ea_rr = 295; + protected static final int op_moveml_ea_rr = 289; - protected static final int op_moveml_aips_rr = 300; + protected static final int op_moveml_aips_rr = 293; - protected static final int op_bcc8 = 305; + protected static final int op_bcc8 = 297; - protected static final int op_bra8 = 306; + protected static final int op_bra8 = 298; - protected static final int op_bcc16 = 307; + protected static final int op_bcc16 = 299; - protected static final int op_bra16 = 308; + protected static final int op_bra16 = 300; - protected static final int op_bcc32 = 309; + protected static final int op_bcc32 = 301; - protected static final int op_bra32 = 310; + protected static final int op_bra32 = 302; - protected static final int op_bsr8 = 311; + protected static final int op_bsr8 = 303; - protected static final int op_bsr16 = 313; + protected static final int op_bsr16 = 305; - protected static final int op_bsr32 = 315; + protected static final int op_bsr32 = 307; - protected static final int op_dbcc = 317; + protected static final int op_dbcc = 309; - protected static final int op_bkpt = 319; + protected static final int op_bkpt = 311; - protected static final int op_illegal = 320; + protected static final int op_illegal = 312; - protected static final int op_jmp = 321; + protected static final int op_jmp = 313; - protected static final int op_jsr = 322; + protected static final int op_jsr = 314; - protected static final int op_linea = 324; + protected static final int op_linea = 316; - protected static final int op_linef = 325; + protected static final int op_linef = 317; - protected static final int op_nop = 326; + protected static final int op_nop = 318; - protected static final int op_rte = 327; + protected static final int op_rte = 319; - private static final int check_vob = 328; + private static final int check_vob = 320; - private static final int rteill = 329; + private static final int rteill = 321; - private static final int exit_trap = 330; + private static final int exit_trap = 322; - private static final int rte0000 = 331; + private static final int rte0000 = 323; - private static final int rte1000 = 332; + private static final int rte1000 = 324; - private static final int rte2000 = 333; + private static final int rte2000 = 325; - private static final int rte8000 = 334; + private static final int rte8000 = 326; - protected static final int op_rtr = 335; + protected static final int op_rtr = 327; - protected static final int op_rts = 338; + protected static final int op_rts = 330; - protected static final int op_reset = 340; + protected static final int op_reset = 332; - protected static final int op_trap = 341; + protected static final int op_trap = 333; - protected static final int op_trapv = 342; + protected static final int op_trapv = 334; - protected static final int op_trapcc = 343; + protected static final int op_trapcc = 335; - protected static final int op_trapcc16 = 344; + protected static final int op_trapcc16 = 336; - protected static final int op_trapcc32 = 345; + protected static final int op_trapcc32 = 337; - protected static final int gen_orb_dt_ds = 346; + protected static final int gen_orb_dt_ds = 338; - protected static final int gen_orb_im_ea = 347; + protected static final int gen_orb_im_ea = 339; - protected static final int gen_orw_dt_ds = 348; + protected static final int gen_orw_dt_ds = 340; - protected static final int gen_orw_im_ea = 349; + protected static final int gen_orw_im_ea = 341; - protected static final int gen_orl_dt_ds = 350; + protected static final int gen_orl_dt_ds = 342; - protected static final int gen_orl_im_ea = 351; + protected static final int gen_orl_im_ea = 343; - protected static final int gen_orb_dt_ccr = 352; + protected static final int gen_orb_dt_ccr = 344; - protected static final int gen_orw_dt_sr = 353; + protected static final int gen_orw_dt_sr = 345; - protected static final int gen_btstl_dd_ds = 354; + protected static final int gen_btstl_dd_ds = 346; - protected static final int gen_btstb_dd_ea = 355; + protected static final int gen_btstb_dd_ea = 347; - protected static final int gen_bchgl_dd_ds = 356; + protected static final int gen_bchgl_dd_ds = 348; - protected static final int gen_bchgb_dd_ea = 357; + protected static final int gen_bchgb_dd_ea = 349; - protected static final int gen_bclrl_dd_ds = 358; + protected static final int gen_bclrl_dd_ds = 350; - protected static final int gen_bclrb_dd_ea = 359; + protected static final int gen_bclrb_dd_ea = 351; - protected static final int gen_bsetl_dd_ds = 360; + protected static final int gen_bsetl_dd_ds = 352; - protected static final int gen_bsetb_dd_ea = 361; + protected static final int gen_bsetb_dd_ea = 353; - protected static final int gen_andb_dt_ds = 362; + protected static final int gen_andb_dt_ds = 354; - protected static final int gen_andb_im_ea = 363; + protected static final int gen_andb_im_ea = 355; - protected static final int gen_andw_dt_ds = 364; + protected static final int gen_andw_dt_ds = 356; - protected static final int gen_andw_im_ea = 365; + protected static final int gen_andw_im_ea = 357; - protected static final int gen_andl_dt_ds = 366; + protected static final int gen_andl_dt_ds = 358; - protected static final int gen_andl_im_ea = 367; + protected static final int gen_andl_im_ea = 359; - protected static final int gen_andb_dt_ccr = 368; + protected static final int gen_andb_dt_ccr = 360; - protected static final int gen_andw_dt_sr = 369; + protected static final int gen_andw_dt_sr = 361; - protected static final int gen_subb_dt_ds = 370; + protected static final int gen_subb_dt_ds = 362; - protected static final int gen_subb_im_ea = 371; + protected static final int gen_subb_im_ea = 363; - protected static final int gen_subw_dt_ds = 372; + protected static final int gen_subw_dt_ds = 364; - protected static final int gen_subw_im_ea = 373; + protected static final int gen_subw_im_ea = 365; - protected static final int gen_subl_dt_ds = 374; + protected static final int gen_subl_dt_ds = 366; - protected static final int gen_subl_im_ea = 375; + protected static final int gen_subl_im_ea = 367; - protected static final int gen_addb_dt_ds = 376; + protected static final int gen_addb_dt_ds = 368; - protected static final int gen_addb_im_ea = 377; + protected static final int gen_addb_im_ea = 369; - protected static final int gen_addw_dt_ds = 378; + protected static final int gen_addw_dt_ds = 370; - protected static final int gen_addw_im_ea = 379; + protected static final int gen_addw_im_ea = 371; - protected static final int gen_addl_dt_ds = 380; + protected static final int gen_addl_dt_ds = 372; - protected static final int gen_addl_im_ea = 381; + protected static final int gen_addl_im_ea = 373; - protected static final int gen_btstl_dt_ds = 382; + protected static final int gen_btstl_dt_ds = 374; - protected static final int gen_btstb_im_ea = 383; + protected static final int gen_btstb_im_ea = 375; - protected static final int gen_bchgl_dt_ds = 384; + protected static final int gen_bchgl_dt_ds = 376; - protected static final int gen_bchgb_im_ea = 385; + protected static final int gen_bchgb_im_ea = 377; - protected static final int gen_bclrl_dt_ds = 386; + protected static final int gen_bclrl_dt_ds = 378; - protected static final int gen_bclrb_im_ea = 387; + protected static final int gen_bclrb_im_ea = 379; - protected static final int gen_bsetl_dt_ds = 388; + protected static final int gen_bsetl_dt_ds = 380; - protected static final int gen_bsetb_im_ea = 389; + protected static final int gen_bsetb_im_ea = 381; - protected static final int gen_eorb_dt_ds = 390; + protected static final int gen_eorb_dt_ds = 382; - protected static final int gen_eorb_im_ea = 391; + protected static final int gen_eorb_im_ea = 383; - protected static final int gen_eorw_dt_ds = 392; + protected static final int gen_eorw_dt_ds = 384; - protected static final int gen_eorw_im_ea = 393; + protected static final int gen_eorw_im_ea = 385; - protected static final int gen_eorl_dt_ds = 394; + protected static final int gen_eorl_dt_ds = 386; - protected static final int gen_eorl_im_ea = 395; + protected static final int gen_eorl_im_ea = 387; - protected static final int gen_eorb_dt_ccr = 396; + protected static final int gen_eorb_dt_ccr = 388; - protected static final int gen_eorw_dt_sr = 397; + protected static final int gen_eorw_dt_sr = 389; - protected static final int gen_cmpb_dt_ds = 398; + protected static final int gen_cmpb_dt_ds = 390; - protected static final int gen_cmpb_im_ea = 399; + protected static final int gen_cmpb_im_ea = 391; - protected static final int gen_cmpw_dt_ds = 400; + protected static final int gen_cmpw_dt_ds = 392; - protected static final int gen_cmpw_im_ea = 401; + protected static final int gen_cmpw_im_ea = 393; - protected static final int gen_cmpl_dt_ds = 402; + protected static final int gen_cmpl_dt_ds = 394; - protected static final int gen_cmpl_im_ea = 403; + protected static final int gen_cmpl_im_ea = 395; - protected static final int gen_moveb_ds_ea = 404; + protected static final int gen_moveb_ds_ea = 396; - protected static final int gen_moveb_dt_dd = 405; + protected static final int gen_moveb_dt_dd = 397; - protected static final int gen_moveb_ds_dd = 406; + protected static final int gen_moveb_ds_dd = 398; - protected static final int gen_moveb_dt_ea = 407; + protected static final int gen_moveb_dt_ea = 399; - protected static final int gen_movel_ds_ea = 408; + protected static final int gen_movel_ds_ea = 400; - protected static final int gen_movel_as_ea = 409; + protected static final int gen_movel_as_ea = 401; - protected static final int gen_movel_dt_dd = 410; + protected static final int gen_movel_dt_dd = 402; - protected static final int gen_movel_ds_dd = 411; + protected static final int gen_movel_ds_dd = 403; - protected static final int gen_movel_as_dd = 412; + protected static final int gen_movel_as_dd = 404; - protected static final int gen_movel_dt_ea = 413; + protected static final int gen_movel_dt_ea = 405; - protected static final int gen_movel_ds_ad = 414; + protected static final int gen_movel_ds_ad = 406; - protected static final int gen_movel_as_ad = 415; + protected static final int gen_movel_as_ad = 407; - protected static final int gen_movel_dt_ad = 416; + protected static final int gen_movel_dt_ad = 408; - protected static final int gen_movew_ds_ea = 417; + protected static final int gen_movew_ds_ea = 409; - protected static final int gen_movew_as_ea = 418; + protected static final int gen_movew_as_ea = 410; - protected static final int gen_movew_dt_dd = 419; + protected static final int gen_movew_dt_dd = 411; - protected static final int gen_movew_ds_dd = 420; + protected static final int gen_movew_ds_dd = 412; - protected static final int gen_movew_as_dd = 421; + protected static final int gen_movew_as_dd = 413; - protected static final int gen_movew_dt_ea = 422; + protected static final int gen_movew_dt_ea = 414; - protected static final int gen_movew_ds_ad = 423; + protected static final int gen_movew_ds_ad = 415; - protected static final int gen_movew_as_ad = 424; + protected static final int gen_movew_as_ad = 416; - protected static final int gen_movew_dt_ad = 425; + protected static final int gen_movew_dt_ad = 417; - protected static final int gen_negxb_ds = 426; + protected static final int gen_negxb_ds = 418; - protected static final int gen_negxb_ea = 427; + protected static final int gen_negxb_ea = 419; - protected static final int gen_negxw_ds = 428; + protected static final int gen_negxw_ds = 420; - protected static final int gen_negxw_ea = 429; + protected static final int gen_negxw_ea = 421; - protected static final int gen_negxl_ds = 430; + protected static final int gen_negxl_ds = 422; - protected static final int gen_negxl_ea = 431; + protected static final int gen_negxl_ea = 423; - protected static final int gen_movew_sr_ds = 432; + protected static final int gen_movew_sr_ds = 424; - protected static final int gen_movew_sr_ea = 433; + protected static final int gen_movew_sr_ea = 425; - protected static final int gen_movew_ccr_ds = 434; + protected static final int gen_movew_ccr_ds = 426; - protected static final int gen_movew_ccr_ea = 435; + protected static final int gen_movew_ccr_ea = 427; - protected static final int gen_movew_ds_ccr = 436; + protected static final int gen_movew_ds_ccr = 428; - protected static final int gen_movew_dt_ccr = 437; + protected static final int gen_movew_dt_ccr = 429; - protected static final int gen_movew_ds_sr = 438; + protected static final int gen_movew_ds_sr = 430; - protected static final int gen_movew_dt_sr = 439; + protected static final int gen_movew_dt_sr = 431; - protected static final int gen_negb_ds = 440; + protected static final int gen_negb_ds = 432; - protected static final int gen_negb_ea = 441; + protected static final int gen_negb_ea = 433; - protected static final int gen_negw_ds = 442; + protected static final int gen_negw_ds = 434; - protected static final int gen_negw_ea = 443; + protected static final int gen_negw_ea = 435; - protected static final int gen_negl_ds = 444; + protected static final int gen_negl_ds = 436; - protected static final int gen_negl_ea = 445; + protected static final int gen_negl_ea = 437; - protected static final int gen_notb_ds = 446; + protected static final int gen_notb_ds = 438; - protected static final int gen_notb_ea = 447; + protected static final int gen_notb_ea = 439; - protected static final int gen_notw_ds = 448; + protected static final int gen_notw_ds = 440; - protected static final int gen_notw_ea = 449; + protected static final int gen_notw_ea = 441; - protected static final int gen_notl_ds = 450; + protected static final int gen_notl_ds = 442; - protected static final int gen_notl_ea = 451; + protected static final int gen_notl_ea = 443; - protected static final int gen_nbcdb_ds = 452; + protected static final int gen_nbcdb_ds = 444; - protected static final int gen_nbcdb_ea = 453; + protected static final int gen_nbcdb_ea = 445; - protected static final int gen_tstb_ds = 454; + protected static final int gen_tstb_ds = 446; - protected static final int gen_tstb_ea = 455; + protected static final int gen_tstb_ea = 447; - protected static final int gen_tstw_ds = 456; + protected static final int gen_tstw_ds = 448; - protected static final int gen_tstw_ea = 457; + protected static final int gen_tstw_ea = 449; - protected static final int gen_tstl_ds = 458; + protected static final int gen_tstl_ds = 450; - protected static final int gen_tstl_ea = 459; + protected static final int gen_tstl_ea = 451; - protected static final int gen_addb_ir_ds = 460; + protected static final int gen_addb_ir_ds = 452; - protected static final int gen_addb_ir_ea = 461; + protected static final int gen_addb_ir_ea = 453; - protected static final int gen_addw_ir_ds = 462; + protected static final int gen_addw_ir_ds = 454; - protected static final int gen_addw_ir_as = 463; + protected static final int gen_addw_ir_as = 455; - protected static final int gen_addw_ir_ea = 464; + protected static final int gen_addw_ir_ea = 456; - protected static final int gen_addl_ir_ds = 465; + protected static final int gen_addl_ir_ds = 457; - protected static final int gen_addl_ir_as = 466; + protected static final int gen_addl_ir_as = 458; - protected static final int gen_addl_ir_ea = 467; + protected static final int gen_addl_ir_ea = 459; - protected static final int gen_subb_ir_ds = 468; + protected static final int gen_subb_ir_ds = 460; - protected static final int gen_subb_ir_ea = 469; + protected static final int gen_subb_ir_ea = 461; - protected static final int gen_subw_ir_ds = 470; + protected static final int gen_subw_ir_ds = 462; - protected static final int gen_subw_ir_as = 471; + protected static final int gen_subw_ir_as = 463; - protected static final int gen_subw_ir_ea = 472; + protected static final int gen_subw_ir_ea = 464; - protected static final int gen_subl_ir_ds = 473; + protected static final int gen_subl_ir_ds = 465; - protected static final int gen_subl_ir_as = 474; + protected static final int gen_subl_ir_as = 466; - protected static final int gen_subl_ir_ea = 475; + protected static final int gen_subl_ir_ea = 467; - protected static final int gen_movel_im_dd = 476; + protected static final int gen_movel_im_dd = 468; - protected static final int gen_orb_ds_dd = 477; + protected static final int gen_orb_ds_dd = 469; - protected static final int gen_orb_dt_dd = 478; + protected static final int gen_orb_dt_dd = 470; - protected static final int gen_orw_ds_dd = 479; + protected static final int gen_orw_ds_dd = 471; - protected static final int gen_orw_dt_dd = 480; + protected static final int gen_orw_dt_dd = 472; - protected static final int gen_orl_ds_dd = 481; + protected static final int gen_orl_ds_dd = 473; - protected static final int gen_orl_dt_dd = 482; + protected static final int gen_orl_dt_dd = 474; - protected static final int gen_sbcdb_ds_dd = 483; + protected static final int gen_sbcdb_ds_dd = 475; - protected static final int gen_sbcdb_im_ea = 484; + protected static final int gen_sbcdb_im_ea = 476; - protected static final int gen_orb_dd_ea = 485; + protected static final int gen_orb_dd_ea = 477; - protected static final int gen_orw_dd_ea = 486; + protected static final int gen_orw_dd_ea = 478; - protected static final int gen_orl_dd_ea = 487; + protected static final int gen_orl_dd_ea = 479; - protected static final int gen_subb_ds_dd = 488; + protected static final int gen_subb_ds_dd = 480; - protected static final int gen_subb_dt_dd = 489; + protected static final int gen_subb_dt_dd = 481; - protected static final int gen_subw_ds_dd = 490; + protected static final int gen_subw_ds_dd = 482; - protected static final int gen_subw_as_dd = 491; + protected static final int gen_subw_as_dd = 483; - protected static final int gen_subw_dt_dd = 492; + protected static final int gen_subw_dt_dd = 484; - protected static final int gen_subl_ds_dd = 493; + protected static final int gen_subl_ds_dd = 485; - protected static final int gen_subl_as_dd = 494; + protected static final int gen_subl_as_dd = 486; - protected static final int gen_subl_dt_dd = 495; + protected static final int gen_subl_dt_dd = 487; - protected static final int gen_subb_dd_ea = 496; + protected static final int gen_subb_dd_ea = 488; - protected static final int gen_subw_dd_ea = 497; + protected static final int gen_subw_dd_ea = 489; - protected static final int gen_subl_dd_ea = 498; + protected static final int gen_subl_dd_ea = 490; - protected static final int gen_subxb_ds_dd = 499; + protected static final int gen_subxb_ds_dd = 491; - protected static final int gen_subxb_im_ea = 500; + protected static final int gen_subxb_im_ea = 492; - protected static final int gen_subxw_ds_dd = 501; + protected static final int gen_subxw_ds_dd = 493; - protected static final int gen_subxw_im_ea = 502; + protected static final int gen_subxw_im_ea = 494; - protected static final int gen_subxl_ds_dd = 503; + protected static final int gen_subxl_ds_dd = 495; - protected static final int gen_subxl_im_ea = 504; + protected static final int gen_subxl_im_ea = 496; - protected static final int gen_subw_ds_ad = 505; + protected static final int gen_subw_ds_ad = 497; - protected static final int gen_subw_as_ad = 506; + protected static final int gen_subw_as_ad = 498; - protected static final int gen_subw_dt_ad = 507; + protected static final int gen_subw_dt_ad = 499; - protected static final int gen_subl_ds_ad = 508; + protected static final int gen_subl_ds_ad = 500; - protected static final int gen_subl_as_ad = 509; + protected static final int gen_subl_as_ad = 501; - protected static final int gen_subl_dt_ad = 510; + protected static final int gen_subl_dt_ad = 502; - protected static final int gen_cmpb_ds_dd = 511; + protected static final int gen_cmpb_ds_dd = 503; - protected static final int gen_cmpb_dt_dd = 512; + protected static final int gen_cmpb_dt_dd = 504; - protected static final int gen_cmpw_ds_dd = 513; + protected static final int gen_cmpw_ds_dd = 505; - protected static final int gen_cmpw_as_dd = 514; + protected static final int gen_cmpw_as_dd = 506; - protected static final int gen_cmpw_dt_dd = 515; + protected static final int gen_cmpw_dt_dd = 507; - protected static final int gen_cmpl_ds_dd = 516; + protected static final int gen_cmpl_ds_dd = 508; - protected static final int gen_cmpl_as_dd = 517; + protected static final int gen_cmpl_as_dd = 509; - protected static final int gen_cmpl_dt_dd = 518; + protected static final int gen_cmpl_dt_dd = 510; - protected static final int gen_cmpw_ds_ad = 519; + protected static final int gen_cmpw_ds_ad = 511; - protected static final int gen_cmpw_as_ad = 520; + protected static final int gen_cmpw_as_ad = 512; - protected static final int gen_cmpw_dt_ad = 521; + protected static final int gen_cmpw_dt_ad = 513; - protected static final int gen_cmpl_ds_ad = 522; + protected static final int gen_cmpl_ds_ad = 514; - protected static final int gen_cmpl_as_ad = 523; + protected static final int gen_cmpl_as_ad = 515; - protected static final int gen_cmpl_dt_ad = 524; + protected static final int gen_cmpl_dt_ad = 516; - protected static final int gen_cmpmb_im_ea = 525; + protected static final int gen_cmpmb_im_ea = 517; - protected static final int gen_cmpmw_im_ea = 526; + protected static final int gen_cmpmw_im_ea = 518; - protected static final int gen_cmpml_im_ea = 527; + protected static final int gen_cmpml_im_ea = 519; - protected static final int gen_eorb_dd_ds = 528; + protected static final int gen_eorb_dd_ds = 520; - protected static final int gen_eorb_dd_ea = 529; + protected static final int gen_eorb_dd_ea = 521; - protected static final int gen_eorw_dd_ds = 530; + protected static final int gen_eorw_dd_ds = 522; - protected static final int gen_eorw_dd_ea = 531; + protected static final int gen_eorw_dd_ea = 523; - protected static final int gen_eorl_dd_ds = 532; + protected static final int gen_eorl_dd_ds = 524; - protected static final int gen_eorl_dd_ea = 533; + protected static final int gen_eorl_dd_ea = 525; - protected static final int gen_andb_ds_dd = 534; + protected static final int gen_andb_ds_dd = 526; - protected static final int gen_andb_dt_dd = 535; + protected static final int gen_andb_dt_dd = 527; - protected static final int gen_andw_ds_dd = 536; + protected static final int gen_andw_ds_dd = 528; - protected static final int gen_andw_dt_dd = 537; + protected static final int gen_andw_dt_dd = 529; - protected static final int gen_andl_ds_dd = 538; + protected static final int gen_andl_ds_dd = 530; - protected static final int gen_andl_dt_dd = 539; + protected static final int gen_andl_dt_dd = 531; - protected static final int gen_andb_dd_ea = 540; + protected static final int gen_andb_dd_ea = 532; - protected static final int gen_andw_dd_ea = 541; + protected static final int gen_andw_dd_ea = 533; - protected static final int gen_andl_dd_ea = 542; + protected static final int gen_andl_dd_ea = 534; - protected static final int gen_abcdb_ds_dd = 543; + protected static final int gen_abcdb_ds_dd = 535; - protected static final int gen_abcdb_im_ea = 544; + protected static final int gen_abcdb_im_ea = 536; - protected static final int gen_addb_ds_dd = 545; + protected static final int gen_addb_ds_dd = 537; - protected static final int gen_addb_dt_dd = 546; + protected static final int gen_addb_dt_dd = 538; - protected static final int gen_addw_ds_dd = 547; + protected static final int gen_addw_ds_dd = 539; - protected static final int gen_addw_as_dd = 548; + protected static final int gen_addw_as_dd = 540; - protected static final int gen_addw_dt_dd = 549; + protected static final int gen_addw_dt_dd = 541; - protected static final int gen_addl_ds_dd = 550; + protected static final int gen_addl_ds_dd = 542; - protected static final int gen_addl_as_dd = 551; + protected static final int gen_addl_as_dd = 543; - protected static final int gen_addl_dt_dd = 552; + protected static final int gen_addl_dt_dd = 544; - protected static final int gen_addb_dd_ea = 553; + protected static final int gen_addb_dd_ea = 545; - protected static final int gen_addw_dd_ea = 554; + protected static final int gen_addw_dd_ea = 546; - protected static final int gen_addl_dd_ea = 555; + protected static final int gen_addl_dd_ea = 547; - protected static final int gen_addxb_ds_dd = 556; + protected static final int gen_addxb_ds_dd = 548; - protected static final int gen_addxb_im_ea = 557; + protected static final int gen_addxb_im_ea = 549; - protected static final int gen_addxw_ds_dd = 558; + protected static final int gen_addxw_ds_dd = 550; - protected static final int gen_addxw_im_ea = 559; + protected static final int gen_addxw_im_ea = 551; - protected static final int gen_addxl_ds_dd = 560; + protected static final int gen_addxl_ds_dd = 552; - protected static final int gen_addxl_im_ea = 561; + protected static final int gen_addxl_im_ea = 553; - protected static final int gen_addw_ds_ad = 562; + protected static final int gen_addw_ds_ad = 554; - protected static final int gen_addw_as_ad = 563; + protected static final int gen_addw_as_ad = 555; - protected static final int gen_addw_dt_ad = 564; + protected static final int gen_addw_dt_ad = 556; - protected static final int gen_addl_ds_ad = 565; + protected static final int gen_addl_ds_ad = 557; - protected static final int gen_addl_as_ad = 566; + protected static final int gen_addl_as_ad = 558; - protected static final int gen_addl_dt_ad = 567; + protected static final int gen_addl_dt_ad = 559; - protected static final int gen_asrb_ir_ds = 568; + protected static final int gen_asrb_ir_ds = 560; - protected static final int gen_asrb_dd_ds = 569; + protected static final int gen_asrb_dd_ds = 561; - protected static final int gen_asrw_ir_ds = 570; + protected static final int gen_asrw_ir_ds = 562; - protected static final int gen_asrw_dd_ds = 571; + protected static final int gen_asrw_dd_ds = 563; - protected static final int gen_asrl_ir_ds = 572; + protected static final int gen_asrl_ir_ds = 564; - protected static final int gen_asrl_dd_ds = 573; + protected static final int gen_asrl_dd_ds = 565; - protected static final int gen_asrw_ea = 574; + protected static final int gen_asrw_ea = 566; - protected static final int gen_aslb_ir_ds = 575; + protected static final int gen_aslb_ir_ds = 567; - protected static final int gen_aslb_dd_ds = 576; + protected static final int gen_aslb_dd_ds = 568; - protected static final int gen_aslw_ir_ds = 577; + protected static final int gen_aslw_ir_ds = 569; - protected static final int gen_aslw_dd_ds = 578; + protected static final int gen_aslw_dd_ds = 570; - protected static final int gen_asll_ir_ds = 579; + protected static final int gen_asll_ir_ds = 571; - protected static final int gen_asll_dd_ds = 580; + protected static final int gen_asll_dd_ds = 572; - protected static final int gen_aslw_ea = 581; + protected static final int gen_aslw_ea = 573; - protected static final int gen_lsrb_ir_ds = 582; + protected static final int gen_lsrb_ir_ds = 574; - protected static final int gen_lsrb_dd_ds = 583; + protected static final int gen_lsrb_dd_ds = 575; - protected static final int gen_lsrw_ir_ds = 584; + protected static final int gen_lsrw_ir_ds = 576; - protected static final int gen_lsrw_dd_ds = 585; + protected static final int gen_lsrw_dd_ds = 577; - protected static final int gen_lsrl_ir_ds = 586; + protected static final int gen_lsrl_ir_ds = 578; - protected static final int gen_lsrl_dd_ds = 587; + protected static final int gen_lsrl_dd_ds = 579; - protected static final int gen_lsrw_ea = 588; + protected static final int gen_lsrw_ea = 580; - protected static final int gen_lslb_ir_ds = 589; + protected static final int gen_lslb_ir_ds = 581; - protected static final int gen_lslb_dd_ds = 590; + protected static final int gen_lslb_dd_ds = 582; - protected static final int gen_lslw_ir_ds = 591; + protected static final int gen_lslw_ir_ds = 583; - protected static final int gen_lslw_dd_ds = 592; + protected static final int gen_lslw_dd_ds = 584; - protected static final int gen_lsll_ir_ds = 593; + protected static final int gen_lsll_ir_ds = 585; - protected static final int gen_lsll_dd_ds = 594; + protected static final int gen_lsll_dd_ds = 586; - protected static final int gen_lslw_ea = 595; + protected static final int gen_lslw_ea = 587; - protected static final int gen_rorb_ir_ds = 596; + protected static final int gen_rorb_ir_ds = 588; - protected static final int gen_rorb_dd_ds = 597; + protected static final int gen_rorb_dd_ds = 589; - protected static final int gen_rorw_ir_ds = 598; + protected static final int gen_rorw_ir_ds = 590; - protected static final int gen_rorw_dd_ds = 599; + protected static final int gen_rorw_dd_ds = 591; - protected static final int gen_rorl_ir_ds = 600; + protected static final int gen_rorl_ir_ds = 592; - protected static final int gen_rorl_dd_ds = 601; + protected static final int gen_rorl_dd_ds = 593; - protected static final int gen_rorw_ea = 602; + protected static final int gen_rorw_ea = 594; - protected static final int gen_rolb_ir_ds = 603; + protected static final int gen_rolb_ir_ds = 595; - protected static final int gen_rolb_dd_ds = 604; + protected static final int gen_rolb_dd_ds = 596; - protected static final int gen_rolw_ir_ds = 605; + protected static final int gen_rolw_ir_ds = 597; - protected static final int gen_rolw_dd_ds = 606; + protected static final int gen_rolw_dd_ds = 598; - protected static final int gen_roll_ir_ds = 607; + protected static final int gen_roll_ir_ds = 599; - protected static final int gen_roll_dd_ds = 608; + protected static final int gen_roll_dd_ds = 600; - protected static final int gen_rolw_ea = 609; + protected static final int gen_rolw_ea = 601; public static final int BKPT_EXIT = 0x00010000; @@ -4195,21 +4195,6 @@ public abstract class Core extends CoreALU { case 269: /* op_movemw_rr_ea */ nmpc = 270; elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = fetch16(aob); - scan += 2; - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 270: - dt = dib; - nmpc = 271; - elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { mpc = aerr; @@ -4220,17 +4205,17 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 271: + case 270: alub = 0; - nmpc = 272; - case 272: + nmpc = 271; + case 271: if (alub >= 16) { ssw &= ~0xbfe7; mpc = resume; continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 272; + mpc = 271; continue; } rz = alub == 15 ? sp : alub; @@ -4247,25 +4232,10 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - mpc = 272; + mpc = 271; continue; - case 273: /* op_movemw_rr_pais */ - nmpc = 274; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = fetch16(aob); - scan += 2; - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 274: - dt = dib; - nmpc = 275; + case 272: /* op_movemw_rr_pais */ + nmpc = 273; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4277,10 +4247,10 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 275: + case 273: alub = 0; - nmpc = 276; - case 276: + nmpc = 274; + case 274: if (alub >= 16) { ssw &= ~0xbfe7; ry = ir & 0x0007; @@ -4290,7 +4260,7 @@ public abstract class Core extends CoreALU { continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 276; + mpc = 274; continue; } rz = alub == 0 ? sp : 15 - alub; @@ -4307,24 +4277,51 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - mpc = 276; + mpc = 274; continue; - case 277: /* op_moveml_rr_ea */ - nmpc = 278; + case 275: /* op_moveml_rr_ea */ + nmpc = 276; elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { mpc = aerr; continue; } - dib = fetch16(aob); - scan += 2; + irb = fetch16(aob); if ((ssw & 0x0030) != 0) { mpc = bevt; continue; } - case 278: - dt = dib; + case 276: + alub = 0; + nmpc = 277; + case 277: + if (alub >= 16) { + ssw &= ~0xbfe7; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 277; + continue; + } + rz = alub == 15 ? sp : alub; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + write32(aob, dob = dar[rz]); + alub += 1; + at += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtw32; + continue; + } + mpc = 277; + continue; + case 278: /* op_moveml_rr_pais */ nmpc = 279; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; @@ -4341,63 +4338,6 @@ public abstract class Core extends CoreALU { alub = 0; nmpc = 280; case 280: - if (alub >= 16) { - ssw &= ~0xbfe7; - mpc = resume; - continue; - } else if ((dt & (1 << alub)) == 0) { - alub += 1; - mpc = 280; - continue; - } - rz = alub == 15 ? sp : alub; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; - if (((aob = at) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - write32(aob, dob = dar[rz]); - alub += 1; - at += 4; - if ((ssw & 0x0070) != 0x0040) { - mpc = bevtw32; - continue; - } - mpc = 280; - continue; - case 281: /* op_moveml_rr_pais */ - nmpc = 282; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = fetch16(aob); - scan += 2; - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 282: - dt = dib; - nmpc = 283; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - irb = fetch16(aob); - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 283: - alub = 0; - nmpc = 284; - case 284: if (alub >= 16) { ssw &= ~0xbfe7; ry = ir & 0x0007; @@ -4407,7 +4347,7 @@ public abstract class Core extends CoreALU { continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 284; + mpc = 280; continue; } rz = alub == 0 ? sp : 15 - alub; @@ -4424,100 +4364,70 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - mpc = 284; + mpc = 280; continue; - case 285: /* op_movemw_ea_rr */ - nmpc = 286; + case 281: /* op_movemw_ea_rr */ + nmpc = 282; elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; if (((aob = pc + scan) & 0x000000001) != 0) { mpc = aerr; continue; } - dib = fetch16(aob); - scan += 2; + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 282: + alub = 0; + nmpc = 283; + case 283: + if (alub >= 16) { + ssw &= ~0xbfe7; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 283; + continue; + } + rz = alub == 15 ? sp : alub; + nmpc = 284; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9100; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read16(aob); + alub += 1; + at += 2; + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 284: + dar[rz] = (short) dib; + mpc = 283; + continue; + case 285: /* op_movemw_aips_rr */ + nmpc = 286; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); if ((ssw & 0x0030) != 0) { mpc = bevt; continue; } case 286: - dt = dib; + alub = 0; nmpc = 287; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - irb = fetch16(aob); - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } case 287: - alub = 0; - nmpc = 288; - case 288: - if (alub >= 16) { - ssw &= ~0xbfe7; - mpc = resume; - continue; - } else if ((dt & (1 << alub)) == 0) { - alub += 1; - mpc = 288; - continue; - } - rz = alub == 15 ? sp : alub; - nmpc = 289; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9100; - if (((aob = at) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = read16(aob); - alub += 1; - at += 2; - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 289: - dar[rz] = (short) dib; - mpc = 288; - continue; - case 290: /* op_movemw_aips_rr */ - nmpc = 291; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = fetch16(aob); - scan += 2; - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 291: - dt = dib; - nmpc = 292; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - irb = fetch16(aob); - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 292: - alub = 0; - nmpc = 293; - case 293: if (alub >= 16) { ssw &= ~0xbfe7; ry = ir & 0x0007; @@ -4527,11 +4437,11 @@ public abstract class Core extends CoreALU { continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 293; + mpc = 287; continue; } rz = alub == 15 ? sp : alub; - nmpc = 294; + nmpc = 288; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9100; if (((aob = at) & 0x000000001) != 0) { @@ -4545,102 +4455,72 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } + case 288: + dar[rz] = (short) dib; + mpc = 287; + continue; + case 289: /* op_moveml_ea_rr */ + nmpc = 290; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } + case 290: + alub = 0; + nmpc = 291; + case 291: + if (alub >= 16) { + ssw &= ~0xbfe7; + mpc = resume; + continue; + } else if ((dt & (1 << alub)) == 0) { + alub += 1; + mpc = 291; + continue; + } + rz = alub == 15 ? sp : alub; + nmpc = 292; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c0; + if (((aob = at) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + dib = read32(aob); + alub += 1; + at += 4; + if ((ssw & 0x0070) != 0x0040) { + mpc = bevtr32; + continue; + } + case 292: + dar[rz] = dib; + mpc = 291; + continue; + case 293: /* op_moveml_aips_rr */ + nmpc = 294; + elapsed += 4; + ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; + if (((aob = pc + scan) & 0x000000001) != 0) { + mpc = aerr; + continue; + } + irb = fetch16(aob); + if ((ssw & 0x0030) != 0) { + mpc = bevt; + continue; + } case 294: - dar[rz] = (short) dib; - mpc = 293; - continue; - case 295: /* op_moveml_ea_rr */ - nmpc = 296; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = fetch16(aob); - scan += 2; - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 296: - dt = dib; - nmpc = 297; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - irb = fetch16(aob); - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 297: alub = 0; - nmpc = 298; - case 298: - if (alub >= 16) { - ssw &= ~0xbfe7; - mpc = resume; - continue; - } else if ((dt & (1 << alub)) == 0) { - alub += 1; - mpc = 298; - continue; - } - rz = alub == 15 ? sp : alub; - nmpc = 299; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c0; - if (((aob = at) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = read32(aob); - alub += 1; - at += 4; - if ((ssw & 0x0070) != 0x0040) { - mpc = bevtr32; - continue; - } - case 299: - dar[rz] = dib; - mpc = 298; - continue; - case 300: /* op_moveml_aips_rr */ - nmpc = 301; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - dib = fetch16(aob); - scan += 2; - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 301: - dt = dib; - nmpc = 302; - elapsed += 4; - ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0xa102; - if (((aob = pc + scan) & 0x000000001) != 0) { - mpc = aerr; - continue; - } - irb = fetch16(aob); - if ((ssw & 0x0030) != 0) { - mpc = bevt; - continue; - } - case 302: - alub = 0; - nmpc = 303; - case 303: + nmpc = 295; + case 295: if (alub >= 16) { ssw &= ~0xbfe7; ry = ir & 0x0007; @@ -4650,11 +4530,11 @@ public abstract class Core extends CoreALU { continue; } else if ((dt & (1 << alub)) == 0) { alub += 1; - mpc = 303; + mpc = 295; continue; } rz = alub == 15 ? sp : alub; - nmpc = 304; + nmpc = 296; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c0; if (((aob = at) & 0x000000001) != 0) { @@ -4668,51 +4548,51 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 304: + case 296: dar[rz] = dib; - mpc = 303; + mpc = 295; continue; - case 305: /* op_bcc8 */ + case 297: /* op_bcc8 */ if (!testCC((ir & 0x0f00) >> 8)) { elapsed += 2; mpc = resume_prefetch; continue; } - case 306: /* op_bra8 */ + case 298: /* op_bra8 */ elapsed += 2; scan = (byte) ir; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 307: /* op_bcc16 */ + case 299: /* op_bcc16 */ if (!testCC((ir & 0x0f00) >> 8)) { elapsed += 2; mpc = resume_prefetch; continue; } - case 308: /* op_bra16 */ + case 300: /* op_bra16 */ elapsed += 2; scan = (short) dt; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 309: /* op_bcc32 */ + case 301: /* op_bcc32 */ if (!testCC((ir & 0x0f00) >> 8)) { elapsed += 2; mpc = resume_prefetch; continue; } - case 310: /* op_bra32 */ + case 302: /* op_bra32 */ elapsed += 2; scan = dt; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 311: /* op_bsr8 */ + case 303: /* op_bsr8 */ elapsed += 2; au = dar[sp] - 4; dar[sp] = au; - nmpc = 312; + nmpc = 304; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -4724,16 +4604,16 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 312: + case 304: scan = (byte) ir; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 313: /* op_bsr16 */ + case 305: /* op_bsr16 */ elapsed += 2; au = dar[sp] - 4; dar[sp] = au; - nmpc = 314; + nmpc = 306; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -4745,16 +4625,16 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 314: + case 306: scan = (short) dt; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 315: /* op_bsr32 */ + case 307: /* op_bsr32 */ elapsed += 2; au = dar[sp] - 4; dar[sp] = au; - nmpc = 316; + nmpc = 308; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -4766,12 +4646,12 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 316: + case 308: scan = dt; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 317: /* op_dbcc */ + case 309: /* op_dbcc */ if (testCC((ir & 0x0f00) >> 8)) { elapsed += 2; scan += 2; @@ -4786,7 +4666,7 @@ public abstract class Core extends CoreALU { mpc = resume_prefetch; continue; } - nmpc = 318; + nmpc = 310; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9102; if (((aob = pc + scan) & 0x000000001) != 0) { @@ -4798,12 +4678,12 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 318: + case 310: scan += (short) dib; elapsed += 2; mpc = resume_prefetch; continue; - case 319: /* op_bkpt */ + case 311: /* op_bkpt */ elapsed += 6; hdlr = handle_bkpt(cip, ir & 0x0007); exit |= (hdlr & 0x00010000) != 0; @@ -4817,7 +4697,7 @@ public abstract class Core extends CoreALU { tvn = 16; mpc = trapill; continue; - case 320: /* op_illegal */ + case 312: /* op_illegal */ elapsed += 6; hdlr = handle_illegal(cip, ir); exit |= (hdlr & 0x00010000) != 0; @@ -4830,16 +4710,16 @@ public abstract class Core extends CoreALU { tvn = 16; mpc = trapill; continue; - case 321: /* op_jmp */ + case 313: /* op_jmp */ pc = at; scan = 0; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 322: /* op_jsr */ + case 314: /* op_jsr */ au = dar[sp] - 4; dar[sp] = au; - nmpc = 323; + nmpc = 315; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x80c1; if (((aob = au) & 0x000000001) != 0) { @@ -4851,13 +4731,13 @@ public abstract class Core extends CoreALU { mpc = bevtw32; continue; } - case 323: + case 315: pc = at; scan = 0; sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 324: /* op_linea */ + case 316: /* op_linea */ elapsed += 6; hdlr = handle_linea(cip, ir & 0x0fff); exit |= (hdlr & 0x00010000) != 0; @@ -4870,15 +4750,15 @@ public abstract class Core extends CoreALU { tvn = 40; mpc = trapill; continue; - case 325: /* op_linef */ + case 317: /* op_linef */ elapsed += 6; tvn = 44; mpc = trapill; continue; - case 326: /* op_nop */ + case 318: /* op_nop */ mpc = resume_prefetch; continue; - case 327: /* op_rte */ + case 319: /* op_rte */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -4886,7 +4766,7 @@ public abstract class Core extends CoreALU { continue; } au = dar[sp]; - case 328: /* check_vob */ + case 320: /* check_vob */ elapsed += 4; ssw = (ssw & 0x0018) | 0x9105; if (((aob = au + 0x0006) & 0x000000001) != 0) { @@ -4900,12 +4780,12 @@ public abstract class Core extends CoreALU { } mpc = select_rte(dib); continue; - case 329: /* rteill */ + case 321: /* rteill */ elapsed += 6; tvn = 56; mpc = trapill; continue; - case 330: /* exit_trap */ + case 322: /* exit_trap */ elapsed += 8; ssw = (ssw & 0x0018) | 0x91c5; pc = read32(aob = au + 0x0002); @@ -4925,20 +4805,20 @@ public abstract class Core extends CoreALU { scan = 0; mpc = resume_prefetch; continue; - case 331: /* rte0000 */ + case 323: /* rte0000 */ dar[sp] = au + 8; mpc = exit_trap; continue; - case 332: /* rte1000 */ + case 324: /* rte1000 */ dar[sp] = au + 8; au = dar[sp = spi(sr | 0x1000)]; mpc = check_vob; continue; - case 333: /* rte2000 */ + case 325: /* rte2000 */ dar[sp] = au + 12; mpc = exit_trap; continue; - case 334: /* rte8000 */ + case 326: /* rte8000 */ elapsed += 6; elapsed += 8; ssw = (ssw & 0x0018) | 0x91c5; @@ -5173,9 +5053,9 @@ public abstract class Core extends CoreALU { continue; } break; - case 335: /* op_rtr */ + case 327: /* op_rtr */ au = dar[sp]; - nmpc = 336; + nmpc = 328; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; if (((aob = au + 0x0002) & 0x000000001) != 0) { @@ -5187,9 +5067,9 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 336: + case 328: pc = dib; - nmpc = 337; + nmpc = 329; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x9101; dib = read16(aob = au); @@ -5197,7 +5077,7 @@ public abstract class Core extends CoreALU { mpc = bevt; continue; } - case 337: + case 329: ssw &= ~0xbfe7; sr = (sr & ~0x001f) | (dib & 0x001f); scan = 0; @@ -5205,9 +5085,9 @@ public abstract class Core extends CoreALU { sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 338: /* op_rts */ + case 330: /* op_rts */ au = dar[sp]; - nmpc = 339; + nmpc = 331; elapsed += 4; ssw = (ssw & 0x0018) | ((sr >> 11) & 0x0004) | 0x91c1; if (((aob = au) & 0x000000001) != 0) { @@ -5219,7 +5099,7 @@ public abstract class Core extends CoreALU { mpc = bevtr32; continue; } - case 339: + case 331: pc = dib; ssw &= ~0xbfe7; scan = 0; @@ -5227,16 +5107,16 @@ public abstract class Core extends CoreALU { sswi |= (sr & 0x4000); mpc = resume_prefetch; continue; - case 340: /* op_reset */ + case 332: /* op_reset */ elapsed += 126; mpc = resume_prefetch; continue; - case 341: /* op_trap */ + case 333: /* op_trap */ elapsed += 6; tvn = (32 + (ir & 0x000f)) << 2; mpc = trap0000; continue; - case 342: /* op_trapv */ + case 334: /* op_trapv */ if ((sr & 0x0002) != 0) { elapsed += 4; tvn = 28; @@ -5245,7 +5125,7 @@ public abstract class Core extends CoreALU { } mpc = resume_prefetch; continue; - case 343: /* op_trapcc */ + case 335: /* op_trapcc */ if (!testCC((ir & 0x0f00) >> 8)) { mpc = resume_prefetch; continue; @@ -5254,7 +5134,7 @@ public abstract class Core extends CoreALU { tvn = 28; mpc = trap2000; continue; - case 344: /* op_trapcc16 */ + case 336: /* op_trapcc16 */ scan += 2; if (!testCC((ir & 0x0f00) >> 8)) { mpc = resume_prefetch; @@ -5264,7 +5144,7 @@ public abstract class Core extends CoreALU { tvn = 28; mpc = trap2000; continue; - case 345: /* op_trapcc32 */ + case 337: /* op_trapcc32 */ scan += 4; if (!testCC((ir & 0x0f00) >> 8)) { mpc = resume_prefetch; @@ -5274,41 +5154,41 @@ public abstract class Core extends CoreALU { tvn = 28; mpc = trap2000; continue; - case 346: /* gen_orb_dt_ds */ + case 338: /* gen_orb_dt_ds */ ry = ir & 0x0007; dt = byte_or(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 347: /* gen_orb_im_ea */ + case 339: /* gen_orb_im_ea */ dt = byte_or(alub, dt); mpc = ea_resume_write8; continue; - case 348: /* gen_orw_dt_ds */ + case 340: /* gen_orw_dt_ds */ ry = ir & 0x0007; dt = word_or(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 349: /* gen_orw_im_ea */ + case 341: /* gen_orw_im_ea */ dt = word_or(alub, dt); mpc = ea_resume_write16; continue; - case 350: /* gen_orl_dt_ds */ + case 342: /* gen_orl_dt_ds */ ry = ir & 0x0007; dt = long_or(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 351: /* gen_orl_im_ea */ + case 343: /* gen_orl_im_ea */ dt = long_or(alub, dt); mpc = ea_resume_write32; continue; - case 352: /* gen_orb_dt_ccr */ + case 344: /* gen_orb_dt_ccr */ sr = (sr & ~0xff) | ((sr | dt) & 0x1f); mpc = resume_prefetch; continue; - case 353: /* gen_orw_dt_sr */ + case 345: /* gen_orw_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5318,88 +5198,88 @@ public abstract class Core extends CoreALU { sr = (sr | dt) & 0xf71f; mpc = resume_prefetch; continue; - case 354: /* gen_btstl_dd_ds */ + case 346: /* gen_btstl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; long_btst(dar[rx], dar[ry]); mpc = resume_prefetch; continue; - case 355: /* gen_btstb_dd_ea */ + case 347: /* gen_btstb_dd_ea */ rx = (ir >> 9) & 0x0007; byte_btst(dar[rx], dt); mpc = resume_prefetch; continue; - case 356: /* gen_bchgl_dd_ds */ + case 348: /* gen_bchgl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bchg(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 357: /* gen_bchgb_dd_ea */ + case 349: /* gen_bchgb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_bchg(dar[rx], dt); mpc = ea_resume_write8; continue; - case 358: /* gen_bclrl_dd_ds */ + case 350: /* gen_bclrl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bclr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 359: /* gen_bclrb_dd_ea */ + case 351: /* gen_bclrb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_bclr(dar[rx], dt); mpc = ea_resume_write8; continue; - case 360: /* gen_bsetl_dd_ds */ + case 352: /* gen_bsetl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_bset(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 361: /* gen_bsetb_dd_ea */ + case 353: /* gen_bsetb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_bset(dar[rx], dt); mpc = ea_resume_write8; continue; - case 362: /* gen_andb_dt_ds */ + case 354: /* gen_andb_dt_ds */ ry = ir & 0x0007; dt = byte_and(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 363: /* gen_andb_im_ea */ + case 355: /* gen_andb_im_ea */ dt = byte_and(alub, dt); mpc = ea_resume_write8; continue; - case 364: /* gen_andw_dt_ds */ + case 356: /* gen_andw_dt_ds */ ry = ir & 0x0007; dt = word_and(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 365: /* gen_andw_im_ea */ + case 357: /* gen_andw_im_ea */ dt = word_and(alub, dt); mpc = ea_resume_write16; continue; - case 366: /* gen_andl_dt_ds */ + case 358: /* gen_andl_dt_ds */ ry = ir & 0x0007; dt = long_and(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 367: /* gen_andl_im_ea */ + case 359: /* gen_andl_im_ea */ dt = long_and(alub, dt); mpc = ea_resume_write32; continue; - case 368: /* gen_andb_dt_ccr */ + case 360: /* gen_andb_dt_ccr */ sr = (sr & ~0xff) | (sr & dt & 0x1f); mpc = resume_prefetch; continue; - case 369: /* gen_andw_dt_sr */ + case 361: /* gen_andw_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5409,140 +5289,140 @@ public abstract class Core extends CoreALU { sr = sr & dt; mpc = resume_prefetch; continue; - case 370: /* gen_subb_dt_ds */ + case 362: /* gen_subb_dt_ds */ ry = ir & 0x0007; dt = byte_sub(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 371: /* gen_subb_im_ea */ + case 363: /* gen_subb_im_ea */ dt = byte_sub(alub, dt); mpc = ea_resume_write8; continue; - case 372: /* gen_subw_dt_ds */ + case 364: /* gen_subw_dt_ds */ ry = ir & 0x0007; dt = word_sub(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 373: /* gen_subw_im_ea */ + case 365: /* gen_subw_im_ea */ dt = word_sub(alub, dt); mpc = ea_resume_write16; continue; - case 374: /* gen_subl_dt_ds */ + case 366: /* gen_subl_dt_ds */ ry = ir & 0x0007; dt = long_sub(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 375: /* gen_subl_im_ea */ + case 367: /* gen_subl_im_ea */ dt = long_sub(alub, dt); mpc = ea_resume_write32; continue; - case 376: /* gen_addb_dt_ds */ + case 368: /* gen_addb_dt_ds */ ry = ir & 0x0007; dt = byte_add(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 377: /* gen_addb_im_ea */ + case 369: /* gen_addb_im_ea */ dt = byte_add(alub, dt); mpc = ea_resume_write8; continue; - case 378: /* gen_addw_dt_ds */ + case 370: /* gen_addw_dt_ds */ ry = ir & 0x0007; dt = word_add(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 379: /* gen_addw_im_ea */ + case 371: /* gen_addw_im_ea */ dt = word_add(alub, dt); mpc = ea_resume_write16; continue; - case 380: /* gen_addl_dt_ds */ + case 372: /* gen_addl_dt_ds */ ry = ir & 0x0007; dt = long_add(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 381: /* gen_addl_im_ea */ + case 373: /* gen_addl_im_ea */ dt = long_add(alub, dt); mpc = ea_resume_write32; continue; - case 382: /* gen_btstl_dt_ds */ + case 374: /* gen_btstl_dt_ds */ ry = ir & 0x0007; long_btst(dt, dar[ry]); mpc = resume_prefetch; continue; - case 383: /* gen_btstb_im_ea */ + case 375: /* gen_btstb_im_ea */ byte_btst(alub, dt); mpc = resume_prefetch; continue; - case 384: /* gen_bchgl_dt_ds */ + case 376: /* gen_bchgl_dt_ds */ ry = ir & 0x0007; dt = long_bchg(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 385: /* gen_bchgb_im_ea */ + case 377: /* gen_bchgb_im_ea */ dt = byte_bchg(alub, dt); mpc = ea_resume_write8; continue; - case 386: /* gen_bclrl_dt_ds */ + case 378: /* gen_bclrl_dt_ds */ ry = ir & 0x0007; dt = long_bclr(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 387: /* gen_bclrb_im_ea */ + case 379: /* gen_bclrb_im_ea */ dt = byte_bclr(alub, dt); mpc = ea_resume_write8; continue; - case 388: /* gen_bsetl_dt_ds */ + case 380: /* gen_bsetl_dt_ds */ ry = ir & 0x0007; dt = long_bset(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 389: /* gen_bsetb_im_ea */ + case 381: /* gen_bsetb_im_ea */ dt = byte_bset(alub, dt); mpc = ea_resume_write8; continue; - case 390: /* gen_eorb_dt_ds */ + case 382: /* gen_eorb_dt_ds */ ry = ir & 0x0007; dt = byte_eor(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 391: /* gen_eorb_im_ea */ + case 383: /* gen_eorb_im_ea */ dt = byte_eor(alub, dt); mpc = ea_resume_write8; continue; - case 392: /* gen_eorw_dt_ds */ + case 384: /* gen_eorw_dt_ds */ ry = ir & 0x0007; dt = word_eor(dt, dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 393: /* gen_eorw_im_ea */ + case 385: /* gen_eorw_im_ea */ dt = word_eor(alub, dt); mpc = ea_resume_write16; continue; - case 394: /* gen_eorl_dt_ds */ + case 386: /* gen_eorl_dt_ds */ ry = ir & 0x0007; dt = long_eor(dt, dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 395: /* gen_eorl_im_ea */ + case 387: /* gen_eorl_im_ea */ dt = long_eor(alub, dt); mpc = ea_resume_write32; continue; - case 396: /* gen_eorb_dt_ccr */ + case 388: /* gen_eorb_dt_ccr */ sr = (sr & ~0xff) | ((sr ^ dt) & 0x1f); mpc = resume_prefetch; continue; - case 397: /* gen_eorw_dt_sr */ + case 389: /* gen_eorw_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5552,83 +5432,83 @@ public abstract class Core extends CoreALU { sr = (sr ^ dt) & 0xf71f; mpc = resume_prefetch; continue; - case 398: /* gen_cmpb_dt_ds */ + case 390: /* gen_cmpb_dt_ds */ ry = ir & 0x0007; byte_cmp(dt, dar[ry]); mpc = resume_prefetch; continue; - case 399: /* gen_cmpb_im_ea */ + case 391: /* gen_cmpb_im_ea */ byte_cmp(alub, dt); mpc = resume_prefetch; continue; - case 400: /* gen_cmpw_dt_ds */ + case 392: /* gen_cmpw_dt_ds */ ry = ir & 0x0007; word_cmp(dt, dar[ry]); mpc = resume_prefetch; continue; - case 401: /* gen_cmpw_im_ea */ + case 393: /* gen_cmpw_im_ea */ word_cmp(alub, dt); mpc = resume_prefetch; continue; - case 402: /* gen_cmpl_dt_ds */ + case 394: /* gen_cmpl_dt_ds */ ry = ir & 0x0007; long_cmp(dt, dar[ry]); mpc = resume_prefetch; continue; - case 403: /* gen_cmpl_im_ea */ + case 395: /* gen_cmpl_im_ea */ long_cmp(alub, dt); mpc = resume_prefetch; continue; - case 404: /* gen_moveb_ds_ea */ + case 396: /* gen_moveb_ds_ea */ ry = ir & 0x0007; byte_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write8; continue; - case 405: /* gen_moveb_dt_dd */ + case 397: /* gen_moveb_dt_dd */ rx = (ir >> 9) & 0x0007; byte_tst(dt); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 406: /* gen_moveb_ds_dd */ + case 398: /* gen_moveb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; byte_tst(dar[ry]); dar[rx] = (dar[rx] & ~0xff) | (dar[ry] & 0xff); mpc = resume_prefetch; continue; - case 407: /* gen_moveb_dt_ea */ + case 399: /* gen_moveb_dt_ea */ byte_tst(dt); mpc = ea_resume_write8; continue; - case 408: /* gen_movel_ds_ea */ + case 400: /* gen_movel_ds_ea */ ry = ir & 0x0007; long_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write32; continue; - case 409: /* gen_movel_as_ea */ + case 401: /* gen_movel_as_ea */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; long_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write32; continue; - case 410: /* gen_movel_dt_dd */ + case 402: /* gen_movel_dt_dd */ rx = (ir >> 9) & 0x0007; long_tst(dt); dar[rx] = dt; mpc = resume_prefetch; continue; - case 411: /* gen_movel_ds_dd */ + case 403: /* gen_movel_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; long_tst(dar[ry]); dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 412: /* gen_movel_as_dd */ + case 404: /* gen_movel_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5636,18 +5516,18 @@ public abstract class Core extends CoreALU { dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 413: /* gen_movel_dt_ea */ + case 405: /* gen_movel_dt_ea */ long_tst(dt); mpc = ea_resume_write32; continue; - case 414: /* gen_movel_ds_ad */ + case 406: /* gen_movel_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 415: /* gen_movel_as_ad */ + case 407: /* gen_movel_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5655,39 +5535,39 @@ public abstract class Core extends CoreALU { dar[rx] = dar[ry]; mpc = resume_prefetch; continue; - case 416: /* gen_movel_dt_ad */ + case 408: /* gen_movel_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dt; mpc = resume_prefetch; continue; - case 417: /* gen_movew_ds_ea */ + case 409: /* gen_movew_ds_ea */ ry = ir & 0x0007; word_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write16; continue; - case 418: /* gen_movew_as_ea */ + case 410: /* gen_movew_as_ea */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; word_tst(dar[ry]); dt = dar[ry]; mpc = ea_resume_write16; continue; - case 419: /* gen_movew_dt_dd */ + case 411: /* gen_movew_dt_dd */ rx = (ir >> 9) & 0x0007; word_tst(dt); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 420: /* gen_movew_ds_dd */ + case 412: /* gen_movew_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; word_tst(dar[ry]); dar[rx] = (dar[rx] & ~0xffff) | (dar[ry] & 0xffff); mpc = resume_prefetch; continue; - case 421: /* gen_movew_as_dd */ + case 413: /* gen_movew_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5695,18 +5575,18 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dar[ry] & 0xffff); mpc = resume_prefetch; continue; - case 422: /* gen_movew_dt_ea */ + case 414: /* gen_movew_dt_ea */ word_tst(dt); mpc = ea_resume_write16; continue; - case 423: /* gen_movew_ds_ad */ + case 415: /* gen_movew_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = (short) dar[ry]; mpc = resume_prefetch; continue; - case 424: /* gen_movew_as_ad */ + case 416: /* gen_movew_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -5714,43 +5594,43 @@ public abstract class Core extends CoreALU { dar[rx] = (short) dar[ry]; mpc = resume_prefetch; continue; - case 425: /* gen_movew_dt_ad */ + case 417: /* gen_movew_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = (short) dt; mpc = resume_prefetch; continue; - case 426: /* gen_negxb_ds */ + case 418: /* gen_negxb_ds */ ry = ir & 0x0007; dt = byte_negx(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 427: /* gen_negxb_ea */ + case 419: /* gen_negxb_ea */ dt = byte_negx(dt); mpc = ea_resume_write8; continue; - case 428: /* gen_negxw_ds */ + case 420: /* gen_negxw_ds */ ry = ir & 0x0007; dt = word_negx(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 429: /* gen_negxw_ea */ + case 421: /* gen_negxw_ea */ dt = word_negx(dt); mpc = ea_resume_write16; continue; - case 430: /* gen_negxl_ds */ + case 422: /* gen_negxl_ds */ ry = ir & 0x0007; dt = long_negx(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 431: /* gen_negxl_ea */ + case 423: /* gen_negxl_ea */ dt = long_negx(dt); mpc = ea_resume_write32; continue; - case 432: /* gen_movew_sr_ds */ + case 424: /* gen_movew_sr_ds */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5761,7 +5641,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (sr & 0xffff); mpc = resume_prefetch; continue; - case 433: /* gen_movew_sr_ea */ + case 425: /* gen_movew_sr_ea */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5771,25 +5651,25 @@ public abstract class Core extends CoreALU { dt = (sr & 0xf71f); mpc = ea_resume_write16; continue; - case 434: /* gen_movew_ccr_ds */ + case 426: /* gen_movew_ccr_ds */ ry = ir & 0x0007; dar[ry] = (dar[ry] & ~0xffff) | (sr & 0x001f); mpc = resume_prefetch; continue; - case 435: /* gen_movew_ccr_ea */ + case 427: /* gen_movew_ccr_ea */ dt = (sr & 0x001f); mpc = ea_resume_write16; continue; - case 436: /* gen_movew_ds_ccr */ + case 428: /* gen_movew_ds_ccr */ ry = ir & 0x0007; sr = (sr & ~0xff) | (dar[ry] & 0x001f); mpc = resume_prefetch; continue; - case 437: /* gen_movew_dt_ccr */ + case 429: /* gen_movew_dt_ccr */ sr = (sr & ~0xff) | (dt & 0x001f); mpc = resume_prefetch; continue; - case 438: /* gen_movew_ds_sr */ + case 430: /* gen_movew_ds_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5800,7 +5680,7 @@ public abstract class Core extends CoreALU { sr = dar[ry] & 0xf71f; mpc = resume_prefetch; continue; - case 439: /* gen_movew_dt_sr */ + case 431: /* gen_movew_dt_sr */ if ((sr & 0x2000) == 0) { elapsed += 6; tvn = 32; @@ -5810,104 +5690,104 @@ public abstract class Core extends CoreALU { sr = dt & 0xf71f; mpc = resume_prefetch; continue; - case 440: /* gen_negb_ds */ + case 432: /* gen_negb_ds */ ry = ir & 0x0007; dt = byte_neg(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 441: /* gen_negb_ea */ + case 433: /* gen_negb_ea */ dt = byte_neg(dt); mpc = ea_resume_write8; continue; - case 442: /* gen_negw_ds */ + case 434: /* gen_negw_ds */ ry = ir & 0x0007; dt = word_neg(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 443: /* gen_negw_ea */ + case 435: /* gen_negw_ea */ dt = word_neg(dt); mpc = ea_resume_write16; continue; - case 444: /* gen_negl_ds */ + case 436: /* gen_negl_ds */ ry = ir & 0x0007; dt = long_neg(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 445: /* gen_negl_ea */ + case 437: /* gen_negl_ea */ dt = long_neg(dt); mpc = ea_resume_write32; continue; - case 446: /* gen_notb_ds */ + case 438: /* gen_notb_ds */ ry = ir & 0x0007; dt = byte_not(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 447: /* gen_notb_ea */ + case 439: /* gen_notb_ea */ dt = byte_not(dt); mpc = ea_resume_write8; continue; - case 448: /* gen_notw_ds */ + case 440: /* gen_notw_ds */ ry = ir & 0x0007; dt = word_not(dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 449: /* gen_notw_ea */ + case 441: /* gen_notw_ea */ dt = word_not(dt); mpc = ea_resume_write16; continue; - case 450: /* gen_notl_ds */ + case 442: /* gen_notl_ds */ ry = ir & 0x0007; dt = long_not(dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 451: /* gen_notl_ea */ + case 443: /* gen_notl_ea */ dt = long_not(dt); mpc = ea_resume_write32; continue; - case 452: /* gen_nbcdb_ds */ + case 444: /* gen_nbcdb_ds */ ry = ir & 0x0007; dt = byte_nbcd(dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 453: /* gen_nbcdb_ea */ + case 445: /* gen_nbcdb_ea */ dt = byte_nbcd(dt); mpc = ea_resume_write8; continue; - case 454: /* gen_tstb_ds */ + case 446: /* gen_tstb_ds */ ry = ir & 0x0007; byte_tst(dar[ry]); mpc = resume_prefetch; continue; - case 455: /* gen_tstb_ea */ + case 447: /* gen_tstb_ea */ byte_tst(dt); mpc = resume_prefetch; continue; - case 456: /* gen_tstw_ds */ + case 448: /* gen_tstw_ds */ ry = ir & 0x0007; word_tst(dar[ry]); mpc = resume_prefetch; continue; - case 457: /* gen_tstw_ea */ + case 449: /* gen_tstw_ea */ word_tst(dt); mpc = resume_prefetch; continue; - case 458: /* gen_tstl_ds */ + case 450: /* gen_tstl_ds */ ry = ir & 0x0007; long_tst(dar[ry]); mpc = resume_prefetch; continue; - case 459: /* gen_tstl_ea */ + case 451: /* gen_tstl_ea */ long_tst(dt); mpc = resume_prefetch; continue; - case 460: /* gen_addb_ir_ds */ + case 452: /* gen_addb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5917,7 +5797,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 461: /* gen_addb_ir_ea */ + case 453: /* gen_addb_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5925,7 +5805,7 @@ public abstract class Core extends CoreALU { dt = byte_add(alub, dt); mpc = ea_resume_write8; continue; - case 462: /* gen_addw_ir_ds */ + case 454: /* gen_addw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5935,7 +5815,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 463: /* gen_addw_ir_as */ + case 455: /* gen_addw_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5945,7 +5825,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] + ((short) alub); mpc = resume_prefetch; continue; - case 464: /* gen_addw_ir_ea */ + case 456: /* gen_addw_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5953,7 +5833,7 @@ public abstract class Core extends CoreALU { dt = word_add(alub, dt); mpc = ea_resume_write16; continue; - case 465: /* gen_addl_ir_ds */ + case 457: /* gen_addl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5963,7 +5843,7 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 466: /* gen_addl_ir_as */ + case 458: /* gen_addl_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5973,7 +5853,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] + alub; mpc = resume_prefetch; continue; - case 467: /* gen_addl_ir_ea */ + case 459: /* gen_addl_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5981,7 +5861,7 @@ public abstract class Core extends CoreALU { dt = long_add(alub, dt); mpc = ea_resume_write32; continue; - case 468: /* gen_subb_ir_ds */ + case 460: /* gen_subb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5991,7 +5871,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 469: /* gen_subb_ir_ea */ + case 461: /* gen_subb_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -5999,7 +5879,7 @@ public abstract class Core extends CoreALU { dt = byte_sub(alub, dt); mpc = ea_resume_write8; continue; - case 470: /* gen_subw_ir_ds */ + case 462: /* gen_subw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6009,7 +5889,7 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 471: /* gen_subw_ir_as */ + case 463: /* gen_subw_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6019,7 +5899,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] - ((short) alub); mpc = resume_prefetch; continue; - case 472: /* gen_subw_ir_ea */ + case 464: /* gen_subw_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6027,7 +5907,7 @@ public abstract class Core extends CoreALU { dt = word_sub(alub, dt); mpc = ea_resume_write16; continue; - case 473: /* gen_subl_ir_ds */ + case 465: /* gen_subl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6037,7 +5917,7 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 474: /* gen_subl_ir_as */ + case 466: /* gen_subl_ir_as */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6047,7 +5927,7 @@ public abstract class Core extends CoreALU { dar[ry] = dar[ry] - alub; mpc = resume_prefetch; continue; - case 475: /* gen_subl_ir_ea */ + case 467: /* gen_subl_ir_ea */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6055,99 +5935,99 @@ public abstract class Core extends CoreALU { dt = long_sub(alub, dt); mpc = ea_resume_write32; continue; - case 476: /* gen_movel_im_dd */ + case 468: /* gen_movel_im_dd */ dt = (byte) ir; rx = (ir >> 9) & 0x0007; long_tst(dt); dar[rx] = dt; mpc = resume_prefetch; continue; - case 477: /* gen_orb_ds_dd */ + case 469: /* gen_orb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_or(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 478: /* gen_orb_dt_dd */ + case 470: /* gen_orb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_or(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 479: /* gen_orw_ds_dd */ + case 471: /* gen_orw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_or(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 480: /* gen_orw_dt_dd */ + case 472: /* gen_orw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_or(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 481: /* gen_orl_ds_dd */ + case 473: /* gen_orl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_or(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 482: /* gen_orl_dt_dd */ + case 474: /* gen_orl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_or(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 483: /* gen_sbcdb_ds_dd */ + case 475: /* gen_sbcdb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_sbcd(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 484: /* gen_sbcdb_im_ea */ + case 476: /* gen_sbcdb_im_ea */ dt = byte_sbcd(alub, dt); mpc = ea_resume_write8; continue; - case 485: /* gen_orb_dd_ea */ + case 477: /* gen_orb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_or(dar[rx], dt); mpc = ea_resume_write8; continue; - case 486: /* gen_orw_dd_ea */ + case 478: /* gen_orw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_or(dar[rx], dt); mpc = ea_resume_write16; continue; - case 487: /* gen_orl_dd_ea */ + case 479: /* gen_orl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_or(dar[rx], dt); mpc = ea_resume_write32; continue; - case 488: /* gen_subb_ds_dd */ + case 480: /* gen_subb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_sub(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 489: /* gen_subb_dt_dd */ + case 481: /* gen_subb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_sub(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 490: /* gen_subw_ds_dd */ + case 482: /* gen_subw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_sub(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 491: /* gen_subw_as_dd */ + case 483: /* gen_subw_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6155,20 +6035,20 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 492: /* gen_subw_dt_dd */ + case 484: /* gen_subw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_sub(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 493: /* gen_subl_ds_dd */ + case 485: /* gen_subl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_sub(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 494: /* gen_subl_as_dd */ + case 486: /* gen_subl_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6176,68 +6056,68 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 495: /* gen_subl_dt_dd */ + case 487: /* gen_subl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_sub(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 496: /* gen_subb_dd_ea */ + case 488: /* gen_subb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_sub(dar[rx], dt); mpc = ea_resume_write8; continue; - case 497: /* gen_subw_dd_ea */ + case 489: /* gen_subw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_sub(dar[rx], dt); mpc = ea_resume_write16; continue; - case 498: /* gen_subl_dd_ea */ + case 490: /* gen_subl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_sub(dar[rx], dt); mpc = ea_resume_write32; continue; - case 499: /* gen_subxb_ds_dd */ + case 491: /* gen_subxb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_subx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 500: /* gen_subxb_im_ea */ + case 492: /* gen_subxb_im_ea */ dt = byte_subx(alub, dt); mpc = ea_resume_write8; continue; - case 501: /* gen_subxw_ds_dd */ + case 493: /* gen_subxw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_subx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 502: /* gen_subxw_im_ea */ + case 494: /* gen_subxw_im_ea */ dt = word_subx(alub, dt); mpc = ea_resume_write16; continue; - case 503: /* gen_subxl_ds_dd */ + case 495: /* gen_subxl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_subx(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 504: /* gen_subxl_im_ea */ + case 496: /* gen_subxl_im_ea */ dt = long_subx(alub, dt); mpc = ea_resume_write32; continue; - case 505: /* gen_subw_ds_ad */ + case 497: /* gen_subw_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - ((short) dar[ry]); mpc = resume_prefetch; continue; - case 506: /* gen_subw_as_ad */ + case 498: /* gen_subw_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6245,20 +6125,20 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] - ((short) dar[ry]); mpc = resume_prefetch; continue; - case 507: /* gen_subw_dt_ad */ + case 499: /* gen_subw_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - ((short) dt); mpc = resume_prefetch; continue; - case 508: /* gen_subl_ds_ad */ + case 500: /* gen_subl_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - dar[ry]; mpc = resume_prefetch; continue; - case 509: /* gen_subl_as_ad */ + case 501: /* gen_subl_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6266,67 +6146,67 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] - dar[ry]; mpc = resume_prefetch; continue; - case 510: /* gen_subl_dt_ad */ + case 502: /* gen_subl_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] - dt; mpc = resume_prefetch; continue; - case 511: /* gen_cmpb_ds_dd */ + case 503: /* gen_cmpb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; byte_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 512: /* gen_cmpb_dt_dd */ + case 504: /* gen_cmpb_dt_dd */ rx = (ir >> 9) & 0x0007; byte_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 513: /* gen_cmpw_ds_dd */ + case 505: /* gen_cmpw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; word_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 514: /* gen_cmpw_as_dd */ + case 506: /* gen_cmpw_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; word_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 515: /* gen_cmpw_dt_dd */ + case 507: /* gen_cmpw_dt_dd */ rx = (ir >> 9) & 0x0007; word_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 516: /* gen_cmpl_ds_dd */ + case 508: /* gen_cmpl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 517: /* gen_cmpl_as_dd */ + case 509: /* gen_cmpl_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 518: /* gen_cmpl_dt_dd */ + case 510: /* gen_cmpl_dt_dd */ rx = (ir >> 9) & 0x0007; long_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 519: /* gen_cmpw_ds_ad */ + case 511: /* gen_cmpw_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp((short) dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 520: /* gen_cmpw_as_ad */ + case 512: /* gen_cmpw_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6334,20 +6214,20 @@ public abstract class Core extends CoreALU { long_cmp((short) dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 521: /* gen_cmpw_dt_ad */ + case 513: /* gen_cmpw_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp((short) dt, dar[rx]); mpc = resume_prefetch; continue; - case 522: /* gen_cmpl_ds_ad */ + case 514: /* gen_cmpl_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 523: /* gen_cmpl_as_ad */ + case 515: /* gen_cmpl_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6355,146 +6235,146 @@ public abstract class Core extends CoreALU { long_cmp(dar[ry], dar[rx]); mpc = resume_prefetch; continue; - case 524: /* gen_cmpl_dt_ad */ + case 516: /* gen_cmpl_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; long_cmp(dt, dar[rx]); mpc = resume_prefetch; continue; - case 525: /* gen_cmpmb_im_ea */ + case 517: /* gen_cmpmb_im_ea */ byte_cmp(alub, dt); mpc = resume_prefetch; continue; - case 526: /* gen_cmpmw_im_ea */ + case 518: /* gen_cmpmw_im_ea */ word_cmp(alub, dt); mpc = resume_prefetch; continue; - case 527: /* gen_cmpml_im_ea */ + case 519: /* gen_cmpml_im_ea */ long_cmp(alub, dt); mpc = resume_prefetch; continue; - case 528: /* gen_eorb_dd_ds */ + case 520: /* gen_eorb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_eor(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 529: /* gen_eorb_dd_ea */ + case 521: /* gen_eorb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_eor(dar[rx], dt); mpc = ea_resume_write8; continue; - case 530: /* gen_eorw_dd_ds */ + case 522: /* gen_eorw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_eor(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 531: /* gen_eorw_dd_ea */ + case 523: /* gen_eorw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_eor(dar[rx], dt); mpc = ea_resume_write16; continue; - case 532: /* gen_eorl_dd_ds */ + case 524: /* gen_eorl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_eor(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 533: /* gen_eorl_dd_ea */ + case 525: /* gen_eorl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_eor(dar[rx], dt); mpc = ea_resume_write32; continue; - case 534: /* gen_andb_ds_dd */ + case 526: /* gen_andb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_and(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 535: /* gen_andb_dt_dd */ + case 527: /* gen_andb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_and(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 536: /* gen_andw_ds_dd */ + case 528: /* gen_andw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_and(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 537: /* gen_andw_dt_dd */ + case 529: /* gen_andw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_and(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 538: /* gen_andl_ds_dd */ + case 530: /* gen_andl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_and(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 539: /* gen_andl_dt_dd */ + case 531: /* gen_andl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_and(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 540: /* gen_andb_dd_ea */ + case 532: /* gen_andb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_and(dar[rx], dt); mpc = ea_resume_write8; continue; - case 541: /* gen_andw_dd_ea */ + case 533: /* gen_andw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_and(dar[rx], dt); mpc = ea_resume_write16; continue; - case 542: /* gen_andl_dd_ea */ + case 534: /* gen_andl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_and(dar[rx], dt); mpc = ea_resume_write32; continue; - case 543: /* gen_abcdb_ds_dd */ + case 535: /* gen_abcdb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_abcd(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 544: /* gen_abcdb_im_ea */ + case 536: /* gen_abcdb_im_ea */ dt = byte_abcd(alub, dt); mpc = ea_resume_write8; continue; - case 545: /* gen_addb_ds_dd */ + case 537: /* gen_addb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_add(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 546: /* gen_addb_dt_dd */ + case 538: /* gen_addb_dt_dd */ rx = (ir >> 9) & 0x0007; dt = byte_add(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 547: /* gen_addw_ds_dd */ + case 539: /* gen_addw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_add(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 548: /* gen_addw_as_dd */ + case 540: /* gen_addw_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6502,20 +6382,20 @@ public abstract class Core extends CoreALU { dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 549: /* gen_addw_dt_dd */ + case 541: /* gen_addw_dt_dd */ rx = (ir >> 9) & 0x0007; dt = word_add(dt, dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 550: /* gen_addl_ds_dd */ + case 542: /* gen_addl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_add(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 551: /* gen_addl_as_dd */ + case 543: /* gen_addl_as_dd */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6523,68 +6403,68 @@ public abstract class Core extends CoreALU { dar[rx] = dt; mpc = resume_prefetch; continue; - case 552: /* gen_addl_dt_dd */ + case 544: /* gen_addl_dt_dd */ rx = (ir >> 9) & 0x0007; dt = long_add(dt, dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 553: /* gen_addb_dd_ea */ + case 545: /* gen_addb_dd_ea */ rx = (ir >> 9) & 0x0007; dt = byte_add(dar[rx], dt); mpc = ea_resume_write8; continue; - case 554: /* gen_addw_dd_ea */ + case 546: /* gen_addw_dd_ea */ rx = (ir >> 9) & 0x0007; dt = word_add(dar[rx], dt); mpc = ea_resume_write16; continue; - case 555: /* gen_addl_dd_ea */ + case 547: /* gen_addl_dd_ea */ rx = (ir >> 9) & 0x0007; dt = long_add(dar[rx], dt); mpc = ea_resume_write32; continue; - case 556: /* gen_addxb_ds_dd */ + case 548: /* gen_addxb_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = byte_addx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 557: /* gen_addxb_im_ea */ + case 549: /* gen_addxb_im_ea */ dt = byte_addx(alub, dt); mpc = ea_resume_write8; continue; - case 558: /* gen_addxw_ds_dd */ + case 550: /* gen_addxw_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = word_addx(dar[ry], dar[rx]); dar[rx] = (dar[rx] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 559: /* gen_addxw_im_ea */ + case 551: /* gen_addxw_im_ea */ dt = word_addx(alub, dt); mpc = ea_resume_write16; continue; - case 560: /* gen_addxl_ds_dd */ + case 552: /* gen_addxl_ds_dd */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; dt = long_addx(dar[ry], dar[rx]); dar[rx] = dt; mpc = resume_prefetch; continue; - case 561: /* gen_addxl_im_ea */ + case 553: /* gen_addxl_im_ea */ dt = long_addx(alub, dt); mpc = ea_resume_write32; continue; - case 562: /* gen_addw_ds_ad */ + case 554: /* gen_addw_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + ((short) dar[ry]); mpc = resume_prefetch; continue; - case 563: /* gen_addw_as_ad */ + case 555: /* gen_addw_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6592,20 +6472,20 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] + ((short) dar[ry]); mpc = resume_prefetch; continue; - case 564: /* gen_addw_dt_ad */ + case 556: /* gen_addw_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + ((short) dt); mpc = resume_prefetch; continue; - case 565: /* gen_addl_ds_ad */ + case 557: /* gen_addl_ds_ad */ ry = ir & 0x0007; rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + dar[ry]; mpc = resume_prefetch; continue; - case 566: /* gen_addl_as_ad */ + case 558: /* gen_addl_as_ad */ ry = ir & 0x0007; ry = ry == 7 ? sp : ry | 8; rx = (ir >> 9) & 0x0007; @@ -6613,13 +6493,13 @@ public abstract class Core extends CoreALU { dar[rx] = dar[rx] + dar[ry]; mpc = resume_prefetch; continue; - case 567: /* gen_addl_dt_ad */ + case 559: /* gen_addl_dt_ad */ rx = (ir >> 9) & 0x0007; rx = rx == 7 ? sp : rx | 8; dar[rx] = dar[rx] + dt; mpc = resume_prefetch; continue; - case 568: /* gen_asrb_ir_ds */ + case 560: /* gen_asrb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6629,14 +6509,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 569: /* gen_asrb_dd_ds */ + case 561: /* gen_asrb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_asr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 570: /* gen_asrw_ir_ds */ + case 562: /* gen_asrw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6646,14 +6526,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 571: /* gen_asrw_dd_ds */ + case 563: /* gen_asrw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_asr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 572: /* gen_asrl_ir_ds */ + case 564: /* gen_asrl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6663,18 +6543,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 573: /* gen_asrl_dd_ds */ + case 565: /* gen_asrl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_asr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 574: /* gen_asrw_ea */ + case 566: /* gen_asrw_ea */ dt = word_asr(1, dt); mpc = ea_resume_write16; continue; - case 575: /* gen_aslb_ir_ds */ + case 567: /* gen_aslb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6684,14 +6564,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 576: /* gen_aslb_dd_ds */ + case 568: /* gen_aslb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_asl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 577: /* gen_aslw_ir_ds */ + case 569: /* gen_aslw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6701,14 +6581,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 578: /* gen_aslw_dd_ds */ + case 570: /* gen_aslw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_asl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 579: /* gen_asll_ir_ds */ + case 571: /* gen_asll_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6718,18 +6598,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 580: /* gen_asll_dd_ds */ + case 572: /* gen_asll_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_asl(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 581: /* gen_aslw_ea */ + case 573: /* gen_aslw_ea */ dt = word_asl(1, dt); mpc = ea_resume_write16; continue; - case 582: /* gen_lsrb_ir_ds */ + case 574: /* gen_lsrb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6739,14 +6619,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 583: /* gen_lsrb_dd_ds */ + case 575: /* gen_lsrb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_lsr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 584: /* gen_lsrw_ir_ds */ + case 576: /* gen_lsrw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6756,14 +6636,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 585: /* gen_lsrw_dd_ds */ + case 577: /* gen_lsrw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_lsr(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 586: /* gen_lsrl_ir_ds */ + case 578: /* gen_lsrl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6773,18 +6653,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 587: /* gen_lsrl_dd_ds */ + case 579: /* gen_lsrl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_lsr(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 588: /* gen_lsrw_ea */ + case 580: /* gen_lsrw_ea */ dt = word_lsr(1, dt); mpc = ea_resume_write16; continue; - case 589: /* gen_lslb_ir_ds */ + case 581: /* gen_lslb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6794,14 +6674,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 590: /* gen_lslb_dd_ds */ + case 582: /* gen_lslb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_lsl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 591: /* gen_lslw_ir_ds */ + case 583: /* gen_lslw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6811,14 +6691,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 592: /* gen_lslw_dd_ds */ + case 584: /* gen_lslw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_lsl(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 593: /* gen_lsll_ir_ds */ + case 585: /* gen_lsll_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6828,18 +6708,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 594: /* gen_lsll_dd_ds */ + case 586: /* gen_lsll_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_lsl(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 595: /* gen_lslw_ea */ + case 587: /* gen_lslw_ea */ dt = word_lsl(1, dt); mpc = ea_resume_write16; continue; - case 596: /* gen_rorb_ir_ds */ + case 588: /* gen_rorb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6849,14 +6729,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 597: /* gen_rorb_dd_ds */ + case 589: /* gen_rorb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_ror(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 598: /* gen_rorw_ir_ds */ + case 590: /* gen_rorw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6866,14 +6746,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 599: /* gen_rorw_dd_ds */ + case 591: /* gen_rorw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_ror(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 600: /* gen_rorl_ir_ds */ + case 592: /* gen_rorl_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6883,18 +6763,18 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 601: /* gen_rorl_dd_ds */ + case 593: /* gen_rorl_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_ror(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 602: /* gen_rorw_ea */ + case 594: /* gen_rorw_ea */ dt = word_ror(1, dt); mpc = ea_resume_write16; continue; - case 603: /* gen_rolb_ir_ds */ + case 595: /* gen_rolb_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6904,14 +6784,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 604: /* gen_rolb_dd_ds */ + case 596: /* gen_rolb_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = byte_rol(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xff) | (dt & 0xff); mpc = resume_prefetch; continue; - case 605: /* gen_rolw_ir_ds */ + case 597: /* gen_rolw_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6921,14 +6801,14 @@ public abstract class Core extends CoreALU { dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 606: /* gen_rolw_dd_ds */ + case 598: /* gen_rolw_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = word_rol(dar[rx], dar[ry]); dar[ry] = (dar[ry] & ~0xffff) | (dt & 0xffff); mpc = resume_prefetch; continue; - case 607: /* gen_roll_ir_ds */ + case 599: /* gen_roll_ir_ds */ alub = (ir >> 9) & 0x0007; if (alub == 0) { alub = 8; @@ -6938,14 +6818,14 @@ public abstract class Core extends CoreALU { dar[ry] = dt; mpc = resume_prefetch; continue; - case 608: /* gen_roll_dd_ds */ + case 600: /* gen_roll_dd_ds */ rx = (ir >> 9) & 0x0007; ry = ir & 0x0007; dt = long_rol(dar[rx], dar[ry]); dar[ry] = dt; mpc = resume_prefetch; continue; - case 609: /* gen_rolw_ea */ + case 601: /* gen_rolw_ea */ dt = word_rol(1, dt); mpc = ea_resume_write16; continue; diff --git a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java index a7da561..2930fa2 100644 --- a/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java +++ b/miggy-emu/src/main/java/miggy/cpupoet/MacroPLA.java @@ -1812,39 +1812,39 @@ public enum MacroPLA { ext_w_ds(0x4880, 0xfff8, op_extw_ds, dbrr, dbrr), - movem_w_list_ais(0x4890, 0xfff8, ea_ais16, dbrr, op_movemw_rr_ea), + movem_w_list_ais(0x4890, 0xfff8, op_imm16, ea_ais16, op_movemw_rr_ea), - movem_w_listp_pais(0x48a0, 0xfff8, ea_pais16, dbrr, op_movemw_rr_pais), + movem_w_listp_pais(0x48a0, 0xfff8, op_imm16, ea_ais16, op_movemw_rr_pais), - movem_w_list_das(0x48a8, 0xfff8, ea_das16, dbrr, op_movemw_rr_ea), + movem_w_list_das(0x48a8, 0xfff8, op_imm16, ea_das16, op_movemw_rr_ea), - movem_w_list_dais(0x48b0, 0xfff8, ea_dais16, dbrr, op_movemw_rr_ea), + movem_w_list_dais(0x48b0, 0xfff8, op_imm16, ea_dais16, op_movemw_rr_ea), - movem_w_list_adr16(0x48b8, 0xffff, ea_adr16s16, dbrr, op_movemw_rr_ea), + movem_w_list_adr16(0x48b8, 0xffff, op_imm16, ea_adr16s16, op_movemw_rr_ea), - movem_w_list_adr32(0x48b9, 0xffff, ea_adr32s16, dbrr, op_movemw_rr_ea), + movem_w_list_adr32(0x48b9, 0xffff, op_imm16, ea_adr32s16, op_movemw_rr_ea), - movem_w_list_dpc(0x48ba, 0xffff, ea_dpc16, dbrr, op_movemw_rr_ea), + movem_w_list_dpc(0x48ba, 0xffff, op_imm16, ea_dpc16, op_movemw_rr_ea), - movem_w_list_dpci(0x48bb, 0xffff, ea_dpci16, dbrr, op_movemw_rr_ea), + movem_w_list_dpci(0x48bb, 0xffff, op_imm16, ea_dpci16, op_movemw_rr_ea), ext_l_ds(0x48c0, 0xfff8, op_extl_ds, dbrr, dbrr), - movem_l_list_ais(0x48d0, 0xfff8, ea_ais32, dbrr, op_moveml_rr_ea), + movem_l_list_ais(0x48d0, 0xfff8, op_imm16, ea_ais32, op_moveml_rr_ea), - movem_l_listp_pais(0x48e0, 0xfff8, ea_pais32, dbrr, op_moveml_rr_pais), + movem_l_listp_pais(0x48e0, 0xfff8, op_imm16, ea_ais32, op_moveml_rr_pais), - movem_l_list_das(0x48e8, 0xfff8, ea_das32, dbrr, op_moveml_rr_ea), + movem_l_list_das(0x48e8, 0xfff8, op_imm16, ea_das32, op_moveml_rr_ea), - movem_l_list_dais(0x48f0, 0xfff8, ea_dais32, dbrr, op_moveml_rr_ea), + movem_l_list_dais(0x48f0, 0xfff8, op_imm16, ea_dais32, op_moveml_rr_ea), - movem_l_list_adr16(0x48f8, 0xffff, ea_adr16s32, dbrr, op_moveml_rr_ea), + movem_l_list_adr16(0x48f8, 0xffff, op_imm16, ea_adr16s32, op_moveml_rr_ea), - movem_l_list_adr32(0x48f9, 0xffff, ea_adr32s32, dbrr, op_moveml_rr_ea), + movem_l_list_adr32(0x48f9, 0xffff, op_imm16, ea_adr32s32, op_moveml_rr_ea), - movem_l_list_dpc(0x48fa, 0xffff, ea_dpc32, dbrr, op_moveml_rr_ea), + movem_l_list_dpc(0x48fa, 0xffff, op_imm16, ea_dpc32, op_moveml_rr_ea), - movem_l_list_dpci(0x48fb, 0xffff, ea_dpci32, dbrr, op_moveml_rr_ea), + movem_l_list_dpci(0x48fb, 0xffff, op_imm16, ea_dpci32, op_moveml_rr_ea), extb_l_ds(0x49c0, 0xfff8, op_extbl_ds, dbrr, dbrr), @@ -1898,37 +1898,37 @@ public enum MacroPLA { illegal(0x4afc, 0xffff, op_illegal, dbrr, dbrr), - movem_w_ais_list(0x4c90, 0xfff8, ea_ais16, dbrr, op_movemw_ea_rr), + movem_w_ais_list(0x4c90, 0xfff8, op_imm16, ea_ais16, op_movemw_ea_rr), - movem_w_aips_list(0x4c98, 0xfff8, ea_aips16, dbrr, op_movemw_aips_rr), + movem_w_aips_list(0x4c98, 0xfff8, op_imm16, ea_ais16, op_movemw_aips_rr), - movem_w_das_list(0x4ca8, 0xfff8, ea_das16, dbrr, op_movemw_ea_rr), + movem_w_das_list(0x4ca8, 0xfff8, op_imm16, ea_das16, op_movemw_ea_rr), - movem_w_dais_list(0x4cb0, 0xfff8, ea_dais16, dbrr, op_movemw_ea_rr), + movem_w_dais_list(0x4cb0, 0xfff8, op_imm16, ea_dais16, op_movemw_ea_rr), - movem_w_adr16_list(0x4cb8, 0xffff, ea_adr16s16, dbrr, op_movemw_ea_rr), + movem_w_adr16_list(0x4cb8, 0xffff, op_imm16, ea_adr16s16, op_movemw_ea_rr), - movem_w_adr32_list(0x4cb9, 0xffff, ea_adr32s16, dbrr, op_movemw_ea_rr), + movem_w_adr32_list(0x4cb9, 0xffff, op_imm16, ea_adr32s16, op_movemw_ea_rr), - movem_w_dpc_list(0x4cba, 0xffff, ea_dpc16, dbrr, op_movemw_ea_rr), + movem_w_dpc_list(0x4cba, 0xffff, op_imm16, ea_dpc16, op_movemw_ea_rr), - movem_w_dpci_list(0x4cbb, 0xffff, ea_dpci16, dbrr, op_movemw_ea_rr), + movem_w_dpci_list(0x4cbb, 0xffff, op_imm16, ea_dpci16, op_movemw_ea_rr), - movem_l_ais_list(0x4cd0, 0xfff8, ea_ais32, dbrr, op_moveml_ea_rr), + movem_l_ais_list(0x4cd0, 0xfff8, op_imm16, ea_ais32, op_moveml_ea_rr), - movem_l_aips_list(0x4cd8, 0xfff8, ea_aips32, dbrr, op_moveml_aips_rr), + movem_l_aips_list(0x4cd8, 0xfff8, op_imm16, ea_ais32, op_moveml_aips_rr), - movem_l_das_list(0x4ce8, 0xfff8, ea_das32, dbrr, op_moveml_ea_rr), + movem_l_das_list(0x4ce8, 0xfff8, op_imm16, ea_das32, op_moveml_ea_rr), - movem_l_dais_list(0x4cf0, 0xfff8, ea_dais32, dbrr, op_moveml_ea_rr), + movem_l_dais_list(0x4cf0, 0xfff8, op_imm16, ea_dais32, op_moveml_ea_rr), - movem_l_adr16_list(0x4cf8, 0xffff, ea_adr16s32, dbrr, op_moveml_ea_rr), + movem_l_adr16_list(0x4cf8, 0xffff, op_imm16, ea_adr16s32, op_moveml_ea_rr), - movem_l_adr32_list(0x4cf9, 0xffff, ea_adr32s32, dbrr, op_moveml_ea_rr), + movem_l_adr32_list(0x4cf9, 0xffff, op_imm16, ea_adr32s32, op_moveml_ea_rr), - movem_l_dpc_list(0x4cfa, 0xffff, ea_dpc32, dbrr, op_moveml_ea_rr), + movem_l_dpc_list(0x4cfa, 0xffff, op_imm16, ea_dpc32, op_moveml_ea_rr), - movem_l_dpci_list(0x4cfb, 0xffff, ea_dpci32, dbrr, op_moveml_ea_rr), + movem_l_dpci_list(0x4cfb, 0xffff, op_imm16, ea_dpci32, op_moveml_ea_rr), trap_imm4(0x4e40, 0xfff0, op_trap, dbrr, dbrr), diff --git a/miggy-emu/src/test/java/miggy/cpupoet/CoreTest.java b/miggy-emu/src/test/java/miggy/cpupoet/CoreTest.java index a3821ce..8c59db9 100644 --- a/miggy-emu/src/test/java/miggy/cpupoet/CoreTest.java +++ b/miggy-emu/src/test/java/miggy/cpupoet/CoreTest.java @@ -44,7 +44,7 @@ public class CoreTest extends Core { for (int i = 0; i < numTests; i++) { boolean skip = checkSkip(i, skips); - if ((i == 383) && "Bcc".equals(name)) { + if ((i == 40) && "MOVEM.w".equals(name)) { toString(); } executeBinTest(buffer, skip); @@ -194,7 +194,7 @@ public class CoreTest extends Core { core.write16(value.addr, value.data); } - core.mpc = 11; + core.mpc = execute_trap; core.sswi &= ~(SR_T1 | SR_T0); } diff --git a/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java b/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java index abbb71d..464e540 100644 --- a/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java +++ b/miggy-emu/src/test/java/miggy/cpupoet/InstructionTests.java @@ -179,8 +179,8 @@ public class InstructionTests extends TestCase { test.executeBinTest("MOVEA.w"); test.executeBinTest("MOVEA.l"); -// test.executeBinTest("MOVEM.w"); -// test.executeBinTest("MOVEM.l"); + test.executeBinTest("MOVEM.w"); + test.executeBinTest("MOVEM.l"); test.executeBinTest("MOVEtoCCR"); test.executeBinTest("MOVEtoUSP"); diff --git a/miggy-emu/src/test/resources/miggy/cpupoet/MOVEM.l.json.bin b/miggy-emu/src/test/resources/miggy/cpupoet/MOVEM.l.json.bin new file mode 100644 index 0000000..c14dcf1 Binary files /dev/null and b/miggy-emu/src/test/resources/miggy/cpupoet/MOVEM.l.json.bin differ diff --git a/miggy-emu/src/test/resources/miggy/cpupoet/MOVEM.w.json.bin b/miggy-emu/src/test/resources/miggy/cpupoet/MOVEM.w.json.bin new file mode 100644 index 0000000..8bb3067 Binary files /dev/null and b/miggy-emu/src/test/resources/miggy/cpupoet/MOVEM.w.json.bin differ