package miggy.cpupoet;

import junit.framework.TestCase;

public class ResetTest extends TestCase {
	public void testReset() {
		CoreTest core = new CoreTest();
		
		core.setInitialSSP(0x4000);
		core.setInitialPC(0x8000);

		core.write16(0x8000, 0x4849);
		
		core.getBErrs().add(0);
		core.getBErrs().add(4);
		core.getBErrs().add(0x8000);
		
		core.execute(50);
		
		assertTrue(core.getISP() != 0x4000); // isp did not fetch because of bus err
		assertTrue(core.getPC() != 0x8000);
		assertEquals(CoreALU.SSWI_DERR, core.getSSWI() & CoreALU.SSWI_DERR);

		core.getBErrs().remove(0);
		core.execute(50);

		assertTrue(core.getISP() != 0x4000); // still not fetched because CPU is stuck on dbrr
		assertTrue(core.getPC() != 0x8000);
		assertEquals(CoreALU.SSWI_DERR, core.getSSWI() & CoreALU.SSWI_DERR);

		core.pulse_reset(); // now pulse reset signal		
		core.execute(50);
		
		assertTrue(core.getISP() == 0x4000); // isp fetched
		assertTrue(core.getPC() != 0x8000); // but not PC
		assertEquals(CoreALU.SSWI_DERR, core.getSSWI() & CoreALU.SSWI_DERR);
		core.pulse_reset(); // pulse reset signal again
		
		core.getBErrs().remove(4); // unlock pc
		core.execute(50);

		// now both fetched, but still stuck to dbrr because prefetch of irb failed
		assertTrue(core.getISP() == 0x4000);
		assertTrue(core.getPC() == 0x8000);
		assertEquals(CoreALU.SSWI_DERR, core.getSSWI() & CoreALU.SSWI_DERR);
		
		core.getBErrs().remove(0x8000);
		core.pulse_reset();
		core.execute(50);

		// we did exit because of breackpoint
		assertTrue(core.getISP() == 0x4000);
		assertTrue(core.getCIP() == 0x8000);
		assertTrue(core.getPC() == 0x8002);
		assertEquals(0, core.getSSWI() & CoreALU.SSWI_DERR);
	}
}
