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New articles: - 01_hardware/common/memory_types.md: comprehensive Chip/Fast/Slow RAM reference with DMA accessibility matrix, per-model configurations (A500-A4000), accelerator memory expansion (classic + modern), adaptive software behavior, pitfalls with impact analysis, FPGA/emulation notes - AGENTS.md: documentation standards and methodology guidelines Blitter programming (08_graphics/blitter_programming.md): - Rewrote minterm truth table with narrative explanation and worked example - Added 7 advanced use cases with assembly/C code: shifted BOB, hardware scroll, area fill polygon, interleaved bitplane BOBs, double-buffered game loop, GUI window drag, tile map renderer - Added Good/Bad Patterns section with 5 named antipatterns - Added Practical Limitations table (10 constraints with workarounds) - Expanded Common Minterms table with Description and Real-World Use Case columns Cross-reference updates: - Root README: added memory types to coverage, quick start, section index - 01_hardware/README: updated common/ folder description - address_space.md: linked to memory_types.md and chip_ram_expansion.md - memory_management.md (exec): linked to hardware memory types reference - bitmap.md, sprites.md, animation.md, audio.md: linked to memory_types.md explaining DMA Chip RAM requirement for each subsystem - chip_ram_expansion.md: linked to comprehensive memory types article |
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|---|---|---|
| .. | ||
| chip_ram_expansion.md | ||
| chipset_ecs.md | ||
| ecs_registers_delta.md | ||
| gary_gayle.md | ||
| productivity_modes.md | ||
| README.md | ||
ECS Chipset — A600 / A3000 / A500+
Overview
The Enhanced Chip Set (ECS) is a significant revision of OCS, shipping from 1990 onward. It adds 2 MB Chip RAM addressing, programmable display timing, and extended registers while maintaining full backward compatibility with OCS software.
Chip Summary
| Chip | Part | Changes from OCS |
|---|---|---|
| Super Agnus | MOS 8372A | Addresses 2 MB Chip RAM, extended DMA window |
| ECS Denise | MOS 8373 | BPLCON3, border blank, programmable sync |
| Paula | MOS 8364 | Unchanged |
Contents
| File | Topic |
|---|---|
| chipset_ecs.md | Super Agnus and ECS Denise internals |
| ecs_registers_delta.md | New/changed registers vs OCS |
| productivity_modes.md | Multiscan/productivity display modes |
| gary_gayle.md | Gary (A3000) and Gayle (A600) chips: IDE, PCMCIA |
| chip_ram_expansion.md | 2 MB Chip RAM with Super Agnus |
ECS vs OCS — Key Differences
| Feature | OCS | ECS |
|---|---|---|
| Max Chip RAM | 1 MB (Fat Agnus) | 2 MB (Super Agnus) |
| Display sync | Fixed NTSC/PAL | BEAMCON0 — programmable |
| Bitplane scroll | 4-bit (BPLCON1) | Extended (ECS Denise) |
| Border blank | No | BPLCON3 border control |
| Hires sprites | No | ECS Denise extended sprite control |
| DMA window | Smaller | Extended: wider bitplane fetch |
Identifying ECS at Runtime
#include <exec/execbase.h>
struct ExecBase *SysBase = *((struct ExecBase **)4);
/* AttnFlags does not directly identify chipset */
/* Use graphics.library GfxBase->ChipRevBits0 */
#include <graphics/gfxbase.h>
struct GfxBase *GfxBase = (struct GfxBase *)OpenLibrary("graphics.library", 0);
if (GfxBase->ChipRevBits0 & GFXB_BIG_BLITTER) { /* ECS+ */ }
if (GfxBase->ChipRevBits0 & GFXB_HR_AGNUS) { /* Super Agnus */ }
if (GfxBase->ChipRevBits0 & GFXB_HR_DENISE) { /* ECS Denise */ }
Machines Using ECS
| Model | Notes |
|---|---|
| A3000 | Super Agnus + ECS Denise; 68030; SCSI; Zorro III |
| A500+ | Super Agnus (1 MB variant); ECS Denise; no IDE |
| A600 | Super Agnus (1 MB variant); ECS Denise; Gayle; IDE; PCMCIA |
| A2000 (late) | Some late rev boards shipped with ECS chips |
References
- ADCD 2.1 Hardware Manual — ECS extension chapters
- NDK39:
graphics/gfxbase.h— ChipRevBits0 flags - Amiga Hardware Reference Manual 3rd ed. — ECS appendix