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Bus and memory updates

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Ilia Sharin 2026-04-30 11:15:34 -04:00
parent f11d9a2882
commit cdc18c4ae3
10 changed files with 894 additions and 3 deletions
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@ -117,6 +117,7 @@ Articles were scored against [AGENTS.md](../amiga/AGENTS.md) "Deep" criteria:
| `autoconfig.md` | common | 662 | ✅ Deep | AutoConfig protocol: CFGIN/CFGOUT chain, ExpansionRom encoding, nibble-pair map, size codes, shut-up mechanism, Z2/Z3 differences, antipatterns, FPGA notes, boot sequence positioning |
| `dma_architecture.md` | common | 581 | ✅ Deep | Scanline slot allocation, even/odd interleaving, DMA channel priority, bitplane DMA budget (DDFSTRT/DDFSTOP/BPLxMOD), bus arbitration (Agnus as bus master, DTACK, wait states), Blitter-Nasty/BLTPRI, per-model bus table (A1000→CD32), Buster/Ramsey/SDMAC/Gayle glue chips, AGA FMODE bandwidth equation, alignment requirements, FPGA implementation notes (Minimig state machine, SDRAM timing, common bugs), bandwidth calculation cookbook with 4 worked examples, best practices, FAQ |
| `video_timing.md` | common | 736 | ✅ Deep | Crystal-to-CPU clock tree (PAL/NTSC), scanline anatomy, frame structure, interlace LOF/SHF, beam counters (VPOSR/VHPOSR), BEAMCON0 programmable sync, 23-pin video connector pinout, analog/digital RGB output, video slot (A2000/A3000/A4000), genlock/XCLK/PIXELSW overlay, Video Toaster, scandoublers/flicker fixers (historical + modern Indivision/RGB2HDMI/OSSC), sync→async CPU evolution, per-frame time budgets, best practices, FAQ |
| `bus_architecture.md` | common | 872 | ✅ Deep | Bus hierarchy (dual-domain), 68000 bus cycle anatomy (S-states, DTACK, wait states), Gary/Fat Gary/Gayle/Buster/Ramsey bus glue, bus arbitration algorithms (3-layer: Agnus priority, 68000 handshake, Buster round-robin), custom register access ($DFF000 word-only, CLR.W hazard, volatile, timing), CIA register access (byte-lane, E-clock sync, ICR read-clear), accelerator bus bridge (arbitration, clock domain crossing, penalty ratios), cache coherency with DMA (CachePreDMA/CachePostDMA, 68030/040/060), cross-domain transfer techniques (MOVEM/MOVE16/Blitter relative benchmarks, C2P pipeline, ping-pong audio), per-model address maps (A500/A2000/A3000/A4000/A600/A1200/CD32 with expansion windows), PCI bridge windowing (Mediator/G-REX/Prometheus), best practices & antipatterns |
| `cdtv_hardware.md` | ocs | 283 | ✅ Adequate | CDTV-specific: CD-ROM controller, front panel, boot ROM |
| `custom_registers.md` | ocs | 183 | ✅ Adequate | OCS custom chip register map |
| `blitter.md` | ocs | 154 | ✅ Adequate | Blitter engine basics: channels, minterms, line draw |