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Bus and memory updates

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Ilia Sharin 2026-04-30 11:15:34 -04:00
parent f11d9a2882
commit cdc18c4ae3
10 changed files with 894 additions and 3 deletions
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01_hardware/ocs_a500/gary_system_controller.md
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@ -556,3 +556,4 @@ No. Gary generates every chip-select signal on the board. Without Gary, the 6800
- [Zorro Bus](../common/zorro_bus.md) — Zorro II expansion protocol, AutoConfig, Buster 5721 arbitration
- [CIA Chips](../common/cia_chips.md) — CIA-A Port A OVL bit, interrupt lines, and timer outputs that Gary routes to the 68000
- [Address Space](../common/address_space.md) — Complete A500/A2000 memory map with all Gary-decoded regions annotated
- [Bus Architecture](../common/bus_architecture.md) — Bus hierarchy, register access patterns, accelerator bridge, cache coherency