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Bus and memory updates

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This commit is contained in:
Ilia Sharin 2026-04-30 11:15:34 -04:00
parent f11d9a2882
commit cdc18c4ae3
10 changed files with 894 additions and 3 deletions
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01_hardware/ecs_a600_a3000/gary_system_controller.md
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@ -574,3 +574,4 @@ No. The FPU chip select is hard-wired to decode $E80000–$EFFFFF. There is no G
- [ECS Chipset](chipset_ecs.md) — Super Agnus + ECS Denise (A3000)
- [CPU 030/040](../aga_a1200_a4000/cpu_030_040.md) — Accelerators that must interoperate with Gary's bus arbitration
- [SCSI Device](../../10_devices/scsi.md) — Software interface to the SCSI hardware Gary enables
- [Bus Architecture](../common/bus_architecture.md) — Bus hierarchy, register access patterns, accelerator bridge, cache coherency