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Bus and memory updates

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This commit is contained in:
Ilia Sharin 2026-04-30 11:15:34 -04:00
parent f11d9a2882
commit cdc18c4ae3
10 changed files with 894 additions and 3 deletions
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5
01_hardware/common/video_timing.md
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@ -96,8 +96,8 @@ Each scanline consists of **227.5 color clocks** (alternating 227 and 228 per li
←────────────────── 227.5 color clocks ──────────────────→
┌──────┬──────┬─────────┬──────────────────────┬──────────┐
│ SYNC │BLANK │ Back │ Active Display │ Front │
│ │ │ Porch │ (visible pixels) │ Porch │
│ SYNC │BLANK │ Back │ Active Display │ Front │
│ │ │ Porch │ (visible pixels) │ Porch │
└──────┴──────┴─────────┴──────────────────────┴──────────┘
H=0 H=$81 H=$E3
← HBLANK → ← DDFSTRT...DDFSTOP →
@ -740,3 +740,4 @@ A: For basic display, ±10 ns per clock edge is sufficient. For genlock compatib
- [OCS Chipset](../ocs_a500/chipset_ocs.md) — Agnus/Denise architecture
- [ECS Chipset](../ecs_a600_a3000/chipset_ecs.md) — Super Agnus/Super Denise enhancements
- [AGA Chipset](../aga_a1200_a4000/chipset_aga.md) — Alice/Lisa architecture
- [Bus Architecture & Register Access](bus_architecture.md) — Bus hierarchy, accelerator bridge mechanics, register access rules