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Bus and memory updates

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Ilia Sharin 2026-04-30 11:15:34 -04:00
parent f11d9a2882
commit cdc18c4ae3
10 changed files with 894 additions and 3 deletions
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01_hardware/common/dma_architecture.md
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@ -580,3 +580,4 @@ Still feasible — but add Copper + Blitter and the CPU drops to single digits.
- [Gary System Controller](../ocs_a500/gary_system_controller.md) — Bus timeout, address decode
- [Zorro Bus](zorro_bus.md) — Expansion bus DMA, Buster/Super Buster
- [Video Signal & Timing](video_timing.md) — clock derivation, beam counters, genlock, video output
- [Bus Architecture & Register Access](bus_architecture.md) — CPU bus cycles, register access hazards, accelerator bridge, cache coherency