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Bus and memory updates

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Ilia Sharin 2026-04-30 11:15:34 -04:00
parent f11d9a2882
commit cdc18c4ae3
10 changed files with 894 additions and 3 deletions
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01_hardware/common/README.md
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@ -14,3 +14,4 @@
- [floppy_hardware.md](floppy_hardware.md) — MFM encoding, disk controller, and drive mechanics
- [dma_architecture.md](dma_architecture.md) — DMA architecture: scanline slot allocation, bus arbitration, even/odd interleaving, per-model bus widths, Buster/Ramsey/SDMAC, FMODE bandwidth, FPGA timing
- [video_timing.md](video_timing.md) — Video signal & system timing: crystal-to-CPU clock tree, beam counters, BEAMCON0, genlock overlay, video output signals, scandoublers
- [bus_architecture.md](bus_architecture.md) — Bus hierarchy, CPU bus cycles, register access patterns, accelerator bridges, cache coherency, cross-domain transfers, per-model address maps