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Added ATA/ATAPI article - dramatic story as always

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Ilia Sharin 2026-06-02 23:48:29 -04:00
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01_hardware/ecs_a600_a3000/gary_system_controller.md
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@ -575,3 +575,4 @@ No. The FPU chip select is hard-wired to decode $E80000–$EFFFFF. There is no G
- [CPU 030/040](../aga_a1200_a4000/cpu_030_040.md) — Accelerators that must interoperate with Gary's bus arbitration
- [SCSI Device](../../10_devices/scsi.md) — Software interface to the SCSI hardware Gary enables
- [Bus Architecture](../common/bus_architecture.md) — Bus hierarchy, register access patterns, accelerator bridge, cache coherency
- [ATA/ATAPI Protocol](../../10_devices/atapi.md) — ATA wire protocol for IDE drives; Gayle's successor role to Gary's SCSI integration