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docs(amiga): Mermaid syntax fixes, 68040 FPU elaboration, Gayle trapezoid→quoted, gcc toolchain integration
This commit is contained in:
Ilia Sharin
parent
a59d8350b3
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a383d4c065
11 changed files with 2738 additions and 277 deletions
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@ -21,7 +21,7 @@ The **Enhanced Chip Set** (ECS) is a significant revision of OCS, shipping from
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| [chipset_ecs.md](chipset_ecs.md) | Super Agnus and ECS Denise internals |
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| [ecs_registers_delta.md](ecs_registers_delta.md) | New/changed registers vs OCS |
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| [productivity_modes.md](productivity_modes.md) | Multiscan/productivity display modes |
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| [gary_system_controller.md](gary_system_controller.md) | Gary — A3000 bus controller, DMA arbitration, SCSI glue |
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| [gary_system_controller.md](gary_system_controller.md) | Gary & Fat Gary — system controller gate array: address decode, bus arbitration, AutoConfig, SCSI/FPU glue, chip variants, runtime detection, antipatterns, FPGA timing |
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| [Gayle IDE & PCMCIA](../common/gayle_ide_pcmcia.md) | A600 Gayle: IDE and PCMCIA (shared with A1200) |
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| [chip_ram_expansion.md](chip_ram_expansion.md) | 2 MB Chip RAM with Super Agnus |
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@ -6,7 +6,7 @@
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### Chip RAM Addressing
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OCS Agnus could only generate 19-bit DMA addresses (512 KB) or 20-bit (1 MB with Fat Agnus). Super Agnus extends this to **21 bits**, addressing 2 MB of Chip RAM.
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OCS Agnus could only generate 19-bit DMA addresses (512 KB) or 20-bit (1 MB with Fat Agnus). Super Agnus extends this to **21 bits**, addressing 2 MB of Chip RAM. See [OCS Chipset Internals](../ocs_a500/chipset_ocs.md) for the original Agnus DMA architecture.
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The revision of Super Agnus present determines the Chip RAM limit:
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@ -1,62 +1,576 @@
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[← Home](../../README.md) · [Hardware](../README.md) · [ECS](README.md)
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# Gary — A3000 System Controller
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# Gary & Fat Gary — Amiga System Controller Gate Array
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## Overview
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**Gary** is the custom system controller chip in the Amiga 3000. It consolidates functions that are discrete ICs on the A2000 into a single gate array:
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The **Gary** chip (CSG 5719, "Gate Array") is a custom ASIC that consolidates the system glue logic which, in the original Amiga 1000, required dozens of discrete 74-series TTL ICs and PAL devices. It was first deployed in the Amiga 500 and Amiga 2000 (revision 4.x+) in 1987. Its 32-bit successor, **Fat Gary** (CSG 5391/5393, Commodore P/N 390540-02), debuted in the Amiga 3000 (1990) to support the 68030's full 32-bit address and data busses alongside Zorro III expansion. Together, these two chips span the entire Amiga lineup from the A500 through the A4000T.
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- **Bus controller**: Manages interaction between 68030/68882, chip bus, and Zorro III
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- **Auto-config controller**: Runs Zorro expansion enumeration at boot
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- **DMA arbitration**: Between 68030, custom chips, and Zorro III DMA masters
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- **SCSI interface glue**: Works with the A3000's built-in WD33C93 SCSI controller
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- **ROM decode**: Maps Kickstart ROM into the address space
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Gary is **not directly programmable by user software** — it has no memory-mapped registers that applications can read or write. Its behavior is determined by hardware strapping resistors (pull-ups/pull-downs on specific pins at power-on) and the Kickstart ROM initialization sequence. This makes it fundamentally different from Agnus or Paula, which have rich register files at $DFFxxx.
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Gary is not directly programmable by user software; its configuration is set by hardware strapping and the ROM initialization sequence.
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> [!NOTE]
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> The A4000 desktop model does **not** use Gary. It uses **Ramsey** (DRAM controller), **Budgie** (bus bridge), and **Super Buster** (Zorro III arbitration). The A4000T uses Fat Gary. The A600/A1200 use **Gayle** (which integrates IDE and PCMCIA control on top of Gary-like logic).
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---
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## Architecture — Where Gary Sits
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Gary is the central "traffic cop" between the CPU, custom chips, expansion bus, and peripherals. It decodes the upper address lines (A17–A23 on original Gary, A24–A31 on Fat Gary) to generate chip-select signals for every device on the motherboard:
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```mermaid
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graph LR
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CPU[68030 CPU<br/>+ 68882 FPU] -->|Address Bus A17-A31| Gary[Fat Gary<br/>CSG 5391/5393]
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Gary -->|Chip RAM Select| Agnus[Super Agnus<br/>8372A]
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Gary -->|Register Select| Denise[ECS Denise<br/>8373]
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Gary -->|Register Select| Paula[Paula<br/>8364]
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Gary -->|ROM Select| ROM[Kickstart ROM<br/>512 KB]
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Gary -->|SCSI Select| SCSI[WD33C93A<br/>+ SDMAC]
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Gary -->|Bus Arbitration| Buster[Super Buster<br/>Zorro III]
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Gary -->|Fast RAM| RAMSLOT["/RAMSLOT to Fast RAM<br/>$08000000-$0FFFFFFF"]
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Gary -->|Interrupts| CIA[CIA-A / CIA-B<br/>8520]
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CPU -->|Data Bus D0-D31| RAMSLOT
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CPU -->|Data Bus D0-D31| Agnus
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```
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**Key principle**: Gary does NOT sit on the data bus — it only watches address lines and generates control strobes. Data flows directly between the CPU and the selected device. This is the classic "address decoder + chip select" pattern used in all Northbridge chips.
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---
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## Gary vs Fat Gary — Evolution
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| Feature | Original Gary (CSG 5719) | Fat Gary (CSG 5391/5393) |
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|---|---|---|
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| **Package** | 48-pin DIP | 84-pin PLCC (or PGA) |
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| **Address bus** | 24-bit (A1–A23) | 32-bit (A0–A31) |
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| **Data bus support** | 16-bit (68000 bus) | 32-bit (68030/68040 bus) |
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| **Machines** | A500, A2000 (rev 4.x+), CDTV | A3000, A3000T, A4000T |
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| **Zorro support** | Zorro II (via Buster 5721) | Zorro III (via Super Buster) |
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| **SCSI glue** | None (external controller needed) | WD33C93A + SDMAC chip selects |
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| **FPU decode** | Not supported | Dedicated FPU chip select |
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| **Cache control** | None | /CIIN line for cache-inhibit |
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| **Fast RAM decode** | Via Zorro II only | /RAMSLOT at $08000000–$0FFFFFFF |
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| **Clock input** | 3.58 MHz (C1), 7.16 MHz (NCDAC) | 25–50 MHz (68030 bus clock) |
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| **Interrupt lines** | IPL0–IPL2 (standard 68K) | /INT2, /INT6 + encoded /IPL0–/IPL2 |
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| **Power** | 500 mW at 5 V | ~2 A at 5 V (bus driving) |
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### Why "Fat" Gary?
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Commodore's naming convention was characteristically informal. The original Gary (CSG 5719) handled the 68000's 24-bit address space. When the A3000 needed a 32-bit version, the engineers called it "Fat Gary" — it was the same gate array concept but with a wider bus interface, more pins, and additional decode logic for the 68030-specific features (FPU chip select, cache-inhibit, burst-mode awareness). The name stuck internally and entered community usage through Dave Haynie's developer notes.
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---
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## What Gary Decodes — Address Map
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The following table shows the address ranges decoded by Fat Gary in the A3000. Original Gary uses a subset (no $08000000 range, no SCSI, no FPU).
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| Address Range | Size | Selected Device | /CS Signal | Notes |
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|---|---|---|---|---|
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| `$000000–$1FFFFF` | 2 MB | Chip RAM | Via Agnus | Controlled by Agnus, not Gary directly |
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| `$002000–$07FFFF` | ~0.5 MB | Custom Chip Registers | /CxREG | $DFF000–$DFF1FE (ECS), $DFF000–$DFFxxx (AGA) |
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| `$080000–$0FFFFF` | 8 MB | Motherboard Fast RAM | /RAMSLOT | Fat Gary only; up to 8 MB on A3000 motherboard |
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| `$100000–$7FFFFF` | 7 MB | Zorro III Expansion Space | Via Buster | Configuration + I/O + memory space |
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| `$800000–$BFFFFF` | 4 MB | Zorro II I/O Space | Via Buster | Legacy Zorro II compatibility |
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| `$C00000–$DFFFFF` | 2 MB | Internal I/O | Various | CIA, RTC, SCSI, UART (A3000) |
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| `$E00000–$E7FFFF` | 512 KB | Reserved / Coprocessor | — | Often unused on A3000 |
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| `$E80000–$EFFFFF` | 512 KB | FPU (68881/68882) | /FPUCS | Fat Gary only; decoded from A19–A23 |
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| `$F00000–$F7FFFF` | 512 KB | Kickstart ROM (first half) | /ROMCS0 | ROM overlay at boot |
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| `$F80000–$FFFFFF` | 512 KB | Kickstart ROM (second half) | /ROMCS1 | Extended ROM or second 256 KB |
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> [!NOTE]
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> The FPU at `$E80000` is decoded by Fat Gary, not by the 68030 itself. The 68030 does not have a dedicated coprocessor chip select — it treats the 68881/68882 as a memory-mapped peripheral. Gary generates /FPUCS when it sees an address in `$E80000–$EFFFFF` during a CPU bus cycle. This is why the FPU appears at this address on the A3000 rather than at the coprocessor ID space that the 68030 natively supports.
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---
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## Bus Arbitration
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Gary manages three bus masters:
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Gary manages the fundamental challenge of the Amiga architecture: multiple bus masters contending for a single shared bus.
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| Master | Priority | Description |
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|---|---|---|
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| Custom chips (DMA) | Highest | Agnus DMA for display, audio, disk — must never stall |
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| 68030 CPU | Normal | Program execution |
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| Zorro III cards | Lowest | Expansion bus-mastering DMA |
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### Arbitration Hierarchy
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When a custom chip DMA cycle occurs, Gary holds the 68030 off the bus until the cycle completes. This is the fundamental source of "DMA contention" slowdown on all Amiga models.
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| Priority | Master | Bus Grant Signal | Can Be Stalled? |
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|---|---|---|---|
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| 1 (Highest) | Custom Chip DMA (Agnus) | /CDMAC → /BGACK | Never — display/audio/disk must run in real time |
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| 2 | 68030 CPU | /BR → /BG from Gary | Yes — held off during DMA cycles |
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| 3 | Zorro III Bus Masters | Via Super Buster → Gary | Yes — lowest priority |
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| 4 | 68882 FPU | Shares CPU /BR signal | Yes — FPU is coprocessor to CPU |
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### DMA Contention Mechanics
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When Agnus needs a bus cycle (e.g., to fetch bitplane data for the next scanline pixel), the following sequence occurs:
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1. **Agnus asserts /CDMAC** — a dedicated DMA request line to Gary
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2. **Gary asserts /BR** (Bus Request) to the 68030
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3. **68030 finishes current bus cycle**, asserts /BG (Bus Grant), floats address/data busses
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4. **Gary asserts /BGACK** to hold the 68030 off, then grants Agnus its cycle
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5. **Agnus performs one DMA word transfer** — takes ~280 ns (2 CPU cycles at 7.14 MHz)
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6. **Agnus releases /CDMAC** — Gary de-asserts /BGACK, 68030 resumes
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This cycle repeats for every bitplane fetch, sprite fetch, audio sample, and disk byte. At high resolutions (640×256×4 bitplanes ≈ 128 DMA slots per scanline), the 68030 can lose 30–40% of its bus bandwidth to DMA contention. This is why A3000 accelerators that move execution to a local Fast RAM card (off the shared bus) see dramatic performance gains — the CPU runs unimpeded while DMA cycles occur on the motherboard bus.
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> [!WARNING]
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> Accelerator cards on the A3000 CPU slot **must** correctly implement the /BR, /BG, and /BGACK protocol with Gary. Cards that ignore /BGACK and continue driving the bus during DMA cycles cause screen corruption (garbage pixels from double-driven data lines) and can physically damage bus transceivers. This is a known failure mode with some early third-party accelerators.
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### Fat Gary's Arbitration Precision
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The Fat Gary specification (390540-02) specifies **20 ns resolution** for arbitration timing. This means Gary can switch bus mastership in a single 50 MHz clock cycle. Compared to original Gary's discrete-TTL-era timing (which was measured in hundreds of nanoseconds), this is essential for the A3000's 25 MHz 68030 — the bus can be handed back and forth quickly enough that neither CPU nor DMA starves.
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---
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## Interrupt Controller
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Gary encodes interrupt signals from multiple sources into the 68030's three encoded interrupt level lines (/IPL0, /IPL1, /IPL2).
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| Interrupt Source | Gary Input | Encoded Level | Priority |
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|---|---|---|---|
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| Vertical Blank | /INT2 (from Agnus) | Level 2 | Low (68K vector $68) |
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| CIA-A / CIA-B | /INT6 (from CIAs) | Level 6 | High (68K vector $78, shared) |
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| SCSI Controller | /INT2 via SDMAC | Level 2 | Shared with VBlank |
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| Zorro III Cards | /INT2 or /INT6 (via Buster) | Level 2 or 6 | Per-card configuration |
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| External Interrupt | /EINT (from CPU slot) | Level 2 or 6 | Accelerator use |
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**Key detail**: On the original Gary (A500/A2000), Paula handles some interrupt encoding. On Fat Gary (A3000), the interrupt routing is more centralized through Gary, with Paula's IRQ output feeding into Gary's interrupt encoder. This is why the A3000 interrupt latency can be slightly different from the A500 — the additional gate delay through Gary adds ~5–10 ns of propagation time.
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### Interrupt Acknowledge Cycle
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When the 68030 receives an interrupt, it performs an **IACK cycle** (Interrupt Acknowledge) — a special bus cycle where the CPU reads the vector number from the interrupting device. Gary participates in this cycle by:
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1. Detecting the IACK cycle (FC2–FC0 = 111 on the 68030 function code lines)
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2. Routing the IACK to the highest-priority pending interrupt source
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3. Ensuring the vector number ($64–$78) appears on D0–D7 during the acknowledge
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This is handled transparently — Amiga software never interacts with Gary's interrupt logic directly.
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---
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## A3000 SCSI Integration
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The A3000 includes a built-in **WD33C93A** SCSI controller. Gary provides the glue logic between the SCSI chip and the system bus:
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### The Two-Chip SCSI Subsystem
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| Feature | Details |
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|---|---|
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| SCSI chip | WD33C93A (SBIC) |
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| DMA | SDMAC — dedicated SCSI DMA controller (separate from the CDTV-style DMAC) |
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| Interface | A3000 uses a dedicated SDMAC chip, not the A2091-style DMAC |
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| AmigaOS driver | `scsi.device` in Kickstart ROM |
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The A3000's built-in SCSI uses two chips that Gary glues together:
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| Chip | Part | Function | Gary Role |
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|---|---|---|---|
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| **SBIC** | WD33C93A | SCSI Bus Interface Controller — handles SCSI protocol (arbitration, selection, command/status/data phases) | Decodes /SBIC chip select at $DD0040 |
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| **SDMAC** | Commodore custom | SCSI DMA Controller — transfers data directly between SCSI chip and Chip RAM without CPU involvement | Decodes /SDMACCS, routes DMA cycles through bus arbitration |
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> [!NOTE]
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> The A3000's SDMAC is a different chip from the A2091/CDTV DMAC, despite both interfacing with WD33C93 SCSI controllers. The register layouts are incompatible.
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> The A3000's SDMAC is a **different chip** from the A2091/CDTV DMAC, despite both interfacing with WD33C93 SCSI controllers. The register layouts are incompatible. The SDMAC supports 32-bit addressing and can DMA to any address in the A3000's 2 MB Chip RAM window; the A2091 DMAC is limited to 24-bit addressing.
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## Machines Using Gary
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### SCSI Boot Integration
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| Model | Gary variant | Notes |
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Gary's role at boot is critical for SCSI:
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1. At power-on, Gary asserts /ROMCS0 to map Kickstart ROM at $F00000
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2. Kickstart initializes exec.library, then scans for resident modules
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3. `scsi.device` (in ROM) probes the WD33C93A via Gary's /SBIC chip select
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4. Gary decodes the probe address and routes it to the SCSI chip
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5. If a SCSI disk is found, Kickstart reads the RDB from block 0
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6. Gary's bus arbitration handles the DMA transfer from SDMAC transparently
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The entire boot sequence works because Gary decodes the SCSI addresses without any software initialization — it's "on" from the moment power stabilizes.
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---
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## AutoConfig Controller
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Gary orchestrates the Zorro expansion bus AutoConfig sequence at boot. The process:
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1. **Kickstart probes Zorro space** starting at $E80000 (Zorro II) or $100000–$7FFFFF (Zorro III)
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2. **Gary decodes the probe address** and routes it to Super Buster via the bus grant lines
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3. **Super Buster asserts /CFGIN** to the first card in the daisy chain
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4. **Each card responds** with its AutoConfig ROM (product ID, manufacturer, memory requirements, driver code)
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5. **Kickstart assigns address space** and writes the base address back to the card's configuration register
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6. **Gary generates /CFGOUT** to pass configuration to the next card in the chain
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7. Repeat until no card responds to /CFGIN
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Gary does NOT read the AutoConfig data — it only generates the chip select and configuration strobes. The actual AutoConfig protocol is implemented by Kickstart software and Super Buster hardware. Gary is the address decoder and bus-cycle router.
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---
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## Chip Variants and Machine Assignment
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| CSG Part # | Commodore P/N | Name | Package | Machines | Notes |
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|---|---|---|---|---|---|
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| 5718 | — | Gary | 48-pin DIP | A2000 (early rev 4.x) | Original version; some early boards |
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| 5719 | 318070-01 | Gary | 48-pin DIP | A500, A2000 (rev 6+), CDTV | Standard version; most common |
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| 5391 | 390540-01 | Fat Gary (Level 1) | 84-pin PLCC | A3000 (early rev) | Pre-production; rare |
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| 5393 | 390540-02 | Fat Gary (Level 2) | 84-pin PLCC | A3000 (rev 6+), A3000T, A4000T | Production version; full Zorro III |
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**Revision identifiers**: The Level 2 Fat Gary (5393) is marked with die revision "13H" or later. Early Level 1 chips (5391) lack full Zorro III asynchronous cycle support and may have issues with certain Zorro III DMA cards.
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---
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## Detecting Gary at Runtime
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Since Gary has no readable registers, software must identify it **indirectly**:
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### Method 1: ExecBase AttnFlags (Coarse Detection)
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```c
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/* From exec/execbase.h */
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struct ExecBase *SysBase = *((struct ExecBase **)4);
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if (SysBase->AttnFlags & AFF_68030) {
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/* 68030 present → likely A3000 → Fat Gary */
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/* But could also be an A2000 with 68030 accelerator — not conclusive */
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}
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```
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### Method 2: Graphics ChipRevBits0 (ECS Detection)
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```c
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/* From graphics/gfxbase.h */
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struct GfxBase *GfxBase = (struct GfxBase *)OpenLibrary("graphics.library", 37);
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|
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if (GfxBase->ChipRevBits0 & GFXB_HR_AGNUS) {
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/* Super Agnus present → ECS → could be A3000 or A600 */
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/* Still not conclusive for Gary-specific detection */
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}
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```
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### Method 3: AutoConfig Product ID (Conclusive)
|
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```c
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/* Scan Zorro expansion for known A3000-specific resources.
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* The A3000's motherboard resources (SCSI, RAM, etc.) appear
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* as AutoConfig entries with manufacturer ID 0x0202 (Commodore). */
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|
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struct ExpansionBase *ExpansionBase;
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struct ConfigDev *cd = NULL;
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|
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ExpansionBase = (struct ExpansionBase *)OpenLibrary("expansion.library", 37);
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if (ExpansionBase) {
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while ((cd = FindConfigDev(cd, 0x0202 /* CBM */, -1 /* any product */))) {
|
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/* A3000 motherboard SCSI: product 0x03 */
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/* A3000 motherboard RAM: product 0x02 */
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if (cd->cd_Rom.er_Manufacturer == 0x0202 &&
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cd->cd_Rom.er_Product == 0x03) {
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/* SCSI controller found → Gary or Fat Gary is present */
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}
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}
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CloseLibrary((struct Library *)ExpansionBase);
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}
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```
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### Method 4: Probe Known Addresses (Hack — Use Sparingly)
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|
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Gary controls the FPU chip select at $E80000. You can test whether an FPU is present at this address:
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|
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```asm
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; 68k: probe for FPU via Gary's $E80000 decode
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; This ONLY works on A3000/A4000T with Fat Gary + 68881/68882
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; Returns: D0 = 0 (no FPU), nonzero (FPU present)
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|
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moveq #0,d0 ; assume no FPU
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lea $E80000,a0 ; Fat Gary FPU decode address
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moveq #0,d1
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pmove d1,fpcr ; attempt FPU instruction
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tst.b (a0) ; probe — if FPU absent, bus error
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moveq #1,d0 ; reached → FPU present
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rts
|
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; WARNING: bus error if no FPU — requires trap handler
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```
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|
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> [!NOTE]
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> There is no universally reliable way for software to detect "Gary is present" vs "Gayle is present" vs "Ramsey+Budgie is present." The AmigaOS device driver model was designed so that software never needs to know which system controller chip is in use — it talks to `scsi.device`, `expansion.library`, and `timer.device`, not to Gary directly.
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---
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||||
|
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## Gary vs Gayle vs Ramsey/Budgie/Buster — Decision Guide
|
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|
||||
| Criterion | Gary (A500/A2000/CDTV) | Fat Gary (A3000) | Gayle (A600/A1200) | Ramsey+Budgie (A4000) |
|
||||
|---|---|---|---|---|
|
||||
| **When to target** | Writing for OCS machines, floppy-only code | Writing A3000-specific SCSI or FPU code | IDE hard disk access on wedge models | A4000 motherboard Fast RAM or Zorro III DMA |
|
||||
| **Address bus width** | 24-bit | 32-bit | 24-bit (but with 32-bit CPU) | 32-bit |
|
||||
| **Direct register access** | None — opaque | None — opaque | /GAYLE_ID at $DE0000 (read-only ID byte) | Ramsey DRAM config registers at $C00000 |
|
||||
| **SCSI support** | None | WD33C93A + SDMAC | None (IDE instead) | NCR 53C710 + A4091 (A4000T) |
|
||||
| **OS version required** | Any (1.2+) | 1.4+ (A3000 shipped 1.4/2.0) | 2.05+ (A600), 3.0+ (A1200) | 3.0+ |
|
||||
| **FPGA implementation difficulty** | Low (simple address decoder) | Medium (arbitration timing, 20 ns precision) | Medium (IDE timing emulation) | High (DRAM controller, refresh cycles) |
|
||||
|
||||
---
|
||||
|
||||
## When to Care About Gary / When NOT to
|
||||
|
||||
### When to Care
|
||||
|
||||
- **Writing an accelerator card**: Must correctly implement /BR, /BG, /BGACK handshake with Gary
|
||||
- **Porting Kickstart to new hardware**: Must configure Gary's board-strap options (ROM overlay, FPU presence, RAM size)
|
||||
- **Building an FPGA Amiga core (MiSTer/Minimig)**: Gary's arbitration timing is precision-critical — 20 ns resolution
|
||||
- **Debugging A3000 SCSI issues**: The WD33C93A ↔ SDMAC ↔ Gary interaction is a known source of DMA problems
|
||||
- **Writing system-level diagnostics**: Knowing which chip decodes what address helps narrow hardware failures
|
||||
- **Understanding A3000 vs A4000 differences**: Gary vs Ramsey/Budgie explains why some accelerators work on one but not the other
|
||||
|
||||
### When NOT to Care
|
||||
|
||||
- **Writing application software**: Use `scsi.device`, `graphics.library`, `expansion.library` — never touch Gary directly
|
||||
- **Writing a filesystem**: Use `dos.library` / `exec.library` I/O — the filesystem handler has no visibility into Gary
|
||||
- **Porting between Amiga models**: The OS abstractions insulate you from Gary vs Gayle vs Ramsey — this is by design
|
||||
- **Writing a game that only uses Chip RAM**: Agnus handles all DMA; Gary is invisible to game code
|
||||
- **Writing a CLI tool**: Nothing at the shell level depends on the system controller chip
|
||||
|
||||
---
|
||||
|
||||
## Best Practices
|
||||
|
||||
1. **Never depend on Gary-specific behavior** — use OS abstractions (devices, libraries) that work across all Amiga models
|
||||
2. **Probe SCSI via `expansion.library`**, not by hard-coding addresses — the AutoConfig database tells you what's present
|
||||
3. **On A3000 accelerators, implement the full /BR→/BG→/BGACK handshake** — do NOT hold /BGACK indefinitely or you'll starve DMA
|
||||
4. **Check `SysBase->AttnFlags` for CPU type**, but don't equate "68030" with "Fat Gary" — an A2000 with a 68030 accelerator has a 68030 but NOT Fat Gary
|
||||
5. **Respect the FPU address at $E80000** — this is a Fat Gary convention; on A4000 the FPU lives at a different address decoded by Ramsey
|
||||
6. **When emulating Gary in FPGA, simulate the 20 ns arbitration resolution** — coarser timing breaks SCSI DMA and Zorro III card initialization
|
||||
7. **Test with both Level 1 (5391) and Level 2 (5393) behavior** if you're building FPGA logic — early A3000s with Level 1 have known quirks
|
||||
8. **If writing a boot ROM, do not assume Gary is present** — A4000 uses Ramsey; A1200 uses Gayle; design for the AutoConfig protocol, not the chip
|
||||
|
||||
## Antipatterns
|
||||
|
||||
### 1. The Hard-Coded FPU Address
|
||||
|
||||
**Bad**:
|
||||
```c
|
||||
/* Assumes FPU is at $E80000 (Fat Gary only!) */
|
||||
volatile unsigned long *fpu_base = (unsigned long *)0x00E80000;
|
||||
```
|
||||
|
||||
**Good**:
|
||||
```c
|
||||
/* Use mathieeesingbas.library — it knows where the FPU lives */
|
||||
struct MathIeeeSingBasBase *MathIeeeSingBasBase;
|
||||
MathIeeeSingBasBase = (void *)OpenLibrary("mathieeesingbas.library", 37);
|
||||
if (MathIeeeSingBasBase) {
|
||||
/* FPU is available; library handles addressing */
|
||||
}
|
||||
```
|
||||
|
||||
**Why it breaks**: On A4000 (Ramsey), the FPU decode is different. On A1200 (Gayle, no FPU), this address is unmapped and causes a bus error.
|
||||
|
||||
### 2. The Accelerator Ghost
|
||||
|
||||
**Bad**:
|
||||
```c
|
||||
/* Assume all 68030 systems have Gary's SCSI at $DD0040 */
|
||||
UBYTE scsi_read = *(volatile UBYTE *)0x00DD0040;
|
||||
```
|
||||
|
||||
**Good**:
|
||||
```c
|
||||
/* Open scsi.device and send HD_SCSICMD */
|
||||
struct IOStdReq *io = CreateIORequest(port, sizeof(struct IOStdReq));
|
||||
OpenDevice("scsi.device", 0, (struct IORequest *)io, 0);
|
||||
/* ... use io for SCSI operations ... */
|
||||
```
|
||||
|
||||
**Why it breaks**: An A2000 with a 68030 accelerator has NO SCSI at $DD0040 (unless an A2091 is installed). The address is unmapped.
|
||||
|
||||
### 3. The Bus Grant Hog
|
||||
|
||||
**Bad** (on accelerator firmware):
|
||||
```asm
|
||||
; Take the bus and keep it
|
||||
bset #0,board_control_reg ; assert /BR, get /BG
|
||||
.loop move.l (a0)+,(a1)+ ; fast copy — but DMA is dead!
|
||||
subq.l #1,d0
|
||||
bne .loop
|
||||
bclr #0,board_control_reg ; release /BG
|
||||
```
|
||||
|
||||
**Good**:
|
||||
```asm
|
||||
; Release bus periodically for DMA
|
||||
move.w #256,d1 ; copy 256 longs, then yield
|
||||
.copy move.l (a0)+,(a1)+
|
||||
subq.w #1,d1
|
||||
bne .copy
|
||||
bclr #0,board_control_reg ; release /BG
|
||||
bsr wait_one_scanline ; let DMA run for ~64 µs
|
||||
bset #0,board_control_reg ; re-acquire /BG
|
||||
sub.w #256,d0
|
||||
bgt .copy
|
||||
```
|
||||
|
||||
**Why it breaks**: Holding /BGACK indefinitely starves Agnus of DMA slots. The display freezes, audio stops, and the floppy drive motor runs dry. On the A3000, SCSI DMA also stalls — disk transfers hang.
|
||||
|
||||
---
|
||||
|
||||
## Pitfalls
|
||||
|
||||
### 1. A4000 CPU Slot Assumptions
|
||||
|
||||
Some A3000 CPU slot accelerators were marketed as "A3000/A4000 compatible." They are not — the A4000 uses Ramsey for DRAM control and Super Buster for bus arbitration, while the A3000 uses Fat Gary for both. An accelerator that assumes Fat Gary-style arbitration will fail on the A4000.
|
||||
|
||||
**Symptom**: Accelerator works perfectly on A3000, produces black screen on A4000.
|
||||
|
||||
**Fix**: Check for Gary vs Ramsey at firmware init by probing the AutoConfig database or testing for the presence of Ramsey's DRAM configuration registers at $C00000.
|
||||
|
||||
### 2. SCSI Timeout Cascade
|
||||
|
||||
The WD33C93A + SDMAC + Gary combination can produce a cascading timeout failure:
|
||||
|
||||
1. SCSI drive is slow to respond → WD33C93A asserts /DRQ (Data Request)
|
||||
2. Gary routes /DRQ to SDMAC
|
||||
3. SDMAC asserts bus request, Gary grants, SDMAC starts DMA
|
||||
4. If the SCSI drive stalls mid-transfer, SDMAC holds the bus indefinitely
|
||||
5. Gary cannot revoke /BGACK from SDMAC (design limitation)
|
||||
6. 68030 is locked off the bus → system hang
|
||||
|
||||
**Workaround**: The `scsi.device` in Kickstart 2.0+ implements a watchdog timer that resets the WD33C93A after ~2 seconds of inactivity. Third-party SCSI controllers (GVP, FastLane) use their own DMA engines and bypass this issue entirely.
|
||||
|
||||
### 3. ROM Overlay Boot Failure
|
||||
|
||||
At power-on, Gary maps Kickstart ROM at `$000000` (overlaying Chip RAM) so the 68030 can fetch the initial stack pointer and program counter from vectors 0 and 4. After Kickstart initializes, it writes to a **board strap register** (a write-only latch addressed at a Gary-decoded location) to disable the overlay and expose Chip RAM at `$000000`.
|
||||
|
||||
If the strap register write fails (e.g., a bad connection on the data bus, or a Gary revision that uses a different address), the overlay stays active and Chip RAM is never visible at `$000000`. Kickstart appears to boot but crashes when it tries to use ExecBase or any absolute address in low memory.
|
||||
|
||||
**Diagnosis**: The system shows a dark gray or light gray screen and hangs.
|
||||
|
||||
**Repair**: Re-seat Gary in its PLCC socket; check data bus continuity to the strap register latch.
|
||||
|
||||
---
|
||||
|
||||
## Use Cases
|
||||
|
||||
### What Kind of Software Needs Gary Awareness?
|
||||
|
||||
| Category | Example | Why Gary Matters |
|
||||
|---|---|---|
|
||||
| A3000 | Original Gary | 68030, Zorro III, WD33C93 SCSI |
|
||||
| A3000T | Gary (tower variant) | Same chip; tower form factor with more drive bays |
|
||||
| **Accelerator firmware** | CyberStorm, WarpEngine, GVP A3001 | Must implement bus arbitration protocol that Gary expects |
|
||||
| **Zorro III card firmware** | Picasso IV, A4091 SCSI, Toccata audio | Must respond to AutoConfig strobes generated by Gary via Buster |
|
||||
| **SCSI host adapter firmware** | A3000 motherboard SCSI, FastLane Z3 | DMA engine must handshake with Gary's bus arbitration |
|
||||
| **Kickstart ROM development** | Custom Kickstart builds, AROS/m68k | Must write to Gary's board strap register to disable ROM overlay |
|
||||
| **Hardware diagnostics** | DiagROM, Amiga Test Kit | Probes Gary-decoded addresses to isolate motherboard faults |
|
||||
| **FPGA Amiga implementation** | Minimig, MiSTer, FPGA Arcade | Must replicate Gary's arbitration timing with nanosecond precision |
|
||||
|
||||
The A4000 does **not** use Gary — it uses a different system controller chip called **Ramsey** along with **Budgie** and **Buster** for bus management.
|
||||
### Known Software That Probes Gary
|
||||
|
||||
- **DiagROM**: Tests /ROMCS0 and /ROMCS1 chip selects by reading ROM at mirrored addresses
|
||||
- **WhichAmiga**: Detects A3000 vs A4000 by probing for Gary-typical resources (SCSI at $DD0040)
|
||||
- **SysInfo**: Identifies motherboard model by scanning AutoConfig entries; uses Gary's presence as one input
|
||||
- **AmigaAMP / mpega.library**: Detects FPU at $E80000; the presence and address of the FPU confirms Fat Gary
|
||||
|
||||
---
|
||||
|
||||
## Historical Context
|
||||
|
||||
### The Glue Logic Problem
|
||||
|
||||
The Amiga 1000 (1985) used approximately **30 discrete TTL chips** for system glue logic: address decoding, bus arbitration, interrupt encoding, and peripheral chip selects. This was expensive (board real estate, assembly time, failure points) and slow (signal propagation through multiple TTL gates).
|
||||
|
||||
Commodore's solution was the Gary gate array, designed by the Amiga hardware team led by **Dave Haynie** and fabricated by **Commodore's CSG (Commodore Semiconductor Group)**. By collapsing ~30 chips into one 48-pin ASIC, Gary:
|
||||
- Reduced motherboard cost by ~$15–20 per unit
|
||||
- Shrunk the A500 motherboard from the A1000's large form factor to the compact "wedge" design
|
||||
- Reduced power consumption by ~2 W
|
||||
- Improved reliability: fewer socketed chips, fewer solder joints, fewer field failures
|
||||
|
||||
### Competitive Landscape (1990)
|
||||
|
||||
| Platform | System Controller | Year | Integration Level |
|
||||
|---|---|---|---|
|
||||
| **Amiga 3000 (Fat Gary)** | CSG 5393 — custom gate array | 1990 | Single chip: address decode + arbitration + interrupt + SCSI glue |
|
||||
| **Macintosh IIfx** | Custom ASICs + discrete PALs | 1990 | Multiple chips: separate address decoder, interrupt controller, SCSI controller |
|
||||
| **IBM PS/2 Model 70** | Intel 82380 + discrete logic | 1988 | Two-chip solution: 82380 DMA/interrupt + external decode PALs |
|
||||
| **Atari TT030** | MC68882 + discrete TTL | 1990 | No integrated system controller — all glue in discrete logic |
|
||||
| **NeXTcube** | Custom "PSC" (Peripheral Subsystem Controller) | 1990 | Single ASIC — similar philosophy to Fat Gary but much more complex |
|
||||
|
||||
Fat Gary was competitive but not revolutionary — it was a cost-reduction measure that happened to enable the A3000's compact motherboard. NeXT's PSC chip was more sophisticated (integrated SCSI, DSP interface, and Ethernet).
|
||||
|
||||
### The Ramsey / Budgie Fork
|
||||
|
||||
By 1992, Commodore knew the A4000 needed more than Fat Gary could provide:
|
||||
- The A4000's interleaved DRAM banks required a real **DRAM controller** with refresh timers (Ramsey)
|
||||
- The A4000 needed a bridge between the 32-bit CPU bus and the 16-bit Chip bus (Budgie)
|
||||
- Zorro III arbitration was split off to **Super Buster** (revision 11), removing that burden from the system controller
|
||||
|
||||
This is why the A4000 system controller architecture is **3 chips** (Ramsey + Budgie + Super Buster) while the A3000 does everything with **1 chip** (Fat Gary + Super Buster for Zorro). The A4000's approach is more modular but more expensive; the A3000's approach is more integrated but harder to upgrade.
|
||||
|
||||
---
|
||||
|
||||
## Modern Analogies
|
||||
|
||||
| Amiga Concept | Modern Equivalent | Why the Analogy Holds | Where It Breaks |
|
||||
|---|---|---|---|
|
||||
| **Fat Gary** | **Northbridge** (Intel P45, AMD 990FX) | Both decode address ranges into chip selects, manage bus arbitration between CPU/DMA, and route interrupts | Modern Northbridges have configuration registers (PCI config space); Gary is hard-wired with no software interface |
|
||||
| **Gary's AutoConfig strobes** | **PCI Express enumeration** (BIOS/UEFI) | Both probe the bus, assign address space, and load option ROMs | PCIe uses in-band messaging (TLP packets); Gary uses out-of-band sideband signals (/CFGIN, /CFGOUT) |
|
||||
| **Board strap register** | **GPIO strap pins / devicetree** | Both set hardware configuration at boot via static pin states | Modern straps are read by firmware and stored in variables; Gary's strap register is write-once and read-never |
|
||||
| **Gary's bus arbitration** | **Intel QPI / AMD HyperTransport arbitration** | Both manage shared bus access among multiple masters with priority levels | QPI uses distributed arbitration with credit-based flow control; Gary uses a centralized priority encoder |
|
||||
| **A3000 SCSI DMA via Gary+SDMAC** | **AHCI / NVMe DMA engine** | Both offload data transfer to a dedicated DMA controller transparent to the CPU | Modern DMA engines have descriptor rings and scatter-gather lists; SDMAC is a simple continuous linear DMA |
|
||||
|
||||
---
|
||||
|
||||
## Impact on FPGA / Emulation
|
||||
|
||||
### Critical Timing Requirements
|
||||
|
||||
Gary's arbitration protocol is **timing-sensitive**, not just logic-correct. An FPGA implementation must:
|
||||
|
||||
1. **Respect 20 ns arbitration resolution**: Gary switches bus ownership in one CPU clock cycle (50 MHz A3000). If the FPGA's state machine takes longer, DMA slots are missed, causing display glitches (flickering pixels, missing scanlines).
|
||||
2. **Match propagation delays**: The original Gary has ~7 ns gate delay from address inputs to chip-select outputs. If the FPGA is too fast, chip selects may assert before address lines stabilize. If too slow, SCSI DMA may miss its transfer window.
|
||||
3. **Simulate /BGACK assertion timing**: /BGACK must assert within 1.5 clock cycles of /BG being received. Coarser timing causes the 68030 to proceed with a bus cycle that Gary intended to block — data corruption.
|
||||
|
||||
### Known FPGA Implementations
|
||||
|
||||
| FPGA Core | Gary Model | Status | Notes |
|
||||
|---|---|---|---|
|
||||
| **Minimig** (Dennis van Weeren) | Original Gary (5719) | Working | Used in OCS/ECS Minimig cores; timing relaxed for TG68K |
|
||||
| **MiSTer Minimig** | Original Gary (5719) | Working | ECS support; Fat Gary not yet implemented (no A3000 SCSI simulation) |
|
||||
| **FPGA Arcade Replay** | Fat Gary (5393) | Partial | A3000 mode in development; arbitration timing is the main challenge |
|
||||
| **Apollo 68080 (Vampire)** | N/A | N/A | Does not emulate Gary — the SAGA chipset replaces all custom chips with a modern architecture |
|
||||
|
||||
### Emulation Test Checklist
|
||||
|
||||
For FPGA developers implementing Fat Gary:
|
||||
|
||||
- [ ] SCSI DMA transfers complete without timeout (WD33C93A → SDMAC → Gary arbitration)
|
||||
- [ ] Zorro III cards enumerate correctly via AutoConfig
|
||||
- [ ] ROM overlay disabled correctly after Kickstart init (check Chip RAM visible at $000000)
|
||||
- [ ] FPU accessible at $E80000 when 68882 is configured
|
||||
- [ ] Interrupt acknowledge cycles return correct vectors ($64–$78)
|
||||
- [ ] /BGACK released within one scanline (63.5 µs) to prevent display corruption
|
||||
- [ ] Level 2 (5393) behavior: all Zorro III asynchronous cycles work
|
||||
|
||||
---
|
||||
|
||||
## FAQ
|
||||
|
||||
### Q: Can I read Gary's configuration from software?
|
||||
|
||||
No. Gary has no readable registers. Its configuration is set at power-on by hardware strapping (resistor pull-ups/downs on specific pins). There is no way for software to query Gary's state.
|
||||
|
||||
### Q: How do I know if my A3000 has a Level 1 or Level 2 Fat Gary?
|
||||
|
||||
Open the case and read the chip marking. Level 1 is CSG 5391 (or marked "390540-01"). Level 2 is CSG 5393 (or marked "390540-02", die rev 13H+). If you can't open the case, install a Zorro III DMA card — Level 1 Gary will show data corruption under heavy DMA; Level 2 will work.
|
||||
|
||||
### Q: Does the A3000T use a different Gary from the A3000 desktop?
|
||||
|
||||
No. Both use the same Fat Gary (CSG 5393, P/N 390540-02). The A3000T differs only in form factor and drive bays, not in core logic.
|
||||
|
||||
### Q: Can I replace Gary with Gayle?
|
||||
|
||||
No. They are pin-incompatible (48-pin DIP vs surface-mount), functionally different (Gayle adds IDE/PCMCIA), and designed for different bus architectures (16-bit 68000 vs 32-bit 68030).
|
||||
|
||||
### Q: Why does the A4000 desktop NOT use Gary but the A4000T DOES?
|
||||
|
||||
The A4000T was a tower variant produced by Commodore's subcontractor (originally designed as the "A3500" prototype, then repurposed). It reused the A3000's motherboard logic (Fat Gary + Super Buster) rather than the A4000 desktop's Ramsey/Budgie design. This is why the A4000T is sometimes described as "an A3000 with AGA" — the system controller is identical to the A3000's.
|
||||
|
||||
### Q: Is Gary responsible for the A3000's "SCSI lockup" problem?
|
||||
|
||||
Indirectly. The SCSI lockup is caused by the WD33C93A stalling mid-transfer and the SDMAC holding /BGACK indefinitely. Gary cannot revoke /BGACK from SDMAC — this is a design limitation, not a bug. The workaround is to use a third-party SCSI controller (GVP, FastLane) with its own DMA engine or to upgrade to Kickstart 2.0+ which includes a watchdog timer in `scsi.device`.
|
||||
|
||||
### Q: Can I use Gary's /FPUCS at $E80000 for other peripherals?
|
||||
|
||||
No. The FPU chip select is hard-wired to decode $E80000–$EFFFFF. There is no GPIO or programmable address window on Gary. If you install a custom board in the FPU socket, it will be decoded at this address — but standard AmigaOS expects a 68881/68882 FPU there, and `mathieeesingbas.library` will try to use it.
|
||||
|
||||
---
|
||||
|
||||
## References
|
||||
|
||||
- Commodore A3000 Technical Reference Manual
|
||||
- ADCD 2.1 — Hardware Manual, A3000 chapter
|
||||
- NDK39: hardware headers (community-documented Gary behavior)
|
||||
- **Commodore A3000 System Specification** — The 1991-07-17 document detailing Fat Gary's signal list and timing
|
||||
- **Fat Gary Specification (390540-02)** — Commodore internal datasheet; PDF at `megaburken.net/~patrik/A3000/`
|
||||
- **A3000/A4000 Hardware Developer Notes v1.11** — Commodore engineering notes on Gary arbitration and Zorro III timing
|
||||
- **ADCD 2.1** — Hardware Manual, A3000 chapter
|
||||
- **NDK 3.9**: `exec/execbase.h` (AttnFlags), `graphics/gfxbase.h` (ChipRevBits0), `expansion/expansionbase.h` (ConfigDev)
|
||||
- **Grokipedia: Amiga custom chips** — Gary and Fat Gary overview: `https://grokipedia.com/page/Amiga_custom_chips`
|
||||
- **Dave Haynie interview (2003)** — Historical context on Gary's development: `https://landley.net/history/mirror/commodore/haynie.html`
|
||||
|
||||
## See Also
|
||||
|
||||
- [Gayle — IDE & PCMCIA](../common/gayle_ide_pcmcia.md) — A600/A1200 storage controller (different chip, different function)
|
||||
- [Zorro Bus](../common/zorro_bus.md) — Zorro II/III expansion managed by Gary
|
||||
- [Gayle — IDE & PCMCIA](../common/gayle_ide_pcmcia.md) — A600/A1200 successor integrating IDE and PCMCIA
|
||||
- [Zorro Bus](../common/zorro_bus.md) — Zorro II/III expansion managed by Gary via Buster
|
||||
- [ECS Chipset](chipset_ecs.md) — Super Agnus + ECS Denise (A3000)
|
||||
- [CPU 030/040](../aga_a1200_a4000/cpu_030_040.md) — Accelerators that must interoperate with Gary's bus arbitration
|
||||
- [SCSI Device](../../10_devices/scsi.md) — Software interface to the SCSI hardware Gary enables
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ The **Original Chip Set** (OCS) ships in the Amiga 1000 (1985), A500 (1987), and
|
|||
| [paula_serial.md](paula_serial.md) | Serial port: SERPER/SERDATR, baud rate |
|
||||
| [sprites.md](sprites.md) | Hardware sprites: SPRxPTH, control words, attach mode |
|
||||
| [cdtv_hardware.md](cdtv_hardware.md) | CDTV platform: DMAC, CD-ROM, IR remote, NVRAM |
|
||||
| [gary_system_controller.md](gary_system_controller.md) | Gary CSG 5719: address decode, DMA arbitration, ROM overlay, Zorro II AutoConfig, Slow RAM, antipatterns, FPGA checklist |
|
||||
|
||||
---
|
||||
|
||||
|
|
|
|||
558
01_hardware/ocs_a500/gary_system_controller.md
Normal file
558
01_hardware/ocs_a500/gary_system_controller.md
Normal file
|
|
@ -0,0 +1,558 @@
|
|||
[← Home](../../README.md) · [Hardware](../README.md) · [OCS](README.md)
|
||||
|
||||
# Gary — OCS System Controller — Address Decode, Bus Arbitration, and Peripheral Glue (A500 / A2000 / CDTV)
|
||||
|
||||
## Overview
|
||||
|
||||
The **Gary** chip (CSG 5719, "Gate Array") is a custom ASIC that replaced approximately 30 discrete 74-series TTL ICs and PAL devices used for system glue logic in the Amiga 1000. Deployed in the Amiga 500 and Amiga 2000 from 1987, Gary decodes the upper address lines (A17–A23) of the 68000's 24-bit bus to generate chip-select signals for every device on the motherboard — Agnus, Denise, Paula, the CIA pair, Kickstart ROM, Slow RAM, and the Zorro II expansion bus. Gary is a pure **address decoder and bus arbiter**: it never touches the data bus, has no memory-mapped registers, and is configured entirely by hardware strap resistors at power-on. This makes it opaque to software but essential to every bus cycle the system performs. Its 32-bit successor, **Fat Gary** (CSG 5391/5393), debuted in the A3000 — see [ecs_a600_a3000/gary_system_controller.md](../ecs_a600_a3000/gary_system_controller.md) for that chip.
|
||||
|
||||
---
|
||||
|
||||
## Architecture — Where Gary Sits
|
||||
|
||||
Gary sits on the 68000 address bus and watches A17–A23 to produce chip-select strobes. Data flows directly between the 68000 and the selected device — Gary is never on the critical data path.
|
||||
|
||||
```mermaid
|
||||
graph LR
|
||||
CPU["68000 CPU<br/>7.09 MHz PAL"] -->|"Address Bus A1–A23"| Gary["Gary<br/>CSG 5719"]
|
||||
Gary -->|"Chip RAM / DMA<br/>$000000–$1FFFFF"| Agnus["OCS Agnus<br/>8361 / 8367"]
|
||||
Gary -->|"Register Select<br/>$DFF000–$DFF1FE"| Denise["OCS Denise<br/>8362"]
|
||||
Gary -->|"Register Select<br/>$DFF000–$DFF1FE"| Paula["Paula<br/>8364"]
|
||||
Gary -->|"ROM Select /ROMCS<br/>$F80000–$FFFFFF"| ROM["Kickstart ROM<br/>256–512 KB"]
|
||||
Gary -->|"CIA Select<br/>$BFDxxx / $BFExxx"| CIA["CIA-A / CIA-B<br/>MOS 8520"]
|
||||
Gary -->|"Slow RAM /RAMEN<br/>$C00000–$C7FFFF"| SRAM["Slow RAM<br/>512 KB trapdoor"]
|
||||
Gary -->|"Zorro II via Buster<br/>$E80000–$EFFFFF"| Buster["Buster<br/>CSG 5721"]
|
||||
CPU -->|"Data Bus D0–D15"| Agnus
|
||||
```
|
||||
|
||||
**Key principle**: Gary does not sit on the data bus — it only watches address lines and generates control strobes. Data flows directly between the CPU and the selected device.
|
||||
|
||||
---
|
||||
|
||||
## What Gary Decodes — Address Map
|
||||
|
||||
| Address Range | Size | Device | /CS Signal | Notes |
|
||||
|---|---|---|---|---|
|
||||
| `$000000–$1FFFFF` | 2 MB | Chip RAM (via Agnus) | Via Agnus | OCS Agnus addresses 512 KB; Fat Agnus 8370/8372 addresses 1 MB |
|
||||
| `$BFD000–$BFDFFF` | 4 KB | CIA-B | /CIABCSn | Disk motor, serial, parallel port direction |
|
||||
| `$BFE001–$BFEFFF` | 4 KB | CIA-A | /CIAACSn | Keyboard, parallel data, power LED, OVL overlay bit |
|
||||
| `$C00000–$C7FFFF` | 512 KB | Slow RAM | /RAMEN | Trapdoor expansion; chip-speed bus, not DMA-accessible |
|
||||
| `$DC0000–$DCFFFF` | 64 KB | Real-Time Clock | /RTCCS | A2000 battery-backed Oki MSM6242B; absent on base A500 |
|
||||
| `$DFF000–$DFF1FE` | 512 B | Custom Chip Registers | /OCS | OCS register set for Agnus, Denise, and Paula |
|
||||
| `$E80000–$EFFFFF` | 512 KB | Zorro II AutoConfig | /CFGINn | Card configuration window; first Zorro II card gets /CFGIN |
|
||||
| `$F80000–$FFFFFF` | 512 KB | Kickstart ROM | /ROMCS | 256 KB at $FC0000 (Kickstart 1.x); full 512 KB for 2.0+ |
|
||||
|
||||
> [!NOTE]
|
||||
> At power-on, Gary also maps Kickstart ROM at `$000000–$07FFFF` (the **ROM overlay**) so the 68000 can read initial stack pointer and program counter from vectors 0 and 4. This overlay is cleared by CIA-A Port A bit 0 (OVL) after Kickstart initializes.
|
||||
|
||||
```
|
||||
$000000 ┌─────────────────────────────┐ ─┐
|
||||
│ Chip RAM (via Agnus) │ │
|
||||
│ 512 KB OCS / 1 MB Fat Agnus │ │ 2 MB window
|
||||
$1FFFFF └─────────────────────────────┘ ─┘
|
||||
$200000 ┌─────────────────────────────┐
|
||||
│ Zorro II Auto Fast RAM │
|
||||
│ or reserved │
|
||||
$9FFFFF └─────────────────────────────┘
|
||||
$A00000 ┌─────────────────────────────┐
|
||||
│ CIA space │
|
||||
│ ($BFDxxx CIA-B / $BFExxx A) │
|
||||
$BFFFFF └─────────────────────────────┘
|
||||
$C00000 ┌─────────────────────────────┐
|
||||
│ Slow / Ranger RAM │
|
||||
│ (512 KB trapdoor expansion) │
|
||||
$C7FFFF └─────────────────────────────┘
|
||||
$C80000 ┌─────────────────────────────┐
|
||||
│ Reserved / RTC ($DC0000) │
|
||||
$DFFFFF └─────────────────────────────┘
|
||||
$DFF000 ├ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─┤
|
||||
│ Custom Chip Registers │
|
||||
$DFF1FE └ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─┘
|
||||
$E00000 ┌─────────────────────────────┐
|
||||
│ Reserved │
|
||||
$E7FFFF └─────────────────────────────┘
|
||||
$E80000 ┌─────────────────────────────┐
|
||||
│ Zorro II AutoConfig window │
|
||||
$EFFFFF └─────────────────────────────┘
|
||||
$F00000 ┌─────────────────────────────┐
|
||||
│ Reserved / A500+ Extended │
|
||||
$F7FFFF └─────────────────────────────┘
|
||||
$F80000 ┌─────────────────────────────┐
|
||||
│ Kickstart ROM │
|
||||
│ 256 KB (1.x) / 512 KB (2+) │
|
||||
$FFFFFF └─────────────────────────────┘
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Bus Arbitration
|
||||
|
||||
Gary manages the 68000's bus arbitration — the protocol by which multiple bus masters share a single address and data bus.
|
||||
|
||||
### Arbitration Hierarchy
|
||||
|
||||
| Priority | Master | Signals | Can Be Stalled? |
|
||||
|---|---|---|---|
|
||||
| 1 (Highest) | Custom Chip DMA (Agnus) | /CDMAC → /BGACK | Never — display, audio, and disk DMA are real-time |
|
||||
| 2 | 68000 CPU | /BR → /BG | Yes — held off during every DMA cycle |
|
||||
| 3 | Zorro II Bus Masters | Via Buster CSG 5721 → Gary | Yes — lowest priority |
|
||||
|
||||
### DMA Contention Mechanics
|
||||
|
||||
When Agnus needs a bus cycle — for example, a bitplane fetch for the current scanline:
|
||||
|
||||
1. **Agnus asserts /CDMAC** — dedicated DMA request line to Gary
|
||||
2. **Gary asserts /BR** (Bus Request) to the 68000
|
||||
3. **68000 completes its current bus cycle**, asserts /BG (Bus Grant), floats address and data busses
|
||||
4. **Gary asserts /BGACK** to hold the 68000 off the bus, then grants Agnus the cycle
|
||||
5. **Agnus performs one 16-bit DMA word transfer** — approximately 280 ns (2 CPU cycles at 7.09 MHz PAL)
|
||||
6. **Agnus releases /CDMAC** — Gary de-asserts /BGACK, 68000 resumes
|
||||
|
||||
At 7.09 MHz PAL, each horizontal raster line contains 228 color clocks. With four bitplanes active (OCS maximum in lores), 64 of those slots are consumed by DMA, leaving the 68000 roughly 35% of bus time. Enabling sprites, audio, and disk DMA reduces that further.
|
||||
|
||||
> [!WARNING]
|
||||
> Any hardware on the A500 expansion port that drives the bus without correctly implementing /BR → /BG → /BGACK will corrupt memory and can physically damage bus transceivers. This is the primary failure mode of incorrectly designed trapdoor expansions.
|
||||
|
||||
### /DTACK and Wait States
|
||||
|
||||
Unlike the 68030 on the A3000, the 68000 relies on **/DTACK** (Data Transfer Acknowledge) to complete bus cycles — the CPU inserts wait states until /DTACK is asserted. Gary (or the addressed device) drives /DTACK. Slow RAM and Kickstart ROM run at chip bus speed (~140 ns minimum cycle), inserting 0–1 wait states. This is why code in Fast RAM (Zorro II card) executes measurably faster than equivalent code in ROM or Chip RAM — no DMA contention and no wait-state overhead.
|
||||
|
||||
---
|
||||
|
||||
## Interrupt Controller
|
||||
|
||||
Gary encodes interrupt signals from multiple sources into the 68000's three encoded interrupt level lines (/IPL0, /IPL1, /IPL2). Paula handles primary interrupt encoding on the A500; Gary routes the encoded /IPL lines to the 68000. This contrasts with Fat Gary, which centralizes more interrupt logic internally.
|
||||
|
||||
| Interrupt Source | Gary Input | Encoded Level | 68K Vector |
|
||||
|---|---|---|---|
|
||||
| Vertical Blank | /INT2 (from Agnus) | Level 2 | $68 |
|
||||
| Copper | /INT2 (from Agnus) | Level 2 | $68 (shared) |
|
||||
| Blitter Done | /INT2 (from Agnus) | Level 2 | $68 (shared) |
|
||||
| Audio channels 0–3 | via Paula | Level 2 or 4 | $68 / $70 |
|
||||
| Serial port | /INT5 (from Paula) | Level 5 | $74 |
|
||||
| CIA-A / CIA-B | /INT6 (from CIAs) | Level 6 | $78 (shared) |
|
||||
| External (expansion) | /INT2 or /INT6 | Level 2 or 6 | Per-card |
|
||||
|
||||
### Interrupt Acknowledge Cycle
|
||||
|
||||
When the 68000 recognizes an interrupt it performs an **IACK cycle** (FC2–FC0 = 111 on the function code pins). Gary detects this and routes the acknowledge to the highest-priority pending interrupt source, which places its vector number on D0–D7. Amiga software never interacts with Gary's interrupt routing directly — use `exec.library` `SetIntVector()` and `AddIntServer()`.
|
||||
|
||||
---
|
||||
|
||||
## ROM Overlay
|
||||
|
||||
At power-on, the 68000 reads the initial stack pointer (vector 0) and program counter (vector 4) from address `$000000`. Since Chip RAM is uninitialized at reset, Gary maps Kickstart ROM at `$000000` instead, overlaying the Chip RAM window.
|
||||
|
||||
**Overlay sequence:**
|
||||
1. Power-on — Gary asserts /ROMCS for both `$F80000` and `$000000`
|
||||
2. 68000 reads reset vectors from `$000000` (Gary redirects to ROM)
|
||||
3. Kickstart initializes hardware, builds ExecBase
|
||||
4. Kickstart writes CIA-A Port A (`$BFE001`), clearing bit 0 (OVL) to 0
|
||||
5. Gary detects OVL=0 and removes the ROM overlay — Chip RAM is now visible at `$000000`
|
||||
|
||||
Gary monitors the OVL output of CIA-A continuously. This is the only runtime input Gary responds to after power-on; all other behavior is fixed by board strap resistors.
|
||||
|
||||
> [!NOTE]
|
||||
> The OVL bit lives at CIA-A Port A (`$BFE001`) bit 0. If Gary fails to respond to OVL=0 — bad socket contact, failing CIA-A, or a damaged Gary — Chip RAM never appears at `$000000` and Kickstart crashes while writing ExecBase to low memory.
|
||||
|
||||
---
|
||||
|
||||
## AutoConfig — Zorro II Expansion
|
||||
|
||||
Gary coordinates the Zorro II AutoConfig sequence that assigns address space to expansion cards at boot.
|
||||
|
||||
1. Kickstart probes at `$E80000`
|
||||
2. Gary decodes the address and routes it to **Buster CSG 5721** via expansion bus control lines
|
||||
3. Buster asserts /CFGIN to the first card in the daisy chain
|
||||
4. The card responds with its AutoConfig ROM: product ID, manufacturer ID, memory/IO requirements, option ROM
|
||||
5. Kickstart assigns the card's base address by writing to the card's configuration register
|
||||
6. Gary (via Buster) asserts /CFGOUT to pass configuration authority to the next card
|
||||
7. Repeat until no card responds to /CFGIN
|
||||
|
||||
Gary does not read AutoConfig data — it generates the address decode and bus signals. Kickstart software and Buster hardware implement the actual protocol. This separation means Gary works identically with any standards-compliant Zorro II card.
|
||||
|
||||
The original Gary supports **Zorro II only** (16-bit bus, up to 8 MB address space). Fat Gary on the A3000 adds Zorro III (32-bit) via Super Buster. See [zorro_bus.md](../common/zorro_bus.md) for the full AutoConfig protocol.
|
||||
|
||||
---
|
||||
|
||||
## Chip Variants and Machine Assignment
|
||||
|
||||
| CSG Part | Commodore P/N | Name | Package | Machines | Notes |
|
||||
|---|---|---|---|---|---|
|
||||
| 5718 | — | Gary | 48-pin DIP | A2000 (early rev 3.x–4.x) | Pre-production; minor Zorro II timing differences; rare |
|
||||
| 5719 | 318070-01 | Gary | 48-pin DIP | A500, A2000 (rev 4.x–6.x), CDTV | Standard production version; the chip this article covers |
|
||||
|
||||
Both 5718 and 5719 are pin-compatible and functionally equivalent for software purposes. The 5718 has known issues with some Zorro II timing edge cases on early A2000 boards; 5719 is the reliable production revision. All A500 boards shipped with 5719.
|
||||
|
||||
---
|
||||
|
||||
## Detecting Gary at Runtime
|
||||
|
||||
Gary has no readable registers. Software must detect its presence indirectly.
|
||||
|
||||
### Method 1: CPU Type via ExecBase (Coarse)
|
||||
|
||||
```c
|
||||
/* From exec/execbase.h */
|
||||
struct ExecBase *SysBase = *((struct ExecBase **)4);
|
||||
|
||||
if (!(SysBase->AttnFlags & AFF_68020)) {
|
||||
/* 68000 system → original Gary or Gayle (A600)
|
||||
* Not conclusive on its own — A600 also has 68000 */
|
||||
}
|
||||
```
|
||||
|
||||
### Method 2: AutoConfig Database (Conclusive for A2000/CDTV)
|
||||
|
||||
```c
|
||||
#include <proto/expansion.h>
|
||||
#include <libraries/configvars.h>
|
||||
|
||||
struct ExpansionBase *ExpansionBase;
|
||||
struct ConfigDev *cd = NULL;
|
||||
BOOL found_cbm_device = FALSE;
|
||||
|
||||
ExpansionBase = (struct ExpansionBase *)OpenLibrary("expansion.library", 37);
|
||||
if (ExpansionBase) {
|
||||
/* A2000 + A2091 SCSI shows manufacturer 0x0202, product 0x09.
|
||||
* CDTV DMAC shows manufacturer 0x0202, product 0x02.
|
||||
* Absence of 68020+ in AttnFlags + Commodore AutoConfig = Gary system. */
|
||||
while ((cd = FindConfigDev(cd, 0x0202 /* Commodore */, -1))) {
|
||||
found_cbm_device = TRUE;
|
||||
break;
|
||||
}
|
||||
CloseLibrary((struct Library *)ExpansionBase);
|
||||
}
|
||||
```
|
||||
|
||||
### Method 3: Probe the Slow RAM Window
|
||||
|
||||
```c
|
||||
/* Present only on A500 with trapdoor RAM installed.
|
||||
* Confirms A500 hardware topology but not Gary specifically.
|
||||
* REQUIRES a bus error trap — unmapped on base A500. */
|
||||
volatile UWORD *slow_test = (volatile UWORD *)0x00C00000;
|
||||
UWORD saved = *slow_test;
|
||||
*slow_test = 0x1234;
|
||||
BOOL has_slow_ram = (*slow_test == 0x1234);
|
||||
*slow_test = saved;
|
||||
```
|
||||
|
||||
### Method 4: Gayle ID Register (Negative Test)
|
||||
|
||||
```c
|
||||
/* Gayle (A600/A1200) exposes a readable ID byte at $DE0000.
|
||||
* If this read returns a known Gayle ID (0xD0 or 0xD1),
|
||||
* the system controller is Gayle, not Gary. */
|
||||
volatile UBYTE *gayle_id = (volatile UBYTE *)0x00DE0000;
|
||||
UBYTE id = *gayle_id;
|
||||
BOOL is_gayle = (id == 0xD0 || id == 0xD1);
|
||||
BOOL is_gary = !is_gayle && !(SysBase->AttnFlags & AFF_68020);
|
||||
```
|
||||
|
||||
> [!NOTE]
|
||||
> There is no universally reliable software method to identify Gary by positive detection. The Gayle negative test combined with `AttnFlags` gives a practical working heuristic for A500/A2000/CDTV vs A600 distinction.
|
||||
|
||||
---
|
||||
|
||||
## Gary vs Fat Gary vs Gayle — Decision Guide
|
||||
|
||||
| Criterion | Gary CSG 5719 | Fat Gary CSG 5393 | Gayle (A600 / A1200) |
|
||||
|---|---|---|---|
|
||||
| **Target machines** | A500, A2000, CDTV | A3000, A3000T, A4000T | A600, A1200 |
|
||||
| **CPU** | 68000 @ 7 MHz | 68030 @ 25 MHz | 68000 (A600) / 68020 (A1200) |
|
||||
| **Address bus** | 24-bit | 32-bit | 24-bit (A600), 32-bit (A1200) |
|
||||
| **Data bus** | 16-bit | 32-bit | 16-bit |
|
||||
| **SCSI glue** | None | WD33C93A + SDMAC | None — IDE instead |
|
||||
| **IDE** | None | None | Yes — /GAYLE_ID at `$DE0000` |
|
||||
| **PCMCIA** | None | None | Yes |
|
||||
| **FPU decode** | None | /FPUCS at `$E80000` | None |
|
||||
| **Readable registers** | None | None | /GAYLE_ID (read-only ID byte) |
|
||||
| **Expansion bus** | Zorro II via Buster 5721 | Zorro III via Super Buster | None |
|
||||
| **Package** | 48-pin DIP | 84-pin PLCC | Surface-mount |
|
||||
| **FPGA difficulty** | Low — simple decode | Medium — 20 ns arbitration | Medium — IDE timing emulation |
|
||||
|
||||
---
|
||||
|
||||
## When to Care About Gary
|
||||
|
||||
### When to Care
|
||||
|
||||
- **Writing an A500 trapdoor expansion**: Must correctly implement /BR → /BG → /BGACK handshake with Gary
|
||||
- **Porting Kickstart to new A500 hardware**: Must clear CIA-A OVL bit to expose Chip RAM at `$000000`
|
||||
- **Building a Minimig or MiSTer OCS core**: Gary's arbitration timing determines correct DMA slot assignment
|
||||
- **Debugging A500 boot failures**: ROM overlay, CIA-A OVL, and /ROMCS are the first points to check
|
||||
- **Writing A500 hardware diagnostics**: Probing Gary-decoded addresses isolates motherboard faults
|
||||
- **Developing A2000 ISA bridgeboard firmware**: Must coexist with Gary's Zorro II arbitration
|
||||
|
||||
### When NOT to Care
|
||||
|
||||
- **Writing application software**: Use `graphics.library`, `dos.library`, `exec.library` — Gary is invisible
|
||||
- **Writing a game using only Chip RAM**: Agnus manages all DMA; Gary is transparent to game logic
|
||||
- **Porting between A500 and A1200**: OS abstractions insulate you from Gary vs Gayle differences
|
||||
- **Writing a filesystem handler**: `dos.library` packet I/O has no visibility into Gary
|
||||
- **CLI tools and scripts**: Nothing at shell level depends on the system controller chip
|
||||
|
||||
---
|
||||
|
||||
## Best Practices
|
||||
|
||||
1. **Never depend on Gary-specific behavior** — use OS abstractions that work across all Amiga models
|
||||
2. **Clear OVL via CIA-A Port A bit 0, not by patching Gary directly** — CIA-A is the correct mechanism; this is the only runtime control Gary accepts
|
||||
3. **On expansion hardware, implement the full /BR → /BG → /BGACK handshake** — do NOT hold /BGACK indefinitely or Agnus DMA starves and the display corrupts
|
||||
4. **Probe Zorro II devices via `expansion.library`**, not hard-coded base addresses — the AutoConfig database is authoritative
|
||||
5. **Do not equate "68000 CPU" with "Gary present"** — the A600 also has a 68000 but uses Gayle; use the Gayle ID negative-probe method
|
||||
6. **When emulating Gary in FPGA, validate /DTACK timing** — the 68000 bus cycle requires /DTACK assertion within specific setup windows relative to /AS
|
||||
7. **Allocate DMA targets with `MEMF_CHIP`**, not `MEMF_PUBLIC` — Slow RAM at `$C00000` is not DMA-accessible regardless of what OS 1.3 may return from `AllocMem(MEMF_CHIP)`
|
||||
|
||||
---
|
||||
|
||||
## Antipatterns
|
||||
|
||||
### 1. The Hard-Coded Slow RAM Address
|
||||
|
||||
**Bad**:
|
||||
```c
|
||||
/* Assumes A500 trapdoor RAM is always present at $C00000 */
|
||||
UBYTE *scratch = (UBYTE *)0x00C00000;
|
||||
scratch[0] = 0x42; /* Bus error on base A500 with no trapdoor! */
|
||||
```
|
||||
|
||||
**Good**:
|
||||
```c
|
||||
/* Ask exec — it knows what memory is actually installed */
|
||||
UBYTE *scratch = (UBYTE *)AllocMem(1, MEMF_PUBLIC | MEMF_CLEAR);
|
||||
if (scratch) {
|
||||
scratch[0] = 0x42;
|
||||
FreeMem(scratch, 1);
|
||||
}
|
||||
```
|
||||
|
||||
**Why it breaks**: `$C00000` is unmapped on a base A500 with no trapdoor expansion. Accessing an unmapped Gary-decoded range causes a bus error that crashes the system. On an A2000 with a different expansion memory layout, `$C00000` may map to entirely different hardware.
|
||||
|
||||
### 2. The Bus Grant Hog
|
||||
|
||||
**Bad** (on A500 expansion firmware):
|
||||
```asm
|
||||
; Seize the bus and hold it for a bulk copy — DMA dies
|
||||
bset #0,board_ctrl ; assert /BR, grab /BG from Gary
|
||||
.loop move.l (a0)+,(a1)+ ; display freezes, audio stops
|
||||
subq.l #1,d0
|
||||
bne .loop
|
||||
bclr #0,board_ctrl ; release — screen is already corrupted
|
||||
```
|
||||
|
||||
**Good**:
|
||||
```asm
|
||||
; Copy in bursts, yielding to DMA every horizontal blank
|
||||
.outer move.w #128,d1 ; copy 128 longwords per burst
|
||||
bset #0,board_ctrl ; acquire /BG
|
||||
.inner move.l (a0)+,(a1)+
|
||||
subq.w #1,d1
|
||||
bne .inner
|
||||
bclr #0,board_ctrl ; release — let Agnus DMA run
|
||||
bsr wait_hblank ; wait ~64 µs (one PAL scanline)
|
||||
sub.l #128,d0
|
||||
bgt .outer
|
||||
```
|
||||
|
||||
**Why it breaks**: Holding /BGACK indefinitely starves Agnus of DMA slots. Every bitplane fetch, sprite fetch, audio sample, and disk byte fails. Even holding for two scanlines produces visible horizontal tearing. On the A500, this is the fastest way to produce the infamous "black bars" screen corruption.
|
||||
|
||||
### 3. The Slow RAM / Chip RAM Confusion
|
||||
|
||||
**Bad**:
|
||||
```c
|
||||
/* AmigaOS 1.3 may return Slow RAM for MEMF_CHIP on expanded A500.
|
||||
* Audio DMA to Slow RAM silently fails. */
|
||||
UBYTE *sample_buf = (UBYTE *)AllocMem(sample_size, MEMF_CHIP);
|
||||
LoadSample(sample_buf);
|
||||
StartAudioDMA(sample_buf); /* no sound — DMA cannot reach $C00000 */
|
||||
```
|
||||
|
||||
**Good**:
|
||||
```c
|
||||
/* MEMF_CHIP guarantees DMA-accessible Chip RAM on OS 2.0+.
|
||||
* On OS 1.3, explicitly verify the pointer is below $200000. */
|
||||
UBYTE *sample_buf = (UBYTE *)AllocMem(sample_size, MEMF_CHIP | MEMF_CLEAR);
|
||||
if (sample_buf && (ULONG)sample_buf >= 0x00200000) {
|
||||
/* Got Slow RAM — free it and fail gracefully */
|
||||
FreeMem(sample_buf, sample_size);
|
||||
sample_buf = NULL;
|
||||
}
|
||||
```
|
||||
|
||||
**Why it breaks**: Slow RAM at `$C00000` is connected to the chip bus and accessible by the 68000, but is **not reachable by custom chip DMA**. Agnus's DMA engine can only address memory it has direct bus access to (true Chip RAM). Under OS 1.3 on an expanded A500, `AllocMem(MEMF_CHIP)` may return a pointer into Slow RAM because the OS misidentifies it; the audio, blitter, and disk DMA channels then silently fail or read garbage.
|
||||
|
||||
---
|
||||
|
||||
## Pitfalls
|
||||
|
||||
### 1. ROM Overlay Stuck Active
|
||||
|
||||
At power-on, Gary maps ROM at `$000000`. Kickstart clears CIA-A OVL to remove it. If OVL clearing fails — a cold solder joint on CIA-A, a damaged Gary socket pin, or a CIA-A with a stuck Port A line — the overlay stays active. Chip RAM never appears at `$000000`.
|
||||
|
||||
**Symptom**: Kickstart color indicators appear (green/yellow power LED flash), then the system hangs at a gray screen. The CPU is executing Kickstart from ROM and crashes when it tries to write ExecBase to low Chip RAM, which is still mapped to ROM (read-only — writes are silently ignored).
|
||||
|
||||
**Repair**: Re-seat Gary in its 48-pin DIP socket. Check CIA-A Port A (pin 10) continuity to the data bus. Test CIA-A independently; a failing CIA-A Port A is a common cause of this fault on aged A500 boards.
|
||||
|
||||
### 2. Zorro II Card Timeout During AutoConfig
|
||||
|
||||
Gary drives /CFGIN to the first Zorro II card. If a card holds /CFGIN asserted without returning an AutoConfig response in the expected time window, Buster 5721 may lock the expansion bus. The symptom is a boot hang — the system freezes during the Kickstart card enumeration phase with no display output from Kickstart's progress indicators.
|
||||
|
||||
**Diagnosis**: Boot with all Zorro II cards removed. Add cards one at a time to find the offending card. If the system boots cleanly without expansion hardware, the problem is a card with incompatible AutoConfig timing or a shorted /CFGIN line.
|
||||
|
||||
**Workaround**: Some A2000 boards have an AutoConfig bypass jumper (J500 on rev 6.2 boards) that skips Zorro II enumeration. This allows booting for diagnostics without the offending card blocking /CFGIN.
|
||||
|
||||
### 3. Trapdoor RAM Not Detected by OS
|
||||
|
||||
An A500 trapdoor expansion at `$C00000` is only recognized by AmigaOS if it passes the memory test during Kickstart's memory scan. Kickstart writes a pattern to `$C00000`, reads it back, and if correct, adds the memory to the free list via `AddMemList()`. If the trapdoor RAM has marginal DRAM chips (weak refresh, wrong CAS latency), the test may pass at cold boot but fail after warm-up — producing random crashes after a few minutes of use.
|
||||
|
||||
**Symptom**: The system boots, `AvailMem(MEMF_PUBLIC)` shows 1 MB instead of 512 KB, but random crashes occur under memory pressure within minutes.
|
||||
|
||||
**Diagnosis**: Run a RAM tester (Amiga Test Kit, DiagROM) immediately after boot before the RAM warms up and the failure window closes. Replace DRAM chips on the trapdoor board.
|
||||
|
||||
---
|
||||
|
||||
## Use Cases
|
||||
|
||||
### What Kind of Software Needs Gary Awareness?
|
||||
|
||||
| Category | Example | Why Gary Matters |
|
||||
|---|---|---|
|
||||
| **Trapdoor expansion firmware** | 512 KB RAM + clock (Datel, Cumana, Vortex) | Must implement /BR → /BG → /BGACK handshake; must not hold /BGACK across DMA slots |
|
||||
| **Zorro II card firmware** | GVP Series II, Supra WordSync, A2091 SCSI | AutoConfig ROM must respond to Gary-via-Buster /CFGIN within spec timing |
|
||||
| **Custom boot ROMs** | DiagROM, custom Kickstart builds | Must clear CIA-A OVL bit to disable ROM overlay before accessing Chip RAM at `$000000` |
|
||||
| **Hardware diagnostics** | Amiga Test Kit, DiagROM | Probes Gary-decoded addresses (`$BFE001`, `$DFF000`, `$F80000`) to isolate motherboard faults |
|
||||
| **FPGA Amiga cores (OCS)** | Minimig, MiSTer OCS/ECS | Must replicate Gary's DMA arbitration timing to pass all OCS display modes correctly |
|
||||
| **A2000 ISA bridgeboards** | A2088 (8088), A2286 (286) | Must coexist with Gary's Zorro II arbitration while bridging the ISA bus for PC peripherals |
|
||||
|
||||
### Known Software That Interacts with Gary
|
||||
|
||||
- **DiagROM**: Tests /ROMCS by reading ROM at mirrored addresses; tests CIA-A OVL clear; verifies Chip RAM at `$000000` after overlay removal
|
||||
- **Kickstart 1.2–3.2**: Clears OVL bit during cold boot; enumerates Zorro II cards via AutoConfig
|
||||
- **SysInfo**: Identifies A500 vs A2000 by detecting Zorro II resources and checking CPU type against machine topology
|
||||
- **A-Max II (Mac emulator)**: Mapped its own 128 KB Mac ROM into `$400000–$5FFFFF` — a range Gary does not decode — to avoid conflicting with Kickstart ROM at `$F80000`
|
||||
- **Enforcer**: Probes known Gary-decoded addresses to identify unmapped regions that should generate bus errors; uses these to detect illegal memory accesses
|
||||
|
||||
---
|
||||
|
||||
## Historical Context
|
||||
|
||||
### The Glue Logic Problem
|
||||
|
||||
The Amiga 1000 (1985) used approximately **30 discrete TTL chips** for system glue: address decoding, bus arbitration, interrupt encoding, and peripheral chip selects. Each additional chip was a PCB cost, a power draw, a potential failure point, and a propagation delay in the critical path from CPU address output to device chip select.
|
||||
|
||||
Commodore's hardware team — including **Dave Haynie** and **Bob Raible** at Commodore's West Chester facility — designed Gary as a single 48-pin ASIC that collapsed all that discrete logic. First deployed in the A500 (April 1987):
|
||||
- Reduced motherboard cost by approximately **$12–18 per unit** at 1987 component prices
|
||||
- Enabled the A500's compact **"wedge" form factor** — the A1000 motherboard was significantly larger
|
||||
- Reduced power consumption by approximately **1.5–2 W**
|
||||
- Eliminated roughly **15 solder joint failure points** from the board
|
||||
|
||||
### Competitive Landscape (1987)
|
||||
|
||||
| Platform | System Controller | Year | Integration Level |
|
||||
|---|---|---|---|
|
||||
| **Amiga 500 (Gary)** | CSG 5719 — custom gate array | 1987 | Single chip: address decode + DMA arbitration + interrupt routing + ROM overlay |
|
||||
| **Atari ST (Glue)** | Custom ASIC ("Glue") | 1985 | Single chip: address decode + interrupt control; DMA handled separately by DMA chip |
|
||||
| **Apple IIGS (Mega II)** | Custom ASIC ("Mega II") | 1986 | Single chip: Apple II bus emulation + IIgs bus bridge; similar scope to Gary |
|
||||
| **IBM PC AT** | Intel 8288 + discrete PALs | 1984 | Multi-chip: separate bus controller, interrupt controller (8259A), DMA (8237A) |
|
||||
| **Macintosh SE** | Discrete PALs + VLSI chips | 1987 | Multiple chips: no single Gary-equivalent; address decode spread across multiple devices |
|
||||
|
||||
Gary was ahead of the PC world in single-chip glue integration by approximately two to three years. Intel would not produce a comparable single-chip PC chipset until the 82C206/82C207 "NEAT" chipsets of 1988.
|
||||
|
||||
---
|
||||
|
||||
## Modern Analogies
|
||||
|
||||
| Amiga Concept | Modern Equivalent | Why the Analogy Holds | Where It Breaks |
|
||||
|---|---|---|---|
|
||||
| **Gary** | **Northbridge** (Intel 440BX, VIA Apollo Pro) | Both decode address ranges into chip selects, manage bus arbitration among CPU and DMA, route interrupts | Modern Northbridges have PCI configuration registers (in-band config space); Gary has no software interface at all |
|
||||
| **Gary's AutoConfig strobes** | **PCI bus enumeration** (BIOS Plug and Play) | Both probe the bus, assign address space, and load option ROMs | PCI uses in-band messaging (config cycles); Gary uses sideband signals (/CFGIN, /CFGOUT daisy chain) |
|
||||
| **OVL bit via CIA-A** | **GPIO strap pins / firmware early-boot flags** | Both switch the boot memory map after initial CPU execution, then lock down | Modern straps are one-time fuses or NVRAM; Gary's OVL is a real-time input that Gary monitors continuously |
|
||||
| **Gary's bus arbitration** | **PCI bus master arbitration (REQ/GNT)** | Both grant and revoke bus ownership among multiple masters at defined priority levels | PCI uses a distributed, pipelined arbiter with multiple REQ/GNT pairs; Gary is a centralized priority encoder |
|
||||
| **Slow RAM at $C00000** | **Uncached DRAM region (MTRR WC)** | Both are CPU-accessible but excluded from coherent DMA | Modern uncached regions are defined by page table attributes (MTRRs, PAT); Gary's exclusion is hard-wired in silicon |
|
||||
|
||||
---
|
||||
|
||||
## Impact on FPGA / Emulation
|
||||
|
||||
### Critical Timing Requirements
|
||||
|
||||
An FPGA Gary implementation must satisfy:
|
||||
|
||||
1. **68000 /DTACK timing**: The 68000 requires /DTACK to be asserted no later than the falling edge of S4 in a normal bus cycle (≈ 140 ns at 7.09 MHz PAL). Gary must generate /DTACK (or ensure the target device does) within this window or insert wait states precisely; inserting too many wait states degrades performance and breaks timing-sensitive floppy I/O.
|
||||
2. **DMA slot boundaries**: The A500's DMA slot schedule is fixed within each horizontal line — Gary must assert /BGACK on exact color-clock boundaries. Granting the bus one color clock early or late produces bitplane horizontal scroll errors (image shifted one pixel left or right relative to sprites).
|
||||
3. **CIA-A OVL decoding**: Gary must monitor CIA-A Port A bit 0 and switch ROM overlay state within one bus cycle of the CIA-A write. A delayed response corrupts the Kickstart boot sequence because the CPU reads from the wrong memory.
|
||||
|
||||
### Known FPGA Implementations
|
||||
|
||||
| FPGA Core | Gary Model | Status | Notes |
|
||||
|---|---|---|---|
|
||||
| **Minimig** (Dennis van Weeren) | CSG 5719 | Working | Reference Verilog implementation in `rtl/gary.v` |
|
||||
| **MiSTer Minimig** | CSG 5719 | Working | Full ECS support; most widely deployed OCS/ECS core |
|
||||
| **FPGA Arcade Replay** | CSG 5719 | Working | Alternative implementation for the Replay board |
|
||||
| **UAE / WinUAE** | Software emulation | Working | Gary logic in `custom.c`; definitive reference for timing edge cases |
|
||||
|
||||
### Emulation Test Checklist
|
||||
|
||||
For FPGA developers implementing Gary (CSG 5719):
|
||||
|
||||
- [ ] ROM overlay active at reset: `$000000` reads Kickstart ROM, not Chip RAM
|
||||
- [ ] OVL=0 (CIA-A PRA bit 0 cleared) removes overlay within one bus cycle: `$000000` now shows Chip RAM
|
||||
- [ ] `$DFF000–$DFF1FE` asserts /OCS and selects custom chips
|
||||
- [ ] `$F80000–$FFFFFF` asserts /ROMCS for 256 KB or 512 KB ROM depending on configuration strap
|
||||
- [ ] `$BFD000` selects CIA-B; `$BFE001` selects CIA-A
|
||||
- [ ] `$E80000` AutoConfig probe reaches Buster 5721 / first Zorro II card via /CFGIN
|
||||
- [ ] /BGACK asserted within one bus cycle of /BG receipt from 68000
|
||||
- [ ] /BGACK released within one scanline (63.5 µs PAL) to prevent horizontal display corruption
|
||||
- [ ] Slow RAM at `$C00000–$C7FFFF` asserts /RAMEN when trapdoor expansion is configured
|
||||
- [ ] Bus error generated for accesses to unmapped regions (no /DTACK fallback)
|
||||
|
||||
---
|
||||
|
||||
## FAQ
|
||||
|
||||
### Q: Does the A500 Gary differ from the A2000 Gary?
|
||||
|
||||
Functionally no. Both A500 and A2000 (rev 4.x+) use the same CSG 5719. The A2000 adds a larger board with five Zorro II slots, ISA slots, and a video slot, but Gary's behavior is identical across both machines. Early A2000 boards (rev 3.x) used CSG 5718, which is functionally equivalent but has minor Zorro II timing differences on some card combinations.
|
||||
|
||||
### Q: Why is Slow RAM called "Slow RAM" if the A500's CPU is already slow by modern standards?
|
||||
|
||||
The name contrasts with **Fast RAM** (Zorro II expansion memory), not with modern CPU speeds. Slow RAM at `$C00000` runs at chip bus speed (7.09 MHz, with DMA contention). Fast RAM on a Zorro II card has no DMA overhead and the 68000 accesses it at its full 7.09 MHz synchronous speed — no wait states from DMA slot arbitration. "Slow" and "Fast" are relative terms within the A500's memory hierarchy.
|
||||
|
||||
### Q: Can I replace a failed Gary in an A500?
|
||||
|
||||
Yes. Gary is socketed in a 48-pin DIP socket on all A500 revisions. Replacement CSG 5719 chips can be harvested from dead A500 or A2000 boards. There is no commercial FPGA drop-in replacement for the 48-pin DIP Gary as of 2025, but FPGA-based A500 replacements (ReAmiga boards) implement Gary logic in an FPGA alongside all other custom chips.
|
||||
|
||||
### Q: Is Gary responsible for A500 "black screen of death"?
|
||||
|
||||
Gary-related failures typically produce a **gray screen** (Kickstart loaded from ROM but crashed writing ExecBase to Chip RAM that is still overlaid with ROM), not a black screen. A completely black screen usually indicates dead Agnus (no video output regardless of CPU state), a dead 68000, or missing Kickstart ROM. If the screen is gray and the floppy does not spin after initial seeking, suspect Gary or CIA-A OVL.
|
||||
|
||||
### Q: Does Gary control the power LED?
|
||||
|
||||
No. The power LED is driven by CIA-A Port A bit 1 (`$BFE001` bit 1). Gary decodes the CIA address range and generates the CIA chip select, but the LED logic is entirely within CIA-A. Bit 1 = 0 lights the LED at full brightness; bit 1 = 1 lets the LED be controlled by CIA-A timer output (dimming effect used by some disk access indicators).
|
||||
|
||||
### Q: Can the A500 run without Gary?
|
||||
|
||||
No. Gary generates every chip-select signal on the board. Without Gary, the 68000 address bus drives nothing — no ROM chip select means no ROM overlay at boot, so the CPU fetches garbage reset vectors and immediately executes undefined instructions. Gary is as fundamental to the A500 as Agnus.
|
||||
|
||||
---
|
||||
|
||||
## References
|
||||
|
||||
- *Amiga Hardware Reference Manual*, 3rd ed. (Addison-Wesley, 1991) — Sections 5–8: custom chip bus, address map, CIA, bus arbitration
|
||||
- **ADCD 2.1 Hardware Manual** — Chapter 2: Memory Map; Chapter 4: Bus Arbitration — http://amigadev.elowar.com/read/ADCD_2.1/Hardware_Manual_guide/
|
||||
- **Amiga 500 Schematics** (rev 5 and rev 6) — Full Gary pinout and strap resistor network; available at `amigapcb.org`
|
||||
- **Minimig RTL source** — `rtl/gary.v` implements CSG 5719 in Verilog: `github.com/rkrajnc/minimig-mist`
|
||||
- **UAE/WinUAE source** — `custom.c` and `memory.c` document Gary address decode and timing behavior: `github.com/tonioni/WinUAE`
|
||||
- **NDK 3.9** — `exec/execbase.h` (AttnFlags), `hardware/cia.h` (CIA-A OVL bit), `libraries/configvars.h` (AutoConfig structures)
|
||||
- **Dave Haynie developer notes (1990–1993)** — Context on Gary design decisions and the transition to Fat Gary
|
||||
|
||||
## See Also
|
||||
|
||||
- [Fat Gary (A3000)](../ecs_a600_a3000/gary_system_controller.md) — 32-bit successor with SCSI glue, Zorro III, FPU chip select, and 20 ns arbitration precision
|
||||
- [OCS Chipset Internals](chipset_ocs.md) — DMA priorities, Agnus bus mastering, Copper and Blitter contention
|
||||
- [Custom Chip Registers](custom_registers.md) — Full OCS register map at `$DFF000–$DFF1FE` that Gary's /OCS line enables
|
||||
- [Zorro Bus](../common/zorro_bus.md) — Zorro II expansion protocol, AutoConfig, Buster 5721 arbitration
|
||||
- [CIA Chips](../common/cia_chips.md) — CIA-A Port A OVL bit, interrupt lines, and timer outputs that Gary routes to the 68000
|
||||
- [Address Space](../common/address_space.md) — Complete A500/A2000 memory map with all Gary-decoded regions annotated
|
||||
Loading…
Add table
Add a link
Reference in a new issue