Restructure - dedicated for copper and blitter separate subfolders to have the room to expand

01_hardware/common/memory_types.md

@@ -6,7 +6,7 @@
 
 The Amiga's memory architecture is fundamentally different from any other home computer of its era. Rather than treating all RAM as equal, the system divides memory into **distinct classes** based on which hardware can access it. This division exists because the custom chipset (Agnus/Alice, Denise/Lisa, Paula) has its own DMA engine that operates on a dedicated bus — and that bus only reaches certain RAM.
 
-Understanding this distinction is not optional. It determines where screen buffers live, why games run faster with expansion RAM, why the [Blitter](../../08_graphics/blitter_programming.md) can't touch Fast RAM, and why a $50 accelerator card with 8 MB of Fast RAM can feel like a new machine.
+Understanding this distinction is not optional. It determines where screen buffers live, why games run faster with expansion RAM, why the [Blitter](../../08_graphics/blitter/blitter_programming.md) can't touch Fast RAM, and why a $50 accelerator card with 8 MB of Fast RAM can feel like a new machine.
 
 > [!WARNING]
 > The 68000 is **Big-Endian**. All multi-byte values in memory (pointers, word-sized registers, structure fields) are stored most-significant byte first. Modern developers working with Amiga memory dumps or binary formats will misread data if they assume little-endian layout.
@@ -419,7 +419,7 @@ A: WHDLoad patches old games that assume all memory is Chip RAM. It redirects al
 - See also: [address_space.md](address_space.md) — full 24-bit/32-bit address map
 - See also: [chip_ram_expansion.md](../ecs_a600_a3000/chip_ram_expansion.md) — 2 MB Chip RAM with Super Agnus
 - See also: [zorro_bus.md](zorro_bus.md) — Zorro II/III expansion bus (Fast RAM cards)
-- See also: [blitter_programming.md](../../08_graphics/blitter_programming.md) — Blitter DMA (Chip RAM only)
+- See also: [blitter_programming.md](../../08_graphics/blitter/blitter_programming.md) — Blitter DMA (Chip RAM only)
 - See also: [exec_memory.md](../../06_exec_os/exec_memory.md) — AmigaOS memory management API
 - See also: [dma_architecture.md](dma_architecture.md) — DMA slot allocation, bus arbitration, why Chip RAM bandwidth matters
 - See also: [bus_architecture.md](bus_architecture.md) — Bus hierarchy, Chip↔Fast RAM transfer techniques, cache coherency

01_hardware/common/video_timing.md

@@ -15,7 +15,7 @@ This article documents **the complete signal path** from crystal to screen — t
 > - **Clock derivation and signal generation** — primary coverage here
 > - **DMA slot allocation and bandwidth** — see [DMA Architecture](dma_architecture.md)
 > - **ModeID selection and OS display API** — see [Display Modes](../../08_graphics/display_modes.md)
-> - **Copper instruction programming** — see [Copper Programming](../../08_graphics/copper_programming.md)
+> - **Copper instruction programming** — see [Copper Programming](../../08_graphics/copper/copper_programming.md)
 
 ---
 
@@ -732,8 +732,8 @@ A: For basic display, ±10 ns per clock edge is sufficient. For genlock compatib
 
 - [DMA Architecture](dma_architecture.md) — scanline slot allocation, bus arbitration, bandwidth calculations
 - [Display Modes](../../08_graphics/display_modes.md) — ModeID system, OS display API, chipset comparison
-- [Copper Programming](../../08_graphics/copper_programming.md) — beam-synchronized register writes
-- [Copper — UCopList](../../08_graphics/copper.md) — system copper list management
+- [Copper Programming](../../08_graphics/copper/copper_programming.md) — beam-synchronized register writes
+- [Copper — UCopList](../../08_graphics/copper/copper.md) — system copper list management
 - [ECS Productivity Modes](../ecs_a600_a3000/productivity_modes.md) — BEAMCON0 programming examples
 - [CIA Chips](cia_chips.md) — E-clock, timers, TOD counter
 - [Memory Types](memory_types.md) — Chip RAM vs Fast RAM, DMA visibility