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90 changed files with 7794 additions and 705 deletions
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@ -128,7 +128,7 @@ ULONG changeCount = diskReq->iotd_Req.io_Actual;
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diskReq->iotd_Req.io_Command = TD_ADDCHANGEINT;
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diskReq->iotd_Req.io_Data = (APTR)&myInterrupt;
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SendIO((struct IORequest *)diskReq);
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/* myInterrupt is signalled on disk change */
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/* myInterrupt is signaled on disk change */
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```
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### Track Caching
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@ -141,7 +141,7 @@ Read sector 11 → new track → DMA reads track 1
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Read sector 5 → cache hit (still in track 0 buffer)
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```
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> **FPGA implication**: the MiSTer core must emulate this whole-track DMA behaviour for correct timing. Games that measure seek+read latency will behave incorrectly if only single sectors are transferred.
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> **FPGA implication**: the MiSTer core must emulate this whole-track DMA behavior for correct timing. Games that measure seek+read latency will behave incorrectly if only single sectors are transferred.
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---
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