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01_hardware/ocs_a500/chipset_ocs.md
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## DMA Channels and Priorities
Agnus schedules DMA cycles across a fixed priority scheme within each horizontal raster line (228 colour clocks per line, PAL):
Agnus schedules DMA cycles across a fixed priority scheme within each horizontal raster line (228 color clocks per line, PAL):
| Priority | DMA Channel | Register Bits |
|---|---|---|