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@ -4,14 +4,14 @@
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## Overview
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The **Advanced Graphics Architecture** (AGA) is the final custom chipset developed by Commodore, shipping from 1992. It dramatically expands colour depth, palette size, sprite capabilities, and blitter bandwidth while retaining full OCS/ECS backward compatibility.
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The **Advanced Graphics Architecture** (AGA) is the final custom chipset developed by Commodore, shipping from 1992. It dramatically expands color depth, palette size, sprite capabilities, and blitter bandwidth while retaining full OCS/ECS backward compatibility.
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## Chip Summary
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| Chip | Name | Changes from ECS |
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|---|---|---|
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| **Alice** | MOS 8374 | Super Agnus successor: 64-bit bus, FMODE register |
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| **Lisa** | (unnamed MOS) | ECS Denise successor: 8-bit palette, 256 colours |
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| **Lisa** | (unnamed MOS) | ECS Denise successor: 8-bit palette, 256 colors |
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| **Paula** | MOS 8364 | Unchanged from OCS/ECS |
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## Contents
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@ -20,8 +20,8 @@ The **Advanced Graphics Architecture** (AGA) is the final custom chipset develop
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|---|---|
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| [chipset_aga.md](chipset_aga.md) | Alice and Lisa internals, AGA architecture |
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| [aga_registers_delta.md](aga_registers_delta.md) | New/changed registers vs ECS |
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| [aga_palette.md](aga_palette.md) | 24-bit colour system, 256 registers |
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| [aga_display_modes.md](aga_display_modes.md) | HAM8, 256-colour, doublescan, VGA |
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| [aga_palette.md](aga_palette.md) | 24-bit color system, 256 registers |
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| [aga_display_modes.md](aga_display_modes.md) | HAM8, 256-color, doublescan, VGA |
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| [aga_blitter.md](aga_blitter.md) | 64-bit blitter bus, FMODE |
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| [aga_copper.md](aga_copper.md) | AGA Copper programming guide |
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| [cpu_030_040.md](cpu_030_040.md) | 68030/040 on A3000/A4000: cache, MMU, FPU |
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@ -32,11 +32,11 @@ The **Advanced Graphics Architecture** (AGA) is the final custom chipset develop
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| Feature | ECS | AGA |
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|---|---|---|
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| Colour registers | 32 (12-bit) | **256 (24-bit)** |
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| Max simultaneous colours | 64 EHB / HAM | **256** (or HAM8: 262,144) |
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| Color registers | 32 (12-bit) | **256 (24-bit)** |
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| Max simultaneous colors | 64 EHB / HAM | **256** (or HAM8: 262,144) |
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| Blitter bus | 16-bit | **64-bit** (FMODE) |
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| Sprite width | 16 px | **64 px** |
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| Sprite colours | 3+transparent | **15+transparent** (64-colour attached) |
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| Sprite colors | 3+transparent | **15+transparent** (64-color attached) |
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| Bitplane depth | 6 planes max | **8 planes** |
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| Palette select | 1 bank | **4 bitplane banks, 4 sprite banks** |
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@ -28,7 +28,7 @@ Think of it as a **hardware GPU for 2D raster operations** — years before PC g
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| No rotation | Cannot rotate — must be pre-rendered in software |
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| No 3D | No perspective, texture mapping, or Z-buffer |
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| No chunky pixels | Operates on **planar** bitplanes only (1 plane at a time) |
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| No colour blending | Pure Boolean logic — no alpha, no transparency gradients |
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| No color blending | Pure Boolean logic — no alpha, no transparency gradients |
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| Word-aligned width | Minimum operation width is 16 pixels (1 word) |
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### How Software Uses It
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@ -70,7 +70,7 @@ move.w #$0300, $DFF1FC ; BLT_FMODE = 10 (64-bit)
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```
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> [!IMPORTANT]
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> FMODE must be set **before** loading blitter registers and starting the blit. Changing FMODE mid-blit causes undefined behaviour.
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> FMODE must be set **before** loading blitter registers and starting the blit. Changing FMODE mid-blit causes undefined behavior.
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## Width Calculation with FMODE
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@ -4,13 +4,13 @@
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## What Is the Copper?
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The **Copper** (Co-Processor) is one of the most distinctive pieces of hardware in any computer ever built. It is a tiny, ultra-simple programmable DMA engine that executes a program — called a **copper list** — in perfect synchronisation with the video beam as it sweeps across the screen.
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The **Copper** (Co-Processor) is one of the most distinctive pieces of hardware in any computer ever built. It is a tiny, ultra-simple programmable DMA engine that executes a program — called a **copper list** — in perfect synchronization with the video beam as it sweeps across the screen.
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The Copper watches the beam position and can **write any value to any custom chip register at any specific screen position**. This single capability enables an astonishing range of visual effects.
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### Why Does It Matter?
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On a conventional computer, changing display parameters (colours, scroll positions, resolutions) requires the CPU to execute code at precisely the right moment. This is fragile, wastes CPU time, and is limited by interrupt latency.
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On a conventional computer, changing display parameters (colors, scroll positions, resolutions) requires the CPU to execute code at precisely the right moment. This is fragile, wastes CPU time, and is limited by interrupt latency.
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The Copper does this **automatically, for free, with perfect timing** — every single frame, without any CPU involvement at all.
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@ -50,20 +50,20 @@ The Copper does this **automatically, for free, with perfect timing** — every
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│ │ │ │ │
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│ ┌─────┴──────────────────┴────────────────────────┴─────────┐ │
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│ │ BEAM COUNTER (V count, H count) │ │
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│ │ Increments every colour clock, resets each frame │ │
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│ │ Increments every color clock, resets each frame │ │
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│ │ PAL: 312 lines × 227 clocks NTSC: 262 × 227 │ │
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│ └───────────────────────────────────────────────────────────┘ │
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└──────────┬─────────────────────────────────────────────────────────┘
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└──────────┬──────────────────────────────────────────────────────────┘
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│ register writes ($DFF000–$DFF1FE)
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▼
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┌─────────────────────────────────────────────────────────────────────┐
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│ DENISE / LISA (Video Encoder) │
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│ │
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│ Receives bitplane data + sprite data + colour register values │
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│ Receives bitplane data + sprite data + color register values │
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│ Composites them into a final pixel stream: │
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│ │
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│ ┌────────────┐ ┌──────────┐ ┌──────────┐ ┌──────────────────┐ │
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│ │ Bitplane │ │ Sprite │ │ Colour │ │ Playfield │ │
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│ │ Bitplane │ │ Sprite │ │ Color │ │ Playfield │ │
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│ │ Decode │→ │ Priority │→ │ Palette │→ │ Priority & │ │
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│ │ (planar→ │ │ Merge │ │ Lookup │ │ Genlock Control │ │
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│ │ index) │ │ │ │ (32/256) │ │ │ │
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@ -90,10 +90,10 @@ The Copper does this **automatically, for free, with perfect timing** — every
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### Component Interactions
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**Copper ↔ Chip RAM:**
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The Copper fetches its program (the copper list) from Chip RAM via DMA. It reads one instruction (2 words = 4 bytes) every 4 colour clocks. The copper list **must** reside in Chip RAM — it cannot be in Fast RAM because only Chip RAM is DMA-accessible.
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The Copper fetches its program (the copper list) from Chip RAM via DMA. It reads one instruction (2 words = 4 bytes) every 4 color clocks. The copper list **must** reside in Chip RAM — it cannot be in Fast RAM because only Chip RAM is DMA-accessible.
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**Copper ↔ Custom Registers:**
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When the Copper executes a MOVE instruction, it writes directly to a custom chip register (`$DFF000`–`$DFF1FE`). This is the exact same register space the CPU writes to. The Copper can set colours, bitplane pointers, sprite pointers, display window, scroll offsets, DMA control, and audio parameters.
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When the Copper executes a MOVE instruction, it writes directly to a custom chip register (`$DFF000`–`$DFF1FE`). This is the exact same register space the CPU writes to. The Copper can set colors, bitplane pointers, sprite pointers, display window, scroll offsets, DMA control, and audio parameters.
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**Copper ↔ Beam Counter:**
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The Copper continuously compares the current beam position (V count, H count) against WAIT instructions. When the beam reaches or passes the specified position, execution continues. This is a hardware comparator — no polling loop, no interrupt latency.
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@ -117,12 +117,12 @@ A WAIT instruction with bit 15 of the mask word cleared becomes a "blitter-finis
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| Effect | How | Used In |
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|---|---|---|
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| **Per-line colour changes** | WAIT for line, MOVE colour register | Gradient skies, rainbow bars |
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| **Per-line color changes** | WAIT for line, MOVE color register | Gradient skies, rainbow bars |
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| **Split screens** | Change bitplane pointers mid-frame | Status bar + scrolling playfield |
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| **Parallax scrolling** | Change BPLCON1 (scroll offset) at different lines | Multi-layer side-scrollers |
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| **Resolution changes** | Change BPLCON0 mid-frame | HiRes menu + LoRes game area |
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| **Sprite multiplexing** | Repoint sprite DMA pointers after sprite finishes | More than 8 sprites per frame |
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| **Palette animation** | Modify colour registers each frame | Cycling colours, water shimmer |
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| **Palette animation** | Modify color registers each frame | Cycling colors, water shimmer |
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| **Display window tricks** | Change DIWSTRT/DIWSTOP | Overscan, letterbox |
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| **Interlace tricks** | Toggle LOF bit | Custom interlace effects |
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@ -134,7 +134,7 @@ A WAIT instruction with bit 15 of the mask word cleared becomes a "blitter-finis
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| No memory read | Can only WRITE to registers, never read |
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| Write-only to custom regs | Cannot write to CPU memory, CIA, or Fast RAM |
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| Limited register set | Protected registers ($000–$03E) need `COPCON` unlock |
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| No sub-pixel timing | Horizontal resolution is 4 colour clocks (~8 low-res pixels) |
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| No sub-pixel timing | Horizontal resolution is 4 color clocks (~8 low-res pixels) |
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| Vertical wrapping | V counter wraps at 255; PAL lines 256+ need two WAITs |
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---
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@ -191,7 +191,7 @@ Example: Skip next if beam is past line 200:
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## Your First Copper List
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Here's the simplest possible copper list — it changes the background colour at line 128:
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Here's the simplest possible copper list — it changes the background color at line 128:
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```asm
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SECTION copperlist,DATA_C ; *** MUST be in Chip RAM! ***
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@ -220,7 +220,7 @@ To activate it:
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---
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## Rainbow Gradient (Colour Per Scanline)
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## Rainbow Gradient (Color Per Scanline)
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```asm
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RainbowCopper:
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@ -242,7 +242,7 @@ RainbowCopper:
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dc.w $FFFF,$FFFE
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```
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This produces a smooth colour gradient down the screen — **zero CPU cost**.
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This produces a smooth color gradient down the screen — **zero CPU cost**.
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---
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@ -325,23 +325,23 @@ AGA (Alice chip) keeps the same 3-instruction Copper but gains access to the **e
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| AGA Feature | Copper Can Set |
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|---|---|
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| 256-colour palette | `COLOR00–COLOR255` via BPLCON3 bank select |
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| Extended sprites | 64-colour sprites via palette banks |
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| 256-color palette | `COLOR00–COLOR255` via BPLCON3 bank select |
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| Extended sprites | 64-color sprites via palette banks |
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| FMODE | DMA fetch width (but careful — affects in-progress DMA) |
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| BPLCON3/BPLCON4 | AGA-specific bitplane/sprite control |
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### AGA Palette via Copper
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AGA has 256 colours but still only 32 colour registers visible at a time. To load all 256 colours, the Copper uses BPLCON3 to select palette banks:
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AGA has 256 colors but still only 32 color registers visible at a time. To load all 256 colors, the Copper uses BPLCON3 to select palette banks:
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```asm
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; Load colours 0–31 (bank 0)
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; Load colors 0–31 (bank 0)
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dc.w $0106,$0000 ; BPLCON3: bank 0
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dc.w $0180,$0000 ; COLOR00
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dc.w $0182,$0111 ; COLOR01
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; ... all 32 colours ...
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; Switch to bank 1 (colours 32–63)
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; ... all 32 colors ...
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; Switch to bank 1 (colors 32–63)
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dc.w $0106,$2000 ; BPLCON3: bank 1
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dc.w $0180,$0222 ; COLOR32
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dc.w $0182,$0333 ; COLOR33
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@ -354,9 +354,9 @@ AGA has 256 colours but still only 32 colour registers visible at a time. To loa
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| Parameter | Value |
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|---|---|
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| Instruction time | 4 colour clocks (= 8 lo-res pixels = ~1.12 µs) |
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| Instruction time | 4 color clocks (= 8 lo-res pixels = ~1.12 µs) |
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| Max instructions per line | ~112 (NTSC) / ~114 (PAL) |
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| Horizontal resolution | 4 colour clocks (~8 lo-res pixels) |
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| Horizontal resolution | 4 color clocks (~8 lo-res pixels) |
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| Vertical range | 0–255 (wraps; use double-WAIT for PAL lines 256+) |
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| PAL visible lines | 44–300 (256 visible) |
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| NTSC visible lines | 44–244 (200 visible) |
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@ -36,7 +36,7 @@ Mode flags (lower 16 bits):
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## Standard AGA Modes
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| Mode ID | Resolution | Colours | H rate |
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| Mode ID | Resolution | Colors | H rate |
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|---|---|---|---|
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| `PAL_MONITOR_ID \| LORES_KEY` | 320×256 | 256 | 15.6 kHz |
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| `PAL_MONITOR_ID \| HIRES_KEY` | 640×256 | 256 | 15.6 kHz |
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struct Screen *scr;
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/* 256-colour AGA screen, PAL, 320×256 */
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/* 256-color AGA screen, PAL, 320×256 */
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scr = OpenScreenTags(NULL,
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SA_DisplayID, PAL_MONITOR_ID | LORES_KEY,
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SA_Width, 320,
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SA_Height, 256,
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SA_Depth, 8, /* 8 bitplanes = 256 colours */
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SA_Colors32, (ULONG)colour_table, /* LoadRGB32 format */
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SA_Depth, 8, /* 8 bitplanes = 256 colors */
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SA_Colors32, (ULONG)color_table, /* LoadRGB32 format */
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SA_Title, (ULONG)"My AGA Screen",
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SA_Quiet, TRUE,
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TAG_DONE);
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@ -79,7 +79,7 @@ scr = OpenScreenTags(NULL,
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```
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> [!NOTE]
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> HAM8 screens require 8 bitplanes. The display system automatically programmes BPLCON0 with HAM=1. The first 64 colour registers are used as the HAM8 index palette.
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> HAM8 screens require 8 bitplanes. The display system automatically programmes BPLCON0 with HAM=1. The first 64 color registers are used as the HAM8 index palette.
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## BestModeID() — Querying Available Modes
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@ -1,12 +1,12 @@
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[← Home](../../README.md) · [Hardware](../README.md) · [AGA](README.md)
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# AGA Palette & Colour System
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# AGA Palette & Color System
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## Overview
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AGA provides **256 colour registers** (COLOR00–COLOR255), each **24-bit RGB** (8 bits per channel). This replaces OCS/ECS's 32 registers with 12-bit colour.
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AGA provides **256 color registers** (COLOR00–COLOR255), each **24-bit RGB** (8 bits per channel). This replaces OCS/ECS's 32 registers with 12-bit color.
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## Colour Register Layout
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## Color Register Layout
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```
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ADDRESS: $DFF180 + (n × 2) for register n (0–255)
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@ -18,11 +18,11 @@ $DFF180–$DFF1BE COLOR00–COLOR31 (same addresses as OCS/ECS)
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$DFF180–$DFF3BE COLOR00–COLOR255 (full AGA range — needs BPLCON4 bank select)
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```
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The 256 colour registers are accessed in 64-register **banks** selected by `BPLCON4`.
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The 256 color registers are accessed in 64-register **banks** selected by `BPLCON4`.
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## Writing 24-bit Colours
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## Writing 24-bit Colors
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Each colour register holds 12 bits directly (OCS/ECS compatible). The upper 12 bits (the "low nibble") are written via a second access with `LOCT` set in BPLCON3.
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Each color register holds 12 bits directly (OCS/ECS compatible). The upper 12 bits (the "low nibble") are written via a second access with `LOCT` set in BPLCON3.
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### Manual 24-bit write sequence:
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@ -52,7 +52,7 @@ The preferred OS call:
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/* Table: count, index, then 0x00RRGGBB values, terminated by ~0 */
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ULONG table[] = {
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4, 0, /* 4 colours starting at index 0 */
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4, 0, /* 4 colors starting at index 0 */
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0x00FF0000, /* COLOR00: red */
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0x0000FF00, /* COLOR01: green */
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0x000000FF, /* COLOR02: blue */
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|
@ -62,13 +62,13 @@ ULONG table[] = {
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LoadRGB32(viewport, table);
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```
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`LoadRGB32()` (graphics.library LVO -$192) is the AGA-correct way to set colours. It handles the two-write LOCT protocol internally and is available from OS 3.0+.
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`LoadRGB32()` (graphics.library LVO -$192) is the AGA-correct way to set colors. It handles the two-write LOCT protocol internally and is available from OS 3.0+.
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### Using LoadRGB4() — OCS/ECS compatible (12-bit)
|
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|
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```c
|
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UWORD colours[32] = { 0x000, 0xF00, 0x0F0, ... };
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LoadRGB4(viewport, colours, 32); /* sets 32 colours from 12-bit table */
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UWORD colors[32] = { 0x000, 0xF00, 0x0F0, ... };
|
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LoadRGB4(viewport, colors, 32); /* sets 32 colors from 12-bit table */
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```
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`LoadRGB4()` is safe on all chipsets but only provides 12-bit precision on AGA.
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|
@ -82,9 +82,9 @@ HAM8 is the AGA extension of OCS's HAM6. It uses 8 bitplanes:
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- `01` = modify blue channel
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- `10` = modify red channel
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- `11` = modify green channel
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- **Bits 5-0**: 6-bit value for the selected channel (or 6-bit colour index)
|
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- **Bits 5-0**: 6-bit value for the selected channel (or 6-bit color index)
|
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|
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Result: 2^18 = **262,144 simultaneous colours** from adjacent-pixel modification.
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Result: 2^18 = **262,144 simultaneous colors** from adjacent-pixel modification.
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|
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Enabling HAM8:
|
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```asm
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|
@ -92,19 +92,19 @@ Enabling HAM8:
|
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move.w #$9811, BPLCON0+custom
|
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```
|
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## Colour Modes Summary
|
||||
## Color Modes Summary
|
||||
|
||||
| Mode | Planes | Colours | Method |
|
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| Mode | Planes | Colors | Method |
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|---|---|---|---|
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| Standard | 1–8 | 2–256 | Direct palette lookup |
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| EHB | 6 | 64 | Extra Half-Brite (OCS/ECS compat) |
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| HAM6 | 6 | 4096 | Hold-and-modify 4-bit channels |
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| HAM8 | 8 | 262,144 | Hold-and-modify 6-bit channels |
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| Dual Playfield | 3+3 | 8+8 | Two independent 8-colour layers |
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| Dual Playfield | 3+3 | 8+8 | Two independent 8-color layers |
|
||||
|
||||
## Colour Bank Selection (BPLCON4)
|
||||
## Color Bank Selection (BPLCON4)
|
||||
|
||||
The 256 colour registers are split into 4 banks of 64:
|
||||
The 256 color registers are split into 4 banks of 64:
|
||||
|
||||
| BPLAM | Bank | Registers |
|
||||
|---|---|---|
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||||
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|
@ -113,15 +113,15 @@ The 256 colour registers are split into 4 banks of 64:
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|||
| $80 | 2 | COLOR128–COLOR191 |
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| $C0 | 3 | COLOR192–COLOR255 |
|
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|
||||
Dual playfield can use BPLCON4 to give each playfield a different 64-colour bank.
|
||||
Dual playfield can use BPLCON4 to give each playfield a different 64-color bank.
|
||||
|
||||
## OS Colour Management
|
||||
## OS Color Management
|
||||
|
||||
`graphics.library` manages palette via the `ColorMap` structure attached to a `ViewPort`:
|
||||
|
||||
```c
|
||||
struct ColorMap *cm = GetColorMap(256); /* allocate 256-entry AGA map */
|
||||
SetRGB32(vp, n, r, g, b); /* set one colour (24-bit each) */
|
||||
SetRGB32(vp, n, r, g, b); /* set one color (24-bit each) */
|
||||
LoadRGB32(vp, table); /* bulk load */
|
||||
FreeColorMap(cm);
|
||||
```
|
||||
|
|
@ -131,4 +131,4 @@ FreeColorMap(cm);
|
|||
- NDK39: `graphics/view.h` — ColorMap, LoadRGB32
|
||||
- ADCD 2.1 Autodocs: graphics — LoadRGB32, SetRGB32
|
||||
- http://amigadev.elowar.com/read/ADCD_2.1/Libraries_Manual_guide/node02B4.html
|
||||
- AmigaMail Vol. 2 — AGA colour system articles
|
||||
- AmigaMail Vol. 2 — AGA color system articles
|
||||
|
|
|
|||
|
|
@ -10,16 +10,16 @@ DMA fetch mode — see [chipset_aga.md](chipset_aga.md) for full description.
|
|||
|
||||
### BPLCON4 — $DFF10C (AGA only)
|
||||
|
||||
Bitplane and sprite colour bank selection:
|
||||
Bitplane and sprite color bank selection:
|
||||
|
||||
```
|
||||
bits 15-8: BPLAM7-0 — Bitplane XOR pattern (AGA colour bank XOR)
|
||||
bits 7-4: ESPRM7-4 — Even sprite colour bank (bits 7:4 of colour reg index)
|
||||
bits 3-0: OSPRM7-4 — Odd sprite colour bank
|
||||
bits 15-8: BPLAM7-0 — Bitplane XOR pattern (AGA color bank XOR)
|
||||
bits 7-4: ESPRM7-4 — Even sprite color bank (bits 7:4 of color reg index)
|
||||
bits 3-0: OSPRM7-4 — Odd sprite color bank
|
||||
```
|
||||
|
||||
**Bitplane bank select via BPLAM:**
|
||||
- BPLAM provides an XOR mask applied to the 8-bit colour index before palette lookup
|
||||
- BPLAM provides an XOR mask applied to the 8-bit color index before palette lookup
|
||||
- BPLAM = $00 → use COLOR00–COLOR63 (bank 0)
|
||||
- BPLAM = $40 → use COLOR64–COLOR127 (bank 1)
|
||||
- BPLAM = $80 → use COLOR128–COLOR191 (bank 2)
|
||||
|
|
@ -27,14 +27,14 @@ bits 3-0: OSPRM7-4 — Odd sprite colour bank
|
|||
|
||||
### COLOR00–COLOR255 — $DFF180–$DFF3BE (AGA)
|
||||
|
||||
AGA extends the colour table from 32 registers (OCS/ECS) to **256 registers**.
|
||||
AGA extends the color table from 32 registers (OCS/ECS) to **256 registers**.
|
||||
|
||||
Each AGA colour register is 32 bits (accessed as two word writes via BPLCON3 latch):
|
||||
Each AGA color register is 32 bits (accessed as two word writes via BPLCON3 latch):
|
||||
|
||||
```asm
|
||||
; Write 24-bit colour to COLOR00:
|
||||
; Write 24-bit color to COLOR00:
|
||||
; First write sets high nibble, second sets low nibble
|
||||
move.w #$0000, BPLCON3+custom ; set LACE=0, select low colour word
|
||||
move.w #$0000, BPLCON3+custom ; set LACE=0, select low color word
|
||||
move.w #$0FFF, COLOR00+custom ; write $RGB (high 12 bits)
|
||||
bset #9, BPLCON3_shadow ; set LOCT (low nibble enable)
|
||||
move.w #$0FFF, COLOR00+custom ; write low nibble of each channel
|
||||
|
|
@ -47,7 +47,7 @@ The standard `LoadRGB32()` and `LoadRGB4()` graphics library calls manage this t
|
|||
### BPLCON2 — $DFF104 (AGA extended)
|
||||
|
||||
```
|
||||
bits 14-9: KILLEHB — kill EHB mode (AGA replaces EHB with 256 colour)
|
||||
bits 14-9: KILLEHB — kill EHB mode (AGA replaces EHB with 256 color)
|
||||
bit 6: RDRAM — read bitplane data from RAM (not registered in Lisa)
|
||||
bits 5-3: PF2PRI — playfield 2 priority
|
||||
bits 2-0: PF1PRI — playfield 1 priority + sprite priority
|
||||
|
|
@ -57,7 +57,7 @@ bits 2-0: PF1PRI — playfield 1 priority + sprite priority
|
|||
|
||||
Additional AGA bits:
|
||||
```
|
||||
bit 9: LOCT — low colour write enable (for 24-bit colour access)
|
||||
bit 9: LOCT — low color write enable (for 24-bit color access)
|
||||
bit 3: BRDSPRT — sprites visible in border
|
||||
```
|
||||
|
||||
|
|
@ -65,28 +65,28 @@ bit 3: BRDSPRT — sprites visible in border
|
|||
|
||||
See [chipset_aga.md](chipset_aga.md) — bit 4 is the MSB of the bitplane count for 7/8-plane modes.
|
||||
|
||||
## Colour Register Access — Low Nibble Protocol
|
||||
## Color Register Access — Low Nibble Protocol
|
||||
|
||||
Writing 24-bit colour to AGA registers requires two steps per colour:
|
||||
Writing 24-bit color to AGA registers requires two steps per color:
|
||||
|
||||
1. **Write high nibble** (standard): `COLOR00 = $0RGB` (bits [11:0] = R[3:0], G[3:0], B[3:0])
|
||||
2. **Set LOCT** in BPLCON3 (bit 9)
|
||||
3. **Write low nibble**: `COLOR00 = $0rgb` (bits [11:0] = R[3:0], G[3:0], B[3:0], these are the low 4 bits)
|
||||
|
||||
This two-write sequence gives 8 bits per channel (R[7:0], G[7:0], B[7:0]) = 24-bit colour.
|
||||
This two-write sequence gives 8 bits per channel (R[7:0], G[7:0], B[7:0]) = 24-bit color.
|
||||
|
||||
`LoadRGB32()` does this automatically:
|
||||
```c
|
||||
/* AGA 32-bit colour table format:
|
||||
Count, then pairs: [colour_index, 0x00RRGGBB] */
|
||||
ULONG colour_table[] = {
|
||||
32, 0, /* 32 colours starting at index 0 */
|
||||
/* AGA 32-bit color table format:
|
||||
Count, then pairs: [color_index, 0x00RRGGBB] */
|
||||
ULONG color_table[] = {
|
||||
32, 0, /* 32 colors starting at index 0 */
|
||||
0x00FF0000, /* COLOR00 = red */
|
||||
0x0000FF00, /* COLOR01 = green */
|
||||
/* ... */
|
||||
~0UL /* terminator */
|
||||
};
|
||||
LoadRGB32(vp, colour_table);
|
||||
LoadRGB32(vp, color_table);
|
||||
```
|
||||
|
||||
## References
|
||||
|
|
@ -94,4 +94,4 @@ LoadRGB32(vp, colour_table);
|
|||
- ADCD 2.1 Hardware Manual — AGA register appendix
|
||||
- NDK39: `hardware/custom.h`, `graphics/view.h`
|
||||
- Commodore A1200/A4000 Technical Reference Manuals
|
||||
- AmigaMail Vol. 2 — AGA colour programming
|
||||
- AmigaMail Vol. 2 — AGA color programming
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ Output: 8 longwords of planar data (1 longword per bitplane × 8 planes)
|
|||
move.l (a1), (a2)+ ; bitplane 7
|
||||
```
|
||||
|
||||
#### Optimised Loop (MOVEM)
|
||||
#### Optimized Loop (MOVEM)
|
||||
|
||||
In practice, the entire 32-pixel conversion is done with two MOVEM instructions:
|
||||
|
||||
|
|
@ -119,7 +119,7 @@ In practice, the entire 32-pixel conversion is done with two MOVEM instructions:
|
|||
|
||||
#### Full-Screen Conversion Example
|
||||
|
||||
For a 320×256 screen at 8 bitplanes (256 colours):
|
||||
For a 320×256 screen at 8 bitplanes (256 colors):
|
||||
|
||||
```asm
|
||||
; Total pixels = 320 × 256 = 81,920
|
||||
|
|
@ -203,9 +203,9 @@ Communication with the drive is command/response based through the Akiko registe
|
|||
|
||||
The CD32 boots exclusively from CD-ROM (no floppy drive). The boot sequence:
|
||||
|
||||
1. Kickstart 3.1 initialises from ROM (`$F80000`)
|
||||
1. Kickstart 3.1 initializes from ROM (`$F80000`)
|
||||
2. Extended ROM at `$E00000` provides `cd.device` and the CD filesystem
|
||||
3. Akiko initialises the CD-ROM drive
|
||||
3. Akiko initializes the CD-ROM drive
|
||||
4. The system reads the TOC and looks for a boot block (Amiga executable format)
|
||||
5. If found, the boot executable is loaded and run — this is the game/application entry point
|
||||
|
||||
|
|
|
|||
|
|
@ -12,10 +12,10 @@ Alice is the successor to Super Agnus and is the DMA controller and Copper/Blitt
|
|||
Alice can fetch 2 or 4 words per DMA cycle via the `FMODE` register ($DFF1FC). This dramatically increases the bandwidth available to the blitter and bitplane DMA.
|
||||
|
||||
**Extended bitplane depth:**
|
||||
Alice supports up to **8 bitplanes** (256 colours), compared to OCS/ECS's 6-plane limit.
|
||||
Alice supports up to **8 bitplanes** (256 colors), compared to OCS/ECS's 6-plane limit.
|
||||
|
||||
**BPLCON4:**
|
||||
Alice adds `BPLCON4` to control bitplane bank selection — which 64-entry block of the 256-entry colour table is used by the bitplanes.
|
||||
Alice adds `BPLCON4` to control bitplane bank selection — which 64-entry block of the 256-entry color table is used by the bitplanes.
|
||||
|
||||
### ALICE_ID
|
||||
|
||||
|
|
@ -34,18 +34,18 @@ lsr.w #8, d0
|
|||
|
||||
## Lisa (AGA Denise)
|
||||
|
||||
Lisa is the display chip successor to ECS Denise, providing 8-bit colour output (256 colour registers) and extended sprite capabilities.
|
||||
Lisa is the display chip successor to ECS Denise, providing 8-bit color output (256 color registers) and extended sprite capabilities.
|
||||
|
||||
### Key Enhancements over ECS Denise
|
||||
|
||||
**256 colour registers:**
|
||||
**256 color registers:**
|
||||
Lisa provides COLOR00–COLOR255, each 24-bit (32-bit register with low byte unused).
|
||||
|
||||
**4 colour banks for bitplanes:**
|
||||
`BPLCON4` selects which 64-register bank (0–3) the bitplanes use for lookup. This allows dual-playfield each using a different 64-colour palette.
|
||||
**4 color banks for bitplanes:**
|
||||
`BPLCON4` selects which 64-register bank (0–3) the bitplanes use for lookup. This allows dual-playfield each using a different 64-color palette.
|
||||
|
||||
**Sprite bank selection:**
|
||||
`BPLCON3` bits select which colour bank sprite pairs use.
|
||||
`BPLCON3` bits select which color bank sprite pairs use.
|
||||
|
||||
**Extended sprite width:**
|
||||
Sprites can be 16 or 64 pixels wide in AGA mode.
|
||||
|
|
@ -105,7 +105,7 @@ bits 14-12: BPU2-0 — lower 3 bits of bitplane count
|
|||
bit 4: BPU3 — MSB of bitplane count (AGA: allows 7, 8 planes)
|
||||
```
|
||||
|
||||
To use 8 bitplanes (256 colours):
|
||||
To use 8 bitplanes (256 colors):
|
||||
```asm
|
||||
move.w #$9411, BPLCON0+custom ; HIRES=1 (if needed), BPU=8 (BPU3=1, BPU2-0=000), ECSENA=1
|
||||
```
|
||||
|
|
@ -123,4 +123,4 @@ move.w #$9411, BPLCON0+custom ; HIRES=1 (if needed), BPU=8 (BPU3=1, BPU2-0=000
|
|||
|
||||
- [Akiko — CD32 Custom Chip](akiko_cd32.md) — CD32-exclusive ASIC (C2P, CD-ROM, NVRAM) that sits alongside Alice/Lisa/Paula
|
||||
- [AGA Blitter](aga_blitter.md) — 64-bit FMODE blitter details
|
||||
- [AGA Palette](aga_palette.md) — 256-register 24-bit colour system
|
||||
- [AGA Palette](aga_palette.md) — 256-register 24-bit color system
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue