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exec_os: enrich all stubs to bootcamp-quality reference articles
Complete rewrite of 14 exec_os articles from stubs to comprehensive deep-dive technical references with architecture diagrams, pitfalls, and best practices. New: multitasking.md (scheduler, IPC, memory safety, real-world scenarios) Enriched: exec_base, tasks_processes, library_system, library_vectors, interrupts, exceptions_traps, memory_management, message_ports, signals, semaphores, io_requests, lists_nodes, resident_modules Updated indexes: 06_exec_os/README.md, root README.md
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Ilia Sharin
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16 changed files with 4463 additions and 678 deletions
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@ -4,123 +4,401 @@
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## Overview
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AmigaOS supports 7 hardware interrupt levels (68k IPL0–IPL6) plus a software interrupt mechanism. Custom chip interrupts are filtered through the `INTENA` / `INTREQ` registers; CIA-generated interrupts arrive on level 2 (CIA-A) and level 6 (CIA-B).
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AmigaOS supports 7 hardware interrupt levels (68k IPL0–IPL6) plus a software interrupt mechanism. Custom chip interrupts are filtered through the `INTENA` / `INTREQ` registers; CIA-generated interrupts arrive on level 2 (CIA-A) and level 6 (CIA-B). The interrupt system is the foundation of all real-time behavior — audio DMA, vertical blank timing, keyboard input, and the scheduler itself all depend on it.
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---
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## Architecture
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```mermaid
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graph TB
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subgraph "Hardware Sources"
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SER["Serial Port"]
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DSK["Disk Controller"]
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KBD["Keyboard (CIA-A)"]
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TMR["CIA Timers"]
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COP["Copper"]
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VBL["Vertical Blank"]
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BLT["Blitter"]
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AUD["Audio DMA"]
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EXT["External (CIA-B)"]
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end
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subgraph "Custom Chips"
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INTREQ["INTREQ<br/>($DFF09C)"]
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INTENA["INTENA<br/>($DFF09A)"]
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end
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subgraph "68k CPU"
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IPL["IPL0-IPL6<br/>(priority encoder)"]
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VEC["Exception Vector<br/>($64–$78)"]
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ISR["Exec Interrupt<br/>Dispatcher"]
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end
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subgraph "Exec"
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CHAIN["Interrupt Server<br/>Chain (per level)"]
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SOFT["Software Interrupt<br/>Queue"]
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end
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SER --> INTREQ
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DSK --> INTREQ
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COP --> INTREQ
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VBL --> INTREQ
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BLT --> INTREQ
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AUD --> INTREQ
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KBD --> INTREQ
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EXT --> INTREQ
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INTREQ --> INTENA
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INTENA --> IPL
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IPL --> VEC
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VEC --> ISR
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ISR --> CHAIN
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CHAIN --> SOFT
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style INTREQ fill:#fff3e0,stroke:#ff9800,color:#333
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style INTENA fill:#fff3e0,stroke:#ff9800,color:#333
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style ISR fill:#e8f4fd,stroke:#2196f3,color:#333
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```
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---
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## Interrupt Priority Levels
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| IPL | Source | AmigaOS Use |
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|---|---|---|
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| 1 | TBE, DSKBLK, SOFTINT | Software interrupts (`SoftInt`) |
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| 2 | PORTS (CIA-A) | Keyboard, timer, parallel, floppy motor |
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| 3 | COPER, VERTB, BLIT | Copper, vertical blank, blitter |
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| 4 | AUD0–AUD3 | Audio DMA completion |
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| 5 | RBF, DSKSYNC | Serial receive, disk sync |
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| 6 | EXTER (CIA-B) | External interrupts, CIA-B timers, TOD |
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| 7 | NMI | Non-maskable (unused on stock Amiga) |
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| IPL | Source Bits | AmigaOS Use | Typical Latency |
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|---|---|---|---|
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| 1 | TBE, DSKBLK, SOFTINT | Software interrupts, serial TX, disk DMA complete | ~10 µs |
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| 2 | PORTS (CIA-A) | Keyboard, CIA-A timers, parallel port, floppy index | ~15 µs |
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| 3 | COPER, VERTB, BLIT | Copper, vertical blank, blitter done | ~10 µs |
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| 4 | AUD0–AUD3 | Audio channel DMA completion | ~10 µs |
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| 5 | RBF, DSKSYNC | Serial receive, disk sync word | ~8 µs |
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| 6 | EXTER (CIA-B) | CIA-B timers, external interrupts, TOD alarm | ~8 µs |
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| 7 | NMI | Non-maskable (unused on stock Amiga hardware) | — |
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Higher IPL = higher priority. A level 6 interrupt can preempt level 1–5 handlers. The CPU's SR (Status Register) mask bits determine which levels are currently enabled.
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### Interrupt Sources per Level
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```mermaid
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graph LR
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subgraph "Level 1"
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L1A["TBE<br/>Serial TX"]
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L1B["DSKBLK<br/>Disk DMA"]
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L1C["SOFTINT<br/>Software"]
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end
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subgraph "Level 2"
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L2["PORTS<br/>CIA-A"]
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end
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subgraph "Level 3"
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L3A["COPER<br/>Copper"]
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L3B["VERTB<br/>VBlank"]
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L3C["BLIT<br/>Blitter"]
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end
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subgraph "Level 4"
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L4A["AUD0"]
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L4B["AUD1"]
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L4C["AUD2"]
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L4D["AUD3"]
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end
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subgraph "Level 5"
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L5A["RBF<br/>Serial RX"]
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L5B["DSKSYNC<br/>Disk sync"]
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end
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subgraph "Level 6"
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L6["EXTER<br/>CIA-B"]
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end
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```
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---
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## Custom Chip Interrupt Registers
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| Register | Address | Description |
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|---|---|---|
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| `INTENAR` | `$DFF01C` | Interrupt enable status (read) |
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| `INTENA` | `$DFF09A` | Interrupt enable set/clear (write) |
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| `INTREQR` | `$DFF01E` | Interrupt request status (read) |
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| `INTREQ` | `$DFF09C` | Interrupt request clear/set (write) |
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| Register | Address | R/W | Description |
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|---|---|---|---|
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| `INTENAR` | `$DFF01C` | R | Interrupt enable status (read) |
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| `INTENA` | `$DFF09A` | W | Interrupt enable set/clear (write) |
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| `INTREQR` | `$DFF01E` | R | Interrupt request status (read) |
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| `INTREQ` | `$DFF09C` | W | Interrupt request clear/set (write) |
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### INTENA / INTREQ Bit Map
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| Bit | Constant | Source |
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|---|---|---|
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| 0 | `INTF_TBE` | Serial transmit buffer empty |
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| 1 | `INTF_DSKBLK` | Disk DMA block complete |
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| 2 | `INTF_SOFTINT` | Software interrupt |
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| 3 | `INTF_PORTS` | CIA-A interrupt (level 2) |
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| 4 | `INTF_COPER` | Copper interrupt |
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| 5 | `INTF_VERTB` | Vertical blank |
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| 6 | `INTF_BLIT` | Blitter interrupt |
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| 7 | `INTF_AUD0` | Audio channel 0 |
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| 8 | `INTF_AUD1` | Audio channel 1 |
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| 9 | `INTF_AUD2` | Audio channel 2 |
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| 10 | `INTF_AUD3` | Audio channel 3 |
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| 11 | `INTF_RBF` | Serial receive buffer full |
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| 12 | `INTF_DSKSYNC` | Disk sync word match |
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| 13 | `INTF_EXTER` | CIA-B / external interrupt |
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| 14 | `INTF_INTEN` | Master interrupt enable bit |
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| Bit | Constant | Level | Source |
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|---|---|---|---|
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| 0 | `INTF_TBE` | 1 | Serial transmit buffer empty |
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| 1 | `INTF_DSKBLK` | 1 | Disk DMA block complete |
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| 2 | `INTF_SOFTINT` | 1 | Software interrupt |
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| 3 | `INTF_PORTS` | 2 | CIA-A interrupt (keyboard, timers) |
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| 4 | `INTF_COPER` | 3 | Copper interrupt |
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| 5 | `INTF_VERTB` | 3 | Vertical blank |
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| 6 | `INTF_BLIT` | 3 | Blitter finished |
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| 7 | `INTF_AUD0` | 4 | Audio channel 0 DMA done |
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| 8 | `INTF_AUD1` | 4 | Audio channel 1 DMA done |
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| 9 | `INTF_AUD2` | 4 | Audio channel 2 DMA done |
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| 10 | `INTF_AUD3` | 4 | Audio channel 3 DMA done |
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| 11 | `INTF_RBF` | 5 | Serial receive buffer full |
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| 12 | `INTF_DSKSYNC` | 5 | Disk sync word match |
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| 13 | `INTF_EXTER` | 6 | CIA-B / external interrupt |
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| 14 | `INTF_INTEN` | — | **Master interrupt enable** |
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| 15 | `INTF_SETCLR` | — | Set/Clear control bit (write only) |
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To enable vertical blank: write `$C005` to `INTENA` (bit 14 set = enable, bit 5 = VERTB).
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To clear vertical blank request: write `$0020` to `INTREQ`.
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### Enabling and Clearing Interrupts
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```c
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/* Enable vertical blank interrupt:
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Bit 15 (SET) | Bit 14 (INTEN) | Bit 5 (VERTB) = $C020 */
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custom.intena = INTF_SETCLR | INTF_INTEN | INTF_VERTB;
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/* Disable vertical blank (clear bit 5): */
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custom.intena = INTF_VERTB; /* Bit 15 clear = CLEAR mode */
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/* Acknowledge (clear) a vertical blank request: */
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custom.intreq = INTF_VERTB;
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```
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> **Important**: You must write `INTF_SETCLR` (bit 15) to SET bits. Without it, you CLEAR them. This is a common source of bugs.
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---
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## Adding an Interrupt Server
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## Exec Interrupt Dispatch
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### Server Chain vs Direct Handler
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Exec provides two models for handling interrupts:
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| Model | Function | Use Case |
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|---|---|---|
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| **Server chain** | `AddIntServer()` / `RemIntServer()` | Shared interrupts (multiple handlers per level) |
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| **Direct handler** | `SetIntVector()` | Exclusive interrupt ownership |
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For levels with multiple sources (VBL, PORTS), use the **server chain**. Each handler in the chain checks if the interrupt is for it and returns D0=0 (not mine) or D0≠0 (handled).
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### Adding an Interrupt Server
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```c
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struct Interrupt myVBL = {
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{ NULL, NULL, NT_INTERRUPT, 0, "My VBL" },
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NULL, /* is_Data (passed to handler) */
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myVBLHandler /* is_Code */
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};
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/* Vertical blank interrupt server */
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struct Interrupt myVBL;
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AddIntServer(INTB_VERTB, &myVBL); /* INTB_VERTB = 5 */
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/* ... run ... */
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RemIntServer(INTB_VERTB, &myVBL); /* always remove before exit */
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myVBL.is_Node.ln_Type = NT_INTERRUPT;
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myVBL.is_Node.ln_Pri = 0; /* Priority within this level */
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myVBL.is_Node.ln_Name = "MyApp VBL";
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myVBL.is_Data = myDataPtr; /* Passed in A1 */
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myVBL.is_Code = myVBLFunc; /* Handler address */
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AddIntServer(INTB_VERTB, &myVBL); /* INTB_VERTB = 5 */
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/* ... application runs ... */
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RemIntServer(INTB_VERTB, &myVBL); /* MUST remove before exit! */
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```
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### Interrupt Handler Rules
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### Interrupt Handler Implementation
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- Handler is called at interrupt level — **no OS calls that Wait()**
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- D0–D1, A0–A1 may be trashed; all others preserved
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- Return D0 = 0 if you did not handle it (pass to next server)
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- Return D0 ≠ 0 if you handled it (stop server chain)
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```c
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/* C handler — called at interrupt level */
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ULONG __saveds __interrupt MyVBLHandler(
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struct Interrupt *irq __asm("a1")) /* is_Data in A1 */
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{
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struct MyData *data = (struct MyData *)irq;
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/* Do fast work only */
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data->frameCount++;
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if (data->needUpdate)
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{
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data->needUpdate = FALSE;
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Signal(data->mainTask, data->updateSig); /* Wake main task */
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}
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return 1; /* Handled — stop chain (for exclusive sources)
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Return 0 to let next server in chain try */
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}
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```
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### Assembly Handler (Maximum Performance)
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Handler signature:
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```asm
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myVBLHandler:
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; A1 = is_Data pointer (from struct Interrupt)
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; do fast work only
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MOVEQ #1, D0 ; handled — stop chain
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RTS
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; A1 = is_Data pointer
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; Must preserve D2-D7, A2-A6
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; May trash D0, D1, A0, A1
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MyVBLHandler:
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move.l (a1),a0 ; Load data pointer
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addq.l #1,FRAMECOUNT(a0)
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moveq #1,d0 ; Handled
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rts
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```
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---
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## Handler Rules
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| Rule | Reason | Consequence |
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|---|---|---|
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| **No `Wait()` or `WaitPort()`** | Can't sleep at interrupt level | System freeze |
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| **No `AllocMem()` / `FreeMem()`** | May internally `Wait()` | System freeze |
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| **No DOS calls** | DOS is not reentrant | Corruption |
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| **No Intuition calls** | May `Wait()` internally | Deadlock |
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| **Preserve D2-D7, A2-A6** | Calling convention | Register corruption |
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| **Minimize execution time** | Blocks all lower-priority interrupts | Audio glitches, serial data loss |
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| **Use `Signal()` for deferred work** | Only safe IPC from interrupt context | — |
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| **Always acknowledge the interrupt** | Write to INTREQ to clear the request | Infinite interrupt loop |
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---
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## CIA Interrupts
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CIA-A (at `$BFEC01`) generates level 2 interrupts. CIA-B (at `$BFD000`) generates level 6. Each CIA has an ICR (Interrupt Control Register) with 5 sources:
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CIA-A (`$BFE001`) generates level 2 (PORTS) interrupts. CIA-B (`$BFD000`) generates level 6 (EXTER) interrupts. Each CIA has an ICR (Interrupt Control Register) with 5 sources:
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| Bit | Source |
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|---|---|
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| 0 | Timer A underflow |
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| 1 | Timer B underflow |
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| 2 | TOD alarm |
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| 3 | Serial register full |
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| 4 | Flag pin / FLG |
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| Bit | Source | CIA-A Use | CIA-B Use |
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|---|---|---|---|
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| 0 | Timer A underflow | Keyboard scan timer | System timer |
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| 1 | Timer B underflow | Available | Available |
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| 2 | TOD alarm | Real-time clock alarm | VSync counter |
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| 3 | Serial register (SP) | Keyboard data received | Available |
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| 4 | FLAG pin | Accent key / disk index | Available |
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CIA interrupts are serviced via AddIntServer on `INTB_PORTS` (level 2, CIA-A) or `INTB_EXTER` (level 6, CIA-B).
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### CIA Interrupt Handler
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```c
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/* CIA-A keyboard interrupt (level 2) */
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struct Interrupt kbdHandler;
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kbdHandler.is_Code = KbdISR;
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kbdHandler.is_Data = kbdData;
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kbdHandler.is_Node.ln_Pri = 120; /* High priority within level 2 */
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AddIntServer(INTB_PORTS, &kbdHandler); /* Level 2 = CIA-A */
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ULONG __interrupt KbdISR(struct Interrupt *irq __asm("a1"))
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{
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UBYTE icr = ciaa.ciaicr; /* Read + acknowledge CIA-A interrupts */
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if (icr & 0x08) /* Bit 3 = serial port (keyboard data) */
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{
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UBYTE rawKey = ciaa.ciasdr;
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/* Process key... */
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Signal(mainTask, keySig);
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return 1; /* Handled */
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}
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return 0; /* Not ours — pass to next handler */
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}
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```
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---
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## Software Interrupts
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Software interrupts run at level 1 priority but are scheduled by exec, not hardware. They're used for deferred interrupt processing — a hardware interrupt handler can queue a software interrupt to do longer processing at a lower priority:
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```c
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/* Cause a software interrupt */
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struct Interrupt softInt;
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softInt.is_Code = MySoftHandler;
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softInt.is_Data = myData;
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softInt.is_Node.ln_Pri = 0; /* -32, -16, 0, +16, +32 are typical */
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|
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Cause(&softInt); /* LVO -78 */
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/* MySoftHandler runs at next opportunity (level 1) */
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||||
```
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|
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### Software Interrupt Priorities
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||||
|
||||
| Priority | Constant | Use |
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|---|---|---|
|
||||
| +32 | `SIH_PRIMOUSE` | Mouse/gameport processing |
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| +16 | — | High-priority deferred work |
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| 0 | — | Normal deferred work |
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| -16 | — | Low-priority deferred work |
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||||
| -32 | `SIH_PRISERIAL` | Serial port processing |
|
||||
|
||||
---
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||||
|
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## Disable / Enable vs Forbid / Permit
|
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|
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| Function | Effect | Scope |
|
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|---|---|---|
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| `Forbid()` | Disables task switching | Task-level (interrupts still run) |
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| `Permit()` | Re-enables task switching | Reverses `Forbid()` |
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| `Disable()` | Masks all hardware interrupts | Hardware + task switching |
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| `Enable()` | Unmasks hardware interrupts | Reverses `Disable()` |
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| Function | Effect | Scope | Max Safe Duration |
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|---|---|---|---|
|
||||
| `Forbid()` | Disables task switching | Tasks only (interrupts still run) | ~100 ms |
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| `Permit()` | Re-enables task switching | Reverses `Forbid()` | — |
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||||
| `Disable()` | Masks all hardware interrupts | Hardware + task switching | **~250 µs** |
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| `Enable()` | Unmasks hardware interrupts | Reverses `Disable()` | — |
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||||
> [!CAUTION]
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||||
> `Disable()` / `Enable()` can be held for only a few microseconds — never do I/O or complex operations inside a `Disable()` section.
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> **Caution**: `Disable()` / `Enable()` stop ALL hardware — serial data loss, audio DMA glitches, floppy read errors. Use only for accessing data structures shared between task and interrupt context.
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||||
|
||||
---
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||||
|
||||
## Pitfalls
|
||||
|
||||
### 1. Forgetting to Acknowledge
|
||||
|
||||
```c
|
||||
/* BUG — interrupt fires infinitely */
|
||||
ULONG MyHandler(void)
|
||||
{
|
||||
DoWork();
|
||||
return 1;
|
||||
/* Forgot: custom.intreq = INTF_VERTB; */
|
||||
/* INTREQ bit still set → interrupt fires again immediately → system hangs */
|
||||
}
|
||||
```
|
||||
|
||||
> **Note**: For server-chain interrupts (AddIntServer), exec handles INTREQ acknowledgment. For `SetIntVector`, you must do it yourself.
|
||||
|
||||
### 2. RemIntServer After Handler Memory Freed
|
||||
|
||||
```c
|
||||
/* BUG — handler struct on stack */
|
||||
void SetupVBL(void)
|
||||
{
|
||||
struct Interrupt vbl; /* ON STACK */
|
||||
AddIntServer(INTB_VERTB, &vbl);
|
||||
/* Function returns — stack frame destroyed */
|
||||
/* VBL interrupt fires → jumps to garbage → Guru */
|
||||
}
|
||||
```
|
||||
|
||||
### 3. Spending Too Long in Handler
|
||||
|
||||
```c
|
||||
/* BUG — complex processing at interrupt level */
|
||||
ULONG MyAudioHandler(void)
|
||||
{
|
||||
DecodeMP3Frame(buffer); /* Takes >250 µs on 68000 */
|
||||
/* During this time, keyboard, serial, and disk are unserviced */
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* CORRECT — signal task for heavy processing */
|
||||
ULONG MyAudioHandler(void)
|
||||
{
|
||||
Signal(decoderTask, decodeSig); /* ~5 µs */
|
||||
return 1;
|
||||
}
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Best Practices
|
||||
|
||||
1. **Use server chains** (`AddIntServer`) for VBL, PORTS, EXTER — these are shared levels
|
||||
2. **Always `RemIntServer`** before exit or freeing handler memory
|
||||
3. **Keep handlers fast** — signal your main task for heavy work
|
||||
4. **Use software interrupts** for deferred processing from high-priority hardware handlers
|
||||
5. **Acknowledge interrupts** by writing to `INTREQ` when using `SetIntVector`
|
||||
6. **Preserve registers** D2-D7, A2-A6 in your handler
|
||||
7. **Use `Disable()`/`Enable()`** only to protect interrupt-shared data — never for general synchronization
|
||||
8. **Set appropriate priority** in `is_Node.ln_Pri` — higher priority handlers check first
|
||||
|
||||
---
|
||||
|
||||
## References
|
||||
|
||||
- NDK39: `hardware/intbits.h`, `hardware/cia.h`
|
||||
- ADCD 2.1: `AddIntServer`, `RemIntServer`, `SetIntVector`, `Disable`, `Forbid`
|
||||
- [cia_chips.md](../01_hardware/common/cia_chips.md) — CIA timer and ICR details
|
||||
- [custom_registers.md](../01_hardware/ocs_a500/custom_registers.md) — INTENA/INTREQ register listing
|
||||
- NDK39: `hardware/intbits.h`, `hardware/cia.h`, `exec/interrupts.h`
|
||||
- ADCD 2.1: `AddIntServer`, `RemIntServer`, `SetIntVector`, `Cause`, `Disable`, `Enable`
|
||||
- See also: [CIA Chips](../01_hardware/common/cia_chips.md) — CIA timer and ICR details
|
||||
- See also: [Custom Registers](../01_hardware/ocs_a500/custom_registers.md) — INTENA/INTREQ register listing
|
||||
- See also: [Multitasking](multitasking.md) — how interrupts drive the scheduler
|
||||
- *Amiga ROM Kernel Reference Manual: Exec* — interrupts chapter
|
||||
|
|
|
|||
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Add table
Add a link
Reference in a new issue