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docs(amiga): complete AmigaOS 3.1/3.2 developer reference — 172 files across 17 sections
Comprehensive technical documentation covering: - Hardware: OCS/ECS/AGA custom chip registers, Copper & Blitter deep dives - Boot sequence: cold boot through startup-sequence - Binary format: HUNK executable spec, relocation, debug info - Linking & ABI: .fd files, LVO tables, register calling conventions - Exec kernel: tasks, interrupts, memory, signals, semaphores - AmigaDOS: file I/O, FFS/OFS layout, CLI/Shell scripting - Graphics: planar bitmaps, Copper programming, HAM/EHB modes - Intuition: screens, windows, IDCMP, BOOPSI - Devices: trackdisk, SCSI, serial, timer, audio, keyboard - Libraries: utility, expansion, IFFParse, locale, ARexx - Networking: bsdsocket API, SANA-II, TCP/IP stack comparison - Toolchain: GCC, vasm/vlink, SAS/C, NDK, debugging - Reverse engineering: IDA/Ghidra setup, compiler fingerprints, case studies - CPU & MMU: 68040/060 emulation libs, PMMU, cache management - Driver development: SANA-II, Picasso96/RTG, AHI audio All files include breadcrumb navigation. No local paths or proprietary content.
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15_cpu_and_mmu/mmu_management.md
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[← Home](../README.md) · [CPU & MMU](README.md)
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# MMU Management — 68030/040/060 Memory Management Units
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## Overview
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The Motorola 68030, 68040, and 68060 include on-chip **MMUs** (Memory Management Units) that provide virtual-to-physical address translation, memory protection, and cache control. AmigaOS itself does **not use the MMU** for virtual memory — it was designed for a flat address space. However, several third-party tools and libraries use the MMU for:
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- **Enforcer/MuForce** — detecting illegal memory accesses
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- **VMM** — virtual memory (swap to disk)
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- **CyberGuard/MuGuard** — memory protection
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- **SetPatch/MuSetPatch** — cache management
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---
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## MMU Architecture Comparison
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| Feature | 68030 | 68040 | 68060 |
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|---|---|---|---|
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| MMU type | External (on-chip optional) | On-chip, always present | On-chip, always present |
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| Page sizes | 256B, 512B, 1K, 2K, 4K, 8K, 16K, 32K | 4K, 8K (fixed) | 4K, 8K (fixed) |
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| Table levels | 1–4 configurable | Fixed 3-level | Fixed 3-level |
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| TLB entries | 22 (ATC) | 64 (data) + 64 (instruction) | 48 (data) + 48 (instruction) |
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| PMMU instructions | `PMOVE`, `PFLUSH`, `PTEST`, `PLOAD` | `PFLUSHA`, `PFLUSHN`, `CINV`, `CPUSH` | Same as 040 |
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| Transparent translation | `TT0`, `TT1` (via PMOVE) | `DTT0/1`, `ITT0/1` (via MOVEC) | Same as 040 |
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| Supervisor root pointer | `SRP` (via PMOVE) | `SRP` (via MOVEC) | `SRP` (via MOVEC) |
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| CPU root pointer | `CRP` (via PMOVE) | `URP` (via MOVEC) | `URP` (via MOVEC) |
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---
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## Key Registers
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### 68030
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```
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TC — Translation Control
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Bit 31: E (enable)
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Bits 30–28: SRE, FCL (function code lookup)
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Bits 27–24: PS (page size)
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Bits 23–20: IS (initial shift)
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Bits 19–16: TIA (table index A bits)
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...
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TT0, TT1 — Transparent Translation Registers
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Bit 15: E (enable)
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Bits 31–24: Logical address base
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Bits 23–16: Logical address mask
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Bits 2–0: Function code
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CRP — CPU Root Pointer (64-bit)
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SRP — Supervisor Root Pointer (64-bit)
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```
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### 68040/060
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```
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TC — Translation Control (MOVEC accessible)
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Bit 15: E (enable translation)
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Bit 14: P (page size: 0=4K, 1=8K)
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DTT0, DTT1 — Data Transparent Translation
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ITT0, ITT1 — Instruction Transparent Translation
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Same format: base/mask/enable/cache-mode
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URP — User Root Pointer (32-bit, MOVEC)
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SRP — Supervisor Root Pointer (32-bit, MOVEC)
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```
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---
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## Page Table Entry Format (68040/060)
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```
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31 12 11 10 9 8 7 6 5 4 3 2 1 0
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┌──────────────┬───┬───┬──┬──┬──┬──┬──┬──┬──┬──┬──┐
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│ Physical Addr│ U1│ U0│ S│CM1│CM0│ M│ U│ W│ UDT │
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└──────────────┴───┴───┴──┴──┴──┴──┴──┴──┴──┴──┴──┘
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UDT: 00=invalid, 01=page descriptor, 10=valid4byte, 11=valid8byte
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W: write-protected
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U: used (accessed)
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M: modified (dirty)
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CM: cache mode (00=cacheable/writethrough, 01=cacheable/copyback,
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10=noncacheable/serialized, 11=noncacheable)
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S: supervisor only
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```
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---
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## mmu.library (Third-Party)
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Several third-party `mmu.library` implementations exist:
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| Library | Author | Description |
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|---|---|---|
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| `mmu.library` (MuLib) | Thomas Richter | The standard; used by MuForce, MuGuard, VMM |
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| `68040mmu.library` | Phase5 | Basic 040 MMU setup for CyberStorm |
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### MuLib API (Key Functions)
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```c
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struct Library *MMUBase = OpenLibrary("mmu.library", 46);
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/* Get current MMU context: */
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struct MMUContext *ctx = CurrentContext(MMUBase);
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/* Get page properties: */
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ULONG props = GetPageProperties(ctx, address);
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/* Set page properties: */
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SetPageProperties(ctx, address, length,
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MAPP_READABLE | MAPP_WRITABLE, /* what to set */
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~0UL /* mask */
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);
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/* Remap a virtual page to a different physical address: */
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RemapPage(ctx, virtualAddr, physicalAddr, properties);
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/* Flush TLB: */
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RebuildTree(ctx); /* rebuild MMU tables and flush */
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```
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### Property Flags
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```c
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#define MAPP_READABLE (1<<0)
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#define MAPP_WRITABLE (1<<1)
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#define MAPP_EXECUTABLE (1<<2)
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#define MAPP_CACHEABLE (1<<3)
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#define MAPP_COPYBACK (1<<4)
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#define MAPP_SUPERVISORONLY (1<<5)
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#define MAPP_USERPAGE0 (1<<6)
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#define MAPP_USERPAGE1 (1<<7)
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#define MAPP_GLOBAL (1<<8)
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#define MAPP_BLANK (1<<9) /* invalid/unmapped */
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#define MAPP_SWAPPED (1<<10) /* paged out to disk */
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#define MAPP_TRANSLATED (1<<11) /* virtual ≠ physical */
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```
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---
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## Enforcer — How It Uses MMU
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Enforcer maps address `$000000–$0003FF` (low memory) and `$00C00000+` (unassigned ranges) as **invalid pages**. Any access to these causes an MMU exception that Enforcer catches, logs, and allows the program to continue:
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```
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ENFORCER HIT: 00000000 READ by task "BadApp" at 0002045A
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```
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---
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## VMM — Virtual Memory
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VMM (Virtual Memory Manager) uses the MMU to implement demand-paged virtual memory:
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1. Maps physical RAM pages into the address space
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2. When RAM is full, pages least-recently-used blocks to a swap file on disk
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3. On access to a swapped-out page → MMU exception → VMM reads page back from disk
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4. Transparent to applications — they see continuous RAM
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---
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## Direct MMU Programming (No Library)
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```asm
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; 68040: Enable MMU with 4K pages
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; Set up page tables at PAGE_TABLE_BASE...
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movec.l PAGE_TABLE_BASE,urp ; set User Root Pointer
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movec.l PAGE_TABLE_BASE,srp ; set Supervisor Root Pointer
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move.l #$8000,d0 ; TC: E=1, P=0 (4K pages)
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movec.l d0,tc ; enable translation!
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pflusha ; flush all TLB entries
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; 68040: Set transparent translation (map $00000000–$00FFFFFF 1:1)
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move.l #$00FFE040,d0 ; base=$00, mask=$FF, E=1, CM=writethrough
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movec.l d0,dtt0 ; data transparent translation 0
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movec.l d0,itt0 ; instruction transparent translation 0
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```
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---
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## References
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- Motorola: *MC68030 User's Manual* — MMU chapter
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- Motorola: *MC68040 User's Manual* — MMU chapter
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- Motorola: *MC68060 User's Manual* — MMU chapter
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- Thomas Richter: MuLib documentation (Aminet: `util/libs/MMULib.lha`)
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- Enforcer source (public domain)
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