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docs(amiga): complete AmigaOS 3.1/3.2 developer reference — 172 files across 17 sections
Comprehensive technical documentation covering: - Hardware: OCS/ECS/AGA custom chip registers, Copper & Blitter deep dives - Boot sequence: cold boot through startup-sequence - Binary format: HUNK executable spec, relocation, debug info - Linking & ABI: .fd files, LVO tables, register calling conventions - Exec kernel: tasks, interrupts, memory, signals, semaphores - AmigaDOS: file I/O, FFS/OFS layout, CLI/Shell scripting - Graphics: planar bitmaps, Copper programming, HAM/EHB modes - Intuition: screens, windows, IDCMP, BOOPSI - Devices: trackdisk, SCSI, serial, timer, audio, keyboard - Libraries: utility, expansion, IFFParse, locale, ARexx - Networking: bsdsocket API, SANA-II, TCP/IP stack comparison - Toolchain: GCC, vasm/vlink, SAS/C, NDK, debugging - Reverse engineering: IDA/Ghidra setup, compiler fingerprints, case studies - CPU & MMU: 68040/060 emulation libs, PMMU, cache management - Driver development: SANA-II, Picasso96/RTG, AHI audio All files include breadcrumb navigation. No local paths or proprietary content.
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01_hardware/ocs_a500/custom_registers.md
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[← Home](../../README.md) · [Hardware](../README.md) · [OCS](README.md)
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# OCS Custom Register Map
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Base address: `$00DFF000`. All registers are 16-bit (word) wide. Byte access is valid for the appropriate byte lane.
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Legend: **R** = read, **W** = write, **RW** = read-write, **S** = strobe (write triggers action)
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## DMA and Interrupt Control
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| Offset | Name | Dir | Description |
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|---|---|---|---|
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| $002 | DMACONR | R | DMA control register (read) |
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| $01C | INTENAR | R | Interrupt enable (read) |
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| $01E | INTREQR | R | Interrupt request (read) |
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| $096 | DMACON | W | DMA control (write: bit15=SET/CLR) |
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| $09A | INTENA | W | Interrupt enable (write: bit15=SET/CLR) |
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| $09C | INTREQ | W | Interrupt request — ack / force |
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## Beam Position (Read Only)
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| Offset | Name | Dir | Description |
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|---|---|---|---|
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| $004 | VPOSR | R | Vertical position high, LOF bit |
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| $006 | VHPOSR | R | Vertical + horizontal beam position |
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| $007 | VHPOS | R | Horizontal beam position (byte) |
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## Copper
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| Offset | Name | Dir | Description |
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|---|---|---|---|
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| $02E | COPCON | W | Copper control (CDANG bit) |
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| $080 | COP1LCH | W | Copper list 1 pointer high |
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| $082 | COP1LCL | W | Copper list 1 pointer low |
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| $084 | COP2LCH | W | Copper list 2 pointer high |
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| $086 | COP2LCL | W | Copper list 2 pointer low |
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| $088 | COPJMP1 | S | Restart Copper from list 1 |
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| $08A | COPJMP2 | S | Restart Copper from list 2 |
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| $08C | COPINS | W | Copper instruction (direct write) |
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| $000 | BLTDDAT | R | Blitter dest early read (Copper use) |
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## Blitter
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| Offset | Name | Dir | Description |
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|---|---|---|---|
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| $040 | BLTCON0 | W | Blitter control 0 (minterm, channels) |
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| $042 | BLTCON1 | W | Blitter control 1 (line mode, fill) |
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| $044 | BLTAFWM | W | First word mask, channel A |
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| $046 | BLTALWM | W | Last word mask, channel A |
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| $048 | BLTCPTH | W | Channel C pointer high |
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| $04A | BLTCPTL | W | Channel C pointer low |
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| $04C | BLTBPTH | W | Channel B pointer high |
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| $04E | BLTBPTL | W | Channel B pointer low |
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| $050 | BLTAPTH | W | Channel A pointer high |
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| $052 | BLTAPTL | W | Channel A pointer low |
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| $054 | BLTDPTH | W | Destination pointer high |
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| $056 | BLTDPTL | W | Destination pointer low |
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| $058 | BLTSIZE | W | Blitter size + start (height×64 + width) |
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| $060 | BLTCMOD | W | Channel C modulo |
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| $062 | BLTBMOD | W | Channel B modulo |
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| $064 | BLTAMOD | W | Channel A modulo |
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| $066 | BLTDMOD | W | Destination modulo |
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| $070 | BLTCDAT | W | Channel C data register |
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| $072 | BLTBDAT | W | Channel B data register |
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| $074 | BLTADAT | W | Channel A data register |
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## Bitplane Pointers
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| Offset | Name | Dir | Description |
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|---|---|---|---|
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| $0E0 | BPL1PTH | W | Bitplane 1 pointer high |
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| $0E2 | BPL1PTL | W | Bitplane 1 pointer low |
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| $0E4 | BPL2PTH | W | Bitplane 2 pointer high |
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| $0E6 | BPL2PTL | W | Bitplane 2 pointer low |
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| $0E8 | BPL3PTH | W | Bitplane 3 pointer high |
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| $0EA | BPL3PTL | W | Bitplane 3 pointer low |
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| $0EC | BPL4PTH | W | Bitplane 4 pointer high |
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| $0EE | BPL4PTL | W | Bitplane 4 pointer low |
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| $0F0 | BPL5PTH | W | Bitplane 5 pointer high |
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| $0F2 | BPL5PTL | W | Bitplane 5 pointer low |
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| $0F4 | BPL6PTH | W | Bitplane 6 pointer high |
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| $0F6 | BPL6PTL | W | Bitplane 6 pointer low |
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## Bitplane Control
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| Offset | Name | Dir | Description |
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|---|---|---|---|
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| $100 | BPLCON0 | W | Bitplane control 0 (depth, HAM, HIRES, LACE) |
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| $102 | BPLCON1 | W | Bitplane scroll (fine scroll values) |
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| $104 | BPLCON2 | W | Sprite vs bitplane priority |
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| $108 | BPL1MOD | W | Bitplane modulo (odd planes) |
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| $10A | BPL2MOD | W | Bitplane modulo (even planes) |
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| $110 | BPL1DAT | W | Bitplane 1 data register |
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| $112 | BPL2DAT | W | Bitplane 2 data register |
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| $114 | BPL3DAT | W | Bitplane 3 |
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| $116 | BPL4DAT | W | Bitplane 4 |
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| $118 | BPL5DAT | W | Bitplane 5 |
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| $11A | BPL6DAT | W | Bitplane 6 |
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**BPLCON0 bit layout:**
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```
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bit 15: HIRES (1 = 640 pixel wide)
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bit 14-12: BPU2-0 (number of bitplanes: 0–6)
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bit 11: HAM (1 = Hold-And-Modify mode)
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bit 10: DPF (dual playfield)
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bit 9: COLOR (0 = monochrome, 1 = colour)
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bit 8: GAUD (genlock audio)
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bit 7-4: (various, OCS = 0)
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bit 1: ERSY (external sync)
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bit 0: ECSENA (ECS enable — must be 0 on OCS)
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```
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## Display Window and Fetch
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| Offset | Name | Dir | Description |
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|---|---|---|---|
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| $08E | DIWSTRT | W | Display window start (V and H start) |
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| $090 | DIWSTOP | W | Display window stop |
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| $092 | DDFSTRT | W | Display data fetch start |
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| $094 | DDFSTOP | W | Display data fetch stop |
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## Sprite Pointers and Data
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| Offset | Name | Dir | Description |
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|---|---|---|---|
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| $120 | SPR0PTH | W | Sprite 0 pointer high |
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| $122 | SPR0PTL | W | Sprite 0 pointer low |
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| ... | ... | | Sprites 1–7 follow at +4 each |
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| $13E | SPR7PTL | W | Sprite 7 pointer low |
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| $140 | SPR0POS | W | Sprite 0 position |
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| $142 | SPR0CTL | W | Sprite 0 control |
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| $144 | SPR0DATA | W | Sprite 0 image data word A |
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| $146 | SPR0DATB | W | Sprite 0 image data word B |
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| ... | | | Sprites 1–7 follow |
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| $178 | SPR7DATB | W | Sprite 7 image data word B |
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## Audio Registers
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| Offset | Name | Dir | Description |
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|---|---|---|---|
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| $0A0 | AUD0LCH | W | Audio ch 0 pointer high |
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| $0A2 | AUD0LCL | W | Audio ch 0 pointer low |
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| $0A4 | AUD0LEN | W | Audio ch 0 length (words) |
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| $0A6 | AUD0PER | W | Audio ch 0 period (clock divider) |
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| $0A8 | AUD0VOL | W | Audio ch 0 volume (0–64) |
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| $0AA | AUD0DAT | W | Audio ch 0 data (direct, non-DMA) |
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| ... | | | Channels 1–3 follow at +$10 |
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## Serial Port
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| Offset | Name | Dir | Description |
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|---|---|---|---|
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| $030 | SERDAT | W | Serial data and stop bits |
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| $018 | SERDATR | R | Serial data receive and status |
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| $032 | SERPER | W | Serial period and word length |
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## Disk DMA
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| Offset | Name | Dir | Description |
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|---|---|---|---|
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| $020 | DSKPTH | W | Disk pointer high |
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| $022 | DSKPTL | W | Disk pointer low |
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| $024 | DSKLEN | W | Disk length and write flag |
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| $010 | ADKCONR | R | Audio / disk control (read) |
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| $09E | ADKCON | W | Audio / disk control (write) |
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| $07C | DSKSYNC | W | Disk sync word |
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## Colour Registers
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| Offset | Name | Dir | Description |
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|---|---|---|---|
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| $180 | COLOR00 | W | Background / colour 0 |
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| $182 | COLOR01 | W | Colour 1 |
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| ... | | | |
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| $1BE | COLOR31 | W | Colour 31 |
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OCS colours: 12-bit RGB (4 bits per component, $0RGB format).
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## References
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- *Amiga Hardware Reference Manual* 3rd ed. — Appendix B: Register Summary
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- NDK39: `hardware/custom.h` — struct Custom definition
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- http://amigadev.elowar.com/read/ADCD_2.1/Hardware_Manual_guide/node0000.html
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