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103 lines
3.1 KiB
Markdown
103 lines
3.1 KiB
Markdown
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[← Home](../README.md) · [CPU & MMU](README.md)
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# Cache Management — CacheClearU, CacheControl, CACR
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## Overview
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68020+ processors have instruction and data caches that must be managed correctly, especially when loading code (hunks), self-modifying code, or DMA operations. AmigaOS provides `exec.library` functions for safe cache management.
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---
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## exec.library Cache Functions
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| LVO | Function | Description |
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|---|---|---|
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| −636 | `CacheClearU()` | Flush all caches (user-friendly, safe) |
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| −642 | `CacheClearE(addr, len, caches)` | Flush specific address range |
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| −648 | `CacheControl(cacheBits, cacheMask)` | Enable/disable cache features |
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| −762 | `CachePreDMA(addr, &len, flags)` | Prepare for DMA transfer |
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| −768 | `CachePostDMA(addr, &len, flags)` | Cleanup after DMA transfer |
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---
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## When to Flush Caches
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| Scenario | Function to Call |
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|---|---|
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| After loading code from disk | `CacheClearU()` |
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| After JIT / dynamic code generation | `CacheClearE(code, len, CACRF_ClearI)` |
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| Before DMA read from memory | `CachePreDMA()` (flush dirty data cache) |
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| After DMA write to memory | `CachePostDMA()` (invalidate stale data cache) |
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| After `SetFunction()` patching | `CacheClearU()` |
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---
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## CacheControl Bits
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```c
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/* exec/execbase.h — NDK39 */
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#define CACRF_EnableI (1<<0) /* enable instruction cache */
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#define CACRF_FreezeI (1<<1) /* freeze instruction cache */
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#define CACRF_ClearI (1<<3) /* clear instruction cache */
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#define CACRF_IBE (1<<4) /* instruction burst enable */
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#define CACRF_EnableD (1<<8) /* enable data cache */
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#define CACRF_FreezeD (1<<9) /* freeze data cache */
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#define CACRF_ClearD (1<<11) /* clear data cache */
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#define CACRF_DBE (1<<12) /* data burst enable */
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#define CACRF_WriteAllocate (1<<13) /* write-allocate data cache */
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#define CACRF_EnableE (1<<30) /* enable external cache (A3640) */
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#define CACRF_CopyBack (1<<31) /* enable copyback mode */
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```
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---
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## CACR Register (Direct Access)
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```asm
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; 68040 CACR bits:
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; bit 15: DE (data cache enable)
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; bit 14: — (reserved)
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; bit 13: —
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; bit 12: —
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; bit 11: —
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; bit 10: —
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; bit 9: —
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; bit 8: IE (instruction cache enable)
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; Read CACR:
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movec.l cacr,d0
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; Flush all caches (68040/060):
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cpusha dc ; push data cache
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cpusha ic ; push instruction cache
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cinva dc ; invalidate data cache
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cinva ic ; invalidate instruction cache
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; 68030:
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movec.l cacr,d0
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or.l #$0808,d0 ; set ClearI + ClearD bits
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movec.l d0,cacr
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```
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---
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## DMA and Cache Coherency
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Amiga custom chips (blitter, copper, audio, disk) perform DMA directly to/from Chip RAM, bypassing the CPU cache. This creates coherency issues on 68040/060:
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```c
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/* Before blitter reads data you just wrote: */
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CachePreDMA(data, &length, DMA_ReadFromRAM);
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/* After blitter writes data you want to read: */
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CachePostDMA(data, &length, 0);
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```
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---
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## References
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- NDK39: `exec/execbase.h`
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- Motorola: *MC68040 User's Manual* — cache chapter
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- ADCD 2.1: `CacheClearU`, `CacheClearE`, `CacheControl`
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